drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/bitops.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/blk-mq-pci.h>
  20 #include <linux/cpu.h>
  21 #include <linux/delay.h>
  22 #include <linux/errno.h>
  23 #include <linux/fs.h>
  24 #include <linux/genhd.h>
  25 #include <linux/hdreg.h>
  26 #include <linux/idr.h>
  27 #include <linux/init.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/io.h>
  30 #include <linux/kdev_t.h>
  31 #include <linux/kernel.h>
  32 #include <linux/mm.h>
  33 #include <linux/module.h>
  34 #include <linux/moduleparam.h>
  35 #include <linux/mutex.h>
  36 #include <linux/pci.h>
  37 #include <linux/poison.h>
  38 #include <linux/ptrace.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/t10-pi.h>
  42 #include <linux/timer.h>
  43 #include <linux/types.h>
  44 #include <linux/io-64-nonatomic-lo-hi.h>
  45 #include <asm/unaligned.h>
  46 #include <linux/sed-opal.h>
  47
  48 #include "nvme.h"
  49
  50 #define NVME_Q_DEPTH            1024
  51 #define NVME_AQ_DEPTH           256
  52 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  53 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  54
  55 /*
  56  * We handle AEN commands ourselves and don't even let the
  57  * block layer know about them.
  58  */
  59 #define NVME_AQ_BLKMQ_DEPTH     (NVME_AQ_DEPTH - NVME_NR_AERS)
  60
  61 static int use_threaded_interrupts;
  62 module_param(use_threaded_interrupts, int, 0);
  63
  64 static bool use_cmb_sqes = true;
  65 module_param(use_cmb_sqes, bool, 0644);
  66 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  67
  68 static struct workqueue_struct *nvme_workq;
  69
  70 struct nvme_dev;
  71 struct nvme_queue;
  72
  73 static int nvme_reset(struct nvme_dev *dev);
  74 static void nvme_process_cq(struct nvme_queue *nvmeq);
  75 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  76
  77 /*
  78  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  79  */
  80 struct nvme_dev {
  81         struct nvme_queue **queues;
  82         struct blk_mq_tag_set tagset;
  83         struct blk_mq_tag_set admin_tagset;
  84         u32 __iomem *dbs;
  85         struct device *dev;
  86         struct dma_pool *prp_page_pool;
  87         struct dma_pool *prp_small_pool;
  88         unsigned queue_count;
  89         unsigned online_queues;
  90         unsigned max_qid;
  91         int q_depth;
  92         u32 db_stride;
  93         void __iomem *bar;
  94         struct work_struct reset_work;
  95         struct work_struct remove_work;
  96         struct timer_list watchdog_timer;
  97         struct mutex shutdown_lock;
  98         bool subsystem;
  99         void __iomem *cmb;
 100         dma_addr_t cmb_dma_addr;
 101         u64 cmb_size;
 102         u32 cmbsz;
 103         u32 cmbloc;
 104         struct nvme_ctrl ctrl;
 105         struct completion ioq_wait;
 106 };
 107
 108 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 109 {
 110         return container_of(ctrl, struct nvme_dev, ctrl);
 111 }
 112
 113 /*
 114  * An NVM Express queue.  Each device has at least two (one for admin
 115  * commands and one for I/O commands).
 116  */
 117 struct nvme_queue {
 118         struct device *q_dmadev;
 119         struct nvme_dev *dev;
 120         char irqname[24];       /* nvme4294967295-65535\0 */
 121         spinlock_t q_lock;
 122         struct nvme_command *sq_cmds;
 123         struct nvme_command __iomem *sq_cmds_io;
 124         volatile struct nvme_completion *cqes;
 125         struct blk_mq_tags **tags;
 126         dma_addr_t sq_dma_addr;
 127         dma_addr_t cq_dma_addr;
 128         u32 __iomem *q_db;
 129         u16 q_depth;
 130         s16 cq_vector;
 131         u16 sq_tail;
 132         u16 cq_head;
 133         u16 qid;
 134         u8 cq_phase;
 135         u8 cqe_seen;
 136 };
 137
 138 /*
 139  * The nvme_iod describes the data in an I/O, including the list of PRP
 140  * entries.  You can't see it in this data structure because C doesn't let
 141  * me express that.  Use nvme_init_iod to ensure there's enough space
 142  * allocated to store the PRP list.
 143  */
 144 struct nvme_iod {
 145         struct nvme_request req;
 146         struct nvme_queue *nvmeq;
 147         int aborted;
 148         int npages;             /* In the PRP list. 0 means small pool in use */
 149         int nents;              /* Used in scatterlist */
 150         int length;             /* Of data, in bytes */
 151         dma_addr_t first_dma;
 152         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 153         struct scatterlist *sg;
 154         struct scatterlist inline_sg[0];
 155 };
 156
 157 /*
 158  * Check we didin't inadvertently grow the command struct
 159  */
 160 static inline void _nvme_check_size(void)
 161 {
 162         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 163         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 164         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 165         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 166         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 167         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 168         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 169         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 170         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 171         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 172         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 173         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 174 }
 175
 176 /*
 177  * Max size of iod being embedded in the request payload
 178  */
 179 #define NVME_INT_PAGES          2
 180 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 181
 182 /*
 183  * Will slightly overestimate the number of pages needed.  This is OK
 184  * as it only leads to a small amount of wasted memory for the lifetime of
 185  * the I/O.
 186  */
 187 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 188 {
 189         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 190                                       dev->ctrl.page_size);
 191         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 192 }
 193
 194 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
 195                 unsigned int size, unsigned int nseg)
 196 {
 197         return sizeof(__le64 *) * nvme_npages(size, dev) +
 198                         sizeof(struct scatterlist) * nseg;
 199 }
 200
 201 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 202 {
 203         return sizeof(struct nvme_iod) +
 204                 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
 205 }
 206
 207 static int nvmeq_irq(struct nvme_queue *nvmeq)
 208 {
 209         return pci_irq_vector(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector);
 210 }
 211
 212 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 213                                 unsigned int hctx_idx)
 214 {
 215         struct nvme_dev *dev = data;
 216         struct nvme_queue *nvmeq = dev->queues[0];
 217
 218         WARN_ON(hctx_idx != 0);
 219         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 220         WARN_ON(nvmeq->tags);
 221
 222         hctx->driver_data = nvmeq;
 223         nvmeq->tags = &dev->admin_tagset.tags[0];
 224         return 0;
 225 }
 226
 227 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 228 {
 229         struct nvme_queue *nvmeq = hctx->driver_data;
 230
 231         nvmeq->tags = NULL;
 232 }
 233
 234 static int nvme_admin_init_request(void *data, struct request *req,
 235                                 unsigned int hctx_idx, unsigned int rq_idx,
 236                                 unsigned int numa_node)
 237 {
 238         struct nvme_dev *dev = data;
 239         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 240         struct nvme_queue *nvmeq = dev->queues[0];
 241
 242         BUG_ON(!nvmeq);
 243         iod->nvmeq = nvmeq;
 244         return 0;
 245 }
 246
 247 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 248                           unsigned int hctx_idx)
 249 {
 250         struct nvme_dev *dev = data;
 251         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 252
 253         if (!nvmeq->tags)
 254                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 255
 256         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 257         hctx->driver_data = nvmeq;
 258         return 0;
 259 }
 260
 261 static int nvme_init_request(void *data, struct request *req,
 262                                 unsigned int hctx_idx, unsigned int rq_idx,
 263                                 unsigned int numa_node)
 264 {
 265         struct nvme_dev *dev = data;
 266         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 267         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 268
 269         BUG_ON(!nvmeq);
 270         iod->nvmeq = nvmeq;
 271         return 0;
 272 }
 273
 274 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 275 {
 276         struct nvme_dev *dev = set->driver_data;
 277
 278         return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
 279 }
 280
 281 /**
 282  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 283  * @nvmeq: The queue to use
 284  * @cmd: The command to send
 285  *
 286  * Safe to use from interrupt context
 287  */
 288 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 289                                                 struct nvme_command *cmd)
 290 {
 291         u16 tail = nvmeq->sq_tail;
 292
 293         if (nvmeq->sq_cmds_io)
 294                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 295         else
 296                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 297
 298         if (++tail == nvmeq->q_depth)
 299                 tail = 0;
 300         writel(tail, nvmeq->q_db);
 301         nvmeq->sq_tail = tail;
 302 }
 303
 304 static __le64 **iod_list(struct request *req)
 305 {
 306         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 307         return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req));
 308 }
 309
 310 static int nvme_init_iod(struct request *rq, struct nvme_dev *dev)
 311 {
 312         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 313         int nseg = blk_rq_nr_phys_segments(rq);
 314         unsigned int size = blk_rq_payload_bytes(rq);
 315
 316         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 317                 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
 318                 if (!iod->sg)
 319                         return BLK_MQ_RQ_QUEUE_BUSY;
 320         } else {
 321                 iod->sg = iod->inline_sg;
 322         }
 323
 324         iod->aborted = 0;
 325         iod->npages = -1;
 326         iod->nents = 0;
 327         iod->length = size;
 328
 329         if (!(rq->rq_flags & RQF_DONTPREP)) {
 330                 rq->retries = 0;
 331                 rq->rq_flags |= RQF_DONTPREP;
 332         }
 333         return BLK_MQ_RQ_QUEUE_OK;
 334 }
 335
 336 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 337 {
 338         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 339         const int last_prp = dev->ctrl.page_size / 8 - 1;
 340         int i;
 341         __le64 **list = iod_list(req);
 342         dma_addr_t prp_dma = iod->first_dma;
 343
 344         if (iod->npages == 0)
 345                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 346         for (i = 0; i < iod->npages; i++) {
 347                 __le64 *prp_list = list[i];
 348                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 349                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 350                 prp_dma = next_prp_dma;
 351         }
 352
 353         if (iod->sg != iod->inline_sg)
 354                 kfree(iod->sg);
 355 }
 356
 357 #ifdef CONFIG_BLK_DEV_INTEGRITY
 358 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 359 {
 360         if (be32_to_cpu(pi->ref_tag) == v)
 361                 pi->ref_tag = cpu_to_be32(p);
 362 }
 363
 364 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 365 {
 366         if (be32_to_cpu(pi->ref_tag) == p)
 367                 pi->ref_tag = cpu_to_be32(v);
 368 }
 369
 370 /**
 371  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 372  *
 373  * The virtual start sector is the one that was originally submitted by the
 374  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 375  * start sector may be different. Remap protection information to match the
 376  * physical LBA on writes, and back to the original seed on reads.
 377  *
 378  * Type 0 and 3 do not have a ref tag, so no remapping required.
 379  */
 380 static void nvme_dif_remap(struct request *req,
 381                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 382 {
 383         struct nvme_ns *ns = req->rq_disk->private_data;
 384         struct bio_integrity_payload *bip;
 385         struct t10_pi_tuple *pi;
 386         void *p, *pmap;
 387         u32 i, nlb, ts, phys, virt;
 388
 389         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 390                 return;
 391
 392         bip = bio_integrity(req->bio);
 393         if (!bip)
 394                 return;
 395
 396         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 397
 398         p = pmap;
 399         virt = bip_get_seed(bip);
 400         phys = nvme_block_nr(ns, blk_rq_pos(req));
 401         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 402         ts = ns->disk->queue->integrity.tuple_size;
 403
 404         for (i = 0; i < nlb; i++, virt++, phys++) {
 405                 pi = (struct t10_pi_tuple *)p;
 406                 dif_swap(phys, virt, pi);
 407                 p += ts;
 408         }
 409         kunmap_atomic(pmap);
 410 }
 411 #else /* CONFIG_BLK_DEV_INTEGRITY */
 412 static void nvme_dif_remap(struct request *req,
 413                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 414 {
 415 }
 416 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 417 {
 418 }
 419 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 420 {
 421 }
 422 #endif
 423
 424 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req)
 425 {
 426         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 427         struct dma_pool *pool;
 428         int length = blk_rq_payload_bytes(req);
 429         struct scatterlist *sg = iod->sg;
 430         int dma_len = sg_dma_len(sg);
 431         u64 dma_addr = sg_dma_address(sg);
 432         u32 page_size = dev->ctrl.page_size;
 433         int offset = dma_addr & (page_size - 1);
 434         __le64 *prp_list;
 435         __le64 **list = iod_list(req);
 436         dma_addr_t prp_dma;
 437         int nprps, i;
 438
 439         length -= (page_size - offset);
 440         if (length <= 0)
 441                 return true;
 442
 443         dma_len -= (page_size - offset);
 444         if (dma_len) {
 445                 dma_addr += (page_size - offset);
 446         } else {
 447                 sg = sg_next(sg);
 448                 dma_addr = sg_dma_address(sg);
 449                 dma_len = sg_dma_len(sg);
 450         }
 451
 452         if (length <= page_size) {
 453                 iod->first_dma = dma_addr;
 454                 return true;
 455         }
 456
 457         nprps = DIV_ROUND_UP(length, page_size);
 458         if (nprps <= (256 / 8)) {
 459                 pool = dev->prp_small_pool;
 460                 iod->npages = 0;
 461         } else {
 462                 pool = dev->prp_page_pool;
 463                 iod->npages = 1;
 464         }
 465
 466         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 467         if (!prp_list) {
 468                 iod->first_dma = dma_addr;
 469                 iod->npages = -1;
 470                 return false;
 471         }
 472         list[0] = prp_list;
 473         iod->first_dma = prp_dma;
 474         i = 0;
 475         for (;;) {
 476                 if (i == page_size >> 3) {
 477                         __le64 *old_prp_list = prp_list;
 478                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 479                         if (!prp_list)
 480                                 return false;
 481                         list[iod->npages++] = prp_list;
 482                         prp_list[0] = old_prp_list[i - 1];
 483                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 484                         i = 1;
 485                 }
 486                 prp_list[i++] = cpu_to_le64(dma_addr);
 487                 dma_len -= page_size;
 488                 dma_addr += page_size;
 489                 length -= page_size;
 490                 if (length <= 0)
 491                         break;
 492                 if (dma_len > 0)
 493                         continue;
 494                 BUG_ON(dma_len < 0);
 495                 sg = sg_next(sg);
 496                 dma_addr = sg_dma_address(sg);
 497                 dma_len = sg_dma_len(sg);
 498         }
 499
 500         return true;
 501 }
 502
 503 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
 504                 struct nvme_command *cmnd)
 505 {
 506         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 507         struct request_queue *q = req->q;
 508         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 509                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 510         int ret = BLK_MQ_RQ_QUEUE_ERROR;
 511
 512         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 513         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 514         if (!iod->nents)
 515                 goto out;
 516
 517         ret = BLK_MQ_RQ_QUEUE_BUSY;
 518         if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
 519                                 DMA_ATTR_NO_WARN))
 520                 goto out;
 521
 522         if (!nvme_setup_prps(dev, req))
 523                 goto out_unmap;
 524
 525         ret = BLK_MQ_RQ_QUEUE_ERROR;
 526         if (blk_integrity_rq(req)) {
 527                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 528                         goto out_unmap;
 529
 530                 sg_init_table(&iod->meta_sg, 1);
 531                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 532                         goto out_unmap;
 533
 534                 if (rq_data_dir(req))
 535                         nvme_dif_remap(req, nvme_dif_prep);
 536
 537                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 538                         goto out_unmap;
 539         }
 540
 541         cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 542         cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma);
 543         if (blk_integrity_rq(req))
 544                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 545         return BLK_MQ_RQ_QUEUE_OK;
 546
 547 out_unmap:
 548         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 549 out:
 550         return ret;
 551 }
 552
 553 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 554 {
 555         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 556         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 557                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 558
 559         if (iod->nents) {
 560                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 561                 if (blk_integrity_rq(req)) {
 562                         if (!rq_data_dir(req))
 563                                 nvme_dif_remap(req, nvme_dif_complete);
 564                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 565                 }
 566         }
 567
 568         nvme_cleanup_cmd(req);
 569         nvme_free_iod(dev, req);
 570 }
 571
 572 /*
 573  * NOTE: ns is NULL when called on the admin queue.
 574  */
 575 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 576                          const struct blk_mq_queue_data *bd)
 577 {
 578         struct nvme_ns *ns = hctx->queue->queuedata;
 579         struct nvme_queue *nvmeq = hctx->driver_data;
 580         struct nvme_dev *dev = nvmeq->dev;
 581         struct request *req = bd->rq;
 582         struct nvme_command cmnd;
 583         int ret = BLK_MQ_RQ_QUEUE_OK;
 584
 585         /*
 586          * If formated with metadata, require the block layer provide a buffer
 587          * unless this namespace is formated such that the metadata can be
 588          * stripped/generated by the controller with PRACT=1.
 589          */
 590         if (ns && ns->ms && !blk_integrity_rq(req)) {
 591                 if (!(ns->pi_type && ns->ms == 8) &&
 592                     !blk_rq_is_passthrough(req)) {
 593                         blk_mq_end_request(req, -EFAULT);
 594                         return BLK_MQ_RQ_QUEUE_OK;
 595                 }
 596         }
 597
 598         ret = nvme_setup_cmd(ns, req, &cmnd);
 599         if (ret != BLK_MQ_RQ_QUEUE_OK)
 600                 return ret;
 601
 602         ret = nvme_init_iod(req, dev);
 603         if (ret != BLK_MQ_RQ_QUEUE_OK)
 604                 goto out_free_cmd;
 605
 606         if (blk_rq_nr_phys_segments(req))
 607                 ret = nvme_map_data(dev, req, &cmnd);
 608
 609         if (ret != BLK_MQ_RQ_QUEUE_OK)
 610                 goto out_cleanup_iod;
 611
 612         blk_mq_start_request(req);
 613
 614         spin_lock_irq(&nvmeq->q_lock);
 615         if (unlikely(nvmeq->cq_vector < 0)) {
 616                 if (ns && !test_bit(NVME_NS_DEAD, &ns->flags))
 617                         ret = BLK_MQ_RQ_QUEUE_BUSY;
 618                 else
 619                         ret = BLK_MQ_RQ_QUEUE_ERROR;
 620                 spin_unlock_irq(&nvmeq->q_lock);
 621                 goto out_cleanup_iod;
 622         }
 623         __nvme_submit_cmd(nvmeq, &cmnd);
 624         nvme_process_cq(nvmeq);
 625         spin_unlock_irq(&nvmeq->q_lock);
 626         return BLK_MQ_RQ_QUEUE_OK;
 627 out_cleanup_iod:
 628         nvme_free_iod(dev, req);
 629 out_free_cmd:
 630         nvme_cleanup_cmd(req);
 631         return ret;
 632 }
 633
 634 static void nvme_complete_rq(struct request *req)
 635 {
 636         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 637         struct nvme_dev *dev = iod->nvmeq->dev;
 638         int error = 0;
 639
 640         nvme_unmap_data(dev, req);
 641
 642         if (unlikely(req->errors)) {
 643                 if (nvme_req_needs_retry(req, req->errors)) {
 644                         req->retries++;
 645                         nvme_requeue_req(req);
 646                         return;
 647                 }
 648
 649                 if (blk_rq_is_passthrough(req))
 650                         error = req->errors;
 651                 else
 652                         error = nvme_error_status(req->errors);
 653         }
 654
 655         if (unlikely(iod->aborted)) {
 656                 dev_warn(dev->ctrl.device,
 657                         "completing aborted command with status: %04x\n",
 658                         req->errors);
 659         }
 660
 661         blk_mq_end_request(req, error);
 662 }
 663
 664 /* We read the CQE phase first to check if the rest of the entry is valid */
 665 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
 666                 u16 phase)
 667 {
 668         return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
 669 }
 670
 671 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
 672 {
 673         u16 head, phase;
 674
 675         head = nvmeq->cq_head;
 676         phase = nvmeq->cq_phase;
 677
 678         while (nvme_cqe_valid(nvmeq, head, phase)) {
 679                 struct nvme_completion cqe = nvmeq->cqes[head];
 680                 struct request *req;
 681
 682                 if (++head == nvmeq->q_depth) {
 683                         head = 0;
 684                         phase = !phase;
 685                 }
 686
 687                 if (tag && *tag == cqe.command_id)
 688                         *tag = -1;
 689
 690                 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
 691                         dev_warn(nvmeq->dev->ctrl.device,
 692                                 "invalid id %d completed on queue %d\n",
 693                                 cqe.command_id, le16_to_cpu(cqe.sq_id));
 694                         continue;
 695                 }
 696
 697                 /*
 698                  * AEN requests are special as they don't time out and can
 699                  * survive any kind of queue freeze and often don't respond to
 700                  * aborts.  We don't even bother to allocate a struct request
 701                  * for them but rather special case them here.
 702                  */
 703                 if (unlikely(nvmeq->qid == 0 &&
 704                                 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
 705                         nvme_complete_async_event(&nvmeq->dev->ctrl,
 706                                         cqe.status, &cqe.result);
 707                         continue;
 708                 }
 709
 710                 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
 711                 nvme_req(req)->result = cqe.result;
 712                 blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1);
 713         }
 714
 715         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 716                 return;
 717
 718         if (likely(nvmeq->cq_vector >= 0))
 719                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 720         nvmeq->cq_head = head;
 721         nvmeq->cq_phase = phase;
 722
 723         nvmeq->cqe_seen = 1;
 724 }
 725
 726 static void nvme_process_cq(struct nvme_queue *nvmeq)
 727 {
 728         __nvme_process_cq(nvmeq, NULL);
 729 }
 730
 731 static irqreturn_t nvme_irq(int irq, void *data)
 732 {
 733         irqreturn_t result;
 734         struct nvme_queue *nvmeq = data;
 735         spin_lock(&nvmeq->q_lock);
 736         nvme_process_cq(nvmeq);
 737         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 738         nvmeq->cqe_seen = 0;
 739         spin_unlock(&nvmeq->q_lock);
 740         return result;
 741 }
 742
 743 static irqreturn_t nvme_irq_check(int irq, void *data)
 744 {
 745         struct nvme_queue *nvmeq = data;
 746         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
 747                 return IRQ_WAKE_THREAD;
 748         return IRQ_NONE;
 749 }
 750
 751 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 752 {
 753         struct nvme_queue *nvmeq = hctx->driver_data;
 754
 755         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
 756                 spin_lock_irq(&nvmeq->q_lock);
 757                 __nvme_process_cq(nvmeq, &tag);
 758                 spin_unlock_irq(&nvmeq->q_lock);
 759
 760                 if (tag == -1)
 761                         return 1;
 762         }
 763
 764         return 0;
 765 }
 766
 767 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
 768 {
 769         struct nvme_dev *dev = to_nvme_dev(ctrl);
 770         struct nvme_queue *nvmeq = dev->queues[0];
 771         struct nvme_command c;
 772
 773         memset(&c, 0, sizeof(c));
 774         c.common.opcode = nvme_admin_async_event;
 775         c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
 776
 777         spin_lock_irq(&nvmeq->q_lock);
 778         __nvme_submit_cmd(nvmeq, &c);
 779         spin_unlock_irq(&nvmeq->q_lock);
 780 }
 781
 782 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 783 {
 784         struct nvme_command c;
 785
 786         memset(&c, 0, sizeof(c));
 787         c.delete_queue.opcode = opcode;
 788         c.delete_queue.qid = cpu_to_le16(id);
 789
 790         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 791 }
 792
 793 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 794                                                 struct nvme_queue *nvmeq)
 795 {
 796         struct nvme_command c;
 797         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 798
 799         /*
 800          * Note: we (ab)use the fact the the prp fields survive if no data
 801          * is attached to the request.
 802          */
 803         memset(&c, 0, sizeof(c));
 804         c.create_cq.opcode = nvme_admin_create_cq;
 805         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 806         c.create_cq.cqid = cpu_to_le16(qid);
 807         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 808         c.create_cq.cq_flags = cpu_to_le16(flags);
 809         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 810
 811         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 812 }
 813
 814 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 815                                                 struct nvme_queue *nvmeq)
 816 {
 817         struct nvme_command c;
 818         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 819
 820         /*
 821          * Note: we (ab)use the fact the the prp fields survive if no data
 822          * is attached to the request.
 823          */
 824         memset(&c, 0, sizeof(c));
 825         c.create_sq.opcode = nvme_admin_create_sq;
 826         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 827         c.create_sq.sqid = cpu_to_le16(qid);
 828         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 829         c.create_sq.sq_flags = cpu_to_le16(flags);
 830         c.create_sq.cqid = cpu_to_le16(qid);
 831
 832         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 833 }
 834
 835 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 836 {
 837         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 838 }
 839
 840 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 841 {
 842         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 843 }
 844
 845 static void abort_endio(struct request *req, int error)
 846 {
 847         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 848         struct nvme_queue *nvmeq = iod->nvmeq;
 849         u16 status = req->errors;
 850
 851         dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status);
 852         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
 853         blk_mq_free_request(req);
 854 }
 855
 856 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
 857 {
 858         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 859         struct nvme_queue *nvmeq = iod->nvmeq;
 860         struct nvme_dev *dev = nvmeq->dev;
 861         struct request *abort_req;
 862         struct nvme_command cmd;
 863
 864         /*
 865          * Shutdown immediately if controller times out while starting. The
 866          * reset work will see the pci device disabled when it gets the forced
 867          * cancellation error. All outstanding requests are completed on
 868          * shutdown, so we return BLK_EH_HANDLED.
 869          */
 870         if (dev->ctrl.state == NVME_CTRL_RESETTING) {
 871                 dev_warn(dev->ctrl.device,
 872                          "I/O %d QID %d timeout, disable controller\n",
 873                          req->tag, nvmeq->qid);
 874                 nvme_dev_disable(dev, false);
 875                 req->errors = NVME_SC_CANCELLED;
 876                 return BLK_EH_HANDLED;
 877         }
 878
 879         /*
 880          * Shutdown the controller immediately and schedule a reset if the
 881          * command was already aborted once before and still hasn't been
 882          * returned to the driver, or if this is the admin queue.
 883          */
 884         if (!nvmeq->qid || iod->aborted) {
 885                 dev_warn(dev->ctrl.device,
 886                          "I/O %d QID %d timeout, reset controller\n",
 887                          req->tag, nvmeq->qid);
 888                 nvme_dev_disable(dev, false);
 889                 nvme_reset(dev);
 890
 891                 /*
 892                  * Mark the request as handled, since the inline shutdown
 893                  * forces all outstanding requests to complete.
 894                  */
 895                 req->errors = NVME_SC_CANCELLED;
 896                 return BLK_EH_HANDLED;
 897         }
 898
 899         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
 900                 atomic_inc(&dev->ctrl.abort_limit);
 901                 return BLK_EH_RESET_TIMER;
 902         }
 903         iod->aborted = 1;
 904
 905         memset(&cmd, 0, sizeof(cmd));
 906         cmd.abort.opcode = nvme_admin_abort_cmd;
 907         cmd.abort.cid = req->tag;
 908         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
 909
 910         dev_warn(nvmeq->dev->ctrl.device,
 911                 "I/O %d QID %d timeout, aborting\n",
 912                  req->tag, nvmeq->qid);
 913
 914         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
 915                         BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
 916         if (IS_ERR(abort_req)) {
 917                 atomic_inc(&dev->ctrl.abort_limit);
 918                 return BLK_EH_RESET_TIMER;
 919         }
 920
 921         abort_req->timeout = ADMIN_TIMEOUT;
 922         abort_req->end_io_data = NULL;
 923         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
 924
 925         /*
 926          * The aborted req will be completed on receiving the abort req.
 927          * We enable the timer again. If hit twice, it'll cause a device reset,
 928          * as the device then is in a faulty state.
 929          */
 930         return BLK_EH_RESET_TIMER;
 931 }
 932
 933 static void nvme_free_queue(struct nvme_queue *nvmeq)
 934 {
 935         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 936                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 937         if (nvmeq->sq_cmds)
 938                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 939                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 940         kfree(nvmeq);
 941 }
 942
 943 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
 944 {
 945         int i;
 946
 947         for (i = dev->queue_count - 1; i >= lowest; i--) {
 948                 struct nvme_queue *nvmeq = dev->queues[i];
 949                 dev->queue_count--;
 950                 dev->queues[i] = NULL;
 951                 nvme_free_queue(nvmeq);
 952         }
 953 }
 954
 955 /**
 956  * nvme_suspend_queue - put queue into suspended state
 957  * @nvmeq - queue to suspend
 958  */
 959 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
 960 {
 961         int vector;
 962
 963         spin_lock_irq(&nvmeq->q_lock);
 964         if (nvmeq->cq_vector == -1) {
 965                 spin_unlock_irq(&nvmeq->q_lock);
 966                 return 1;
 967         }
 968         vector = nvmeq_irq(nvmeq);
 969         nvmeq->dev->online_queues--;
 970         nvmeq->cq_vector = -1;
 971         spin_unlock_irq(&nvmeq->q_lock);
 972
 973         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
 974                 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
 975
 976         free_irq(vector, nvmeq);
 977
 978         return 0;
 979 }
 980
 981 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
 982 {
 983         struct nvme_queue *nvmeq = dev->queues[0];
 984
 985         if (!nvmeq)
 986                 return;
 987         if (nvme_suspend_queue(nvmeq))
 988                 return;
 989
 990         if (shutdown)
 991                 nvme_shutdown_ctrl(&dev->ctrl);
 992         else
 993                 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
 994                                                 dev->bar + NVME_REG_CAP));
 995
 996         spin_lock_irq(&nvmeq->q_lock);
 997         nvme_process_cq(nvmeq);
 998         spin_unlock_irq(&nvmeq->q_lock);
 999 }
1000
1001 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1002                                 int entry_size)
1003 {
1004         int q_depth = dev->q_depth;
1005         unsigned q_size_aligned = roundup(q_depth * entry_size,
1006                                           dev->ctrl.page_size);
1007
1008         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1009                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1010                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1011                 q_depth = div_u64(mem_per_q, entry_size);
1012
1013                 /*
1014                  * Ensure the reduced q_depth is above some threshold where it
1015                  * would be better to map queues in system memory with the
1016                  * original depth
1017                  */
1018                 if (q_depth < 64)
1019                         return -ENOMEM;
1020         }
1021
1022         return q_depth;
1023 }
1024
1025 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1026                                 int qid, int depth)
1027 {
1028         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1029                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1030                                                       dev->ctrl.page_size);
1031                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1032                 nvmeq->sq_cmds_io = dev->cmb + offset;
1033         } else {
1034                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1035                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1036                 if (!nvmeq->sq_cmds)
1037                         return -ENOMEM;
1038         }
1039
1040         return 0;
1041 }
1042
1043 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1044                                                         int depth)
1045 {
1046         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1047         if (!nvmeq)
1048                 return NULL;
1049
1050         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1051                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1052         if (!nvmeq->cqes)
1053                 goto free_nvmeq;
1054
1055         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1056                 goto free_cqdma;
1057
1058         nvmeq->q_dmadev = dev->dev;
1059         nvmeq->dev = dev;
1060         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1061                         dev->ctrl.instance, qid);
1062         spin_lock_init(&nvmeq->q_lock);
1063         nvmeq->cq_head = 0;
1064         nvmeq->cq_phase = 1;
1065         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1066         nvmeq->q_depth = depth;
1067         nvmeq->qid = qid;
1068         nvmeq->cq_vector = -1;
1069         dev->queues[qid] = nvmeq;
1070         dev->queue_count++;
1071
1072         return nvmeq;
1073
1074  free_cqdma:
1075         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1076                                                         nvmeq->cq_dma_addr);
1077  free_nvmeq:
1078         kfree(nvmeq);
1079         return NULL;
1080 }
1081
1082 static int queue_request_irq(struct nvme_queue *nvmeq)
1083 {
1084         if (use_threaded_interrupts)
1085                 return request_threaded_irq(nvmeq_irq(nvmeq), nvme_irq_check,
1086                                 nvme_irq, IRQF_SHARED, nvmeq->irqname, nvmeq);
1087         else
1088                 return request_irq(nvmeq_irq(nvmeq), nvme_irq, IRQF_SHARED,
1089                                 nvmeq->irqname, nvmeq);
1090 }
1091
1092 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1093 {
1094         struct nvme_dev *dev = nvmeq->dev;
1095
1096         spin_lock_irq(&nvmeq->q_lock);
1097         nvmeq->sq_tail = 0;
1098         nvmeq->cq_head = 0;
1099         nvmeq->cq_phase = 1;
1100         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1101         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1102         dev->online_queues++;
1103         spin_unlock_irq(&nvmeq->q_lock);
1104 }
1105
1106 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1107 {
1108         struct nvme_dev *dev = nvmeq->dev;
1109         int result;
1110
1111         nvmeq->cq_vector = qid - 1;
1112         result = adapter_alloc_cq(dev, qid, nvmeq);
1113         if (result < 0)
1114                 return result;
1115
1116         result = adapter_alloc_sq(dev, qid, nvmeq);
1117         if (result < 0)
1118                 goto release_cq;
1119
1120         result = queue_request_irq(nvmeq);
1121         if (result < 0)
1122                 goto release_sq;
1123
1124         nvme_init_queue(nvmeq, qid);
1125         return result;
1126
1127  release_sq:
1128         adapter_delete_sq(dev, qid);
1129  release_cq:
1130         adapter_delete_cq(dev, qid);
1131         return result;
1132 }
1133
1134 static struct blk_mq_ops nvme_mq_admin_ops = {
1135         .queue_rq       = nvme_queue_rq,
1136         .complete       = nvme_complete_rq,
1137         .init_hctx      = nvme_admin_init_hctx,
1138         .exit_hctx      = nvme_admin_exit_hctx,
1139         .init_request   = nvme_admin_init_request,
1140         .timeout        = nvme_timeout,
1141 };
1142
1143 static struct blk_mq_ops nvme_mq_ops = {
1144         .queue_rq       = nvme_queue_rq,
1145         .complete       = nvme_complete_rq,
1146         .init_hctx      = nvme_init_hctx,
1147         .init_request   = nvme_init_request,
1148         .map_queues     = nvme_pci_map_queues,
1149         .timeout        = nvme_timeout,
1150         .poll           = nvme_poll,
1151 };
1152
1153 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1154 {
1155         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1156                 /*
1157                  * If the controller was reset during removal, it's possible
1158                  * user requests may be waiting on a stopped queue. Start the
1159                  * queue to flush these to completion.
1160                  */
1161                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1162                 blk_cleanup_queue(dev->ctrl.admin_q);
1163                 blk_mq_free_tag_set(&dev->admin_tagset);
1164         }
1165 }
1166
1167 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1168 {
1169         if (!dev->ctrl.admin_q) {
1170                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1171                 dev->admin_tagset.nr_hw_queues = 1;
1172
1173                 /*
1174                  * Subtract one to leave an empty queue entry for 'Full Queue'
1175                  * condition. See NVM-Express 1.2 specification, section 4.1.2.
1176                  */
1177                 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1178                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1179                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1180                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1181                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1182                 dev->admin_tagset.driver_data = dev;
1183
1184                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1185                         return -ENOMEM;
1186
1187                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1188                 if (IS_ERR(dev->ctrl.admin_q)) {
1189                         blk_mq_free_tag_set(&dev->admin_tagset);
1190                         return -ENOMEM;
1191                 }
1192                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1193                         nvme_dev_remove_admin(dev);
1194                         dev->ctrl.admin_q = NULL;
1195                         return -ENODEV;
1196                 }
1197         } else
1198                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1199
1200         return 0;
1201 }
1202
1203 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1204 {
1205         int result;
1206         u32 aqa;
1207         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1208         struct nvme_queue *nvmeq;
1209
1210         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1211                                                 NVME_CAP_NSSRC(cap) : 0;
1212
1213         if (dev->subsystem &&
1214             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1215                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1216
1217         result = nvme_disable_ctrl(&dev->ctrl, cap);
1218         if (result < 0)
1219                 return result;
1220
1221         nvmeq = dev->queues[0];
1222         if (!nvmeq) {
1223                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1224                 if (!nvmeq)
1225                         return -ENOMEM;
1226         }
1227
1228         aqa = nvmeq->q_depth - 1;
1229         aqa |= aqa << 16;
1230
1231         writel(aqa, dev->bar + NVME_REG_AQA);
1232         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1233         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1234
1235         result = nvme_enable_ctrl(&dev->ctrl, cap);
1236         if (result)
1237                 return result;
1238
1239         nvmeq->cq_vector = 0;
1240         result = queue_request_irq(nvmeq);
1241         if (result) {
1242                 nvmeq->cq_vector = -1;
1243                 return result;
1244         }
1245
1246         return result;
1247 }
1248
1249 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1250 {
1251
1252         /* If true, indicates loss of adapter communication, possibly by a
1253          * NVMe Subsystem reset.
1254          */
1255         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1256
1257         /* If there is a reset ongoing, we shouldn't reset again. */
1258         if (work_busy(&dev->reset_work))
1259                 return false;
1260
1261         /* We shouldn't reset unless the controller is on fatal error state
1262          * _or_ if we lost the communication with it.
1263          */
1264         if (!(csts & NVME_CSTS_CFS) && !nssro)
1265                 return false;
1266
1267         /* If PCI error recovery process is happening, we cannot reset or
1268          * the recovery mechanism will surely fail.
1269          */
1270         if (pci_channel_offline(to_pci_dev(dev->dev)))
1271                 return false;
1272
1273         return true;
1274 }
1275
1276 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1277 {
1278         /* Read a config register to help see what died. */
1279         u16 pci_status;
1280         int result;
1281
1282         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1283                                       &pci_status);
1284         if (result == PCIBIOS_SUCCESSFUL)
1285                 dev_warn(dev->dev,
1286                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1287                          csts, pci_status);
1288         else
1289                 dev_warn(dev->dev,
1290                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1291                          csts, result);
1292 }
1293
1294 static void nvme_watchdog_timer(unsigned long data)
1295 {
1296         struct nvme_dev *dev = (struct nvme_dev *)data;
1297         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1298
1299         /* Skip controllers under certain specific conditions. */
1300         if (nvme_should_reset(dev, csts)) {
1301                 if (!nvme_reset(dev))
1302                         nvme_warn_reset(dev, csts);
1303                 return;
1304         }
1305
1306         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1307 }
1308
1309 static int nvme_create_io_queues(struct nvme_dev *dev)
1310 {
1311         unsigned i, max;
1312         int ret = 0;
1313
1314         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1315                 if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1316                         ret = -ENOMEM;
1317                         break;
1318                 }
1319         }
1320
1321         max = min(dev->max_qid, dev->queue_count - 1);
1322         for (i = dev->online_queues; i <= max; i++) {
1323                 ret = nvme_create_queue(dev->queues[i], i);
1324                 if (ret)
1325                         break;
1326         }
1327
1328         /*
1329          * Ignore failing Create SQ/CQ commands, we can continue with less
1330          * than the desired aount of queues, and even a controller without
1331          * I/O queues an still be used to issue admin commands.  This might
1332          * be useful to upgrade a buggy firmware for example.
1333          */
1334         return ret >= 0 ? 0 : ret;
1335 }
1336
1337 static ssize_t nvme_cmb_show(struct device *dev,
1338                              struct device_attribute *attr,
1339                              char *buf)
1340 {
1341         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1342
1343         return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1344                        ndev->cmbloc, ndev->cmbsz);
1345 }
1346 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1347
1348 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1349 {
1350         u64 szu, size, offset;
1351         resource_size_t bar_size;
1352         struct pci_dev *pdev = to_pci_dev(dev->dev);
1353         void __iomem *cmb;
1354         dma_addr_t dma_addr;
1355
1356         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1357         if (!(NVME_CMB_SZ(dev->cmbsz)))
1358                 return NULL;
1359         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1360
1361         if (!use_cmb_sqes)
1362                 return NULL;
1363
1364         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1365         size = szu * NVME_CMB_SZ(dev->cmbsz);
1366         offset = szu * NVME_CMB_OFST(dev->cmbloc);
1367         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc));
1368
1369         if (offset > bar_size)
1370                 return NULL;
1371
1372         /*
1373          * Controllers may support a CMB size larger than their BAR,
1374          * for example, due to being behind a bridge. Reduce the CMB to
1375          * the reported size of the BAR
1376          */
1377         if (size > bar_size - offset)
1378                 size = bar_size - offset;
1379
1380         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset;
1381         cmb = ioremap_wc(dma_addr, size);
1382         if (!cmb)
1383                 return NULL;
1384
1385         dev->cmb_dma_addr = dma_addr;
1386         dev->cmb_size = size;
1387         return cmb;
1388 }
1389
1390 static inline void nvme_release_cmb(struct nvme_dev *dev)
1391 {
1392         if (dev->cmb) {
1393                 iounmap(dev->cmb);
1394                 dev->cmb = NULL;
1395         }
1396 }
1397
1398 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1399 {
1400         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1401 }
1402
1403 static int nvme_setup_io_queues(struct nvme_dev *dev)
1404 {
1405         struct nvme_queue *adminq = dev->queues[0];
1406         struct pci_dev *pdev = to_pci_dev(dev->dev);
1407         int result, nr_io_queues, size;
1408
1409         nr_io_queues = num_online_cpus();
1410         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1411         if (result < 0)
1412                 return result;
1413
1414         if (nr_io_queues == 0)
1415                 return 0;
1416
1417         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1418                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1419                                 sizeof(struct nvme_command));
1420                 if (result > 0)
1421                         dev->q_depth = result;
1422                 else
1423                         nvme_release_cmb(dev);
1424         }
1425
1426         size = db_bar_size(dev, nr_io_queues);
1427         if (size > 8192) {
1428                 iounmap(dev->bar);
1429                 do {
1430                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1431                         if (dev->bar)
1432                                 break;
1433                         if (!--nr_io_queues)
1434                                 return -ENOMEM;
1435                         size = db_bar_size(dev, nr_io_queues);
1436                 } while (1);
1437                 dev->dbs = dev->bar + 4096;
1438                 adminq->q_db = dev->dbs;
1439         }
1440
1441         /* Deregister the admin queue's interrupt */
1442         free_irq(pci_irq_vector(pdev, 0), adminq);
1443
1444         /*
1445          * If we enable msix early due to not intx, disable it again before
1446          * setting up the full range we need.
1447          */
1448         pci_free_irq_vectors(pdev);
1449         nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1450                         PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1451         if (nr_io_queues <= 0)
1452                 return -EIO;
1453         dev->max_qid = nr_io_queues;
1454
1455         /*
1456          * Should investigate if there's a performance win from allocating
1457          * more queues than interrupt vectors; it might allow the submission
1458          * path to scale better, even if the receive path is limited by the
1459          * number of interrupts.
1460          */
1461
1462         result = queue_request_irq(adminq);
1463         if (result) {
1464                 adminq->cq_vector = -1;
1465                 return result;
1466         }
1467         return nvme_create_io_queues(dev);
1468 }
1469
1470 static void nvme_del_queue_end(struct request *req, int error)
1471 {
1472         struct nvme_queue *nvmeq = req->end_io_data;
1473
1474         blk_mq_free_request(req);
1475         complete(&nvmeq->dev->ioq_wait);
1476 }
1477
1478 static void nvme_del_cq_end(struct request *req, int error)
1479 {
1480         struct nvme_queue *nvmeq = req->end_io_data;
1481
1482         if (!error) {
1483                 unsigned long flags;
1484
1485                 /*
1486                  * We might be called with the AQ q_lock held
1487                  * and the I/O queue q_lock should always
1488                  * nest inside the AQ one.
1489                  */
1490                 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1491                                         SINGLE_DEPTH_NESTING);
1492                 nvme_process_cq(nvmeq);
1493                 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1494         }
1495
1496         nvme_del_queue_end(req, error);
1497 }
1498
1499 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1500 {
1501         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1502         struct request *req;
1503         struct nvme_command cmd;
1504
1505         memset(&cmd, 0, sizeof(cmd));
1506         cmd.delete_queue.opcode = opcode;
1507         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1508
1509         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1510         if (IS_ERR(req))
1511                 return PTR_ERR(req);
1512
1513         req->timeout = ADMIN_TIMEOUT;
1514         req->end_io_data = nvmeq;
1515
1516         blk_execute_rq_nowait(q, NULL, req, false,
1517                         opcode == nvme_admin_delete_cq ?
1518                                 nvme_del_cq_end : nvme_del_queue_end);
1519         return 0;
1520 }
1521
1522 static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
1523 {
1524         int pass;
1525         unsigned long timeout;
1526         u8 opcode = nvme_admin_delete_sq;
1527
1528         for (pass = 0; pass < 2; pass++) {
1529                 int sent = 0, i = queues;
1530
1531                 reinit_completion(&dev->ioq_wait);
1532  retry:
1533                 timeout = ADMIN_TIMEOUT;
1534                 for (; i > 0; i--, sent++)
1535                         if (nvme_delete_queue(dev->queues[i], opcode))
1536                                 break;
1537
1538                 while (sent--) {
1539                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1540                         if (timeout == 0)
1541                                 return;
1542                         if (i)
1543                                 goto retry;
1544                 }
1545                 opcode = nvme_admin_delete_cq;
1546         }
1547 }
1548
1549 /*
1550  * Return: error value if an error occurred setting up the queues or calling
1551  * Identify Device.  0 if these succeeded, even if adding some of the
1552  * namespaces failed.  At the moment, these failures are silent.  TBD which
1553  * failures should be reported.
1554  */
1555 static int nvme_dev_add(struct nvme_dev *dev)
1556 {
1557         if (!dev->ctrl.tagset) {
1558                 dev->tagset.ops = &nvme_mq_ops;
1559                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1560                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1561                 dev->tagset.numa_node = dev_to_node(dev->dev);
1562                 dev->tagset.queue_depth =
1563                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1564                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1565                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1566                 dev->tagset.driver_data = dev;
1567
1568                 if (blk_mq_alloc_tag_set(&dev->tagset))
1569                         return 0;
1570                 dev->ctrl.tagset = &dev->tagset;
1571         } else {
1572                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1573
1574                 /* Free previously allocated queues that are no longer usable */
1575                 nvme_free_queues(dev, dev->online_queues);
1576         }
1577
1578         return 0;
1579 }
1580
1581 static int nvme_pci_enable(struct nvme_dev *dev)
1582 {
1583         u64 cap;
1584         int result = -ENOMEM;
1585         struct pci_dev *pdev = to_pci_dev(dev->dev);
1586
1587         if (pci_enable_device_mem(pdev))
1588                 return result;
1589
1590         pci_set_master(pdev);
1591
1592         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1593             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1594                 goto disable;
1595
1596         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1597                 result = -ENODEV;
1598                 goto disable;
1599         }
1600
1601         /*
1602          * Some devices and/or platforms don't advertise or work with INTx
1603          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1604          * adjust this later.
1605          */
1606         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1607         if (result < 0)
1608                 return result;
1609
1610         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1611
1612         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1613         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1614         dev->dbs = dev->bar + 4096;
1615
1616         /*
1617          * Temporary fix for the Apple controller found in the MacBook8,1 and
1618          * some MacBook7,1 to avoid controller resets and data loss.
1619          */
1620         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1621                 dev->q_depth = 2;
1622                 dev_warn(dev->dev, "detected Apple NVMe controller, set "
1623                         "queue depth=%u to work around controller resets\n",
1624                         dev->q_depth);
1625         }
1626
1627         /*
1628          * CMBs can currently only exist on >=1.2 PCIe devices. We only
1629          * populate sysfs if a CMB is implemented. Note that we add the
1630          * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1631          * it on exit. Since nvme_dev_attrs_group has no name we can pass
1632          * NULL as final argument to sysfs_add_file_to_group.
1633          */
1634
1635         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
1636                 dev->cmb = nvme_map_cmb(dev);
1637
1638                 if (dev->cmbsz) {
1639                         if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1640                                                     &dev_attr_cmb.attr, NULL))
1641                                 dev_warn(dev->dev,
1642                                          "failed to add sysfs attribute for CMB\n");
1643                 }
1644         }
1645
1646         pci_enable_pcie_error_reporting(pdev);
1647         pci_save_state(pdev);
1648         return 0;
1649
1650  disable:
1651         pci_disable_device(pdev);
1652         return result;
1653 }
1654
1655 static void nvme_dev_unmap(struct nvme_dev *dev)
1656 {
1657         if (dev->bar)
1658                 iounmap(dev->bar);
1659         pci_release_mem_regions(to_pci_dev(dev->dev));
1660 }
1661
1662 static void nvme_pci_disable(struct nvme_dev *dev)
1663 {
1664         struct pci_dev *pdev = to_pci_dev(dev->dev);
1665
1666         pci_free_irq_vectors(pdev);
1667
1668         if (pci_is_enabled(pdev)) {
1669                 pci_disable_pcie_error_reporting(pdev);
1670                 pci_disable_device(pdev);
1671         }
1672 }
1673
1674 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1675 {
1676         int i, queues;
1677         u32 csts = -1;
1678
1679         del_timer_sync(&dev->watchdog_timer);
1680
1681         mutex_lock(&dev->shutdown_lock);
1682         if (pci_is_enabled(to_pci_dev(dev->dev))) {
1683                 nvme_stop_queues(&dev->ctrl);
1684                 csts = readl(dev->bar + NVME_REG_CSTS);
1685         }
1686
1687         queues = dev->online_queues - 1;
1688         for (i = dev->queue_count - 1; i > 0; i--)
1689                 nvme_suspend_queue(dev->queues[i]);
1690
1691         if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
1692                 /* A device might become IO incapable very soon during
1693                  * probe, before the admin queue is configured. Thus,
1694                  * queue_count can be 0 here.
1695                  */
1696                 if (dev->queue_count)
1697                         nvme_suspend_queue(dev->queues[0]);
1698         } else {
1699                 nvme_disable_io_queues(dev, queues);
1700                 nvme_disable_admin_queue(dev, shutdown);
1701         }
1702         nvme_pci_disable(dev);
1703
1704         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
1705         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
1706         mutex_unlock(&dev->shutdown_lock);
1707 }
1708
1709 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1710 {
1711         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1712                                                 PAGE_SIZE, PAGE_SIZE, 0);
1713         if (!dev->prp_page_pool)
1714                 return -ENOMEM;
1715
1716         /* Optimisation for I/Os between 4k and 128k */
1717         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1718                                                 256, 256, 0);
1719         if (!dev->prp_small_pool) {
1720                 dma_pool_destroy(dev->prp_page_pool);
1721                 return -ENOMEM;
1722         }
1723         return 0;
1724 }
1725
1726 static void nvme_release_prp_pools(struct nvme_dev *dev)
1727 {
1728         dma_pool_destroy(dev->prp_page_pool);
1729         dma_pool_destroy(dev->prp_small_pool);
1730 }
1731
1732 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1733 {
1734         struct nvme_dev *dev = to_nvme_dev(ctrl);
1735
1736         put_device(dev->dev);
1737         if (dev->tagset.tags)
1738                 blk_mq_free_tag_set(&dev->tagset);
1739         if (dev->ctrl.admin_q)
1740                 blk_put_queue(dev->ctrl.admin_q);
1741         kfree(dev->queues);
1742         kfree(dev->ctrl.opal_dev);
1743         kfree(dev);
1744 }
1745
1746 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
1747 {
1748         dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
1749
1750         kref_get(&dev->ctrl.kref);
1751         nvme_dev_disable(dev, false);
1752         if (!schedule_work(&dev->remove_work))
1753                 nvme_put_ctrl(&dev->ctrl);
1754 }
1755
1756 static void nvme_reset_work(struct work_struct *work)
1757 {
1758         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1759         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
1760         int result = -ENODEV;
1761
1762         if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING))
1763                 goto out;
1764
1765         /*
1766          * If we're called to reset a live controller first shut it down before
1767          * moving on.
1768          */
1769         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
1770                 nvme_dev_disable(dev, false);
1771
1772         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
1773                 goto out;
1774
1775         result = nvme_pci_enable(dev);
1776         if (result)
1777                 goto out;
1778
1779         result = nvme_configure_admin_queue(dev);
1780         if (result)
1781                 goto out;
1782
1783         nvme_init_queue(dev->queues[0], 0);
1784         result = nvme_alloc_admin_tags(dev);
1785         if (result)
1786                 goto out;
1787
1788         result = nvme_init_identify(&dev->ctrl);
1789         if (result)
1790                 goto out;
1791
1792         if ((dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) && !dev->ctrl.opal_dev) {
1793                 dev->ctrl.opal_dev =
1794                         init_opal_dev(&dev->ctrl, &nvme_sec_submit);
1795         }
1796
1797         if (was_suspend)
1798                 opal_unlock_from_suspend(dev->ctrl.opal_dev);
1799
1800         result = nvme_setup_io_queues(dev);
1801         if (result)
1802                 goto out;
1803
1804         /*
1805          * A controller that can not execute IO typically requires user
1806          * intervention to correct. For such degraded controllers, the driver
1807          * should not submit commands the user did not request, so skip
1808          * registering for asynchronous event notification on this condition.
1809          */
1810         if (dev->online_queues > 1)
1811                 nvme_queue_async_events(&dev->ctrl);
1812
1813         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1814
1815         /*
1816          * Keep the controller around but remove all namespaces if we don't have
1817          * any working I/O queue.
1818          */
1819         if (dev->online_queues < 2) {
1820                 dev_warn(dev->ctrl.device, "IO queues not created\n");
1821                 nvme_kill_queues(&dev->ctrl);
1822                 nvme_remove_namespaces(&dev->ctrl);
1823         } else {
1824                 nvme_start_queues(&dev->ctrl);
1825                 nvme_dev_add(dev);
1826         }
1827
1828         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
1829                 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
1830                 goto out;
1831         }
1832
1833         if (dev->online_queues > 1)
1834                 nvme_queue_scan(&dev->ctrl);
1835         return;
1836
1837  out:
1838         nvme_remove_dead_ctrl(dev, result);
1839 }
1840
1841 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1842 {
1843         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1844         struct pci_dev *pdev = to_pci_dev(dev->dev);
1845
1846         nvme_kill_queues(&dev->ctrl);
1847         if (pci_get_drvdata(pdev))
1848                 device_release_driver(&pdev->dev);
1849         nvme_put_ctrl(&dev->ctrl);
1850 }
1851
1852 static int nvme_reset(struct nvme_dev *dev)
1853 {
1854         if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
1855                 return -ENODEV;
1856         if (work_busy(&dev->reset_work))
1857                 return -ENODEV;
1858         if (!queue_work(nvme_workq, &dev->reset_work))
1859                 return -EBUSY;
1860         return 0;
1861 }
1862
1863 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
1864 {
1865         *val = readl(to_nvme_dev(ctrl)->bar + off);
1866         return 0;
1867 }
1868
1869 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
1870 {
1871         writel(val, to_nvme_dev(ctrl)->bar + off);
1872         return 0;
1873 }
1874
1875 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
1876 {
1877         *val = readq(to_nvme_dev(ctrl)->bar + off);
1878         return 0;
1879 }
1880
1881 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
1882 {
1883         struct nvme_dev *dev = to_nvme_dev(ctrl);
1884         int ret = nvme_reset(dev);
1885
1886         if (!ret)
1887                 flush_work(&dev->reset_work);
1888         return ret;
1889 }
1890
1891 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1892         .name                   = "pcie",
1893         .module                 = THIS_MODULE,
1894         .reg_read32             = nvme_pci_reg_read32,
1895         .reg_write32            = nvme_pci_reg_write32,
1896         .reg_read64             = nvme_pci_reg_read64,
1897         .reset_ctrl             = nvme_pci_reset_ctrl,
1898         .free_ctrl              = nvme_pci_free_ctrl,
1899         .submit_async_event     = nvme_pci_submit_async_event,
1900 };
1901
1902 static int nvme_dev_map(struct nvme_dev *dev)
1903 {
1904         struct pci_dev *pdev = to_pci_dev(dev->dev);
1905
1906         if (pci_request_mem_regions(pdev, "nvme"))
1907                 return -ENODEV;
1908
1909         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1910         if (!dev->bar)
1911                 goto release;
1912
1913         return 0;
1914   release:
1915         pci_release_mem_regions(pdev);
1916         return -ENODEV;
1917 }
1918
1919 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1920 {
1921         int node, result = -ENOMEM;
1922         struct nvme_dev *dev;
1923
1924         node = dev_to_node(&pdev->dev);
1925         if (node == NUMA_NO_NODE)
1926                 set_dev_node(&pdev->dev, first_memory_node);
1927
1928         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
1929         if (!dev)
1930                 return -ENOMEM;
1931         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
1932                                                         GFP_KERNEL, node);
1933         if (!dev->queues)
1934                 goto free;
1935
1936         dev->dev = get_device(&pdev->dev);
1937         pci_set_drvdata(pdev, dev);
1938
1939         result = nvme_dev_map(dev);
1940         if (result)
1941                 goto free;
1942
1943         INIT_WORK(&dev->reset_work, nvme_reset_work);
1944         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
1945         setup_timer(&dev->watchdog_timer, nvme_watchdog_timer,
1946                 (unsigned long)dev);
1947         mutex_init(&dev->shutdown_lock);
1948         init_completion(&dev->ioq_wait);
1949
1950         result = nvme_setup_prp_pools(dev);
1951         if (result)
1952                 goto put_pci;
1953
1954         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
1955                         id->driver_data);
1956         if (result)
1957                 goto release_pools;
1958
1959         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
1960
1961         queue_work(nvme_workq, &dev->reset_work);
1962         return 0;
1963
1964  release_pools:
1965         nvme_release_prp_pools(dev);
1966  put_pci:
1967         put_device(dev->dev);
1968         nvme_dev_unmap(dev);
1969  free:
1970         kfree(dev->queues);
1971         kfree(dev);
1972         return result;
1973 }
1974
1975 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
1976 {
1977         struct nvme_dev *dev = pci_get_drvdata(pdev);
1978
1979         if (prepare)
1980                 nvme_dev_disable(dev, false);
1981         else
1982                 nvme_reset(dev);
1983 }
1984
1985 static void nvme_shutdown(struct pci_dev *pdev)
1986 {
1987         struct nvme_dev *dev = pci_get_drvdata(pdev);
1988         nvme_dev_disable(dev, true);
1989 }
1990
1991 /*
1992  * The driver's remove may be called on a device in a partially initialized
1993  * state. This function must not have any dependencies on the device state in
1994  * order to proceed.
1995  */
1996 static void nvme_remove(struct pci_dev *pdev)
1997 {
1998         struct nvme_dev *dev = pci_get_drvdata(pdev);
1999
2000         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2001
2002         pci_set_drvdata(pdev, NULL);
2003
2004         if (!pci_device_is_present(pdev))
2005                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2006
2007         flush_work(&dev->reset_work);
2008         nvme_uninit_ctrl(&dev->ctrl);
2009         nvme_dev_disable(dev, true);
2010         nvme_dev_remove_admin(dev);
2011         nvme_free_queues(dev, 0);
2012         nvme_release_cmb(dev);
2013         nvme_release_prp_pools(dev);
2014         nvme_dev_unmap(dev);
2015         nvme_put_ctrl(&dev->ctrl);
2016 }
2017
2018 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2019 {
2020         int ret = 0;
2021
2022         if (numvfs == 0) {
2023                 if (pci_vfs_assigned(pdev)) {
2024                         dev_warn(&pdev->dev,
2025                                 "Cannot disable SR-IOV VFs while assigned\n");
2026                         return -EPERM;
2027                 }
2028                 pci_disable_sriov(pdev);
2029                 return 0;
2030         }
2031
2032         ret = pci_enable_sriov(pdev, numvfs);
2033         return ret ? ret : numvfs;
2034 }
2035
2036 #ifdef CONFIG_PM_SLEEP
2037 static int nvme_suspend(struct device *dev)
2038 {
2039         struct pci_dev *pdev = to_pci_dev(dev);
2040         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2041
2042         nvme_dev_disable(ndev, true);
2043         return 0;
2044 }
2045
2046 static int nvme_resume(struct device *dev)
2047 {
2048         struct pci_dev *pdev = to_pci_dev(dev);
2049         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2050
2051         nvme_reset(ndev);
2052         return 0;
2053 }
2054 #endif
2055
2056 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2057
2058 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2059                                                 pci_channel_state_t state)
2060 {
2061         struct nvme_dev *dev = pci_get_drvdata(pdev);
2062
2063         /*
2064          * A frozen channel requires a reset. When detected, this method will
2065          * shutdown the controller to quiesce. The controller will be restarted
2066          * after the slot reset through driver's slot_reset callback.
2067          */
2068         switch (state) {
2069         case pci_channel_io_normal:
2070                 return PCI_ERS_RESULT_CAN_RECOVER;
2071         case pci_channel_io_frozen:
2072                 dev_warn(dev->ctrl.device,
2073                         "frozen state error detected, reset controller\n");
2074                 nvme_dev_disable(dev, false);
2075                 return PCI_ERS_RESULT_NEED_RESET;
2076         case pci_channel_io_perm_failure:
2077                 dev_warn(dev->ctrl.device,
2078                         "failure state error detected, request disconnect\n");
2079                 return PCI_ERS_RESULT_DISCONNECT;
2080         }
2081         return PCI_ERS_RESULT_NEED_RESET;
2082 }
2083
2084 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2085 {
2086         struct nvme_dev *dev = pci_get_drvdata(pdev);
2087
2088         dev_info(dev->ctrl.device, "restart after slot reset\n");
2089         pci_restore_state(pdev);
2090         nvme_reset(dev);
2091         return PCI_ERS_RESULT_RECOVERED;
2092 }
2093
2094 static void nvme_error_resume(struct pci_dev *pdev)
2095 {
2096         pci_cleanup_aer_uncorrect_error_status(pdev);
2097 }
2098
2099 static const struct pci_error_handlers nvme_err_handler = {
2100         .error_detected = nvme_error_detected,
2101         .slot_reset     = nvme_slot_reset,
2102         .resume         = nvme_error_resume,
2103         .reset_notify   = nvme_reset_notify,
2104 };
2105
2106 static const struct pci_device_id nvme_id_table[] = {
2107         { PCI_VDEVICE(INTEL, 0x0953),
2108                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2109                                 NVME_QUIRK_DISCARD_ZEROES, },
2110         { PCI_VDEVICE(INTEL, 0x0a53),
2111                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2112                                 NVME_QUIRK_DISCARD_ZEROES, },
2113         { PCI_VDEVICE(INTEL, 0x0a54),
2114                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2115                                 NVME_QUIRK_DISCARD_ZEROES, },
2116         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2117                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2118         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
2119                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2120         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
2121                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2122         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2123         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2124         { 0, }
2125 };
2126 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2127
2128 static struct pci_driver nvme_driver = {
2129         .name           = "nvme",
2130         .id_table       = nvme_id_table,
2131         .probe          = nvme_probe,
2132         .remove         = nvme_remove,
2133         .shutdown       = nvme_shutdown,
2134         .driver         = {
2135                 .pm     = &nvme_dev_pm_ops,
2136         },
2137         .sriov_configure = nvme_pci_sriov_configure,
2138         .err_handler    = &nvme_err_handler,
2139 };
2140
2141 static int __init nvme_init(void)
2142 {
2143         int result;
2144
2145         nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2146         if (!nvme_workq)
2147                 return -ENOMEM;
2148
2149         result = pci_register_driver(&nvme_driver);
2150         if (result)
2151                 destroy_workqueue(nvme_workq);
2152         return result;
2153 }
2154
2155 static void __exit nvme_exit(void)
2156 {
2157         pci_unregister_driver(&nvme_driver);
2158         destroy_workqueue(nvme_workq);
2159         _nvme_check_size();
2160 }
2161
2162 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2163 MODULE_LICENSE("GPL");
2164 MODULE_VERSION("1.0");
2165 module_init(nvme_init);
2166 module_exit(nvme_exit);