drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/bitops.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/blk-mq-pci.h>
  20 #include <linux/cpu.h>
  21 #include <linux/delay.h>
  22 #include <linux/errno.h>
  23 #include <linux/fs.h>
  24 #include <linux/genhd.h>
  25 #include <linux/hdreg.h>
  26 #include <linux/idr.h>
  27 #include <linux/init.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/io.h>
  30 #include <linux/kdev_t.h>
  31 #include <linux/kernel.h>
  32 #include <linux/mm.h>
  33 #include <linux/module.h>
  34 #include <linux/moduleparam.h>
  35 #include <linux/mutex.h>
  36 #include <linux/pci.h>
  37 #include <linux/poison.h>
  38 #include <linux/ptrace.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/t10-pi.h>
  42 #include <linux/timer.h>
  43 #include <linux/types.h>
  44 #include <linux/io-64-nonatomic-lo-hi.h>
  45 #include <asm/unaligned.h>
  46
  47 #include "nvme.h"
  48
  49 #define NVME_Q_DEPTH            1024
  50 #define NVME_AQ_DEPTH           256
  51 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  52 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  53
  54 /*
  55  * We handle AEN commands ourselves and don't even let the
  56  * block layer know about them.
  57  */
  58 #define NVME_AQ_BLKMQ_DEPTH     (NVME_AQ_DEPTH - NVME_NR_AERS)
  59
  60 static int use_threaded_interrupts;
  61 module_param(use_threaded_interrupts, int, 0);
  62
  63 static bool use_cmb_sqes = true;
  64 module_param(use_cmb_sqes, bool, 0644);
  65 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  66
  67 static struct workqueue_struct *nvme_workq;
  68
  69 struct nvme_dev;
  70 struct nvme_queue;
  71
  72 static int nvme_reset(struct nvme_dev *dev);
  73 static void nvme_process_cq(struct nvme_queue *nvmeq);
  74 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  75
  76 /*
  77  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  78  */
  79 struct nvme_dev {
  80         struct nvme_queue **queues;
  81         struct blk_mq_tag_set tagset;
  82         struct blk_mq_tag_set admin_tagset;
  83         u32 __iomem *dbs;
  84         struct device *dev;
  85         struct dma_pool *prp_page_pool;
  86         struct dma_pool *prp_small_pool;
  87         unsigned queue_count;
  88         unsigned online_queues;
  89         unsigned max_qid;
  90         int q_depth;
  91         u32 db_stride;
  92         void __iomem *bar;
  93         struct work_struct reset_work;
  94         struct work_struct remove_work;
  95         struct timer_list watchdog_timer;
  96         struct mutex shutdown_lock;
  97         bool subsystem;
  98         void __iomem *cmb;
  99         dma_addr_t cmb_dma_addr;
 100         u64 cmb_size;
 101         u32 cmbsz;
 102         u32 cmbloc;
 103         struct nvme_ctrl ctrl;
 104         struct completion ioq_wait;
 105 };
 106
 107 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 108 {
 109         return container_of(ctrl, struct nvme_dev, ctrl);
 110 }
 111
 112 /*
 113  * An NVM Express queue.  Each device has at least two (one for admin
 114  * commands and one for I/O commands).
 115  */
 116 struct nvme_queue {
 117         struct device *q_dmadev;
 118         struct nvme_dev *dev;
 119         char irqname[24];       /* nvme4294967295-65535\0 */
 120         spinlock_t q_lock;
 121         struct nvme_command *sq_cmds;
 122         struct nvme_command __iomem *sq_cmds_io;
 123         volatile struct nvme_completion *cqes;
 124         struct blk_mq_tags **tags;
 125         dma_addr_t sq_dma_addr;
 126         dma_addr_t cq_dma_addr;
 127         u32 __iomem *q_db;
 128         u16 q_depth;
 129         s16 cq_vector;
 130         u16 sq_tail;
 131         u16 cq_head;
 132         u16 qid;
 133         u8 cq_phase;
 134         u8 cqe_seen;
 135 };
 136
 137 /*
 138  * The nvme_iod describes the data in an I/O, including the list of PRP
 139  * entries.  You can't see it in this data structure because C doesn't let
 140  * me express that.  Use nvme_init_iod to ensure there's enough space
 141  * allocated to store the PRP list.
 142  */
 143 struct nvme_iod {
 144         struct nvme_request req;
 145         struct nvme_queue *nvmeq;
 146         int aborted;
 147         int npages;             /* In the PRP list. 0 means small pool in use */
 148         int nents;              /* Used in scatterlist */
 149         int length;             /* Of data, in bytes */
 150         dma_addr_t first_dma;
 151         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 152         struct scatterlist *sg;
 153         struct scatterlist inline_sg[0];
 154 };
 155
 156 /*
 157  * Check we didin't inadvertently grow the command struct
 158  */
 159 static inline void _nvme_check_size(void)
 160 {
 161         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 162         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 163         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 164         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 165         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 166         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 167         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 168         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 169         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 170         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 171         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 172         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 173 }
 174
 175 /*
 176  * Max size of iod being embedded in the request payload
 177  */
 178 #define NVME_INT_PAGES          2
 179 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 180
 181 /*
 182  * Will slightly overestimate the number of pages needed.  This is OK
 183  * as it only leads to a small amount of wasted memory for the lifetime of
 184  * the I/O.
 185  */
 186 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 187 {
 188         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 189                                       dev->ctrl.page_size);
 190         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 191 }
 192
 193 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
 194                 unsigned int size, unsigned int nseg)
 195 {
 196         return sizeof(__le64 *) * nvme_npages(size, dev) +
 197                         sizeof(struct scatterlist) * nseg;
 198 }
 199
 200 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 201 {
 202         return sizeof(struct nvme_iod) +
 203                 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
 204 }
 205
 206 static int nvmeq_irq(struct nvme_queue *nvmeq)
 207 {
 208         return pci_irq_vector(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector);
 209 }
 210
 211 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 212                                 unsigned int hctx_idx)
 213 {
 214         struct nvme_dev *dev = data;
 215         struct nvme_queue *nvmeq = dev->queues[0];
 216
 217         WARN_ON(hctx_idx != 0);
 218         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 219         WARN_ON(nvmeq->tags);
 220
 221         hctx->driver_data = nvmeq;
 222         nvmeq->tags = &dev->admin_tagset.tags[0];
 223         return 0;
 224 }
 225
 226 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 227 {
 228         struct nvme_queue *nvmeq = hctx->driver_data;
 229
 230         nvmeq->tags = NULL;
 231 }
 232
 233 static int nvme_admin_init_request(void *data, struct request *req,
 234                                 unsigned int hctx_idx, unsigned int rq_idx,
 235                                 unsigned int numa_node)
 236 {
 237         struct nvme_dev *dev = data;
 238         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 239         struct nvme_queue *nvmeq = dev->queues[0];
 240
 241         BUG_ON(!nvmeq);
 242         iod->nvmeq = nvmeq;
 243         return 0;
 244 }
 245
 246 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 247                           unsigned int hctx_idx)
 248 {
 249         struct nvme_dev *dev = data;
 250         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 251
 252         if (!nvmeq->tags)
 253                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 254
 255         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 256         hctx->driver_data = nvmeq;
 257         return 0;
 258 }
 259
 260 static int nvme_init_request(void *data, struct request *req,
 261                                 unsigned int hctx_idx, unsigned int rq_idx,
 262                                 unsigned int numa_node)
 263 {
 264         struct nvme_dev *dev = data;
 265         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 266         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 267
 268         BUG_ON(!nvmeq);
 269         iod->nvmeq = nvmeq;
 270         return 0;
 271 }
 272
 273 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 274 {
 275         struct nvme_dev *dev = set->driver_data;
 276
 277         return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
 278 }
 279
 280 /**
 281  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 282  * @nvmeq: The queue to use
 283  * @cmd: The command to send
 284  *
 285  * Safe to use from interrupt context
 286  */
 287 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 288                                                 struct nvme_command *cmd)
 289 {
 290         u16 tail = nvmeq->sq_tail;
 291
 292         if (nvmeq->sq_cmds_io)
 293                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 294         else
 295                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 296
 297         if (++tail == nvmeq->q_depth)
 298                 tail = 0;
 299         writel(tail, nvmeq->q_db);
 300         nvmeq->sq_tail = tail;
 301 }
 302
 303 static __le64 **iod_list(struct request *req)
 304 {
 305         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 306         return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req));
 307 }
 308
 309 static int nvme_init_iod(struct request *rq, unsigned size,
 310                 struct nvme_dev *dev)
 311 {
 312         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 313         int nseg = blk_rq_nr_phys_segments(rq);
 314
 315         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 316                 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
 317                 if (!iod->sg)
 318                         return BLK_MQ_RQ_QUEUE_BUSY;
 319         } else {
 320                 iod->sg = iod->inline_sg;
 321         }
 322
 323         iod->aborted = 0;
 324         iod->npages = -1;
 325         iod->nents = 0;
 326         iod->length = size;
 327
 328         if (!(rq->rq_flags & RQF_DONTPREP)) {
 329                 rq->retries = 0;
 330                 rq->rq_flags |= RQF_DONTPREP;
 331         }
 332         return BLK_MQ_RQ_QUEUE_OK;
 333 }
 334
 335 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 336 {
 337         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 338         const int last_prp = dev->ctrl.page_size / 8 - 1;
 339         int i;
 340         __le64 **list = iod_list(req);
 341         dma_addr_t prp_dma = iod->first_dma;
 342
 343         if (iod->npages == 0)
 344                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 345         for (i = 0; i < iod->npages; i++) {
 346                 __le64 *prp_list = list[i];
 347                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 348                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 349                 prp_dma = next_prp_dma;
 350         }
 351
 352         if (iod->sg != iod->inline_sg)
 353                 kfree(iod->sg);
 354 }
 355
 356 #ifdef CONFIG_BLK_DEV_INTEGRITY
 357 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 358 {
 359         if (be32_to_cpu(pi->ref_tag) == v)
 360                 pi->ref_tag = cpu_to_be32(p);
 361 }
 362
 363 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 364 {
 365         if (be32_to_cpu(pi->ref_tag) == p)
 366                 pi->ref_tag = cpu_to_be32(v);
 367 }
 368
 369 /**
 370  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 371  *
 372  * The virtual start sector is the one that was originally submitted by the
 373  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 374  * start sector may be different. Remap protection information to match the
 375  * physical LBA on writes, and back to the original seed on reads.
 376  *
 377  * Type 0 and 3 do not have a ref tag, so no remapping required.
 378  */
 379 static void nvme_dif_remap(struct request *req,
 380                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 381 {
 382         struct nvme_ns *ns = req->rq_disk->private_data;
 383         struct bio_integrity_payload *bip;
 384         struct t10_pi_tuple *pi;
 385         void *p, *pmap;
 386         u32 i, nlb, ts, phys, virt;
 387
 388         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 389                 return;
 390
 391         bip = bio_integrity(req->bio);
 392         if (!bip)
 393                 return;
 394
 395         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 396
 397         p = pmap;
 398         virt = bip_get_seed(bip);
 399         phys = nvme_block_nr(ns, blk_rq_pos(req));
 400         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 401         ts = ns->disk->queue->integrity.tuple_size;
 402
 403         for (i = 0; i < nlb; i++, virt++, phys++) {
 404                 pi = (struct t10_pi_tuple *)p;
 405                 dif_swap(phys, virt, pi);
 406                 p += ts;
 407         }
 408         kunmap_atomic(pmap);
 409 }
 410 #else /* CONFIG_BLK_DEV_INTEGRITY */
 411 static void nvme_dif_remap(struct request *req,
 412                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 413 {
 414 }
 415 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 416 {
 417 }
 418 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 419 {
 420 }
 421 #endif
 422
 423 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req,
 424                 int total_len)
 425 {
 426         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 427         struct dma_pool *pool;
 428         int length = total_len;
 429         struct scatterlist *sg = iod->sg;
 430         int dma_len = sg_dma_len(sg);
 431         u64 dma_addr = sg_dma_address(sg);
 432         u32 page_size = dev->ctrl.page_size;
 433         int offset = dma_addr & (page_size - 1);
 434         __le64 *prp_list;
 435         __le64 **list = iod_list(req);
 436         dma_addr_t prp_dma;
 437         int nprps, i;
 438
 439         length -= (page_size - offset);
 440         if (length <= 0)
 441                 return true;
 442
 443         dma_len -= (page_size - offset);
 444         if (dma_len) {
 445                 dma_addr += (page_size - offset);
 446         } else {
 447                 sg = sg_next(sg);
 448                 dma_addr = sg_dma_address(sg);
 449                 dma_len = sg_dma_len(sg);
 450         }
 451
 452         if (length <= page_size) {
 453                 iod->first_dma = dma_addr;
 454                 return true;
 455         }
 456
 457         nprps = DIV_ROUND_UP(length, page_size);
 458         if (nprps <= (256 / 8)) {
 459                 pool = dev->prp_small_pool;
 460                 iod->npages = 0;
 461         } else {
 462                 pool = dev->prp_page_pool;
 463                 iod->npages = 1;
 464         }
 465
 466         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 467         if (!prp_list) {
 468                 iod->first_dma = dma_addr;
 469                 iod->npages = -1;
 470                 return false;
 471         }
 472         list[0] = prp_list;
 473         iod->first_dma = prp_dma;
 474         i = 0;
 475         for (;;) {
 476                 if (i == page_size >> 3) {
 477                         __le64 *old_prp_list = prp_list;
 478                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 479                         if (!prp_list)
 480                                 return false;
 481                         list[iod->npages++] = prp_list;
 482                         prp_list[0] = old_prp_list[i - 1];
 483                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 484                         i = 1;
 485                 }
 486                 prp_list[i++] = cpu_to_le64(dma_addr);
 487                 dma_len -= page_size;
 488                 dma_addr += page_size;
 489                 length -= page_size;
 490                 if (length <= 0)
 491                         break;
 492                 if (dma_len > 0)
 493                         continue;
 494                 BUG_ON(dma_len < 0);
 495                 sg = sg_next(sg);
 496                 dma_addr = sg_dma_address(sg);
 497                 dma_len = sg_dma_len(sg);
 498         }
 499
 500         return true;
 501 }
 502
 503 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
 504                 unsigned size, struct nvme_command *cmnd)
 505 {
 506         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 507         struct request_queue *q = req->q;
 508         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 509                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 510         int ret = BLK_MQ_RQ_QUEUE_ERROR;
 511
 512         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 513         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 514         if (!iod->nents)
 515                 goto out;
 516
 517         ret = BLK_MQ_RQ_QUEUE_BUSY;
 518         if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
 519                                 DMA_ATTR_NO_WARN))
 520                 goto out;
 521
 522         if (!nvme_setup_prps(dev, req, size))
 523                 goto out_unmap;
 524
 525         ret = BLK_MQ_RQ_QUEUE_ERROR;
 526         if (blk_integrity_rq(req)) {
 527                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 528                         goto out_unmap;
 529
 530                 sg_init_table(&iod->meta_sg, 1);
 531                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 532                         goto out_unmap;
 533
 534                 if (rq_data_dir(req))
 535                         nvme_dif_remap(req, nvme_dif_prep);
 536
 537                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 538                         goto out_unmap;
 539         }
 540
 541         cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 542         cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma);
 543         if (blk_integrity_rq(req))
 544                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 545         return BLK_MQ_RQ_QUEUE_OK;
 546
 547 out_unmap:
 548         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 549 out:
 550         return ret;
 551 }
 552
 553 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 554 {
 555         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 556         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 557                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 558
 559         if (iod->nents) {
 560                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 561                 if (blk_integrity_rq(req)) {
 562                         if (!rq_data_dir(req))
 563                                 nvme_dif_remap(req, nvme_dif_complete);
 564                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 565                 }
 566         }
 567
 568         nvme_cleanup_cmd(req);
 569         nvme_free_iod(dev, req);
 570 }
 571
 572 /*
 573  * NOTE: ns is NULL when called on the admin queue.
 574  */
 575 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 576                          const struct blk_mq_queue_data *bd)
 577 {
 578         struct nvme_ns *ns = hctx->queue->queuedata;
 579         struct nvme_queue *nvmeq = hctx->driver_data;
 580         struct nvme_dev *dev = nvmeq->dev;
 581         struct request *req = bd->rq;
 582         struct nvme_command cmnd;
 583         unsigned map_len;
 584         int ret = BLK_MQ_RQ_QUEUE_OK;
 585
 586         /*
 587          * If formated with metadata, require the block layer provide a buffer
 588          * unless this namespace is formated such that the metadata can be
 589          * stripped/generated by the controller with PRACT=1.
 590          */
 591         if (ns && ns->ms && !blk_integrity_rq(req)) {
 592                 if (!(ns->pi_type && ns->ms == 8) &&
 593                                         req->cmd_type != REQ_TYPE_DRV_PRIV) {
 594                         blk_mq_end_request(req, -EFAULT);
 595                         return BLK_MQ_RQ_QUEUE_OK;
 596                 }
 597         }
 598
 599         ret = nvme_setup_cmd(ns, req, &cmnd);
 600         if (ret != BLK_MQ_RQ_QUEUE_OK)
 601                 return ret;
 602
 603         map_len = nvme_map_len(req);
 604         ret = nvme_init_iod(req, map_len, dev);
 605         if (ret != BLK_MQ_RQ_QUEUE_OK)
 606                 goto out_free_cmd;
 607
 608         if (blk_rq_nr_phys_segments(req))
 609                 ret = nvme_map_data(dev, req, map_len, &cmnd);
 610
 611         if (ret != BLK_MQ_RQ_QUEUE_OK)
 612                 goto out_cleanup_iod;
 613
 614         blk_mq_start_request(req);
 615
 616         spin_lock_irq(&nvmeq->q_lock);
 617         if (unlikely(nvmeq->cq_vector < 0)) {
 618                 if (ns && !test_bit(NVME_NS_DEAD, &ns->flags))
 619                         ret = BLK_MQ_RQ_QUEUE_BUSY;
 620                 else
 621                         ret = BLK_MQ_RQ_QUEUE_ERROR;
 622                 spin_unlock_irq(&nvmeq->q_lock);
 623                 goto out_cleanup_iod;
 624         }
 625         __nvme_submit_cmd(nvmeq, &cmnd);
 626         nvme_process_cq(nvmeq);
 627         spin_unlock_irq(&nvmeq->q_lock);
 628         return BLK_MQ_RQ_QUEUE_OK;
 629 out_cleanup_iod:
 630         nvme_free_iod(dev, req);
 631 out_free_cmd:
 632         nvme_cleanup_cmd(req);
 633         return ret;
 634 }
 635
 636 static void nvme_complete_rq(struct request *req)
 637 {
 638         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 639         struct nvme_dev *dev = iod->nvmeq->dev;
 640         int error = 0;
 641
 642         nvme_unmap_data(dev, req);
 643
 644         if (unlikely(req->errors)) {
 645                 if (nvme_req_needs_retry(req, req->errors)) {
 646                         req->retries++;
 647                         nvme_requeue_req(req);
 648                         return;
 649                 }
 650
 651                 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
 652                         error = req->errors;
 653                 else
 654                         error = nvme_error_status(req->errors);
 655         }
 656
 657         if (unlikely(iod->aborted)) {
 658                 dev_warn(dev->ctrl.device,
 659                         "completing aborted command with status: %04x\n",
 660                         req->errors);
 661         }
 662
 663         blk_mq_end_request(req, error);
 664 }
 665
 666 /* We read the CQE phase first to check if the rest of the entry is valid */
 667 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
 668                 u16 phase)
 669 {
 670         return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
 671 }
 672
 673 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
 674 {
 675         u16 head, phase;
 676
 677         head = nvmeq->cq_head;
 678         phase = nvmeq->cq_phase;
 679
 680         while (nvme_cqe_valid(nvmeq, head, phase)) {
 681                 struct nvme_completion cqe = nvmeq->cqes[head];
 682                 struct request *req;
 683
 684                 if (++head == nvmeq->q_depth) {
 685                         head = 0;
 686                         phase = !phase;
 687                 }
 688
 689                 if (tag && *tag == cqe.command_id)
 690                         *tag = -1;
 691
 692                 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
 693                         dev_warn(nvmeq->dev->ctrl.device,
 694                                 "invalid id %d completed on queue %d\n",
 695                                 cqe.command_id, le16_to_cpu(cqe.sq_id));
 696                         continue;
 697                 }
 698
 699                 /*
 700                  * AEN requests are special as they don't time out and can
 701                  * survive any kind of queue freeze and often don't respond to
 702                  * aborts.  We don't even bother to allocate a struct request
 703                  * for them but rather special case them here.
 704                  */
 705                 if (unlikely(nvmeq->qid == 0 &&
 706                                 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
 707                         nvme_complete_async_event(&nvmeq->dev->ctrl,
 708                                         cqe.status, &cqe.result);
 709                         continue;
 710                 }
 711
 712                 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
 713                 nvme_req(req)->result = cqe.result;
 714                 blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1);
 715         }
 716
 717         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 718                 return;
 719
 720         if (likely(nvmeq->cq_vector >= 0))
 721                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 722         nvmeq->cq_head = head;
 723         nvmeq->cq_phase = phase;
 724
 725         nvmeq->cqe_seen = 1;
 726 }
 727
 728 static void nvme_process_cq(struct nvme_queue *nvmeq)
 729 {
 730         __nvme_process_cq(nvmeq, NULL);
 731 }
 732
 733 static irqreturn_t nvme_irq(int irq, void *data)
 734 {
 735         irqreturn_t result;
 736         struct nvme_queue *nvmeq = data;
 737         spin_lock(&nvmeq->q_lock);
 738         nvme_process_cq(nvmeq);
 739         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 740         nvmeq->cqe_seen = 0;
 741         spin_unlock(&nvmeq->q_lock);
 742         return result;
 743 }
 744
 745 static irqreturn_t nvme_irq_check(int irq, void *data)
 746 {
 747         struct nvme_queue *nvmeq = data;
 748         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
 749                 return IRQ_WAKE_THREAD;
 750         return IRQ_NONE;
 751 }
 752
 753 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 754 {
 755         struct nvme_queue *nvmeq = hctx->driver_data;
 756
 757         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
 758                 spin_lock_irq(&nvmeq->q_lock);
 759                 __nvme_process_cq(nvmeq, &tag);
 760                 spin_unlock_irq(&nvmeq->q_lock);
 761
 762                 if (tag == -1)
 763                         return 1;
 764         }
 765
 766         return 0;
 767 }
 768
 769 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
 770 {
 771         struct nvme_dev *dev = to_nvme_dev(ctrl);
 772         struct nvme_queue *nvmeq = dev->queues[0];
 773         struct nvme_command c;
 774
 775         memset(&c, 0, sizeof(c));
 776         c.common.opcode = nvme_admin_async_event;
 777         c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
 778
 779         spin_lock_irq(&nvmeq->q_lock);
 780         __nvme_submit_cmd(nvmeq, &c);
 781         spin_unlock_irq(&nvmeq->q_lock);
 782 }
 783
 784 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 785 {
 786         struct nvme_command c;
 787
 788         memset(&c, 0, sizeof(c));
 789         c.delete_queue.opcode = opcode;
 790         c.delete_queue.qid = cpu_to_le16(id);
 791
 792         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 793 }
 794
 795 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 796                                                 struct nvme_queue *nvmeq)
 797 {
 798         struct nvme_command c;
 799         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 800
 801         /*
 802          * Note: we (ab)use the fact the the prp fields survive if no data
 803          * is attached to the request.
 804          */
 805         memset(&c, 0, sizeof(c));
 806         c.create_cq.opcode = nvme_admin_create_cq;
 807         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 808         c.create_cq.cqid = cpu_to_le16(qid);
 809         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 810         c.create_cq.cq_flags = cpu_to_le16(flags);
 811         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 812
 813         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 814 }
 815
 816 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 817                                                 struct nvme_queue *nvmeq)
 818 {
 819         struct nvme_command c;
 820         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 821
 822         /*
 823          * Note: we (ab)use the fact the the prp fields survive if no data
 824          * is attached to the request.
 825          */
 826         memset(&c, 0, sizeof(c));
 827         c.create_sq.opcode = nvme_admin_create_sq;
 828         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 829         c.create_sq.sqid = cpu_to_le16(qid);
 830         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 831         c.create_sq.sq_flags = cpu_to_le16(flags);
 832         c.create_sq.cqid = cpu_to_le16(qid);
 833
 834         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 835 }
 836
 837 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 838 {
 839         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 840 }
 841
 842 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 843 {
 844         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 845 }
 846
 847 static void abort_endio(struct request *req, int error)
 848 {
 849         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 850         struct nvme_queue *nvmeq = iod->nvmeq;
 851         u16 status = req->errors;
 852
 853         dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status);
 854         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
 855         blk_mq_free_request(req);
 856 }
 857
 858 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
 859 {
 860         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 861         struct nvme_queue *nvmeq = iod->nvmeq;
 862         struct nvme_dev *dev = nvmeq->dev;
 863         struct request *abort_req;
 864         struct nvme_command cmd;
 865
 866         /*
 867          * Shutdown immediately if controller times out while starting. The
 868          * reset work will see the pci device disabled when it gets the forced
 869          * cancellation error. All outstanding requests are completed on
 870          * shutdown, so we return BLK_EH_HANDLED.
 871          */
 872         if (dev->ctrl.state == NVME_CTRL_RESETTING) {
 873                 dev_warn(dev->ctrl.device,
 874                          "I/O %d QID %d timeout, disable controller\n",
 875                          req->tag, nvmeq->qid);
 876                 nvme_dev_disable(dev, false);
 877                 req->errors = NVME_SC_CANCELLED;
 878                 return BLK_EH_HANDLED;
 879         }
 880
 881         /*
 882          * Shutdown the controller immediately and schedule a reset if the
 883          * command was already aborted once before and still hasn't been
 884          * returned to the driver, or if this is the admin queue.
 885          */
 886         if (!nvmeq->qid || iod->aborted) {
 887                 dev_warn(dev->ctrl.device,
 888                          "I/O %d QID %d timeout, reset controller\n",
 889                          req->tag, nvmeq->qid);
 890                 nvme_dev_disable(dev, false);
 891                 nvme_reset(dev);
 892
 893                 /*
 894                  * Mark the request as handled, since the inline shutdown
 895                  * forces all outstanding requests to complete.
 896                  */
 897                 req->errors = NVME_SC_CANCELLED;
 898                 return BLK_EH_HANDLED;
 899         }
 900
 901         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
 902                 atomic_inc(&dev->ctrl.abort_limit);
 903                 return BLK_EH_RESET_TIMER;
 904         }
 905         iod->aborted = 1;
 906
 907         memset(&cmd, 0, sizeof(cmd));
 908         cmd.abort.opcode = nvme_admin_abort_cmd;
 909         cmd.abort.cid = req->tag;
 910         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
 911
 912         dev_warn(nvmeq->dev->ctrl.device,
 913                 "I/O %d QID %d timeout, aborting\n",
 914                  req->tag, nvmeq->qid);
 915
 916         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
 917                         BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
 918         if (IS_ERR(abort_req)) {
 919                 atomic_inc(&dev->ctrl.abort_limit);
 920                 return BLK_EH_RESET_TIMER;
 921         }
 922
 923         abort_req->timeout = ADMIN_TIMEOUT;
 924         abort_req->end_io_data = NULL;
 925         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
 926
 927         /*
 928          * The aborted req will be completed on receiving the abort req.
 929          * We enable the timer again. If hit twice, it'll cause a device reset,
 930          * as the device then is in a faulty state.
 931          */
 932         return BLK_EH_RESET_TIMER;
 933 }
 934
 935 static void nvme_free_queue(struct nvme_queue *nvmeq)
 936 {
 937         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 938                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 939         if (nvmeq->sq_cmds)
 940                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 941                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 942         kfree(nvmeq);
 943 }
 944
 945 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
 946 {
 947         int i;
 948
 949         for (i = dev->queue_count - 1; i >= lowest; i--) {
 950                 struct nvme_queue *nvmeq = dev->queues[i];
 951                 dev->queue_count--;
 952                 dev->queues[i] = NULL;
 953                 nvme_free_queue(nvmeq);
 954         }
 955 }
 956
 957 /**
 958  * nvme_suspend_queue - put queue into suspended state
 959  * @nvmeq - queue to suspend
 960  */
 961 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
 962 {
 963         int vector;
 964
 965         spin_lock_irq(&nvmeq->q_lock);
 966         if (nvmeq->cq_vector == -1) {
 967                 spin_unlock_irq(&nvmeq->q_lock);
 968                 return 1;
 969         }
 970         vector = nvmeq_irq(nvmeq);
 971         nvmeq->dev->online_queues--;
 972         nvmeq->cq_vector = -1;
 973         spin_unlock_irq(&nvmeq->q_lock);
 974
 975         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
 976                 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
 977
 978         free_irq(vector, nvmeq);
 979
 980         return 0;
 981 }
 982
 983 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
 984 {
 985         struct nvme_queue *nvmeq = dev->queues[0];
 986
 987         if (!nvmeq)
 988                 return;
 989         if (nvme_suspend_queue(nvmeq))
 990                 return;
 991
 992         if (shutdown)
 993                 nvme_shutdown_ctrl(&dev->ctrl);
 994         else
 995                 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
 996                                                 dev->bar + NVME_REG_CAP));
 997
 998         spin_lock_irq(&nvmeq->q_lock);
 999         nvme_process_cq(nvmeq);
1000         spin_unlock_irq(&nvmeq->q_lock);
1001 }
1002
1003 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1004                                 int entry_size)
1005 {
1006         int q_depth = dev->q_depth;
1007         unsigned q_size_aligned = roundup(q_depth * entry_size,
1008                                           dev->ctrl.page_size);
1009
1010         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1011                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1012                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1013                 q_depth = div_u64(mem_per_q, entry_size);
1014
1015                 /*
1016                  * Ensure the reduced q_depth is above some threshold where it
1017                  * would be better to map queues in system memory with the
1018                  * original depth
1019                  */
1020                 if (q_depth < 64)
1021                         return -ENOMEM;
1022         }
1023
1024         return q_depth;
1025 }
1026
1027 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1028                                 int qid, int depth)
1029 {
1030         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1031                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1032                                                       dev->ctrl.page_size);
1033                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1034                 nvmeq->sq_cmds_io = dev->cmb + offset;
1035         } else {
1036                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1037                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1038                 if (!nvmeq->sq_cmds)
1039                         return -ENOMEM;
1040         }
1041
1042         return 0;
1043 }
1044
1045 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1046                                                         int depth)
1047 {
1048         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1049         if (!nvmeq)
1050                 return NULL;
1051
1052         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1053                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1054         if (!nvmeq->cqes)
1055                 goto free_nvmeq;
1056
1057         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1058                 goto free_cqdma;
1059
1060         nvmeq->q_dmadev = dev->dev;
1061         nvmeq->dev = dev;
1062         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1063                         dev->ctrl.instance, qid);
1064         spin_lock_init(&nvmeq->q_lock);
1065         nvmeq->cq_head = 0;
1066         nvmeq->cq_phase = 1;
1067         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1068         nvmeq->q_depth = depth;
1069         nvmeq->qid = qid;
1070         nvmeq->cq_vector = -1;
1071         dev->queues[qid] = nvmeq;
1072         dev->queue_count++;
1073
1074         return nvmeq;
1075
1076  free_cqdma:
1077         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1078                                                         nvmeq->cq_dma_addr);
1079  free_nvmeq:
1080         kfree(nvmeq);
1081         return NULL;
1082 }
1083
1084 static int queue_request_irq(struct nvme_queue *nvmeq)
1085 {
1086         if (use_threaded_interrupts)
1087                 return request_threaded_irq(nvmeq_irq(nvmeq), nvme_irq_check,
1088                                 nvme_irq, IRQF_SHARED, nvmeq->irqname, nvmeq);
1089         else
1090                 return request_irq(nvmeq_irq(nvmeq), nvme_irq, IRQF_SHARED,
1091                                 nvmeq->irqname, nvmeq);
1092 }
1093
1094 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1095 {
1096         struct nvme_dev *dev = nvmeq->dev;
1097
1098         spin_lock_irq(&nvmeq->q_lock);
1099         nvmeq->sq_tail = 0;
1100         nvmeq->cq_head = 0;
1101         nvmeq->cq_phase = 1;
1102         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1103         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1104         dev->online_queues++;
1105         spin_unlock_irq(&nvmeq->q_lock);
1106 }
1107
1108 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1109 {
1110         struct nvme_dev *dev = nvmeq->dev;
1111         int result;
1112
1113         nvmeq->cq_vector = qid - 1;
1114         result = adapter_alloc_cq(dev, qid, nvmeq);
1115         if (result < 0)
1116                 return result;
1117
1118         result = adapter_alloc_sq(dev, qid, nvmeq);
1119         if (result < 0)
1120                 goto release_cq;
1121
1122         result = queue_request_irq(nvmeq);
1123         if (result < 0)
1124                 goto release_sq;
1125
1126         nvme_init_queue(nvmeq, qid);
1127         return result;
1128
1129  release_sq:
1130         adapter_delete_sq(dev, qid);
1131  release_cq:
1132         adapter_delete_cq(dev, qid);
1133         return result;
1134 }
1135
1136 static struct blk_mq_ops nvme_mq_admin_ops = {
1137         .queue_rq       = nvme_queue_rq,
1138         .complete       = nvme_complete_rq,
1139         .init_hctx      = nvme_admin_init_hctx,
1140         .exit_hctx      = nvme_admin_exit_hctx,
1141         .init_request   = nvme_admin_init_request,
1142         .timeout        = nvme_timeout,
1143 };
1144
1145 static struct blk_mq_ops nvme_mq_ops = {
1146         .queue_rq       = nvme_queue_rq,
1147         .complete       = nvme_complete_rq,
1148         .init_hctx      = nvme_init_hctx,
1149         .init_request   = nvme_init_request,
1150         .map_queues     = nvme_pci_map_queues,
1151         .timeout        = nvme_timeout,
1152         .poll           = nvme_poll,
1153 };
1154
1155 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1156 {
1157         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1158                 /*
1159                  * If the controller was reset during removal, it's possible
1160                  * user requests may be waiting on a stopped queue. Start the
1161                  * queue to flush these to completion.
1162                  */
1163                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1164                 blk_cleanup_queue(dev->ctrl.admin_q);
1165                 blk_mq_free_tag_set(&dev->admin_tagset);
1166         }
1167 }
1168
1169 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1170 {
1171         if (!dev->ctrl.admin_q) {
1172                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1173                 dev->admin_tagset.nr_hw_queues = 1;
1174
1175                 /*
1176                  * Subtract one to leave an empty queue entry for 'Full Queue'
1177                  * condition. See NVM-Express 1.2 specification, section 4.1.2.
1178                  */
1179                 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1180                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1181                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1182                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1183                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1184                 dev->admin_tagset.driver_data = dev;
1185
1186                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1187                         return -ENOMEM;
1188
1189                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1190                 if (IS_ERR(dev->ctrl.admin_q)) {
1191                         blk_mq_free_tag_set(&dev->admin_tagset);
1192                         return -ENOMEM;
1193                 }
1194                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1195                         nvme_dev_remove_admin(dev);
1196                         dev->ctrl.admin_q = NULL;
1197                         return -ENODEV;
1198                 }
1199         } else
1200                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1201
1202         return 0;
1203 }
1204
1205 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1206 {
1207         int result;
1208         u32 aqa;
1209         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1210         struct nvme_queue *nvmeq;
1211
1212         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1213                                                 NVME_CAP_NSSRC(cap) : 0;
1214
1215         if (dev->subsystem &&
1216             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1217                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1218
1219         result = nvme_disable_ctrl(&dev->ctrl, cap);
1220         if (result < 0)
1221                 return result;
1222
1223         nvmeq = dev->queues[0];
1224         if (!nvmeq) {
1225                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1226                 if (!nvmeq)
1227                         return -ENOMEM;
1228         }
1229
1230         aqa = nvmeq->q_depth - 1;
1231         aqa |= aqa << 16;
1232
1233         writel(aqa, dev->bar + NVME_REG_AQA);
1234         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1235         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1236
1237         result = nvme_enable_ctrl(&dev->ctrl, cap);
1238         if (result)
1239                 return result;
1240
1241         nvmeq->cq_vector = 0;
1242         result = queue_request_irq(nvmeq);
1243         if (result) {
1244                 nvmeq->cq_vector = -1;
1245                 return result;
1246         }
1247
1248         return result;
1249 }
1250
1251 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1252 {
1253
1254         /* If true, indicates loss of adapter communication, possibly by a
1255          * NVMe Subsystem reset.
1256          */
1257         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1258
1259         /* If there is a reset ongoing, we shouldn't reset again. */
1260         if (work_busy(&dev->reset_work))
1261                 return false;
1262
1263         /* We shouldn't reset unless the controller is on fatal error state
1264          * _or_ if we lost the communication with it.
1265          */
1266         if (!(csts & NVME_CSTS_CFS) && !nssro)
1267                 return false;
1268
1269         /* If PCI error recovery process is happening, we cannot reset or
1270          * the recovery mechanism will surely fail.
1271          */
1272         if (pci_channel_offline(to_pci_dev(dev->dev)))
1273                 return false;
1274
1275         return true;
1276 }
1277
1278 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1279 {
1280         /* Read a config register to help see what died. */
1281         u16 pci_status;
1282         int result;
1283
1284         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1285                                       &pci_status);
1286         if (result == PCIBIOS_SUCCESSFUL)
1287                 dev_warn(dev->dev,
1288                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1289                          csts, pci_status);
1290         else
1291                 dev_warn(dev->dev,
1292                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1293                          csts, result);
1294 }
1295
1296 static void nvme_watchdog_timer(unsigned long data)
1297 {
1298         struct nvme_dev *dev = (struct nvme_dev *)data;
1299         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1300
1301         /* Skip controllers under certain specific conditions. */
1302         if (nvme_should_reset(dev, csts)) {
1303                 if (!nvme_reset(dev))
1304                         nvme_warn_reset(dev, csts);
1305                 return;
1306         }
1307
1308         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1309 }
1310
1311 static int nvme_create_io_queues(struct nvme_dev *dev)
1312 {
1313         unsigned i, max;
1314         int ret = 0;
1315
1316         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1317                 if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1318                         ret = -ENOMEM;
1319                         break;
1320                 }
1321         }
1322
1323         max = min(dev->max_qid, dev->queue_count - 1);
1324         for (i = dev->online_queues; i <= max; i++) {
1325                 ret = nvme_create_queue(dev->queues[i], i);
1326                 if (ret)
1327                         break;
1328         }
1329
1330         /*
1331          * Ignore failing Create SQ/CQ commands, we can continue with less
1332          * than the desired aount of queues, and even a controller without
1333          * I/O queues an still be used to issue admin commands.  This might
1334          * be useful to upgrade a buggy firmware for example.
1335          */
1336         return ret >= 0 ? 0 : ret;
1337 }
1338
1339 static ssize_t nvme_cmb_show(struct device *dev,
1340                              struct device_attribute *attr,
1341                              char *buf)
1342 {
1343         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1344
1345         return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1346                        ndev->cmbloc, ndev->cmbsz);
1347 }
1348 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1349
1350 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1351 {
1352         u64 szu, size, offset;
1353         resource_size_t bar_size;
1354         struct pci_dev *pdev = to_pci_dev(dev->dev);
1355         void __iomem *cmb;
1356         dma_addr_t dma_addr;
1357
1358         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1359         if (!(NVME_CMB_SZ(dev->cmbsz)))
1360                 return NULL;
1361         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1362
1363         if (!use_cmb_sqes)
1364                 return NULL;
1365
1366         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1367         size = szu * NVME_CMB_SZ(dev->cmbsz);
1368         offset = szu * NVME_CMB_OFST(dev->cmbloc);
1369         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc));
1370
1371         if (offset > bar_size)
1372                 return NULL;
1373
1374         /*
1375          * Controllers may support a CMB size larger than their BAR,
1376          * for example, due to being behind a bridge. Reduce the CMB to
1377          * the reported size of the BAR
1378          */
1379         if (size > bar_size - offset)
1380                 size = bar_size - offset;
1381
1382         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset;
1383         cmb = ioremap_wc(dma_addr, size);
1384         if (!cmb)
1385                 return NULL;
1386
1387         dev->cmb_dma_addr = dma_addr;
1388         dev->cmb_size = size;
1389         return cmb;
1390 }
1391
1392 static inline void nvme_release_cmb(struct nvme_dev *dev)
1393 {
1394         if (dev->cmb) {
1395                 iounmap(dev->cmb);
1396                 dev->cmb = NULL;
1397         }
1398 }
1399
1400 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1401 {
1402         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1403 }
1404
1405 static int nvme_setup_io_queues(struct nvme_dev *dev)
1406 {
1407         struct nvme_queue *adminq = dev->queues[0];
1408         struct pci_dev *pdev = to_pci_dev(dev->dev);
1409         int result, nr_io_queues, size;
1410
1411         nr_io_queues = num_online_cpus();
1412         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1413         if (result < 0)
1414                 return result;
1415
1416         if (nr_io_queues == 0)
1417                 return 0;
1418
1419         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1420                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1421                                 sizeof(struct nvme_command));
1422                 if (result > 0)
1423                         dev->q_depth = result;
1424                 else
1425                         nvme_release_cmb(dev);
1426         }
1427
1428         size = db_bar_size(dev, nr_io_queues);
1429         if (size > 8192) {
1430                 iounmap(dev->bar);
1431                 do {
1432                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1433                         if (dev->bar)
1434                                 break;
1435                         if (!--nr_io_queues)
1436                                 return -ENOMEM;
1437                         size = db_bar_size(dev, nr_io_queues);
1438                 } while (1);
1439                 dev->dbs = dev->bar + 4096;
1440                 adminq->q_db = dev->dbs;
1441         }
1442
1443         /* Deregister the admin queue's interrupt */
1444         free_irq(pci_irq_vector(pdev, 0), adminq);
1445
1446         /*
1447          * If we enable msix early due to not intx, disable it again before
1448          * setting up the full range we need.
1449          */
1450         pci_free_irq_vectors(pdev);
1451         nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1452                         PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1453         if (nr_io_queues <= 0)
1454                 return -EIO;
1455         dev->max_qid = nr_io_queues;
1456
1457         /*
1458          * Should investigate if there's a performance win from allocating
1459          * more queues than interrupt vectors; it might allow the submission
1460          * path to scale better, even if the receive path is limited by the
1461          * number of interrupts.
1462          */
1463
1464         result = queue_request_irq(adminq);
1465         if (result) {
1466                 adminq->cq_vector = -1;
1467                 return result;
1468         }
1469         return nvme_create_io_queues(dev);
1470 }
1471
1472 static void nvme_del_queue_end(struct request *req, int error)
1473 {
1474         struct nvme_queue *nvmeq = req->end_io_data;
1475
1476         blk_mq_free_request(req);
1477         complete(&nvmeq->dev->ioq_wait);
1478 }
1479
1480 static void nvme_del_cq_end(struct request *req, int error)
1481 {
1482         struct nvme_queue *nvmeq = req->end_io_data;
1483
1484         if (!error) {
1485                 unsigned long flags;
1486
1487                 /*
1488                  * We might be called with the AQ q_lock held
1489                  * and the I/O queue q_lock should always
1490                  * nest inside the AQ one.
1491                  */
1492                 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1493                                         SINGLE_DEPTH_NESTING);
1494                 nvme_process_cq(nvmeq);
1495                 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1496         }
1497
1498         nvme_del_queue_end(req, error);
1499 }
1500
1501 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1502 {
1503         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1504         struct request *req;
1505         struct nvme_command cmd;
1506
1507         memset(&cmd, 0, sizeof(cmd));
1508         cmd.delete_queue.opcode = opcode;
1509         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1510
1511         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1512         if (IS_ERR(req))
1513                 return PTR_ERR(req);
1514
1515         req->timeout = ADMIN_TIMEOUT;
1516         req->end_io_data = nvmeq;
1517
1518         blk_execute_rq_nowait(q, NULL, req, false,
1519                         opcode == nvme_admin_delete_cq ?
1520                                 nvme_del_cq_end : nvme_del_queue_end);
1521         return 0;
1522 }
1523
1524 static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
1525 {
1526         int pass;
1527         unsigned long timeout;
1528         u8 opcode = nvme_admin_delete_sq;
1529
1530         for (pass = 0; pass < 2; pass++) {
1531                 int sent = 0, i = queues;
1532
1533                 reinit_completion(&dev->ioq_wait);
1534  retry:
1535                 timeout = ADMIN_TIMEOUT;
1536                 for (; i > 0; i--, sent++)
1537                         if (nvme_delete_queue(dev->queues[i], opcode))
1538                                 break;
1539
1540                 while (sent--) {
1541                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1542                         if (timeout == 0)
1543                                 return;
1544                         if (i)
1545                                 goto retry;
1546                 }
1547                 opcode = nvme_admin_delete_cq;
1548         }
1549 }
1550
1551 /*
1552  * Return: error value if an error occurred setting up the queues or calling
1553  * Identify Device.  0 if these succeeded, even if adding some of the
1554  * namespaces failed.  At the moment, these failures are silent.  TBD which
1555  * failures should be reported.
1556  */
1557 static int nvme_dev_add(struct nvme_dev *dev)
1558 {
1559         if (!dev->ctrl.tagset) {
1560                 dev->tagset.ops = &nvme_mq_ops;
1561                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1562                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1563                 dev->tagset.numa_node = dev_to_node(dev->dev);
1564                 dev->tagset.queue_depth =
1565                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1566                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1567                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1568                 dev->tagset.driver_data = dev;
1569
1570                 if (blk_mq_alloc_tag_set(&dev->tagset))
1571                         return 0;
1572                 dev->ctrl.tagset = &dev->tagset;
1573         } else {
1574                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1575
1576                 /* Free previously allocated queues that are no longer usable */
1577                 nvme_free_queues(dev, dev->online_queues);
1578         }
1579
1580         return 0;
1581 }
1582
1583 static int nvme_pci_enable(struct nvme_dev *dev)
1584 {
1585         u64 cap;
1586         int result = -ENOMEM;
1587         struct pci_dev *pdev = to_pci_dev(dev->dev);
1588
1589         if (pci_enable_device_mem(pdev))
1590                 return result;
1591
1592         pci_set_master(pdev);
1593
1594         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1595             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1596                 goto disable;
1597
1598         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1599                 result = -ENODEV;
1600                 goto disable;
1601         }
1602
1603         /*
1604          * Some devices and/or platforms don't advertise or work with INTx
1605          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1606          * adjust this later.
1607          */
1608         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1609         if (result < 0)
1610                 return result;
1611
1612         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1613
1614         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1615         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1616         dev->dbs = dev->bar + 4096;
1617
1618         /*
1619          * Temporary fix for the Apple controller found in the MacBook8,1 and
1620          * some MacBook7,1 to avoid controller resets and data loss.
1621          */
1622         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1623                 dev->q_depth = 2;
1624                 dev_warn(dev->dev, "detected Apple NVMe controller, set "
1625                         "queue depth=%u to work around controller resets\n",
1626                         dev->q_depth);
1627         }
1628
1629         /*
1630          * CMBs can currently only exist on >=1.2 PCIe devices. We only
1631          * populate sysfs if a CMB is implemented. Note that we add the
1632          * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1633          * it on exit. Since nvme_dev_attrs_group has no name we can pass
1634          * NULL as final argument to sysfs_add_file_to_group.
1635          */
1636
1637         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
1638                 dev->cmb = nvme_map_cmb(dev);
1639
1640                 if (dev->cmbsz) {
1641                         if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1642                                                     &dev_attr_cmb.attr, NULL))
1643                                 dev_warn(dev->dev,
1644                                          "failed to add sysfs attribute for CMB\n");
1645                 }
1646         }
1647
1648         pci_enable_pcie_error_reporting(pdev);
1649         pci_save_state(pdev);
1650         return 0;
1651
1652  disable:
1653         pci_disable_device(pdev);
1654         return result;
1655 }
1656
1657 static void nvme_dev_unmap(struct nvme_dev *dev)
1658 {
1659         if (dev->bar)
1660                 iounmap(dev->bar);
1661         pci_release_mem_regions(to_pci_dev(dev->dev));
1662 }
1663
1664 static void nvme_pci_disable(struct nvme_dev *dev)
1665 {
1666         struct pci_dev *pdev = to_pci_dev(dev->dev);
1667
1668         pci_free_irq_vectors(pdev);
1669
1670         if (pci_is_enabled(pdev)) {
1671                 pci_disable_pcie_error_reporting(pdev);
1672                 pci_disable_device(pdev);
1673         }
1674 }
1675
1676 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1677 {
1678         int i, queues;
1679         u32 csts = -1;
1680
1681         del_timer_sync(&dev->watchdog_timer);
1682
1683         mutex_lock(&dev->shutdown_lock);
1684         if (pci_is_enabled(to_pci_dev(dev->dev))) {
1685                 nvme_stop_queues(&dev->ctrl);
1686                 csts = readl(dev->bar + NVME_REG_CSTS);
1687         }
1688
1689         queues = dev->online_queues - 1;
1690         for (i = dev->queue_count - 1; i > 0; i--)
1691                 nvme_suspend_queue(dev->queues[i]);
1692
1693         if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
1694                 /* A device might become IO incapable very soon during
1695                  * probe, before the admin queue is configured. Thus,
1696                  * queue_count can be 0 here.
1697                  */
1698                 if (dev->queue_count)
1699                         nvme_suspend_queue(dev->queues[0]);
1700         } else {
1701                 nvme_disable_io_queues(dev, queues);
1702                 nvme_disable_admin_queue(dev, shutdown);
1703         }
1704         nvme_pci_disable(dev);
1705
1706         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
1707         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
1708         mutex_unlock(&dev->shutdown_lock);
1709 }
1710
1711 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1712 {
1713         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1714                                                 PAGE_SIZE, PAGE_SIZE, 0);
1715         if (!dev->prp_page_pool)
1716                 return -ENOMEM;
1717
1718         /* Optimisation for I/Os between 4k and 128k */
1719         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1720                                                 256, 256, 0);
1721         if (!dev->prp_small_pool) {
1722                 dma_pool_destroy(dev->prp_page_pool);
1723                 return -ENOMEM;
1724         }
1725         return 0;
1726 }
1727
1728 static void nvme_release_prp_pools(struct nvme_dev *dev)
1729 {
1730         dma_pool_destroy(dev->prp_page_pool);
1731         dma_pool_destroy(dev->prp_small_pool);
1732 }
1733
1734 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1735 {
1736         struct nvme_dev *dev = to_nvme_dev(ctrl);
1737
1738         put_device(dev->dev);
1739         if (dev->tagset.tags)
1740                 blk_mq_free_tag_set(&dev->tagset);
1741         if (dev->ctrl.admin_q)
1742                 blk_put_queue(dev->ctrl.admin_q);
1743         kfree(dev->queues);
1744         kfree(dev);
1745 }
1746
1747 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
1748 {
1749         dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
1750
1751         kref_get(&dev->ctrl.kref);
1752         nvme_dev_disable(dev, false);
1753         if (!schedule_work(&dev->remove_work))
1754                 nvme_put_ctrl(&dev->ctrl);
1755 }
1756
1757 static void nvme_reset_work(struct work_struct *work)
1758 {
1759         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1760         int result = -ENODEV;
1761
1762         if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING))
1763                 goto out;
1764
1765         /*
1766          * If we're called to reset a live controller first shut it down before
1767          * moving on.
1768          */
1769         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
1770                 nvme_dev_disable(dev, false);
1771
1772         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
1773                 goto out;
1774
1775         result = nvme_pci_enable(dev);
1776         if (result)
1777                 goto out;
1778
1779         result = nvme_configure_admin_queue(dev);
1780         if (result)
1781                 goto out;
1782
1783         nvme_init_queue(dev->queues[0], 0);
1784         result = nvme_alloc_admin_tags(dev);
1785         if (result)
1786                 goto out;
1787
1788         result = nvme_init_identify(&dev->ctrl);
1789         if (result)
1790                 goto out;
1791
1792         result = nvme_setup_io_queues(dev);
1793         if (result)
1794                 goto out;
1795
1796         /*
1797          * A controller that can not execute IO typically requires user
1798          * intervention to correct. For such degraded controllers, the driver
1799          * should not submit commands the user did not request, so skip
1800          * registering for asynchronous event notification on this condition.
1801          */
1802         if (dev->online_queues > 1)
1803                 nvme_queue_async_events(&dev->ctrl);
1804
1805         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1806
1807         /*
1808          * Keep the controller around but remove all namespaces if we don't have
1809          * any working I/O queue.
1810          */
1811         if (dev->online_queues < 2) {
1812                 dev_warn(dev->ctrl.device, "IO queues not created\n");
1813                 nvme_kill_queues(&dev->ctrl);
1814                 nvme_remove_namespaces(&dev->ctrl);
1815         } else {
1816                 nvme_start_queues(&dev->ctrl);
1817                 nvme_dev_add(dev);
1818         }
1819
1820         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
1821                 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
1822                 goto out;
1823         }
1824
1825         if (dev->online_queues > 1)
1826                 nvme_queue_scan(&dev->ctrl);
1827         return;
1828
1829  out:
1830         nvme_remove_dead_ctrl(dev, result);
1831 }
1832
1833 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1834 {
1835         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1836         struct pci_dev *pdev = to_pci_dev(dev->dev);
1837
1838         nvme_kill_queues(&dev->ctrl);
1839         if (pci_get_drvdata(pdev))
1840                 device_release_driver(&pdev->dev);
1841         nvme_put_ctrl(&dev->ctrl);
1842 }
1843
1844 static int nvme_reset(struct nvme_dev *dev)
1845 {
1846         if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
1847                 return -ENODEV;
1848         if (work_busy(&dev->reset_work))
1849                 return -ENODEV;
1850         if (!queue_work(nvme_workq, &dev->reset_work))
1851                 return -EBUSY;
1852         return 0;
1853 }
1854
1855 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
1856 {
1857         *val = readl(to_nvme_dev(ctrl)->bar + off);
1858         return 0;
1859 }
1860
1861 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
1862 {
1863         writel(val, to_nvme_dev(ctrl)->bar + off);
1864         return 0;
1865 }
1866
1867 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
1868 {
1869         *val = readq(to_nvme_dev(ctrl)->bar + off);
1870         return 0;
1871 }
1872
1873 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
1874 {
1875         struct nvme_dev *dev = to_nvme_dev(ctrl);
1876         int ret = nvme_reset(dev);
1877
1878         if (!ret)
1879                 flush_work(&dev->reset_work);
1880         return ret;
1881 }
1882
1883 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1884         .name                   = "pcie",
1885         .module                 = THIS_MODULE,
1886         .reg_read32             = nvme_pci_reg_read32,
1887         .reg_write32            = nvme_pci_reg_write32,
1888         .reg_read64             = nvme_pci_reg_read64,
1889         .reset_ctrl             = nvme_pci_reset_ctrl,
1890         .free_ctrl              = nvme_pci_free_ctrl,
1891         .submit_async_event     = nvme_pci_submit_async_event,
1892 };
1893
1894 static int nvme_dev_map(struct nvme_dev *dev)
1895 {
1896         struct pci_dev *pdev = to_pci_dev(dev->dev);
1897
1898         if (pci_request_mem_regions(pdev, "nvme"))
1899                 return -ENODEV;
1900
1901         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1902         if (!dev->bar)
1903                 goto release;
1904
1905         return 0;
1906   release:
1907         pci_release_mem_regions(pdev);
1908         return -ENODEV;
1909 }
1910
1911 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1912 {
1913         int node, result = -ENOMEM;
1914         struct nvme_dev *dev;
1915
1916         node = dev_to_node(&pdev->dev);
1917         if (node == NUMA_NO_NODE)
1918                 set_dev_node(&pdev->dev, first_memory_node);
1919
1920         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
1921         if (!dev)
1922                 return -ENOMEM;
1923         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
1924                                                         GFP_KERNEL, node);
1925         if (!dev->queues)
1926                 goto free;
1927
1928         dev->dev = get_device(&pdev->dev);
1929         pci_set_drvdata(pdev, dev);
1930
1931         result = nvme_dev_map(dev);
1932         if (result)
1933                 goto free;
1934
1935         INIT_WORK(&dev->reset_work, nvme_reset_work);
1936         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
1937         setup_timer(&dev->watchdog_timer, nvme_watchdog_timer,
1938                 (unsigned long)dev);
1939         mutex_init(&dev->shutdown_lock);
1940         init_completion(&dev->ioq_wait);
1941
1942         result = nvme_setup_prp_pools(dev);
1943         if (result)
1944                 goto put_pci;
1945
1946         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
1947                         id->driver_data);
1948         if (result)
1949                 goto release_pools;
1950
1951         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
1952
1953         queue_work(nvme_workq, &dev->reset_work);
1954         return 0;
1955
1956  release_pools:
1957         nvme_release_prp_pools(dev);
1958  put_pci:
1959         put_device(dev->dev);
1960         nvme_dev_unmap(dev);
1961  free:
1962         kfree(dev->queues);
1963         kfree(dev);
1964         return result;
1965 }
1966
1967 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
1968 {
1969         struct nvme_dev *dev = pci_get_drvdata(pdev);
1970
1971         if (prepare)
1972                 nvme_dev_disable(dev, false);
1973         else
1974                 nvme_reset(dev);
1975 }
1976
1977 static void nvme_shutdown(struct pci_dev *pdev)
1978 {
1979         struct nvme_dev *dev = pci_get_drvdata(pdev);
1980         nvme_dev_disable(dev, true);
1981 }
1982
1983 /*
1984  * The driver's remove may be called on a device in a partially initialized
1985  * state. This function must not have any dependencies on the device state in
1986  * order to proceed.
1987  */
1988 static void nvme_remove(struct pci_dev *pdev)
1989 {
1990         struct nvme_dev *dev = pci_get_drvdata(pdev);
1991
1992         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1993
1994         pci_set_drvdata(pdev, NULL);
1995
1996         if (!pci_device_is_present(pdev))
1997                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1998
1999         flush_work(&dev->reset_work);
2000         nvme_uninit_ctrl(&dev->ctrl);
2001         nvme_dev_disable(dev, true);
2002         nvme_dev_remove_admin(dev);
2003         nvme_free_queues(dev, 0);
2004         nvme_release_cmb(dev);
2005         nvme_release_prp_pools(dev);
2006         nvme_dev_unmap(dev);
2007         nvme_put_ctrl(&dev->ctrl);
2008 }
2009
2010 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2011 {
2012         int ret = 0;
2013
2014         if (numvfs == 0) {
2015                 if (pci_vfs_assigned(pdev)) {
2016                         dev_warn(&pdev->dev,
2017                                 "Cannot disable SR-IOV VFs while assigned\n");
2018                         return -EPERM;
2019                 }
2020                 pci_disable_sriov(pdev);
2021                 return 0;
2022         }
2023
2024         ret = pci_enable_sriov(pdev, numvfs);
2025         return ret ? ret : numvfs;
2026 }
2027
2028 #ifdef CONFIG_PM_SLEEP
2029 static int nvme_suspend(struct device *dev)
2030 {
2031         struct pci_dev *pdev = to_pci_dev(dev);
2032         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2033
2034         nvme_dev_disable(ndev, true);
2035         return 0;
2036 }
2037
2038 static int nvme_resume(struct device *dev)
2039 {
2040         struct pci_dev *pdev = to_pci_dev(dev);
2041         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2042
2043         nvme_reset(ndev);
2044         return 0;
2045 }
2046 #endif
2047
2048 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2049
2050 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2051                                                 pci_channel_state_t state)
2052 {
2053         struct nvme_dev *dev = pci_get_drvdata(pdev);
2054
2055         /*
2056          * A frozen channel requires a reset. When detected, this method will
2057          * shutdown the controller to quiesce. The controller will be restarted
2058          * after the slot reset through driver's slot_reset callback.
2059          */
2060         switch (state) {
2061         case pci_channel_io_normal:
2062                 return PCI_ERS_RESULT_CAN_RECOVER;
2063         case pci_channel_io_frozen:
2064                 dev_warn(dev->ctrl.device,
2065                         "frozen state error detected, reset controller\n");
2066                 nvme_dev_disable(dev, false);
2067                 return PCI_ERS_RESULT_NEED_RESET;
2068         case pci_channel_io_perm_failure:
2069                 dev_warn(dev->ctrl.device,
2070                         "failure state error detected, request disconnect\n");
2071                 return PCI_ERS_RESULT_DISCONNECT;
2072         }
2073         return PCI_ERS_RESULT_NEED_RESET;
2074 }
2075
2076 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2077 {
2078         struct nvme_dev *dev = pci_get_drvdata(pdev);
2079
2080         dev_info(dev->ctrl.device, "restart after slot reset\n");
2081         pci_restore_state(pdev);
2082         nvme_reset(dev);
2083         return PCI_ERS_RESULT_RECOVERED;
2084 }
2085
2086 static void nvme_error_resume(struct pci_dev *pdev)
2087 {
2088         pci_cleanup_aer_uncorrect_error_status(pdev);
2089 }
2090
2091 static const struct pci_error_handlers nvme_err_handler = {
2092         .error_detected = nvme_error_detected,
2093         .slot_reset     = nvme_slot_reset,
2094         .resume         = nvme_error_resume,
2095         .reset_notify   = nvme_reset_notify,
2096 };
2097
2098 static const struct pci_device_id nvme_id_table[] = {
2099         { PCI_VDEVICE(INTEL, 0x0953),
2100                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2101                                 NVME_QUIRK_DISCARD_ZEROES, },
2102         { PCI_VDEVICE(INTEL, 0x0a53),
2103                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2104                                 NVME_QUIRK_DISCARD_ZEROES, },
2105         { PCI_VDEVICE(INTEL, 0x0a54),
2106                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2107                                 NVME_QUIRK_DISCARD_ZEROES, },
2108         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2109                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2110         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
2111                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2112         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
2113                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2114         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2115         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2116         { 0, }
2117 };
2118 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2119
2120 static struct pci_driver nvme_driver = {
2121         .name           = "nvme",
2122         .id_table       = nvme_id_table,
2123         .probe          = nvme_probe,
2124         .remove         = nvme_remove,
2125         .shutdown       = nvme_shutdown,
2126         .driver         = {
2127                 .pm     = &nvme_dev_pm_ops,
2128         },
2129         .sriov_configure = nvme_pci_sriov_configure,
2130         .err_handler    = &nvme_err_handler,
2131 };
2132
2133 static int __init nvme_init(void)
2134 {
2135         int result;
2136
2137         nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2138         if (!nvme_workq)
2139                 return -ENOMEM;
2140
2141         result = pci_register_driver(&nvme_driver);
2142         if (result)
2143                 destroy_workqueue(nvme_workq);
2144         return result;
2145 }
2146
2147 static void __exit nvme_exit(void)
2148 {
2149         pci_unregister_driver(&nvme_driver);
2150         destroy_workqueue(nvme_workq);
2151         _nvme_check_size();
2152 }
2153
2154 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2155 MODULE_LICENSE("GPL");
2156 MODULE_VERSION("1.0");
2157 module_init(nvme_init);
2158 module_exit(nvme_exit);