2 * PCIe host controller driver for Freescale i.MX6 SoCs
4 * Copyright (C) 2013 Kosagi
5 * http://www.kosagi.com
7 * Author: Sean Cross <xobs@kosagi.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/gpio.h>
17 #include <linux/kernel.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
20 #include <linux/module.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_device.h>
23 #include <linux/pci.h>
24 #include <linux/platform_device.h>
25 #include <linux/regmap.h>
26 #include <linux/resource.h>
27 #include <linux/signal.h>
28 #include <linux/types.h>
29 #include <linux/interrupt.h>
31 #include "pcie-designware.h"
33 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
35 enum imx6_pcie_variants {
44 bool gpio_active_high;
47 struct clk *pcie_inbound_axi;
49 struct regmap *iomuxc_gpr;
50 enum imx6_pcie_variants variant;
52 u32 tx_deemph_gen2_3p5db;
53 u32 tx_deemph_gen2_6db;
59 /* PCIe Root Complex registers (memory-mapped) */
60 #define PCIE_RC_LCR 0x7c
61 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
62 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
63 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
65 #define PCIE_RC_LCSR 0x80
67 /* PCIe Port Logic registers (memory-mapped) */
68 #define PL_OFFSET 0x700
69 #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
70 #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
71 #define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
72 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
73 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
74 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
75 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4)
77 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
78 #define PCIE_PHY_CTRL_DATA_LOC 0
79 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
80 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
81 #define PCIE_PHY_CTRL_WR_LOC 18
82 #define PCIE_PHY_CTRL_RD_LOC 19
84 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
85 #define PCIE_PHY_STAT_ACK_LOC 16
87 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
88 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
90 /* PHY registers (not memory-mapped) */
91 #define PCIE_PHY_RX_ASIC_OUT 0x100D
92 #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0)
94 #define PHY_RX_OVRD_IN_LO 0x1005
95 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
96 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
98 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
100 struct dw_pcie *pci = imx6_pcie->pci;
102 u32 max_iterations = 10;
103 u32 wait_counter = 0;
106 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
107 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
114 } while (wait_counter < max_iterations);
119 static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
121 struct dw_pcie *pci = imx6_pcie->pci;
125 val = addr << PCIE_PHY_CTRL_DATA_LOC;
126 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
128 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
129 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
131 ret = pcie_phy_poll_ack(imx6_pcie, 1);
135 val = addr << PCIE_PHY_CTRL_DATA_LOC;
136 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
138 return pcie_phy_poll_ack(imx6_pcie, 0);
141 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
142 static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
144 struct dw_pcie *pci = imx6_pcie->pci;
148 ret = pcie_phy_wait_ack(imx6_pcie, addr);
152 /* assert Read signal */
153 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
154 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
156 ret = pcie_phy_poll_ack(imx6_pcie, 1);
160 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
161 *data = val & 0xffff;
163 /* deassert Read signal */
164 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
166 return pcie_phy_poll_ack(imx6_pcie, 0);
169 static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
171 struct dw_pcie *pci = imx6_pcie->pci;
177 ret = pcie_phy_wait_ack(imx6_pcie, addr);
181 var = data << PCIE_PHY_CTRL_DATA_LOC;
182 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
185 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
186 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
188 ret = pcie_phy_poll_ack(imx6_pcie, 1);
192 /* deassert cap data */
193 var = data << PCIE_PHY_CTRL_DATA_LOC;
194 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
196 /* wait for ack de-assertion */
197 ret = pcie_phy_poll_ack(imx6_pcie, 0);
201 /* assert wr signal */
202 var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
203 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
206 ret = pcie_phy_poll_ack(imx6_pcie, 1);
210 /* deassert wr signal */
211 var = data << PCIE_PHY_CTRL_DATA_LOC;
212 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
214 /* wait for ack de-assertion */
215 ret = pcie_phy_poll_ack(imx6_pcie, 0);
219 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0);
224 static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
228 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
229 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
230 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
231 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
233 usleep_range(2000, 3000);
235 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
236 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
237 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
238 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
241 /* Added for PCI abort handling */
242 static int imx6q_pcie_abort_handler(unsigned long addr,
243 unsigned int fsr, struct pt_regs *regs)
248 static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
250 switch (imx6_pcie->variant) {
252 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
253 IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
254 IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
255 /* Force PCIe PHY reset */
256 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
257 IMX6SX_GPR5_PCIE_BTNRST_RESET,
258 IMX6SX_GPR5_PCIE_BTNRST_RESET);
261 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
262 IMX6Q_GPR1_PCIE_SW_RST,
263 IMX6Q_GPR1_PCIE_SW_RST);
266 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
267 IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
268 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
269 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
274 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
276 struct dw_pcie *pci = imx6_pcie->pci;
277 struct device *dev = pci->dev;
280 switch (imx6_pcie->variant) {
282 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
284 dev_err(dev, "unable to enable pcie_axi clock\n");
288 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
289 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
291 case IMX6QP: /* FALLTHROUGH */
293 /* power up core phy and enable ref clock */
294 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
295 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
297 * the async reset input need ref clock to sync internally,
298 * when the ref clock comes after reset, internal synced
299 * reset time is too short, cannot meet the requirement.
300 * add one ~10us delay here.
303 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
304 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
311 static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
313 struct dw_pcie *pci = imx6_pcie->pci;
314 struct device *dev = pci->dev;
317 ret = clk_prepare_enable(imx6_pcie->pcie_phy);
319 dev_err(dev, "unable to enable pcie_phy clock\n");
323 ret = clk_prepare_enable(imx6_pcie->pcie_bus);
325 dev_err(dev, "unable to enable pcie_bus clock\n");
329 ret = clk_prepare_enable(imx6_pcie->pcie);
331 dev_err(dev, "unable to enable pcie clock\n");
335 ret = imx6_pcie_enable_ref_clk(imx6_pcie);
337 dev_err(dev, "unable to enable pcie ref clock\n");
341 /* allow the clocks to stabilize */
342 usleep_range(200, 500);
344 /* Some boards don't have PCIe reset GPIO. */
345 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
346 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
347 imx6_pcie->gpio_active_high);
349 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
350 !imx6_pcie->gpio_active_high);
353 switch (imx6_pcie->variant) {
355 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
356 IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
359 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
360 IMX6Q_GPR1_PCIE_SW_RST, 0);
362 usleep_range(200, 500);
364 case IMX6Q: /* Nothing to do */
371 clk_disable_unprepare(imx6_pcie->pcie);
373 clk_disable_unprepare(imx6_pcie->pcie_bus);
375 clk_disable_unprepare(imx6_pcie->pcie_phy);
378 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
380 if (imx6_pcie->variant == IMX6SX)
381 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
382 IMX6SX_GPR12_PCIE_RX_EQ_MASK,
383 IMX6SX_GPR12_PCIE_RX_EQ_2);
385 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
386 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
388 /* configure constant input signal to the pcie ctrl and phy */
389 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
390 IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
391 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
392 IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
394 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
395 IMX6Q_GPR8_TX_DEEMPH_GEN1,
396 imx6_pcie->tx_deemph_gen1 << 0);
397 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
398 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
399 imx6_pcie->tx_deemph_gen2_3p5db << 6);
400 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
401 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
402 imx6_pcie->tx_deemph_gen2_6db << 12);
403 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
404 IMX6Q_GPR8_TX_SWING_FULL,
405 imx6_pcie->tx_swing_full << 18);
406 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
407 IMX6Q_GPR8_TX_SWING_LOW,
408 imx6_pcie->tx_swing_low << 25);
411 static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
413 struct dw_pcie *pci = imx6_pcie->pci;
414 struct device *dev = pci->dev;
416 /* check if the link is up or not */
417 if (!dw_pcie_wait_for_link(pci))
420 dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
421 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
422 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
426 static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
428 struct dw_pcie *pci = imx6_pcie->pci;
429 struct device *dev = pci->dev;
431 unsigned int retries;
433 for (retries = 0; retries < 200; retries++) {
434 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
435 /* Test if the speed change finished. */
436 if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
438 usleep_range(100, 1000);
441 dev_err(dev, "Speed change timeout\n");
445 static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
447 struct imx6_pcie *imx6_pcie = arg;
448 struct dw_pcie *pci = imx6_pcie->pci;
449 struct pcie_port *pp = &pci->pp;
451 return dw_handle_msi_irq(pp);
454 static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
456 struct dw_pcie *pci = imx6_pcie->pci;
457 struct device *dev = pci->dev;
462 * Force Gen1 operation when starting the link. In case the link is
463 * started in Gen2 mode, there is a possibility the devices on the
464 * bus will not be detected at all. This happens with PCIe switches.
466 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
467 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
468 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
469 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
472 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
473 IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
475 ret = imx6_pcie_wait_for_link(imx6_pcie);
479 if (imx6_pcie->link_gen == 2) {
480 /* Allow Gen2 mode after the link is up. */
481 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
482 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
483 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
484 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
486 dev_info(dev, "Link: Gen2 disabled\n");
490 * Start Directed Speed Change so the best possible speed both link
491 * partners support can be negotiated.
493 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
494 tmp |= PORT_LOGIC_SPEED_CHANGE;
495 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
497 ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
499 dev_err(dev, "Failed to bring link up!\n");
503 /* Make sure link training is finished as well! */
504 ret = imx6_pcie_wait_for_link(imx6_pcie);
506 dev_err(dev, "Failed to bring link up!\n");
510 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR);
511 dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
515 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
516 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
517 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
518 imx6_pcie_reset_phy(imx6_pcie);
522 static void imx6_pcie_host_init(struct pcie_port *pp)
524 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
525 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
527 imx6_pcie_assert_core_reset(imx6_pcie);
528 imx6_pcie_init_phy(imx6_pcie);
529 imx6_pcie_deassert_core_reset(imx6_pcie);
530 dw_pcie_setup_rc(pp);
531 imx6_pcie_establish_link(imx6_pcie);
533 if (IS_ENABLED(CONFIG_PCI_MSI))
534 dw_pcie_msi_init(pp);
537 static int imx6_pcie_link_up(struct dw_pcie *pci)
539 return dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1) &
540 PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
543 static struct dw_pcie_host_ops imx6_pcie_host_ops = {
544 .host_init = imx6_pcie_host_init,
547 static int __init imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,
548 struct platform_device *pdev)
550 struct dw_pcie *pci = imx6_pcie->pci;
551 struct pcie_port *pp = &pci->pp;
552 struct device *dev = &pdev->dev;
555 if (IS_ENABLED(CONFIG_PCI_MSI)) {
556 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
557 if (pp->msi_irq <= 0) {
558 dev_err(dev, "failed to get MSI irq\n");
562 ret = devm_request_irq(dev, pp->msi_irq,
563 imx6_pcie_msi_handler,
564 IRQF_SHARED | IRQF_NO_THREAD,
565 "mx6-pcie-msi", imx6_pcie);
567 dev_err(dev, "failed to request MSI irq\n");
572 pp->root_bus_nr = -1;
573 pp->ops = &imx6_pcie_host_ops;
575 ret = dw_pcie_host_init(pp);
577 dev_err(dev, "failed to initialize host\n");
584 static const struct dw_pcie_ops dw_pcie_ops = {
585 .link_up = imx6_pcie_link_up,
588 static int __init imx6_pcie_probe(struct platform_device *pdev)
590 struct device *dev = &pdev->dev;
592 struct imx6_pcie *imx6_pcie;
593 struct resource *dbi_base;
594 struct device_node *node = dev->of_node;
597 imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
601 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
606 pci->ops = &dw_pcie_ops;
608 imx6_pcie->pci = pci;
610 (enum imx6_pcie_variants)of_device_get_match_data(dev);
612 /* Added for PCI abort handling */
613 hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
614 "imprecise external abort");
616 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
617 pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
618 if (IS_ERR(pci->dbi_base))
619 return PTR_ERR(pci->dbi_base);
622 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
623 imx6_pcie->gpio_active_high = of_property_read_bool(node,
624 "reset-gpio-active-high");
625 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
626 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
627 imx6_pcie->gpio_active_high ?
628 GPIOF_OUT_INIT_HIGH :
632 dev_err(dev, "unable to get reset gpio\n");
638 imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
639 if (IS_ERR(imx6_pcie->pcie_phy)) {
640 dev_err(dev, "pcie_phy clock source missing or invalid\n");
641 return PTR_ERR(imx6_pcie->pcie_phy);
644 imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
645 if (IS_ERR(imx6_pcie->pcie_bus)) {
646 dev_err(dev, "pcie_bus clock source missing or invalid\n");
647 return PTR_ERR(imx6_pcie->pcie_bus);
650 imx6_pcie->pcie = devm_clk_get(dev, "pcie");
651 if (IS_ERR(imx6_pcie->pcie)) {
652 dev_err(dev, "pcie clock source missing or invalid\n");
653 return PTR_ERR(imx6_pcie->pcie);
656 if (imx6_pcie->variant == IMX6SX) {
657 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
659 if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
660 dev_err(dev, "pcie_inbound_axi clock missing or invalid\n");
661 return PTR_ERR(imx6_pcie->pcie_inbound_axi);
665 /* Grab GPR config register range */
666 imx6_pcie->iomuxc_gpr =
667 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
668 if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
669 dev_err(dev, "unable to find iomuxc registers\n");
670 return PTR_ERR(imx6_pcie->iomuxc_gpr);
673 /* Grab PCIe PHY Tx Settings */
674 if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
675 &imx6_pcie->tx_deemph_gen1))
676 imx6_pcie->tx_deemph_gen1 = 0;
678 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
679 &imx6_pcie->tx_deemph_gen2_3p5db))
680 imx6_pcie->tx_deemph_gen2_3p5db = 0;
682 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
683 &imx6_pcie->tx_deemph_gen2_6db))
684 imx6_pcie->tx_deemph_gen2_6db = 20;
686 if (of_property_read_u32(node, "fsl,tx-swing-full",
687 &imx6_pcie->tx_swing_full))
688 imx6_pcie->tx_swing_full = 127;
690 if (of_property_read_u32(node, "fsl,tx-swing-low",
691 &imx6_pcie->tx_swing_low))
692 imx6_pcie->tx_swing_low = 127;
694 /* Limit link speed */
695 ret = of_property_read_u32(node, "fsl,max-link-speed",
696 &imx6_pcie->link_gen);
698 imx6_pcie->link_gen = 1;
700 platform_set_drvdata(pdev, imx6_pcie);
702 ret = imx6_add_pcie_port(imx6_pcie, pdev);
709 static void imx6_pcie_shutdown(struct platform_device *pdev)
711 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
713 /* bring down link, so bootloader gets clean state in case of reboot */
714 imx6_pcie_assert_core_reset(imx6_pcie);
717 static const struct of_device_id imx6_pcie_of_match[] = {
718 { .compatible = "fsl,imx6q-pcie", .data = (void *)IMX6Q, },
719 { .compatible = "fsl,imx6sx-pcie", .data = (void *)IMX6SX, },
720 { .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, },
724 static struct platform_driver imx6_pcie_driver = {
726 .name = "imx6q-pcie",
727 .of_match_table = imx6_pcie_of_match,
729 .shutdown = imx6_pcie_shutdown,
732 static int __init imx6_pcie_init(void)
734 return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
736 device_initcall(imx6_pcie_init);