3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/export.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/proc_fs.h>
17 #include <linux/msi.h>
18 #include <linux/smp.h>
19 #include <linux/errno.h>
21 #include <linux/slab.h>
25 static int pci_msi_enable = 1;
26 int pci_msi_ignore_mask;
28 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
33 struct msi_controller * __weak pcibios_msi_controller(struct pci_dev *dev)
38 static struct msi_controller *pci_msi_controller(struct pci_dev *dev)
40 struct msi_controller *msi_ctrl = dev->bus->msi;
45 return pcibios_msi_controller(dev);
48 int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
50 struct msi_controller *chip = pci_msi_controller(dev);
53 if (!chip || !chip->setup_irq)
56 err = chip->setup_irq(chip, dev, desc);
60 irq_set_chip_data(desc->irq, chip);
65 void __weak arch_teardown_msi_irq(unsigned int irq)
67 struct msi_controller *chip = irq_get_chip_data(irq);
69 if (!chip || !chip->teardown_irq)
72 chip->teardown_irq(chip, irq);
75 int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
77 struct msi_desc *entry;
81 * If an architecture wants to support multiple MSI, it needs to
82 * override arch_setup_msi_irqs()
84 if (type == PCI_CAP_ID_MSI && nvec > 1)
87 list_for_each_entry(entry, &dev->msi_list, list) {
88 ret = arch_setup_msi_irq(dev, entry);
99 * We have a default implementation available as a separate non-weak
100 * function, as it is used by the Xen x86 PCI code
102 void default_teardown_msi_irqs(struct pci_dev *dev)
104 struct msi_desc *entry;
106 list_for_each_entry(entry, &dev->msi_list, list) {
110 if (entry->nvec_used)
111 nvec = entry->nvec_used;
113 nvec = 1 << entry->msi_attrib.multiple;
114 for (i = 0; i < nvec; i++)
115 arch_teardown_msi_irq(entry->irq + i);
119 void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
121 return default_teardown_msi_irqs(dev);
124 static void default_restore_msi_irq(struct pci_dev *dev, int irq)
126 struct msi_desc *entry;
129 if (dev->msix_enabled) {
130 list_for_each_entry(entry, &dev->msi_list, list) {
131 if (irq == entry->irq)
134 } else if (dev->msi_enabled) {
135 entry = irq_get_msi_desc(irq);
139 __write_msi_msg(entry, &entry->msg);
142 void __weak arch_restore_msi_irqs(struct pci_dev *dev)
144 return default_restore_msi_irqs(dev);
147 static void msi_set_enable(struct pci_dev *dev, int enable)
151 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
152 control &= ~PCI_MSI_FLAGS_ENABLE;
154 control |= PCI_MSI_FLAGS_ENABLE;
155 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
158 static void msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
162 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
165 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
168 static inline __attribute_const__ u32 msi_mask(unsigned x)
170 /* Don't shift by >= width of type */
173 return (1 << (1 << x)) - 1;
177 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
178 * mask all MSI interrupts by clearing the MSI enable bit does not work
179 * reliably as devices without an INTx disable bit will then generate a
180 * level IRQ which will never be cleared.
182 u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
184 u32 mask_bits = desc->masked;
186 if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
191 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
196 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
198 desc->masked = __msi_mask_irq(desc, mask, flag);
202 * This internal function does not flush PCI writes to the device.
203 * All users must ensure that they read from the device before either
204 * assuming that the device state is up to date, or returning out of this
205 * file. This saves a few milliseconds when initialising devices with lots
206 * of MSI-X interrupts.
208 u32 __msix_mask_irq(struct msi_desc *desc, u32 flag)
210 u32 mask_bits = desc->masked;
211 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
212 PCI_MSIX_ENTRY_VECTOR_CTRL;
214 if (pci_msi_ignore_mask)
217 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
219 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
220 writel(mask_bits, desc->mask_base + offset);
225 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
227 desc->masked = __msix_mask_irq(desc, flag);
230 static void msi_set_mask_bit(struct irq_data *data, u32 flag)
232 struct msi_desc *desc = irq_data_get_msi(data);
234 if (desc->msi_attrib.is_msix) {
235 msix_mask_irq(desc, flag);
236 readl(desc->mask_base); /* Flush write to device */
238 unsigned offset = data->irq - desc->irq;
239 msi_mask_irq(desc, 1 << offset, flag << offset);
243 void mask_msi_irq(struct irq_data *data)
245 msi_set_mask_bit(data, 1);
248 void unmask_msi_irq(struct irq_data *data)
250 msi_set_mask_bit(data, 0);
253 void default_restore_msi_irqs(struct pci_dev *dev)
255 struct msi_desc *entry;
257 list_for_each_entry(entry, &dev->msi_list, list) {
258 default_restore_msi_irq(dev, entry->irq);
262 void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
264 BUG_ON(entry->dev->current_state != PCI_D0);
266 if (entry->msi_attrib.is_msix) {
267 void __iomem *base = entry->mask_base +
268 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
270 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
271 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
272 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
274 struct pci_dev *dev = entry->dev;
275 int pos = dev->msi_cap;
278 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
280 if (entry->msi_attrib.is_64) {
281 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
283 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
286 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
292 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
294 struct msi_desc *entry = irq_get_msi_desc(irq);
296 __read_msi_msg(entry, msg);
299 void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
301 /* Assert that the cache is valid, assuming that
302 * valid messages are not all-zeroes. */
303 BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo |
309 void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
311 struct msi_desc *entry = irq_get_msi_desc(irq);
313 __get_cached_msi_msg(entry, msg);
315 EXPORT_SYMBOL_GPL(get_cached_msi_msg);
317 void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
319 if (entry->dev->current_state != PCI_D0) {
320 /* Don't touch the hardware now */
321 } else if (entry->msi_attrib.is_msix) {
323 base = entry->mask_base +
324 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
326 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
327 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
328 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
330 struct pci_dev *dev = entry->dev;
331 int pos = dev->msi_cap;
334 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
335 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
336 msgctl |= entry->msi_attrib.multiple << 4;
337 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
339 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
341 if (entry->msi_attrib.is_64) {
342 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
344 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
347 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
354 void write_msi_msg(unsigned int irq, struct msi_msg *msg)
356 struct msi_desc *entry = irq_get_msi_desc(irq);
358 __write_msi_msg(entry, msg);
360 EXPORT_SYMBOL_GPL(write_msi_msg);
362 static void free_msi_irqs(struct pci_dev *dev)
364 struct msi_desc *entry, *tmp;
365 struct attribute **msi_attrs;
366 struct device_attribute *dev_attr;
369 list_for_each_entry(entry, &dev->msi_list, list) {
373 if (entry->nvec_used)
374 nvec = entry->nvec_used;
376 nvec = 1 << entry->msi_attrib.multiple;
377 for (i = 0; i < nvec; i++)
378 BUG_ON(irq_has_action(entry->irq + i));
381 arch_teardown_msi_irqs(dev);
383 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
384 if (entry->msi_attrib.is_msix) {
385 if (list_is_last(&entry->list, &dev->msi_list))
386 iounmap(entry->mask_base);
389 list_del(&entry->list);
393 if (dev->msi_irq_groups) {
394 sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
395 msi_attrs = dev->msi_irq_groups[0]->attrs;
396 while (msi_attrs[count]) {
397 dev_attr = container_of(msi_attrs[count],
398 struct device_attribute, attr);
399 kfree(dev_attr->attr.name);
404 kfree(dev->msi_irq_groups[0]);
405 kfree(dev->msi_irq_groups);
406 dev->msi_irq_groups = NULL;
410 static struct msi_desc *alloc_msi_entry(struct pci_dev *dev)
412 struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL);
416 INIT_LIST_HEAD(&desc->list);
422 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
424 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
425 pci_intx(dev, enable);
428 static void __pci_restore_msi_state(struct pci_dev *dev)
431 struct msi_desc *entry;
433 if (!dev->msi_enabled)
436 entry = irq_get_msi_desc(dev->irq);
438 pci_intx_for_msi(dev, 0);
439 msi_set_enable(dev, 0);
440 arch_restore_msi_irqs(dev);
442 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
443 msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),
445 control &= ~PCI_MSI_FLAGS_QSIZE;
446 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
447 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
450 static void __pci_restore_msix_state(struct pci_dev *dev)
452 struct msi_desc *entry;
454 if (!dev->msix_enabled)
456 BUG_ON(list_empty(&dev->msi_list));
458 /* route the table */
459 pci_intx_for_msi(dev, 0);
460 msix_clear_and_set_ctrl(dev, 0,
461 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
463 arch_restore_msi_irqs(dev);
464 list_for_each_entry(entry, &dev->msi_list, list) {
465 msix_mask_irq(entry, entry->masked);
468 msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
471 void pci_restore_msi_state(struct pci_dev *dev)
473 __pci_restore_msi_state(dev);
474 __pci_restore_msix_state(dev);
476 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
478 static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
481 struct msi_desc *entry;
485 retval = kstrtoul(attr->attr.name, 10, &irq);
489 entry = irq_get_msi_desc(irq);
491 return sprintf(buf, "%s\n",
492 entry->msi_attrib.is_msix ? "msix" : "msi");
497 static int populate_msi_sysfs(struct pci_dev *pdev)
499 struct attribute **msi_attrs;
500 struct attribute *msi_attr;
501 struct device_attribute *msi_dev_attr;
502 struct attribute_group *msi_irq_group;
503 const struct attribute_group **msi_irq_groups;
504 struct msi_desc *entry;
509 /* Determine how many msi entries we have */
510 list_for_each_entry(entry, &pdev->msi_list, list) {
516 /* Dynamically create the MSI attributes for the PCI device */
517 msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL);
520 list_for_each_entry(entry, &pdev->msi_list, list) {
521 msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
524 msi_attrs[count] = &msi_dev_attr->attr;
526 sysfs_attr_init(&msi_dev_attr->attr);
527 msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
529 if (!msi_dev_attr->attr.name)
531 msi_dev_attr->attr.mode = S_IRUGO;
532 msi_dev_attr->show = msi_mode_show;
536 msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
539 msi_irq_group->name = "msi_irqs";
540 msi_irq_group->attrs = msi_attrs;
542 msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL);
544 goto error_irq_group;
545 msi_irq_groups[0] = msi_irq_group;
547 ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
549 goto error_irq_groups;
550 pdev->msi_irq_groups = msi_irq_groups;
555 kfree(msi_irq_groups);
557 kfree(msi_irq_group);
560 msi_attr = msi_attrs[count];
562 msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
563 kfree(msi_attr->name);
566 msi_attr = msi_attrs[count];
572 static struct msi_desc *msi_setup_entry(struct pci_dev *dev)
575 struct msi_desc *entry;
577 /* MSI Entry Initialization */
578 entry = alloc_msi_entry(dev);
582 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
584 entry->msi_attrib.is_msix = 0;
585 entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
586 entry->msi_attrib.entry_nr = 0;
587 entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
588 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
589 entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
591 if (control & PCI_MSI_FLAGS_64BIT)
592 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
594 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
596 /* Save the initial mask status */
597 if (entry->msi_attrib.maskbit)
598 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
604 * msi_capability_init - configure device's MSI capability structure
605 * @dev: pointer to the pci_dev data structure of MSI device function
606 * @nvec: number of interrupts to allocate
608 * Setup the MSI capability structure of the device with the requested
609 * number of interrupts. A return value of zero indicates the successful
610 * setup of an entry with the new MSI irq. A negative return value indicates
611 * an error, and a positive return value indicates the number of interrupts
612 * which could have been allocated.
614 static int msi_capability_init(struct pci_dev *dev, int nvec)
616 struct msi_desc *entry;
620 msi_set_enable(dev, 0); /* Disable MSI during set up */
622 entry = msi_setup_entry(dev);
626 /* All MSIs are unmasked by default, Mask them all */
627 mask = msi_mask(entry->msi_attrib.multi_cap);
628 msi_mask_irq(entry, mask, mask);
630 list_add_tail(&entry->list, &dev->msi_list);
632 /* Configure MSI capability structure */
633 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
635 msi_mask_irq(entry, mask, ~mask);
640 ret = populate_msi_sysfs(dev);
642 msi_mask_irq(entry, mask, ~mask);
647 /* Set MSI enabled bits */
648 pci_intx_for_msi(dev, 0);
649 msi_set_enable(dev, 1);
650 dev->msi_enabled = 1;
652 dev->irq = entry->irq;
656 static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
658 resource_size_t phys_addr;
662 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
664 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
665 table_offset &= PCI_MSIX_TABLE_OFFSET;
666 phys_addr = pci_resource_start(dev, bir) + table_offset;
668 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
671 static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
672 struct msix_entry *entries, int nvec)
674 struct msi_desc *entry;
677 for (i = 0; i < nvec; i++) {
678 entry = alloc_msi_entry(dev);
684 /* No enough memory. Don't try again */
688 entry->msi_attrib.is_msix = 1;
689 entry->msi_attrib.is_64 = 1;
690 entry->msi_attrib.entry_nr = entries[i].entry;
691 entry->msi_attrib.default_irq = dev->irq;
692 entry->mask_base = base;
694 list_add_tail(&entry->list, &dev->msi_list);
700 static void msix_program_entries(struct pci_dev *dev,
701 struct msix_entry *entries)
703 struct msi_desc *entry;
706 list_for_each_entry(entry, &dev->msi_list, list) {
707 int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +
708 PCI_MSIX_ENTRY_VECTOR_CTRL;
710 entries[i].vector = entry->irq;
711 irq_set_msi_desc(entry->irq, entry);
712 entry->masked = readl(entry->mask_base + offset);
713 msix_mask_irq(entry, 1);
719 * msix_capability_init - configure device's MSI-X capability
720 * @dev: pointer to the pci_dev data structure of MSI-X device function
721 * @entries: pointer to an array of struct msix_entry entries
722 * @nvec: number of @entries
724 * Setup the MSI-X capability structure of device function with a
725 * single MSI-X irq. A return of zero indicates the successful setup of
726 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
728 static int msix_capability_init(struct pci_dev *dev,
729 struct msix_entry *entries, int nvec)
735 /* Ensure MSI-X is disabled while it is set up */
736 msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
738 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
739 /* Request & Map MSI-X table region */
740 base = msix_map_region(dev, msix_table_size(control));
744 ret = msix_setup_entries(dev, base, entries, nvec);
748 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
753 * Some devices require MSI-X to be enabled before we can touch the
754 * MSI-X registers. We need to mask all the vectors to prevent
755 * interrupts coming in before they're fully set up.
757 msix_clear_and_set_ctrl(dev, 0,
758 PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE);
760 msix_program_entries(dev, entries);
762 ret = populate_msi_sysfs(dev);
766 /* Set MSI-X enabled bits and unmask the function */
767 pci_intx_for_msi(dev, 0);
768 dev->msix_enabled = 1;
770 msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
777 * If we had some success, report the number of irqs
778 * we succeeded in setting up.
780 struct msi_desc *entry;
783 list_for_each_entry(entry, &dev->msi_list, list) {
798 * pci_msi_supported - check whether MSI may be enabled on a device
799 * @dev: pointer to the pci_dev data structure of MSI device function
800 * @nvec: how many MSIs have been requested ?
802 * Look at global flags, the device itself, and its parent buses
803 * to determine if MSI/-X are supported for the device. If MSI/-X is
804 * supported return 1, else return 0.
806 static int pci_msi_supported(struct pci_dev *dev, int nvec)
810 /* MSI must be globally enabled and supported by the device */
814 if (!dev || dev->no_msi || dev->current_state != PCI_D0)
818 * You can't ask to have 0 or less MSIs configured.
820 * b) the list manipulation code assumes nvec >= 1.
826 * Any bridge which does NOT route MSI transactions from its
827 * secondary bus to its primary bus must set NO_MSI flag on
828 * the secondary pci_bus.
829 * We expect only arch-specific PCI host bus controller driver
830 * or quirks for specific PCI bridges to be setting NO_MSI.
832 for (bus = dev->bus; bus; bus = bus->parent)
833 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
840 * pci_msi_vec_count - Return the number of MSI vectors a device can send
841 * @dev: device to report about
843 * This function returns the number of MSI vectors a device requested via
844 * Multiple Message Capable register. It returns a negative errno if the
845 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
846 * and returns a power of two, up to a maximum of 2^5 (32), according to the
849 int pci_msi_vec_count(struct pci_dev *dev)
857 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
858 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
862 EXPORT_SYMBOL(pci_msi_vec_count);
864 void pci_msi_shutdown(struct pci_dev *dev)
866 struct msi_desc *desc;
869 if (!pci_msi_enable || !dev || !dev->msi_enabled)
872 BUG_ON(list_empty(&dev->msi_list));
873 desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
875 msi_set_enable(dev, 0);
876 pci_intx_for_msi(dev, 1);
877 dev->msi_enabled = 0;
879 /* Return the device with MSI unmasked as initial states */
880 mask = msi_mask(desc->msi_attrib.multi_cap);
881 /* Keep cached state to be restored */
882 __msi_mask_irq(desc, mask, ~mask);
884 /* Restore dev->irq to its default pin-assertion irq */
885 dev->irq = desc->msi_attrib.default_irq;
888 void pci_disable_msi(struct pci_dev *dev)
890 if (!pci_msi_enable || !dev || !dev->msi_enabled)
893 pci_msi_shutdown(dev);
896 EXPORT_SYMBOL(pci_disable_msi);
899 * pci_msix_vec_count - return the number of device's MSI-X table entries
900 * @dev: pointer to the pci_dev data structure of MSI-X device function
901 * This function returns the number of device's MSI-X table entries and
902 * therefore the number of MSI-X vectors device is capable of sending.
903 * It returns a negative errno if the device is not capable of sending MSI-X
906 int pci_msix_vec_count(struct pci_dev *dev)
913 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
914 return msix_table_size(control);
916 EXPORT_SYMBOL(pci_msix_vec_count);
919 * pci_enable_msix - configure device's MSI-X capability structure
920 * @dev: pointer to the pci_dev data structure of MSI-X device function
921 * @entries: pointer to an array of MSI-X entries
922 * @nvec: number of MSI-X irqs requested for allocation by device driver
924 * Setup the MSI-X capability structure of device function with the number
925 * of requested irqs upon its software driver call to request for
926 * MSI-X mode enabled on its hardware device function. A return of zero
927 * indicates the successful configuration of MSI-X capability structure
928 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
929 * Or a return of > 0 indicates that driver request is exceeding the number
930 * of irqs or MSI-X vectors available. Driver should use the returned value to
931 * re-send its request.
933 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
938 if (!pci_msi_supported(dev, nvec))
944 nr_entries = pci_msix_vec_count(dev);
947 if (nvec > nr_entries)
950 /* Check for any invalid entries */
951 for (i = 0; i < nvec; i++) {
952 if (entries[i].entry >= nr_entries)
953 return -EINVAL; /* invalid entry */
954 for (j = i + 1; j < nvec; j++) {
955 if (entries[i].entry == entries[j].entry)
956 return -EINVAL; /* duplicate entry */
959 WARN_ON(!!dev->msix_enabled);
961 /* Check whether driver already requested for MSI irq */
962 if (dev->msi_enabled) {
963 dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
966 return msix_capability_init(dev, entries, nvec);
968 EXPORT_SYMBOL(pci_enable_msix);
970 void pci_msix_shutdown(struct pci_dev *dev)
972 struct msi_desc *entry;
974 if (!pci_msi_enable || !dev || !dev->msix_enabled)
977 /* Return the device with MSI-X masked as initial states */
978 list_for_each_entry(entry, &dev->msi_list, list) {
979 /* Keep cached states to be restored */
980 __msix_mask_irq(entry, 1);
983 msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
984 pci_intx_for_msi(dev, 1);
985 dev->msix_enabled = 0;
988 void pci_disable_msix(struct pci_dev *dev)
990 if (!pci_msi_enable || !dev || !dev->msix_enabled)
993 pci_msix_shutdown(dev);
996 EXPORT_SYMBOL(pci_disable_msix);
998 void pci_no_msi(void)
1004 * pci_msi_enabled - is MSI enabled?
1006 * Returns true if MSI has not been disabled by the command-line option
1009 int pci_msi_enabled(void)
1011 return pci_msi_enable;
1013 EXPORT_SYMBOL(pci_msi_enabled);
1015 void pci_msi_init_pci_dev(struct pci_dev *dev)
1017 INIT_LIST_HEAD(&dev->msi_list);
1019 /* Disable the msi hardware to avoid screaming interrupts
1020 * during boot. This is the power on reset default so
1021 * usually this should be a noop.
1023 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1025 msi_set_enable(dev, 0);
1027 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1029 msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1033 * pci_enable_msi_range - configure device's MSI capability structure
1034 * @dev: device to configure
1035 * @minvec: minimal number of interrupts to configure
1036 * @maxvec: maximum number of interrupts to configure
1038 * This function tries to allocate a maximum possible number of interrupts in a
1039 * range between @minvec and @maxvec. It returns a negative errno if an error
1040 * occurs. If it succeeds, it returns the actual number of interrupts allocated
1041 * and updates the @dev's irq member to the lowest new interrupt number;
1042 * the other interrupt numbers allocated to this device are consecutive.
1044 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec)
1049 if (!pci_msi_supported(dev, minvec))
1052 WARN_ON(!!dev->msi_enabled);
1054 /* Check whether driver already requested MSI-X irqs */
1055 if (dev->msix_enabled) {
1057 "can't enable MSI (MSI-X already enabled)\n");
1061 if (maxvec < minvec)
1064 nvec = pci_msi_vec_count(dev);
1067 else if (nvec < minvec)
1069 else if (nvec > maxvec)
1073 rc = msi_capability_init(dev, nvec);
1076 } else if (rc > 0) {
1085 EXPORT_SYMBOL(pci_enable_msi_range);
1088 * pci_enable_msix_range - configure device's MSI-X capability structure
1089 * @dev: pointer to the pci_dev data structure of MSI-X device function
1090 * @entries: pointer to an array of MSI-X entries
1091 * @minvec: minimum number of MSI-X irqs requested
1092 * @maxvec: maximum number of MSI-X irqs requested
1094 * Setup the MSI-X capability structure of device function with a maximum
1095 * possible number of interrupts in the range between @minvec and @maxvec
1096 * upon its software driver call to request for MSI-X mode enabled on its
1097 * hardware device function. It returns a negative errno if an error occurs.
1098 * If it succeeds, it returns the actual number of interrupts allocated and
1099 * indicates the successful configuration of MSI-X capability structure
1100 * with new allocated MSI-X interrupts.
1102 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1103 int minvec, int maxvec)
1108 if (maxvec < minvec)
1112 rc = pci_enable_msix(dev, entries, nvec);
1115 } else if (rc > 0) {
1124 EXPORT_SYMBOL(pci_enable_msix_range);