drivers/pci/pci.c

   1 /*
   2  * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   3  * Andreas Heppel <aheppel@sysgo.de>
   4  *
   5  * (C) Copyright 2002, 2003
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * PCI routines
  29  */
  30
  31 #include <common.h>
  32
  33 #include <command.h>
  34 #include <asm/processor.h>
  35 #include <asm/io.h>
  36 #include <pci.h>
  37
  38 #define PCI_HOSE_OP(rw, size, type)                                     \
  39 int pci_hose_##rw##_config_##size(struct pci_controller *hose,          \
  40                                   pci_dev_t dev,                        \
  41                                   int offset, type value)               \
  42 {                                                                       \
  43         return hose->rw##_##size(hose, dev, offset, value);             \
  44 }
  45
  46 PCI_HOSE_OP(read, byte, u8 *)
  47 PCI_HOSE_OP(read, word, u16 *)
  48 PCI_HOSE_OP(read, dword, u32 *)
  49 PCI_HOSE_OP(write, byte, u8)
  50 PCI_HOSE_OP(write, word, u16)
  51 PCI_HOSE_OP(write, dword, u32)
  52
  53 #ifndef CONFIG_IXP425
  54 #define PCI_OP(rw, size, type, error_code)                              \
  55 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value)     \
  56 {                                                                       \
  57         struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev));    \
  58                                                                         \
  59         if (!hose)                                                      \
  60         {                                                               \
  61                 error_code;                                             \
  62                 return -1;                                              \
  63         }                                                               \
  64                                                                         \
  65         return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
  66 }
  67
  68 PCI_OP(read, byte, u8 *, *value = 0xff)
  69 PCI_OP(read, word, u16 *, *value = 0xffff)
  70 PCI_OP(read, dword, u32 *, *value = 0xffffffff)
  71 PCI_OP(write, byte, u8, )
  72 PCI_OP(write, word, u16, )
  73 PCI_OP(write, dword, u32, )
  74 #endif  /* CONFIG_IXP425 */
  75
  76 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask)                     \
  77 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
  78                                         pci_dev_t dev,                  \
  79                                         int offset, type val)           \
  80 {                                                                       \
  81         u32 val32;                                                      \
  82                                                                         \
  83         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
  84                 *val = -1;                                              \
  85                 return -1;                                              \
  86         }                                                               \
  87                                                                         \
  88         *val = (val32 >> ((offset & (int)off_mask) * 8));               \
  89                                                                         \
  90         return 0;                                                       \
  91 }
  92
  93 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask)          \
  94 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
  95                                              pci_dev_t dev,             \
  96                                              int offset, type val)      \
  97 {                                                                       \
  98         u32 val32, mask, ldata, shift;                                  \
  99                                                                         \
 100         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
 101                 return -1;                                              \
 102                                                                         \
 103         shift = ((offset & (int)off_mask) * 8);                         \
 104         ldata = (((unsigned long)val) & val_mask) << shift;             \
 105         mask = val_mask << shift;                                       \
 106         val32 = (val32 & ~mask) | ldata;                                \
 107                                                                         \
 108         if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
 109                 return -1;                                              \
 110                                                                         \
 111         return 0;                                                       \
 112 }
 113
 114 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
 115 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
 116 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
 117 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
 118
 119 /*
 120  *
 121  */
 122
 123 static struct pci_controller* hose_head = NULL;
 124
 125 void pci_register_hose(struct pci_controller* hose)
 126 {
 127         struct pci_controller **phose = &hose_head;
 128
 129         while(*phose)
 130                 phose = &(*phose)->next;
 131
 132         hose->next = NULL;
 133
 134         *phose = hose;
 135 }
 136
 137 struct pci_controller *pci_bus_to_hose (int bus)
 138 {
 139         struct pci_controller *hose;
 140
 141         for (hose = hose_head; hose; hose = hose->next)
 142                 if (bus >= hose->first_busno && bus <= hose->last_busno)
 143                         return hose;
 144
 145         printf("pci_bus_to_hose() failed\n");
 146         return NULL;
 147 }
 148
 149 #ifndef CONFIG_IXP425
 150 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
 151 {
 152         struct pci_controller * hose;
 153         u16 vendor, device;
 154         u8 header_type;
 155         pci_dev_t bdf;
 156         int i, bus, found_multi = 0;
 157
 158         for (hose = hose_head; hose; hose = hose->next)
 159         {
 160 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
 161                 for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
 162 #else
 163                 for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
 164 #endif
 165                         for (bdf = PCI_BDF(bus,0,0);
 166 #if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
 167                              bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
 168 #else
 169                              bdf < PCI_BDF(bus+1,0,0);
 170 #endif
 171                              bdf += PCI_BDF(0,0,1))
 172                         {
 173                                 if (!PCI_FUNC(bdf)) {
 174                                         pci_read_config_byte(bdf,
 175                                                              PCI_HEADER_TYPE,
 176                                                              &header_type);
 177
 178                                         found_multi = header_type & 0x80;
 179                                 } else {
 180                                         if (!found_multi)
 181                                                 continue;
 182                                 }
 183
 184                                 pci_read_config_word(bdf,
 185                                                      PCI_VENDOR_ID,
 186                                                      &vendor);
 187                                 pci_read_config_word(bdf,
 188                                                      PCI_DEVICE_ID,
 189                                                      &device);
 190
 191                                 for (i=0; ids[i].vendor != 0; i++)
 192                                         if (vendor == ids[i].vendor &&
 193                                             device == ids[i].device)
 194                                         {
 195                                                 if (index <= 0)
 196                                                         return bdf;
 197
 198                                                 index--;
 199                                         }
 200                         }
 201         }
 202
 203         return (-1);
 204 }
 205 #endif  /* CONFIG_IXP425 */
 206
 207 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
 208 {
 209         static struct pci_device_id ids[2] = {{}, {0, 0}};
 210
 211         ids[0].vendor = vendor;
 212         ids[0].device = device;
 213
 214         return pci_find_devices(ids, index);
 215 }
 216
 217 /*
 218  *
 219  */
 220
 221 int __pci_hose_phys_to_bus (struct pci_controller *hose,
 222                                 phys_addr_t phys_addr,
 223                                 unsigned long flags,
 224                                 unsigned long skip_mask,
 225                                 pci_addr_t *ba)
 226 {
 227         struct pci_region *res;
 228         pci_addr_t bus_addr;
 229         int i;
 230
 231         for (i = 0; i < hose->region_count; i++) {
 232                 res = &hose->regions[i];
 233
 234                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 235                         continue;
 236
 237                 if (res->flags & skip_mask)
 238                         continue;
 239
 240                 bus_addr = phys_addr - res->phys_start + res->bus_start;
 241
 242                 if (bus_addr >= res->bus_start &&
 243                         bus_addr < res->bus_start + res->size) {
 244                         *ba = bus_addr;
 245                         return 0;
 246                 }
 247         }
 248
 249         return 1;
 250 }
 251
 252 pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
 253                                     phys_addr_t phys_addr,
 254                                     unsigned long flags)
 255 {
 256         pci_addr_t bus_addr = 0;
 257         int ret;
 258
 259         if (!hose) {
 260                 puts ("pci_hose_phys_to_bus: invalid hose\n");
 261                 return bus_addr;
 262         }
 263
 264         /* if PCI_REGION_MEM is set we do a two pass search with preference
 265          * on matches that don't have PCI_REGION_SYS_MEMORY set */
 266         if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
 267                 ret = __pci_hose_phys_to_bus(hose, phys_addr,
 268                                 flags, PCI_REGION_SYS_MEMORY, &bus_addr);
 269                 if (!ret)
 270                         return bus_addr;
 271         }
 272
 273         ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
 274
 275         if (ret)
 276                 puts ("pci_hose_phys_to_bus: invalid physical address\n");
 277
 278         return bus_addr;
 279 }
 280
 281 int __pci_hose_bus_to_phys (struct pci_controller *hose,
 282                                 pci_addr_t bus_addr,
 283                                 unsigned long flags,
 284                                 unsigned long skip_mask,
 285                                 phys_addr_t *pa)
 286 {
 287         struct pci_region *res;
 288         int i;
 289
 290         for (i = 0; i < hose->region_count; i++) {
 291                 res = &hose->regions[i];
 292
 293                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 294                         continue;
 295
 296                 if (res->flags & skip_mask)
 297                         continue;
 298
 299                 if (bus_addr >= res->bus_start &&
 300                         bus_addr < res->bus_start + res->size) {
 301                         *pa = (bus_addr - res->bus_start + res->phys_start);
 302                         return 0;
 303                 }
 304         }
 305
 306         return 1;
 307 }
 308
 309 phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
 310                                  pci_addr_t bus_addr,
 311                                  unsigned long flags)
 312 {
 313         phys_addr_t phys_addr = 0;
 314         int ret;
 315
 316         if (!hose) {
 317                 puts ("pci_hose_bus_to_phys: invalid hose\n");
 318                 return phys_addr;
 319         }
 320
 321         /* if PCI_REGION_MEM is set we do a two pass search with preference
 322          * on matches that don't have PCI_REGION_SYS_MEMORY set */
 323         if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
 324                 ret = __pci_hose_bus_to_phys(hose, bus_addr,
 325                                 flags, PCI_REGION_SYS_MEMORY, &phys_addr);
 326                 if (!ret)
 327                         return phys_addr;
 328         }
 329
 330         ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
 331
 332         if (ret)
 333                 puts ("pci_hose_bus_to_phys: invalid physical address\n");
 334
 335         return phys_addr;
 336 }
 337
 338 /*
 339  *
 340  */
 341
 342 int pci_hose_config_device(struct pci_controller *hose,
 343                            pci_dev_t dev,
 344                            unsigned long io,
 345                            pci_addr_t mem,
 346                            unsigned long command)
 347 {
 348         unsigned int bar_response, old_command;
 349         pci_addr_t bar_value;
 350         pci_size_t bar_size;
 351         unsigned char pin;
 352         int bar, found_mem64;
 353
 354         debug ("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n",
 355                 io, (u64)mem, command);
 356
 357         pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0);
 358
 359         for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_5; bar += 4) {
 360                 pci_hose_write_config_dword (hose, dev, bar, 0xffffffff);
 361                 pci_hose_read_config_dword (hose, dev, bar, &bar_response);
 362
 363                 if (!bar_response)
 364                         continue;
 365
 366                 found_mem64 = 0;
 367
 368                 /* Check the BAR type and set our address mask */
 369                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 370                         bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
 371                         /* round up region base address to a multiple of size */
 372                         io = ((io - 1) | (bar_size - 1)) + 1;
 373                         bar_value = io;
 374                         /* compute new region base address */
 375                         io = io + bar_size;
 376                 } else {
 377                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 378                                 PCI_BASE_ADDRESS_MEM_TYPE_64) {
 379                                 u32 bar_response_upper;
 380                                 u64 bar64;
 381                                 pci_hose_write_config_dword(hose, dev, bar+4, 0xffffffff);
 382                                 pci_hose_read_config_dword(hose, dev, bar+4, &bar_response_upper);
 383
 384                                 bar64 = ((u64)bar_response_upper << 32) | bar_response;
 385
 386                                 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
 387                                 found_mem64 = 1;
 388                         } else {
 389                                 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
 390                         }
 391
 392                         /* round up region base address to multiple of size */
 393                         mem = ((mem - 1) | (bar_size - 1)) + 1;
 394                         bar_value = mem;
 395                         /* compute new region base address */
 396                         mem = mem + bar_size;
 397                 }
 398
 399                 /* Write it out and update our limit */
 400                 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
 401
 402                 if (found_mem64) {
 403                         bar += 4;
 404 #ifdef CONFIG_SYS_PCI_64BIT
 405                         pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
 406 #else
 407                         pci_hose_write_config_dword (hose, dev, bar, 0x00000000);
 408 #endif
 409                 }
 410         }
 411
 412         /* Configure Cache Line Size Register */
 413         pci_hose_write_config_byte (hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
 414
 415         /* Configure Latency Timer */
 416         pci_hose_write_config_byte (hose, dev, PCI_LATENCY_TIMER, 0x80);
 417
 418         /* Disable interrupt line, if device says it wants to use interrupts */
 419         pci_hose_read_config_byte (hose, dev, PCI_INTERRUPT_PIN, &pin);
 420         if (pin != 0) {
 421                 pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, 0xff);
 422         }
 423
 424         pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &old_command);
 425         pci_hose_write_config_dword (hose, dev, PCI_COMMAND,
 426                                      (old_command & 0xffff0000) | command);
 427
 428         return 0;
 429 }
 430
 431 /*
 432  *
 433  */
 434
 435 struct pci_config_table *pci_find_config(struct pci_controller *hose,
 436                                          unsigned short class,
 437                                          unsigned int vendor,
 438                                          unsigned int device,
 439                                          unsigned int bus,
 440                                          unsigned int dev,
 441                                          unsigned int func)
 442 {
 443         struct pci_config_table *table;
 444
 445         for (table = hose->config_table; table && table->vendor; table++) {
 446                 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
 447                     (table->device == PCI_ANY_ID || table->device == device) &&
 448                     (table->class  == PCI_ANY_ID || table->class  == class)  &&
 449                     (table->bus    == PCI_ANY_ID || table->bus    == bus)    &&
 450                     (table->dev    == PCI_ANY_ID || table->dev    == dev)    &&
 451                     (table->func   == PCI_ANY_ID || table->func   == func)) {
 452                         return table;
 453                 }
 454         }
 455
 456         return NULL;
 457 }
 458
 459 void pci_cfgfunc_config_device(struct pci_controller *hose,
 460                                pci_dev_t dev,
 461                                struct pci_config_table *entry)
 462 {
 463         pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], entry->priv[2]);
 464 }
 465
 466 void pci_cfgfunc_do_nothing(struct pci_controller *hose,
 467                             pci_dev_t dev, struct pci_config_table *entry)
 468 {
 469 }
 470
 471 /*
 472  *
 473  */
 474
 475 /* HJF: Changed this to return int. I think this is required
 476  * to get the correct result when scanning bridges
 477  */
 478 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
 479 extern void pciauto_config_init(struct pci_controller *hose);
 480
 481 int __pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
 482 {
 483         /*
 484          * Check if pci device should be skipped in configuration
 485          */
 486         if (dev == PCI_BDF(hose->first_busno, 0, 0)) {
 487 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
 488                 /*
 489                  * Only skip configuration if "pciconfighost" is not set
 490                  */
 491                 if (getenv("pciconfighost") == NULL)
 492                         return 1;
 493 #else
 494                 return 1;
 495 #endif
 496         }
 497
 498         return 0;
 499 }
 500 int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
 501         __attribute__((weak, alias("__pci_skip_dev")));
 502
 503 #ifdef CONFIG_PCI_SCAN_SHOW
 504 int __pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
 505 {
 506         if (dev == PCI_BDF(hose->first_busno, 0, 0))
 507                 return 0;
 508
 509         return 1;
 510 }
 511 int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
 512         __attribute__((weak, alias("__pci_print_dev")));
 513 #endif /* CONFIG_PCI_SCAN_SHOW */
 514
 515 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
 516 {
 517         unsigned int sub_bus, found_multi=0;
 518         unsigned short vendor, device, class;
 519         unsigned char header_type;
 520         struct pci_config_table *cfg;
 521         pci_dev_t dev;
 522
 523         sub_bus = bus;
 524
 525         for (dev =  PCI_BDF(bus,0,0);
 526              dev <  PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
 527              dev += PCI_BDF(0,0,1)) {
 528
 529                 if (pci_skip_dev(hose, dev))
 530                         continue;
 531
 532                 if (PCI_FUNC(dev) && !found_multi)
 533                         continue;
 534
 535                 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
 536
 537                 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
 538
 539                 if (vendor != 0xffff && vendor != 0x0000) {
 540
 541                         if (!PCI_FUNC(dev))
 542                                 found_multi = header_type & 0x80;
 543
 544                         debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n",
 545                                 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
 546
 547                         pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
 548                         pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 549
 550                         cfg = pci_find_config(hose, class, vendor, device,
 551                                               PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
 552                         if (cfg) {
 553                                 cfg->config_device(hose, dev, cfg);
 554                                 sub_bus = max(sub_bus, hose->current_busno);
 555 #ifdef CONFIG_PCI_PNP
 556                         } else {
 557                                 int n = pciauto_config_device(hose, dev);
 558
 559                                 sub_bus = max(sub_bus, n);
 560 #endif
 561                         }
 562                         if (hose->fixup_irq)
 563                                 hose->fixup_irq(hose, dev);
 564
 565 #ifdef CONFIG_PCI_SCAN_SHOW
 566                         if (pci_print_dev(hose, dev)) {
 567                                 unsigned char int_line;
 568
 569                                 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_LINE,
 570                                                           &int_line);
 571                                 printf("        %02x  %02x  %04x  %04x  %04x  %02x\n",
 572                                        PCI_BUS(dev), PCI_DEV(dev), vendor, device, class,
 573                                        int_line);
 574                         }
 575 #endif
 576                 }
 577         }
 578
 579         return sub_bus;
 580 }
 581
 582 int pci_hose_scan(struct pci_controller *hose)
 583 {
 584         /* Start scan at current_busno.
 585          * PCIe will start scan at first_busno+1.
 586          */
 587         /* For legacy support, ensure current>=first */
 588         if (hose->first_busno > hose->current_busno)
 589                 hose->current_busno = hose->first_busno;
 590 #ifdef CONFIG_PCI_PNP
 591         pciauto_config_init(hose);
 592 #endif
 593         return pci_hose_scan_bus(hose, hose->current_busno);
 594 }
 595
 596 void pci_init(void)
 597 {
 598 #if defined(CONFIG_PCI_BOOTDELAY)
 599         char *s;
 600         int i;
 601
 602         /* wait "pcidelay" ms (if defined)... */
 603         s = getenv ("pcidelay");
 604         if (s) {
 605                 int val = simple_strtoul (s, NULL, 10);
 606                 for (i=0; i<val; i++)
 607                         udelay (1000);
 608         }
 609 #endif /* CONFIG_PCI_BOOTDELAY */
 610
 611         /* now call board specific pci_init()... */
 612         pci_init_board();
 613 }