2 * File: drivers/pci/pcie/aspm.c
3 * Enabling PCIe link L0s/L1 state and Clock Power Management
5 * Copyright (C) 2007 Intel
6 * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
7 * Copyright (C) Shaohua Li (shaohua.li@intel.com)
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/pci_regs.h>
15 #include <linux/errno.h>
17 #include <linux/init.h>
18 #include <linux/slab.h>
19 #include <linux/jiffies.h>
20 #include <linux/delay.h>
21 #include <linux/pci-aspm.h>
24 #ifdef MODULE_PARAM_PREFIX
25 #undef MODULE_PARAM_PREFIX
27 #define MODULE_PARAM_PREFIX "pcie_aspm."
29 /* Note: those are not register definitions */
30 #define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
31 #define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
32 #define ASPM_STATE_L1 (4) /* L1 state */
33 #define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */
34 #define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */
35 #define ASPM_STATE_L1_1_PCIPM (0x20) /* PCI PM L1.1 state */
36 #define ASPM_STATE_L1_2_PCIPM (0x40) /* PCI PM L1.2 state */
37 #define ASPM_STATE_L1_SS_PCIPM (ASPM_STATE_L1_1_PCIPM | ASPM_STATE_L1_2_PCIPM)
38 #define ASPM_STATE_L1_2_MASK (ASPM_STATE_L1_2 | ASPM_STATE_L1_2_PCIPM)
39 #define ASPM_STATE_L1SS (ASPM_STATE_L1_1 | ASPM_STATE_L1_1_PCIPM |\
41 #define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
42 #define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \
46 * When L1 substates are enabled, the LTR L1.2 threshold is a timing parameter
47 * that decides whether L1.1 or L1.2 is entered (Refer PCIe spec for details).
48 * Not sure is there is a way to "calculate" this on the fly, but maybe we
49 * could turn it into a parameter in future. This value has been taken from
50 * the following files from Intel's coreboot (which is the only code I found
52 * https://www.coreboot.org/pipermail/coreboot-gerrit/2015-March/021134.html
53 * https://review.coreboot.org/#/c/8832/
55 #define LTR_L1_2_THRESHOLD_BITS ((1 << 21) | (1 << 23) | (1 << 30))
58 u32 l0s; /* L0s latency (nsec) */
59 u32 l1; /* L1 latency (nsec) */
62 struct pcie_link_state {
63 struct pci_dev *pdev; /* Upstream component of the Link */
64 struct pci_dev *downstream; /* Downstream component, function 0 */
65 struct pcie_link_state *root; /* pointer to the root port link */
66 struct pcie_link_state *parent; /* pointer to the parent Link state */
67 struct list_head sibling; /* node in link_list */
68 struct list_head children; /* list of child link states */
69 struct list_head link; /* node in parent's children list */
72 u32 aspm_support:7; /* Supported ASPM state */
73 u32 aspm_enabled:7; /* Enabled ASPM state */
74 u32 aspm_capable:7; /* Capable ASPM state with latency */
75 u32 aspm_default:7; /* Default ASPM state by BIOS */
76 u32 aspm_disable:7; /* Disabled ASPM state */
79 u32 clkpm_capable:1; /* Clock PM capable? */
80 u32 clkpm_enabled:1; /* Current Clock PM state */
81 u32 clkpm_default:1; /* Default Clock PM state by BIOS */
84 struct aspm_latency latency_up; /* Upstream direction exit latency */
85 struct aspm_latency latency_dw; /* Downstream direction exit latency */
87 * Endpoint acceptable latencies. A pcie downstream port only
88 * has one slot under it, so at most there are 8 functions.
90 struct aspm_latency acceptable[8];
92 /* L1 PM Substate info */
94 u32 up_cap_ptr; /* L1SS cap ptr in upstream dev */
95 u32 dw_cap_ptr; /* L1SS cap ptr in downstream dev */
96 u32 ctl1; /* value to be programmed in ctl1 */
97 u32 ctl2; /* value to be programmed in ctl2 */
101 static int aspm_disabled, aspm_force;
102 static bool aspm_support_enabled = true;
103 static DEFINE_MUTEX(aspm_lock);
104 static LIST_HEAD(link_list);
106 #define POLICY_DEFAULT 0 /* BIOS default setting */
107 #define POLICY_PERFORMANCE 1 /* high performance */
108 #define POLICY_POWERSAVE 2 /* high power saving */
109 #define POLICY_POWER_SUPERSAVE 3 /* possibly even more power saving */
111 #ifdef CONFIG_PCIEASPM_PERFORMANCE
112 static int aspm_policy = POLICY_PERFORMANCE;
113 #elif defined CONFIG_PCIEASPM_POWERSAVE
114 static int aspm_policy = POLICY_POWERSAVE;
115 #elif defined CONFIG_PCIEASPM_POWER_SUPERSAVE
116 static int aspm_policy = POLICY_POWER_SUPERSAVE;
118 static int aspm_policy;
121 static const char *policy_str[] = {
122 [POLICY_DEFAULT] = "default",
123 [POLICY_PERFORMANCE] = "performance",
124 [POLICY_POWERSAVE] = "powersave",
125 [POLICY_POWER_SUPERSAVE] = "powersupersave"
128 #define LINK_RETRAIN_TIMEOUT HZ
130 static int policy_to_aspm_state(struct pcie_link_state *link)
132 switch (aspm_policy) {
133 case POLICY_PERFORMANCE:
134 /* Disable ASPM and Clock PM */
136 case POLICY_POWERSAVE:
137 /* Enable ASPM L0s/L1 */
138 return (ASPM_STATE_L0S | ASPM_STATE_L1);
139 case POLICY_POWER_SUPERSAVE:
140 /* Enable Everything */
141 return ASPM_STATE_ALL;
143 return link->aspm_default;
148 static int policy_to_clkpm_state(struct pcie_link_state *link)
150 switch (aspm_policy) {
151 case POLICY_PERFORMANCE:
152 /* Disable ASPM and Clock PM */
154 case POLICY_POWERSAVE:
155 case POLICY_POWER_SUPERSAVE:
156 /* Enable Clock PM */
159 return link->clkpm_default;
164 static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
166 struct pci_dev *child;
167 struct pci_bus *linkbus = link->pdev->subordinate;
168 u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;
170 list_for_each_entry(child, &linkbus->devices, bus_list)
171 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
172 PCI_EXP_LNKCTL_CLKREQ_EN,
174 link->clkpm_enabled = !!enable;
177 static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
179 /* Don't enable Clock PM if the link is not Clock PM capable */
180 if (!link->clkpm_capable)
182 /* Need nothing if the specified equals to current state */
183 if (link->clkpm_enabled == enable)
185 pcie_set_clkpm_nocheck(link, enable);
188 static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
190 int capable = 1, enabled = 1;
193 struct pci_dev *child;
194 struct pci_bus *linkbus = link->pdev->subordinate;
196 /* All functions should have the same cap and state, take the worst */
197 list_for_each_entry(child, &linkbus->devices, bus_list) {
198 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32);
199 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
204 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
205 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
208 link->clkpm_enabled = enabled;
209 link->clkpm_default = enabled;
210 link->clkpm_capable = (blacklist) ? 0 : capable;
214 * pcie_aspm_configure_common_clock: check if the 2 ends of a link
215 * could use common clock. If they are, configure them to use the
216 * common clock. That will reduce the ASPM state exit latency.
218 static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
221 u16 reg16, parent_reg, child_reg[8];
222 unsigned long start_jiffies;
223 struct pci_dev *child, *parent = link->pdev;
224 struct pci_bus *linkbus = parent->subordinate;
226 * All functions of a slot should have the same Slot Clock
227 * Configuration, so just check one function
229 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
230 BUG_ON(!pci_is_pcie(child));
232 /* Check downstream component if bit Slot Clock Configuration is 1 */
233 pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16);
234 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
237 /* Check upstream component if bit Slot Clock Configuration is 1 */
238 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
239 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
242 /* Configure downstream component, all functions */
243 list_for_each_entry(child, &linkbus->devices, bus_list) {
244 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
245 child_reg[PCI_FUNC(child->devfn)] = reg16;
247 reg16 |= PCI_EXP_LNKCTL_CCC;
249 reg16 &= ~PCI_EXP_LNKCTL_CCC;
250 pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);
253 /* Configure upstream component */
254 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
257 reg16 |= PCI_EXP_LNKCTL_CCC;
259 reg16 &= ~PCI_EXP_LNKCTL_CCC;
260 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
263 reg16 |= PCI_EXP_LNKCTL_RL;
264 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
266 /* Wait for link training end. Break out after waiting for timeout */
267 start_jiffies = jiffies;
269 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
270 if (!(reg16 & PCI_EXP_LNKSTA_LT))
272 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
276 if (!(reg16 & PCI_EXP_LNKSTA_LT))
279 /* Training failed. Restore common clock configurations */
280 dev_err(&parent->dev, "ASPM: Could not configure common clock\n");
281 list_for_each_entry(child, &linkbus->devices, bus_list)
282 pcie_capability_write_word(child, PCI_EXP_LNKCTL,
283 child_reg[PCI_FUNC(child->devfn)]);
284 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);
287 /* Convert L0s latency encoding to ns */
288 static u32 calc_l0s_latency(u32 encoding)
291 return (5 * 1000); /* > 4us */
292 return (64 << encoding);
295 /* Convert L0s acceptable latency encoding to ns */
296 static u32 calc_l0s_acceptable(u32 encoding)
300 return (64 << encoding);
303 /* Convert L1 latency encoding to ns */
304 static u32 calc_l1_latency(u32 encoding)
307 return (65 * 1000); /* > 64us */
308 return (1000 << encoding);
311 /* Convert L1 acceptable latency encoding to ns */
312 static u32 calc_l1_acceptable(u32 encoding)
316 return (1000 << encoding);
319 /* Convert L1SS T_pwr encoding to usec */
320 static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val)
330 dev_err(&pdev->dev, "%s: Invalid T_PwrOn scale: %u\n",
335 struct aspm_register_info {
338 u32 latency_encoding_l0s;
339 u32 latency_encoding_l1;
348 static void pcie_get_aspm_reg(struct pci_dev *pdev,
349 struct aspm_register_info *info)
354 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32);
355 info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
356 info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
357 info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
358 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, ®16);
359 info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;
361 /* Read L1 PM substate capabilities */
362 info->l1ss_cap = info->l1ss_ctl1 = info->l1ss_ctl2 = 0;
363 info->l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
364 if (!info->l1ss_cap_ptr)
366 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CAP,
368 if (!(info->l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) {
372 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL1,
374 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL2,
378 static void pcie_aspm_check_latency(struct pci_dev *endpoint)
380 u32 latency, l1_switch_latency = 0;
381 struct aspm_latency *acceptable;
382 struct pcie_link_state *link;
384 /* Device not in D0 doesn't need latency check */
385 if ((endpoint->current_state != PCI_D0) &&
386 (endpoint->current_state != PCI_UNKNOWN))
389 link = endpoint->bus->self->link_state;
390 acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)];
393 /* Check upstream direction L0s latency */
394 if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
395 (link->latency_up.l0s > acceptable->l0s))
396 link->aspm_capable &= ~ASPM_STATE_L0S_UP;
398 /* Check downstream direction L0s latency */
399 if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
400 (link->latency_dw.l0s > acceptable->l0s))
401 link->aspm_capable &= ~ASPM_STATE_L0S_DW;
404 * Every switch on the path to root complex need 1
405 * more microsecond for L1. Spec doesn't mention L0s.
407 * The exit latencies for L1 substates are not advertised
408 * by a device. Since the spec also doesn't mention a way
409 * to determine max latencies introduced by enabling L1
410 * substates on the components, it is not clear how to do
411 * a L1 substate exit latency check. We assume that the
412 * L1 exit latencies advertised by a device include L1
413 * substate latencies (and hence do not do any check).
415 latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);
416 if ((link->aspm_capable & ASPM_STATE_L1) &&
417 (latency + l1_switch_latency > acceptable->l1))
418 link->aspm_capable &= ~ASPM_STATE_L1;
419 l1_switch_latency += 1000;
426 * The L1 PM substate capability is only implemented in function 0 in a
427 * multi function device.
429 static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
431 struct pci_dev *child;
433 list_for_each_entry(child, &linkbus->devices, bus_list)
434 if (PCI_FUNC(child->devfn) == 0)
439 /* Calculate L1.2 PM substate timing parameters */
440 static void aspm_calc_l1ss_info(struct pcie_link_state *link,
441 struct aspm_register_info *upreg,
442 struct aspm_register_info *dwreg)
444 u32 val1, val2, scale1, scale2;
446 link->l1ss.up_cap_ptr = upreg->l1ss_cap_ptr;
447 link->l1ss.dw_cap_ptr = dwreg->l1ss_cap_ptr;
448 link->l1ss.ctl1 = link->l1ss.ctl2 = 0;
450 if (!(link->aspm_support & ASPM_STATE_L1_2_MASK))
453 /* Choose the greater of the two T_cmn_mode_rstr_time */
454 val1 = (upreg->l1ss_cap >> 8) & 0xFF;
455 val2 = (upreg->l1ss_cap >> 8) & 0xFF;
457 link->l1ss.ctl1 |= val1 << 8;
459 link->l1ss.ctl1 |= val2 << 8;
461 * We currently use LTR L1.2 threshold to be fixed constant picked from
464 link->l1ss.ctl1 |= LTR_L1_2_THRESHOLD_BITS;
466 /* Choose the greater of the two T_pwr_on */
467 val1 = (upreg->l1ss_cap >> 19) & 0x1F;
468 scale1 = (upreg->l1ss_cap >> 16) & 0x03;
469 val2 = (dwreg->l1ss_cap >> 19) & 0x1F;
470 scale2 = (dwreg->l1ss_cap >> 16) & 0x03;
472 if (calc_l1ss_pwron(link->pdev, scale1, val1) >
473 calc_l1ss_pwron(link->downstream, scale2, val2))
474 link->l1ss.ctl2 |= scale1 | (val1 << 3);
476 link->l1ss.ctl2 |= scale2 | (val2 << 3);
479 static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
481 struct pci_dev *child, *parent = link->pdev;
482 struct pci_bus *linkbus = parent->subordinate;
483 struct aspm_register_info upreg, dwreg;
486 /* Set enabled/disable so that we will disable ASPM later */
487 link->aspm_enabled = ASPM_STATE_ALL;
488 link->aspm_disable = ASPM_STATE_ALL;
492 /* Get upstream/downstream components' register state */
493 pcie_get_aspm_reg(parent, &upreg);
494 child = pci_function_0(linkbus);
495 pcie_get_aspm_reg(child, &dwreg);
496 link->downstream = child;
499 * If ASPM not supported, don't mess with the clocks and link,
502 if (!(upreg.support & dwreg.support))
505 /* Configure common clock before checking latencies */
506 pcie_aspm_configure_common_clock(link);
509 * Re-read upstream/downstream components' register state
510 * after clock configuration
512 pcie_get_aspm_reg(parent, &upreg);
513 pcie_get_aspm_reg(child, &dwreg);
518 * Note that we must not enable L0s in either direction on a
519 * given link unless components on both sides of the link each
522 if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S)
523 link->aspm_support |= ASPM_STATE_L0S;
524 if (dwreg.enabled & PCIE_LINK_STATE_L0S)
525 link->aspm_enabled |= ASPM_STATE_L0S_UP;
526 if (upreg.enabled & PCIE_LINK_STATE_L0S)
527 link->aspm_enabled |= ASPM_STATE_L0S_DW;
528 link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s);
529 link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s);
532 if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1)
533 link->aspm_support |= ASPM_STATE_L1;
534 if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1)
535 link->aspm_enabled |= ASPM_STATE_L1;
536 link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1);
537 link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1);
539 /* Setup L1 substate */
540 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)
541 link->aspm_support |= ASPM_STATE_L1_1;
542 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)
543 link->aspm_support |= ASPM_STATE_L1_2;
544 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)
545 link->aspm_support |= ASPM_STATE_L1_1_PCIPM;
546 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
547 link->aspm_support |= ASPM_STATE_L1_2_PCIPM;
549 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
550 link->aspm_enabled |= ASPM_STATE_L1_1;
551 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
552 link->aspm_enabled |= ASPM_STATE_L1_2;
553 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
554 link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;
555 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
556 link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
558 if (link->aspm_support & ASPM_STATE_L1SS)
559 aspm_calc_l1ss_info(link, &upreg, &dwreg);
561 /* Save default state */
562 link->aspm_default = link->aspm_enabled;
564 /* Setup initial capable state. Will be updated later */
565 link->aspm_capable = link->aspm_support;
567 * If the downstream component has pci bridge function, don't
570 list_for_each_entry(child, &linkbus->devices, bus_list) {
571 if (pci_pcie_type(child) == PCI_EXP_TYPE_PCI_BRIDGE) {
572 link->aspm_disable = ASPM_STATE_ALL;
577 /* Get and check endpoint acceptable latencies */
578 list_for_each_entry(child, &linkbus->devices, bus_list) {
580 struct aspm_latency *acceptable =
581 &link->acceptable[PCI_FUNC(child->devfn)];
583 if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
584 pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
587 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
588 /* Calculate endpoint L0s acceptable latency */
589 encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
590 acceptable->l0s = calc_l0s_acceptable(encoding);
591 /* Calculate endpoint L1 acceptable latency */
592 encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
593 acceptable->l1 = calc_l1_acceptable(encoding);
595 pcie_aspm_check_latency(child);
599 static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
604 pci_read_config_dword(pdev, pos, &val);
607 pci_write_config_dword(pdev, pos, val);
610 /* Configure the ASPM L1 substates */
611 static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
614 struct pci_dev *child = link->downstream, *parent = link->pdev;
615 u32 up_cap_ptr = link->l1ss.up_cap_ptr;
616 u32 dw_cap_ptr = link->l1ss.dw_cap_ptr;
618 enable_req = (link->aspm_enabled ^ state) & state;
621 * Here are the rules specified in the PCIe spec for enabling L1SS:
622 * - When enabling L1.x, enable bit at parent first, then at child
623 * - When disabling L1.x, disable bit at child first, then at parent
624 * - When enabling ASPM L1.x, need to disable L1
625 * (at child followed by parent).
626 * - The ASPM/PCIPM L1.2 must be disabled while programming timing
629 * To keep it simple, disable all L1SS bits first, and later enable
633 /* Disable all L1 substates */
634 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
635 PCI_L1SS_CTL1_L1SS_MASK, 0);
636 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
637 PCI_L1SS_CTL1_L1SS_MASK, 0);
639 * If needed, disable L1, and it gets enabled later
640 * in pcie_config_aspm_link().
642 if (enable_req & (ASPM_STATE_L1_1 | ASPM_STATE_L1_2)) {
643 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
644 PCI_EXP_LNKCTL_ASPM_L1, 0);
645 pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
646 PCI_EXP_LNKCTL_ASPM_L1, 0);
649 if (enable_req & ASPM_STATE_L1_2_MASK) {
651 /* Program T_pwr_on in both ports */
652 pci_write_config_dword(parent, up_cap_ptr + PCI_L1SS_CTL2,
654 pci_write_config_dword(child, dw_cap_ptr + PCI_L1SS_CTL2,
657 /* Program T_cmn_mode in parent */
658 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
659 0xFF00, link->l1ss.ctl1);
661 /* Program LTR L1.2 threshold in both ports */
662 pci_clear_and_set_dword(parent, dw_cap_ptr + PCI_L1SS_CTL1,
663 0xE3FF0000, link->l1ss.ctl1);
664 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
665 0xE3FF0000, link->l1ss.ctl1);
669 if (state & ASPM_STATE_L1_1)
670 val |= PCI_L1SS_CTL1_ASPM_L1_1;
671 if (state & ASPM_STATE_L1_2)
672 val |= PCI_L1SS_CTL1_ASPM_L1_2;
673 if (state & ASPM_STATE_L1_1_PCIPM)
674 val |= PCI_L1SS_CTL1_PCIPM_L1_1;
675 if (state & ASPM_STATE_L1_2_PCIPM)
676 val |= PCI_L1SS_CTL1_PCIPM_L1_2;
678 /* Enable what we need to enable */
679 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
680 PCI_L1SS_CAP_L1_PM_SS, val);
681 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
682 PCI_L1SS_CAP_L1_PM_SS, val);
685 static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
687 pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
688 PCI_EXP_LNKCTL_ASPMC, val);
691 static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
693 u32 upstream = 0, dwstream = 0;
694 struct pci_dev *child = link->downstream, *parent = link->pdev;
695 struct pci_bus *linkbus = parent->subordinate;
697 /* Enable only the states that were not explicitly disabled */
698 state &= (link->aspm_capable & ~link->aspm_disable);
700 /* Can't enable any substates if L1 is not enabled */
701 if (!(state & ASPM_STATE_L1))
702 state &= ~ASPM_STATE_L1SS;
704 /* Spec says both ports must be in D0 before enabling PCI PM substates*/
705 if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) {
706 state &= ~ASPM_STATE_L1_SS_PCIPM;
707 state |= (link->aspm_enabled & ASPM_STATE_L1_SS_PCIPM);
710 /* Nothing to do if the link is already in the requested state */
711 if (link->aspm_enabled == state)
713 /* Convert ASPM state to upstream/downstream ASPM register state */
714 if (state & ASPM_STATE_L0S_UP)
715 dwstream |= PCI_EXP_LNKCTL_ASPM_L0S;
716 if (state & ASPM_STATE_L0S_DW)
717 upstream |= PCI_EXP_LNKCTL_ASPM_L0S;
718 if (state & ASPM_STATE_L1) {
719 upstream |= PCI_EXP_LNKCTL_ASPM_L1;
720 dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
723 if (link->aspm_capable & ASPM_STATE_L1SS)
724 pcie_config_aspm_l1ss(link, state);
727 * Spec 2.0 suggests all functions should be configured the
728 * same setting for ASPM. Enabling ASPM L1 should be done in
729 * upstream component first and then downstream, and vice
730 * versa for disabling ASPM L1. Spec doesn't mention L0S.
732 if (state & ASPM_STATE_L1)
733 pcie_config_aspm_dev(parent, upstream);
734 list_for_each_entry(child, &linkbus->devices, bus_list)
735 pcie_config_aspm_dev(child, dwstream);
736 if (!(state & ASPM_STATE_L1))
737 pcie_config_aspm_dev(parent, upstream);
739 link->aspm_enabled = state;
742 static void pcie_config_aspm_path(struct pcie_link_state *link)
745 pcie_config_aspm_link(link, policy_to_aspm_state(link));
750 static void free_link_state(struct pcie_link_state *link)
752 link->pdev->link_state = NULL;
756 static int pcie_aspm_sanity_check(struct pci_dev *pdev)
758 struct pci_dev *child;
762 * Some functions in a slot might not all be PCIe functions,
763 * very strange. Disable ASPM for the whole slot
765 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
766 if (!pci_is_pcie(child))
770 * If ASPM is disabled then we're not going to change
771 * the BIOS state. It's safe to continue even if it's a
779 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
780 * RBER bit to determine if a function is 1.1 version device
782 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
783 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
784 dev_info(&child->dev, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n");
791 static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
793 struct pcie_link_state *link;
795 link = kzalloc(sizeof(*link), GFP_KERNEL);
799 INIT_LIST_HEAD(&link->sibling);
800 INIT_LIST_HEAD(&link->children);
801 INIT_LIST_HEAD(&link->link);
805 * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe
808 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
809 pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE) {
812 struct pcie_link_state *parent;
814 parent = pdev->bus->parent->self->link_state;
820 link->parent = parent;
821 link->root = link->parent->root;
822 list_add(&link->link, &parent->children);
825 list_add(&link->sibling, &link_list);
826 pdev->link_state = link;
831 * pcie_aspm_init_link_state: Initiate PCI express link state.
832 * It is called after the pcie and its children devices are scanned.
833 * @pdev: the root port or switch downstream port
835 void pcie_aspm_init_link_state(struct pci_dev *pdev)
837 struct pcie_link_state *link;
838 int blacklist = !!pcie_aspm_sanity_check(pdev);
840 if (!aspm_support_enabled)
843 if (pdev->link_state)
847 * We allocate pcie_link_state for the component on the upstream
848 * end of a Link, so there's nothing to do unless this device has a
849 * Link on its secondary side.
851 if (!pdev->has_secondary_link)
854 /* VIA has a strange chipset, root port is under a bridge */
855 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT &&
859 down_read(&pci_bus_sem);
860 if (list_empty(&pdev->subordinate->devices))
863 mutex_lock(&aspm_lock);
864 link = alloc_pcie_link_state(pdev);
868 * Setup initial ASPM state. Note that we need to configure
869 * upstream links also because capable state of them can be
870 * update through pcie_aspm_cap_init().
872 pcie_aspm_cap_init(link, blacklist);
874 /* Setup initial Clock PM state */
875 pcie_clkpm_cap_init(link, blacklist);
878 * At this stage drivers haven't had an opportunity to change the
879 * link policy setting. Enabling ASPM on broken hardware can cripple
880 * it even before the driver has had a chance to disable ASPM, so
881 * default to a safe level right now. If we're enabling ASPM beyond
882 * the BIOS's expectation, we'll do so once pci_enable_device() is
885 if (aspm_policy != POLICY_POWERSAVE &&
886 aspm_policy != POLICY_POWER_SUPERSAVE) {
887 pcie_config_aspm_path(link);
888 pcie_set_clkpm(link, policy_to_clkpm_state(link));
892 mutex_unlock(&aspm_lock);
894 up_read(&pci_bus_sem);
897 /* Recheck latencies and update aspm_capable for links under the root */
898 static void pcie_update_aspm_capable(struct pcie_link_state *root)
900 struct pcie_link_state *link;
901 BUG_ON(root->parent);
902 list_for_each_entry(link, &link_list, sibling) {
903 if (link->root != root)
905 link->aspm_capable = link->aspm_support;
907 list_for_each_entry(link, &link_list, sibling) {
908 struct pci_dev *child;
909 struct pci_bus *linkbus = link->pdev->subordinate;
910 if (link->root != root)
912 list_for_each_entry(child, &linkbus->devices, bus_list) {
913 if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) &&
914 (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END))
916 pcie_aspm_check_latency(child);
921 /* @pdev: the endpoint device */
922 void pcie_aspm_exit_link_state(struct pci_dev *pdev)
924 struct pci_dev *parent = pdev->bus->self;
925 struct pcie_link_state *link, *root, *parent_link;
927 if (!parent || !parent->link_state)
930 down_read(&pci_bus_sem);
931 mutex_lock(&aspm_lock);
933 * All PCIe functions are in one slot, remove one function will remove
934 * the whole slot, so just wait until we are the last function left.
936 if (!list_is_last(&pdev->bus_list, &parent->subordinate->devices))
939 link = parent->link_state;
941 parent_link = link->parent;
943 /* All functions are removed, so just disable ASPM for the link */
944 pcie_config_aspm_link(link, 0);
945 list_del(&link->sibling);
946 list_del(&link->link);
947 /* Clock PM is for endpoint device */
948 free_link_state(link);
950 /* Recheck latencies and configure upstream links */
952 pcie_update_aspm_capable(root);
953 pcie_config_aspm_path(parent_link);
956 mutex_unlock(&aspm_lock);
957 up_read(&pci_bus_sem);
960 /* @pdev: the root port or switch downstream port */
961 void pcie_aspm_pm_state_change(struct pci_dev *pdev)
963 struct pcie_link_state *link = pdev->link_state;
965 if (aspm_disabled || !link)
968 * Devices changed PM state, we should recheck if latency
969 * meets all functions' requirement
971 down_read(&pci_bus_sem);
972 mutex_lock(&aspm_lock);
973 pcie_update_aspm_capable(link->root);
974 pcie_config_aspm_path(link);
975 mutex_unlock(&aspm_lock);
976 up_read(&pci_bus_sem);
979 void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
981 struct pcie_link_state *link = pdev->link_state;
983 if (aspm_disabled || !link)
986 if (aspm_policy != POLICY_POWERSAVE &&
987 aspm_policy != POLICY_POWER_SUPERSAVE)
990 down_read(&pci_bus_sem);
991 mutex_lock(&aspm_lock);
992 pcie_config_aspm_path(link);
993 pcie_set_clkpm(link, policy_to_clkpm_state(link));
994 mutex_unlock(&aspm_lock);
995 up_read(&pci_bus_sem);
998 static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
1000 struct pci_dev *parent = pdev->bus->self;
1001 struct pcie_link_state *link;
1003 if (!pci_is_pcie(pdev))
1006 if (pdev->has_secondary_link)
1008 if (!parent || !parent->link_state)
1012 * A driver requested that ASPM be disabled on this device, but
1013 * if we don't have permission to manage ASPM (e.g., on ACPI
1014 * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
1015 * the _OSC method), we can't honor that request. Windows has
1016 * a similar mechanism using "PciASPMOptOut", which is also
1017 * ignored in this situation.
1019 if (aspm_disabled) {
1020 dev_warn(&pdev->dev, "can't disable ASPM; OS doesn't have ASPM control\n");
1025 down_read(&pci_bus_sem);
1026 mutex_lock(&aspm_lock);
1027 link = parent->link_state;
1028 if (state & PCIE_LINK_STATE_L0S)
1029 link->aspm_disable |= ASPM_STATE_L0S;
1030 if (state & PCIE_LINK_STATE_L1)
1031 link->aspm_disable |= ASPM_STATE_L1;
1032 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1034 if (state & PCIE_LINK_STATE_CLKPM) {
1035 link->clkpm_capable = 0;
1036 pcie_set_clkpm(link, 0);
1038 mutex_unlock(&aspm_lock);
1040 up_read(&pci_bus_sem);
1043 void pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1045 __pci_disable_link_state(pdev, state, false);
1047 EXPORT_SYMBOL(pci_disable_link_state_locked);
1050 * pci_disable_link_state - Disable device's link state, so the link will
1051 * never enter specific states. Note that if the BIOS didn't grant ASPM
1052 * control to the OS, this does nothing because we can't touch the LNKCTL
1056 * @state: ASPM link state to disable
1058 void pci_disable_link_state(struct pci_dev *pdev, int state)
1060 __pci_disable_link_state(pdev, state, true);
1062 EXPORT_SYMBOL(pci_disable_link_state);
1064 static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp)
1067 struct pcie_link_state *link;
1071 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
1072 if (!strncmp(val, policy_str[i], strlen(policy_str[i])))
1074 if (i >= ARRAY_SIZE(policy_str))
1076 if (i == aspm_policy)
1079 down_read(&pci_bus_sem);
1080 mutex_lock(&aspm_lock);
1082 list_for_each_entry(link, &link_list, sibling) {
1083 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1084 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1086 mutex_unlock(&aspm_lock);
1087 up_read(&pci_bus_sem);
1091 static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp)
1094 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
1095 if (i == aspm_policy)
1096 cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
1098 cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
1102 module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
1105 #ifdef CONFIG_PCIEASPM_DEBUG
1106 static ssize_t link_state_show(struct device *dev,
1107 struct device_attribute *attr,
1110 struct pci_dev *pci_device = to_pci_dev(dev);
1111 struct pcie_link_state *link_state = pci_device->link_state;
1113 return sprintf(buf, "%d\n", link_state->aspm_enabled);
1116 static ssize_t link_state_store(struct device *dev,
1117 struct device_attribute *attr,
1121 struct pci_dev *pdev = to_pci_dev(dev);
1122 struct pcie_link_state *link, *root = pdev->link_state->root;
1128 if (kstrtouint(buf, 10, &state))
1130 if ((state & ~ASPM_STATE_ALL) != 0)
1133 down_read(&pci_bus_sem);
1134 mutex_lock(&aspm_lock);
1135 list_for_each_entry(link, &link_list, sibling) {
1136 if (link->root != root)
1138 pcie_config_aspm_link(link, state);
1140 mutex_unlock(&aspm_lock);
1141 up_read(&pci_bus_sem);
1145 static ssize_t clk_ctl_show(struct device *dev,
1146 struct device_attribute *attr,
1149 struct pci_dev *pci_device = to_pci_dev(dev);
1150 struct pcie_link_state *link_state = pci_device->link_state;
1152 return sprintf(buf, "%d\n", link_state->clkpm_enabled);
1155 static ssize_t clk_ctl_store(struct device *dev,
1156 struct device_attribute *attr,
1160 struct pci_dev *pdev = to_pci_dev(dev);
1163 if (strtobool(buf, &state))
1166 down_read(&pci_bus_sem);
1167 mutex_lock(&aspm_lock);
1168 pcie_set_clkpm_nocheck(pdev->link_state, state);
1169 mutex_unlock(&aspm_lock);
1170 up_read(&pci_bus_sem);
1175 static DEVICE_ATTR_RW(link_state);
1176 static DEVICE_ATTR_RW(clk_ctl);
1178 static char power_group[] = "power";
1179 void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
1181 struct pcie_link_state *link_state = pdev->link_state;
1186 if (link_state->aspm_support)
1187 sysfs_add_file_to_group(&pdev->dev.kobj,
1188 &dev_attr_link_state.attr, power_group);
1189 if (link_state->clkpm_capable)
1190 sysfs_add_file_to_group(&pdev->dev.kobj,
1191 &dev_attr_clk_ctl.attr, power_group);
1194 void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
1196 struct pcie_link_state *link_state = pdev->link_state;
1201 if (link_state->aspm_support)
1202 sysfs_remove_file_from_group(&pdev->dev.kobj,
1203 &dev_attr_link_state.attr, power_group);
1204 if (link_state->clkpm_capable)
1205 sysfs_remove_file_from_group(&pdev->dev.kobj,
1206 &dev_attr_clk_ctl.attr, power_group);
1210 static int __init pcie_aspm_disable(char *str)
1212 if (!strcmp(str, "off")) {
1213 aspm_policy = POLICY_DEFAULT;
1215 aspm_support_enabled = false;
1216 printk(KERN_INFO "PCIe ASPM is disabled\n");
1217 } else if (!strcmp(str, "force")) {
1219 printk(KERN_INFO "PCIe ASPM is forcibly enabled\n");
1224 __setup("pcie_aspm=", pcie_aspm_disable);
1226 void pcie_no_aspm(void)
1229 * Disabling ASPM is intended to prevent the kernel from modifying
1230 * existing hardware state, not to clear existing state. To that end:
1231 * (a) set policy to POLICY_DEFAULT in order to avoid changing state
1232 * (b) prevent userspace from changing policy
1235 aspm_policy = POLICY_DEFAULT;
1240 bool pcie_aspm_support_enabled(void)
1242 return aspm_support_enabled;
1244 EXPORT_SYMBOL(pcie_aspm_support_enabled);