drivers/phy/phy-rockchip-inno-usb2.c

   1 /*
   2  * Rockchip USB2.0 PHY with Innosilicon IP block driver
   3  *
   4  * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/delay.h>
  20 #include <linux/extcon.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/gpio/consumer.h>
  24 #include <linux/jiffies.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/mutex.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/phy/phy.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/power_supply.h>
  35 #include <linux/regmap.h>
  36 #include <linux/mfd/syscon.h>
  37 #include <linux/usb/of.h>
  38 #include <linux/usb/otg.h>
  39
  40 #define BIT_WRITEABLE_SHIFT     16
  41 #define SCHEDULE_DELAY          (60 * HZ)
  42 #define OTG_SCHEDULE_DELAY      (2 * HZ)
  43
  44 enum rockchip_usb2phy_port_id {
  45         USB2PHY_PORT_OTG,
  46         USB2PHY_PORT_HOST,
  47         USB2PHY_NUM_PORTS,
  48 };
  49
  50 enum rockchip_usb2phy_host_state {
  51         PHY_STATE_HS_ONLINE     = 0,
  52         PHY_STATE_DISCONNECT    = 1,
  53         PHY_STATE_CONNECT       = 2,
  54         PHY_STATE_FS_LS_ONLINE  = 4,
  55 };
  56
  57 /**
  58  * Different states involved in USB charger detection.
  59  * USB_CHG_STATE_UNDEFINED      USB charger is not connected or detection
  60  *                              process is not yet started.
  61  * USB_CHG_STATE_WAIT_FOR_DCD   Waiting for Data pins contact.
  62  * USB_CHG_STATE_DCD_DONE       Data pin contact is detected.
  63  * USB_CHG_STATE_PRIMARY_DONE   Primary detection is completed (Detects
  64  *                              between SDP and DCP/CDP).
  65  * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
  66  *                              between DCP and CDP).
  67  * USB_CHG_STATE_DETECTED       USB charger type is determined.
  68  */
  69 enum usb_chg_state {
  70         USB_CHG_STATE_UNDEFINED = 0,
  71         USB_CHG_STATE_WAIT_FOR_DCD,
  72         USB_CHG_STATE_DCD_DONE,
  73         USB_CHG_STATE_PRIMARY_DONE,
  74         USB_CHG_STATE_SECONDARY_DONE,
  75         USB_CHG_STATE_DETECTED,
  76 };
  77
  78 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
  79         EXTCON_USB,
  80         EXTCON_USB_HOST,
  81         EXTCON_CHG_USB_SDP,
  82         EXTCON_CHG_USB_CDP,
  83         EXTCON_CHG_USB_DCP,
  84         EXTCON_CHG_USB_SLOW,
  85         EXTCON_NONE,
  86 };
  87
  88 struct usb2phy_reg {
  89         unsigned int    offset;
  90         unsigned int    bitend;
  91         unsigned int    bitstart;
  92         unsigned int    disable;
  93         unsigned int    enable;
  94 };
  95
  96 /**
  97  * struct rockchip_chg_det_reg: usb charger detect registers
  98  * @cp_det: charging port detected successfully.
  99  * @dcp_det: dedicated charging port detected successfully.
 100  * @dp_det: assert data pin connect successfully.
 101  * @idm_sink_en: open dm sink curren.
 102  * @idp_sink_en: open dp sink current.
 103  * @idp_src_en: open dm source current.
 104  * @rdm_pdwn_en: open dm pull down resistor.
 105  * @vdm_src_en: open dm voltage source.
 106  * @vdp_src_en: open dp voltage source.
 107  * @opmode: utmi operational mode.
 108  */
 109 struct rockchip_chg_det_reg {
 110         struct usb2phy_reg      cp_det;
 111         struct usb2phy_reg      dcp_det;
 112         struct usb2phy_reg      dp_det;
 113         struct usb2phy_reg      idm_sink_en;
 114         struct usb2phy_reg      idp_sink_en;
 115         struct usb2phy_reg      idp_src_en;
 116         struct usb2phy_reg      rdm_pdwn_en;
 117         struct usb2phy_reg      vdm_src_en;
 118         struct usb2phy_reg      vdp_src_en;
 119         struct usb2phy_reg      opmode;
 120 };
 121
 122 /**
 123  * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
 124  * @phy_sus: phy suspend register.
 125  * @bvalid_det_en: vbus valid rise detection enable register.
 126  * @bvalid_det_st: vbus valid rise detection status register.
 127  * @bvalid_det_clr: vbus valid rise detection clear register.
 128  * @ls_det_en: linestate detection enable register.
 129  * @ls_det_st: linestate detection state register.
 130  * @ls_det_clr: linestate detection clear register.
 131  * @utmi_avalid: utmi vbus avalid status register.
 132  * @utmi_bvalid: utmi vbus bvalid status register.
 133  * @utmi_ls: utmi linestate state register.
 134  * @utmi_hstdet: utmi host disconnect register.
 135  */
 136 struct rockchip_usb2phy_port_cfg {
 137         struct usb2phy_reg      phy_sus;
 138         struct usb2phy_reg      bvalid_det_en;
 139         struct usb2phy_reg      bvalid_det_st;
 140         struct usb2phy_reg      bvalid_det_clr;
 141         struct usb2phy_reg      ls_det_en;
 142         struct usb2phy_reg      ls_det_st;
 143         struct usb2phy_reg      ls_det_clr;
 144         struct usb2phy_reg      utmi_avalid;
 145         struct usb2phy_reg      utmi_bvalid;
 146         struct usb2phy_reg      utmi_ls;
 147         struct usb2phy_reg      utmi_hstdet;
 148 };
 149
 150 /**
 151  * struct rockchip_usb2phy_cfg: usb-phy configuration.
 152  * @reg: the address offset of grf for usb-phy config.
 153  * @num_ports: specify how many ports that the phy has.
 154  * @clkout_ctl: keep on/turn off output clk of phy.
 155  * @chg_det: charger detection registers.
 156  */
 157 struct rockchip_usb2phy_cfg {
 158         unsigned int    reg;
 159         unsigned int    num_ports;
 160         struct usb2phy_reg      clkout_ctl;
 161         const struct rockchip_usb2phy_port_cfg  port_cfgs[USB2PHY_NUM_PORTS];
 162         const struct rockchip_chg_det_reg       chg_det;
 163 };
 164
 165 /**
 166  * struct rockchip_usb2phy_port: usb-phy port data.
 167  * @port_id: flag for otg port or host port.
 168  * @suspended: phy suspended flag.
 169  * @utmi_avalid: utmi avalid status usage flag.
 170  *      true    - use avalid to get vbus status
 171  *      flase   - use bvalid to get vbus status
 172  * @vbus_attached: otg device vbus status.
 173  * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
 174  * @ls_irq: IRQ number assigned for linestate detection.
 175  * @mutex: for register updating in sm_work.
 176  * @chg_work: charge detect work.
 177  * @otg_sm_work: OTG state machine work.
 178  * @sm_work: HOST state machine work.
 179  * @phy_cfg: port register configuration, assigned by driver data.
 180  * @event_nb: hold event notification callback.
 181  * @state: define OTG enumeration states before device reset.
 182  * @mode: the dr_mode of the controller.
 183  */
 184 struct rockchip_usb2phy_port {
 185         struct phy      *phy;
 186         unsigned int    port_id;
 187         bool            suspended;
 188         bool            utmi_avalid;
 189         bool            vbus_attached;
 190         int             bvalid_irq;
 191         int             ls_irq;
 192         struct mutex    mutex;
 193         struct          delayed_work chg_work;
 194         struct          delayed_work otg_sm_work;
 195         struct          delayed_work sm_work;
 196         const struct    rockchip_usb2phy_port_cfg *port_cfg;
 197         struct notifier_block   event_nb;
 198         enum usb_otg_state      state;
 199         enum usb_dr_mode        mode;
 200 };
 201
 202 /**
 203  * struct rockchip_usb2phy: usb2.0 phy driver data.
 204  * @grf: General Register Files regmap.
 205  * @clk: clock struct of phy input clk.
 206  * @clk480m: clock struct of phy output clk.
 207  * @clk_hw: clock struct of phy output clk management.
 208  * @chg_state: states involved in USB charger detection.
 209  * @chg_type: USB charger types.
 210  * @dcd_retries: The retry count used to track Data contact
 211  *               detection process.
 212  * @edev: extcon device for notification registration
 213  * @phy_cfg: phy register configuration, assigned by driver data.
 214  * @ports: phy port instance.
 215  */
 216 struct rockchip_usb2phy {
 217         struct device   *dev;
 218         struct regmap   *grf;
 219         struct clk      *clk;
 220         struct clk      *clk480m;
 221         struct clk_hw   clk480m_hw;
 222         enum usb_chg_state      chg_state;
 223         enum power_supply_type  chg_type;
 224         u8                      dcd_retries;
 225         struct extcon_dev       *edev;
 226         const struct rockchip_usb2phy_cfg       *phy_cfg;
 227         struct rockchip_usb2phy_port    ports[USB2PHY_NUM_PORTS];
 228 };
 229
 230 static inline int property_enable(struct rockchip_usb2phy *rphy,
 231                                   const struct usb2phy_reg *reg, bool en)
 232 {
 233         unsigned int val, mask, tmp;
 234
 235         tmp = en ? reg->enable : reg->disable;
 236         mask = GENMASK(reg->bitend, reg->bitstart);
 237         val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
 238
 239         return regmap_write(rphy->grf, reg->offset, val);
 240 }
 241
 242 static inline bool property_enabled(struct rockchip_usb2phy *rphy,
 243                                     const struct usb2phy_reg *reg)
 244 {
 245         int ret;
 246         unsigned int tmp, orig;
 247         unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
 248
 249         ret = regmap_read(rphy->grf, reg->offset, &orig);
 250         if (ret)
 251                 return false;
 252
 253         tmp = (orig & mask) >> reg->bitstart;
 254         return tmp == reg->enable;
 255 }
 256
 257 static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
 258 {
 259         struct rockchip_usb2phy *rphy =
 260                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 261         int ret;
 262
 263         /* turn on 480m clk output if it is off */
 264         if (!property_enabled(rphy, &rphy->phy_cfg->clkout_ctl)) {
 265                 ret = property_enable(rphy, &rphy->phy_cfg->clkout_ctl, true);
 266                 if (ret)
 267                         return ret;
 268
 269                 /* waiting for the clk become stable */
 270                 usleep_range(1200, 1300);
 271         }
 272
 273         return 0;
 274 }
 275
 276 static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw)
 277 {
 278         struct rockchip_usb2phy *rphy =
 279                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 280
 281         /* turn off 480m clk output */
 282         property_enable(rphy, &rphy->phy_cfg->clkout_ctl, false);
 283 }
 284
 285 static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw)
 286 {
 287         struct rockchip_usb2phy *rphy =
 288                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 289
 290         return property_enabled(rphy, &rphy->phy_cfg->clkout_ctl);
 291 }
 292
 293 static unsigned long
 294 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
 295                                      unsigned long parent_rate)
 296 {
 297         return 480000000;
 298 }
 299
 300 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
 301         .prepare = rockchip_usb2phy_clk480m_prepare,
 302         .unprepare = rockchip_usb2phy_clk480m_unprepare,
 303         .is_prepared = rockchip_usb2phy_clk480m_prepared,
 304         .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
 305 };
 306
 307 static void rockchip_usb2phy_clk480m_unregister(void *data)
 308 {
 309         struct rockchip_usb2phy *rphy = data;
 310
 311         of_clk_del_provider(rphy->dev->of_node);
 312         clk_unregister(rphy->clk480m);
 313 }
 314
 315 static int
 316 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
 317 {
 318         struct device_node *node = rphy->dev->of_node;
 319         struct clk_init_data init;
 320         const char *clk_name;
 321         int ret;
 322
 323         init.flags = 0;
 324         init.name = "clk_usbphy_480m";
 325         init.ops = &rockchip_usb2phy_clkout_ops;
 326
 327         /* optional override of the clockname */
 328         of_property_read_string(node, "clock-output-names", &init.name);
 329
 330         if (rphy->clk) {
 331                 clk_name = __clk_get_name(rphy->clk);
 332                 init.parent_names = &clk_name;
 333                 init.num_parents = 1;
 334         } else {
 335                 init.parent_names = NULL;
 336                 init.num_parents = 0;
 337         }
 338
 339         rphy->clk480m_hw.init = &init;
 340
 341         /* register the clock */
 342         rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
 343         if (IS_ERR(rphy->clk480m)) {
 344                 ret = PTR_ERR(rphy->clk480m);
 345                 goto err_ret;
 346         }
 347
 348         ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
 349         if (ret < 0)
 350                 goto err_clk_provider;
 351
 352         ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister,
 353                               rphy);
 354         if (ret < 0)
 355                 goto err_unreg_action;
 356
 357         return 0;
 358
 359 err_unreg_action:
 360         of_clk_del_provider(node);
 361 err_clk_provider:
 362         clk_unregister(rphy->clk480m);
 363 err_ret:
 364         return ret;
 365 }
 366
 367 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
 368 {
 369         int ret;
 370         struct device_node *node = rphy->dev->of_node;
 371         struct extcon_dev *edev;
 372
 373         if (of_property_read_bool(node, "extcon")) {
 374                 edev = extcon_get_edev_by_phandle(rphy->dev, 0);
 375                 if (IS_ERR(edev)) {
 376                         if (PTR_ERR(edev) != -EPROBE_DEFER)
 377                                 dev_err(rphy->dev, "Invalid or missing extcon\n");
 378                         return PTR_ERR(edev);
 379                 }
 380         } else {
 381                 /* Initialize extcon device */
 382                 edev = devm_extcon_dev_allocate(rphy->dev,
 383                                                 rockchip_usb2phy_extcon_cable);
 384
 385                 if (IS_ERR(edev))
 386                         return -ENOMEM;
 387
 388                 ret = devm_extcon_dev_register(rphy->dev, edev);
 389                 if (ret) {
 390                         dev_err(rphy->dev, "failed to register extcon device\n");
 391                         return ret;
 392                 }
 393         }
 394
 395         rphy->edev = edev;
 396
 397         return 0;
 398 }
 399
 400 static int rockchip_usb2phy_init(struct phy *phy)
 401 {
 402         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 403         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 404         int ret = 0;
 405
 406         mutex_lock(&rport->mutex);
 407
 408         if (rport->port_id == USB2PHY_PORT_OTG) {
 409                 if (rport->mode != USB_DR_MODE_HOST) {
 410                         /* clear bvalid status and enable bvalid detect irq */
 411                         ret = property_enable(rphy,
 412                                               &rport->port_cfg->bvalid_det_clr,
 413                                               true);
 414                         if (ret)
 415                                 goto out;
 416
 417                         ret = property_enable(rphy,
 418                                               &rport->port_cfg->bvalid_det_en,
 419                                               true);
 420                         if (ret)
 421                                 goto out;
 422
 423                         schedule_delayed_work(&rport->otg_sm_work,
 424                                               OTG_SCHEDULE_DELAY);
 425                 } else {
 426                         /* If OTG works in host only mode, do nothing. */
 427                         dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
 428                 }
 429         } else if (rport->port_id == USB2PHY_PORT_HOST) {
 430                 /* clear linestate and enable linestate detect irq */
 431                 ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 432                 if (ret)
 433                         goto out;
 434
 435                 ret = property_enable(rphy, &rport->port_cfg->ls_det_en, true);
 436                 if (ret)
 437                         goto out;
 438
 439                 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
 440         }
 441
 442 out:
 443         mutex_unlock(&rport->mutex);
 444         return ret;
 445 }
 446
 447 static int rockchip_usb2phy_power_on(struct phy *phy)
 448 {
 449         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 450         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 451         int ret;
 452
 453         dev_dbg(&rport->phy->dev, "port power on\n");
 454
 455         if (!rport->suspended)
 456                 return 0;
 457
 458         ret = clk_prepare_enable(rphy->clk480m);
 459         if (ret)
 460                 return ret;
 461
 462         ret = property_enable(rphy, &rport->port_cfg->phy_sus, false);
 463         if (ret)
 464                 return ret;
 465
 466         rport->suspended = false;
 467         return 0;
 468 }
 469
 470 static int rockchip_usb2phy_power_off(struct phy *phy)
 471 {
 472         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 473         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 474         int ret;
 475
 476         dev_dbg(&rport->phy->dev, "port power off\n");
 477
 478         if (rport->suspended)
 479                 return 0;
 480
 481         ret = property_enable(rphy, &rport->port_cfg->phy_sus, true);
 482         if (ret)
 483                 return ret;
 484
 485         rport->suspended = true;
 486         clk_disable_unprepare(rphy->clk480m);
 487
 488         return 0;
 489 }
 490
 491 static int rockchip_usb2phy_exit(struct phy *phy)
 492 {
 493         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 494
 495         if (rport->port_id == USB2PHY_PORT_OTG &&
 496             rport->mode != USB_DR_MODE_HOST) {
 497                 cancel_delayed_work_sync(&rport->otg_sm_work);
 498                 cancel_delayed_work_sync(&rport->chg_work);
 499         } else if (rport->port_id == USB2PHY_PORT_HOST)
 500                 cancel_delayed_work_sync(&rport->sm_work);
 501
 502         return 0;
 503 }
 504
 505 static const struct phy_ops rockchip_usb2phy_ops = {
 506         .init           = rockchip_usb2phy_init,
 507         .exit           = rockchip_usb2phy_exit,
 508         .power_on       = rockchip_usb2phy_power_on,
 509         .power_off      = rockchip_usb2phy_power_off,
 510         .owner          = THIS_MODULE,
 511 };
 512
 513 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
 514 {
 515         struct rockchip_usb2phy_port *rport =
 516                 container_of(work, struct rockchip_usb2phy_port,
 517                              otg_sm_work.work);
 518         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 519         static unsigned int cable;
 520         unsigned long delay;
 521         bool vbus_attach, sch_work, notify_charger;
 522
 523         if (rport->utmi_avalid)
 524                 vbus_attach =
 525                         property_enabled(rphy, &rport->port_cfg->utmi_avalid);
 526         else
 527                 vbus_attach =
 528                         property_enabled(rphy, &rport->port_cfg->utmi_bvalid);
 529
 530         sch_work = false;
 531         notify_charger = false;
 532         delay = OTG_SCHEDULE_DELAY;
 533         dev_dbg(&rport->phy->dev, "%s otg sm work\n",
 534                 usb_otg_state_string(rport->state));
 535
 536         switch (rport->state) {
 537         case OTG_STATE_UNDEFINED:
 538                 rport->state = OTG_STATE_B_IDLE;
 539                 if (!vbus_attach)
 540                         rockchip_usb2phy_power_off(rport->phy);
 541                 /* fall through */
 542         case OTG_STATE_B_IDLE:
 543                 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) > 0) {
 544                         dev_dbg(&rport->phy->dev, "usb otg host connect\n");
 545                         rport->state = OTG_STATE_A_HOST;
 546                         rockchip_usb2phy_power_on(rport->phy);
 547                         return;
 548                 } else if (vbus_attach) {
 549                         dev_dbg(&rport->phy->dev, "vbus_attach\n");
 550                         switch (rphy->chg_state) {
 551                         case USB_CHG_STATE_UNDEFINED:
 552                                 schedule_delayed_work(&rport->chg_work, 0);
 553                                 return;
 554                         case USB_CHG_STATE_DETECTED:
 555                                 switch (rphy->chg_type) {
 556                                 case POWER_SUPPLY_TYPE_USB:
 557                                         dev_dbg(&rport->phy->dev,
 558                                                 "sdp cable is connecetd\n");
 559                                         rockchip_usb2phy_power_on(rport->phy);
 560                                         rport->state = OTG_STATE_B_PERIPHERAL;
 561                                         notify_charger = true;
 562                                         sch_work = true;
 563                                         cable = EXTCON_CHG_USB_SDP;
 564                                         break;
 565                                 case POWER_SUPPLY_TYPE_USB_DCP:
 566                                         dev_dbg(&rport->phy->dev,
 567                                                 "dcp cable is connecetd\n");
 568                                         rockchip_usb2phy_power_off(rport->phy);
 569                                         notify_charger = true;
 570                                         sch_work = true;
 571                                         cable = EXTCON_CHG_USB_DCP;
 572                                         break;
 573                                 case POWER_SUPPLY_TYPE_USB_CDP:
 574                                         dev_dbg(&rport->phy->dev,
 575                                                 "cdp cable is connecetd\n");
 576                                         rockchip_usb2phy_power_on(rport->phy);
 577                                         rport->state = OTG_STATE_B_PERIPHERAL;
 578                                         notify_charger = true;
 579                                         sch_work = true;
 580                                         cable = EXTCON_CHG_USB_CDP;
 581                                         break;
 582                                 default:
 583                                         break;
 584                                 }
 585                                 break;
 586                         default:
 587                                 break;
 588                         }
 589                 } else {
 590                         notify_charger = true;
 591                         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
 592                         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
 593                 }
 594
 595                 if (rport->vbus_attached != vbus_attach) {
 596                         rport->vbus_attached = vbus_attach;
 597
 598                         if (notify_charger && rphy->edev) {
 599                                 extcon_set_cable_state_(rphy->edev,
 600                                                         cable, vbus_attach);
 601                                 if (cable == EXTCON_CHG_USB_SDP)
 602                                         extcon_set_state_sync(rphy->edev,
 603                                                               EXTCON_USB,
 604                                                               vbus_attach);
 605                         }
 606                 }
 607                 break;
 608         case OTG_STATE_B_PERIPHERAL:
 609                 if (!vbus_attach) {
 610                         dev_dbg(&rport->phy->dev, "usb disconnect\n");
 611                         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
 612                         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
 613                         rport->state = OTG_STATE_B_IDLE;
 614                         delay = 0;
 615                         rockchip_usb2phy_power_off(rport->phy);
 616                 }
 617                 sch_work = true;
 618                 break;
 619         case OTG_STATE_A_HOST:
 620                 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) == 0) {
 621                         dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
 622                         rport->state = OTG_STATE_B_IDLE;
 623                         rockchip_usb2phy_power_off(rport->phy);
 624                 }
 625                 break;
 626         default:
 627                 break;
 628         }
 629
 630         if (sch_work)
 631                 schedule_delayed_work(&rport->otg_sm_work, delay);
 632 }
 633
 634 static const char *chg_to_string(enum power_supply_type chg_type)
 635 {
 636         switch (chg_type) {
 637         case POWER_SUPPLY_TYPE_USB:
 638                 return "USB_SDP_CHARGER";
 639         case POWER_SUPPLY_TYPE_USB_DCP:
 640                 return "USB_DCP_CHARGER";
 641         case POWER_SUPPLY_TYPE_USB_CDP:
 642                 return "USB_CDP_CHARGER";
 643         default:
 644                 return "INVALID_CHARGER";
 645         }
 646 }
 647
 648 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
 649                                     bool en)
 650 {
 651         property_enable(rphy, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
 652         property_enable(rphy, &rphy->phy_cfg->chg_det.idp_src_en, en);
 653 }
 654
 655 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
 656                                             bool en)
 657 {
 658         property_enable(rphy, &rphy->phy_cfg->chg_det.vdp_src_en, en);
 659         property_enable(rphy, &rphy->phy_cfg->chg_det.idm_sink_en, en);
 660 }
 661
 662 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
 663                                               bool en)
 664 {
 665         property_enable(rphy, &rphy->phy_cfg->chg_det.vdm_src_en, en);
 666         property_enable(rphy, &rphy->phy_cfg->chg_det.idp_sink_en, en);
 667 }
 668
 669 #define CHG_DCD_POLL_TIME       (100 * HZ / 1000)
 670 #define CHG_DCD_MAX_RETRIES     6
 671 #define CHG_PRIMARY_DET_TIME    (40 * HZ / 1000)
 672 #define CHG_SECONDARY_DET_TIME  (40 * HZ / 1000)
 673 static void rockchip_chg_detect_work(struct work_struct *work)
 674 {
 675         struct rockchip_usb2phy_port *rport =
 676                 container_of(work, struct rockchip_usb2phy_port, chg_work.work);
 677         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 678         bool is_dcd, tmout, vout;
 679         unsigned long delay;
 680
 681         dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
 682                 rphy->chg_state);
 683         switch (rphy->chg_state) {
 684         case USB_CHG_STATE_UNDEFINED:
 685                 if (!rport->suspended)
 686                         rockchip_usb2phy_power_off(rport->phy);
 687                 /* put the controller in non-driving mode */
 688                 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, false);
 689                 /* Start DCD processing stage 1 */
 690                 rockchip_chg_enable_dcd(rphy, true);
 691                 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
 692                 rphy->dcd_retries = 0;
 693                 delay = CHG_DCD_POLL_TIME;
 694                 break;
 695         case USB_CHG_STATE_WAIT_FOR_DCD:
 696                 /* get data contact detection status */
 697                 is_dcd = property_enabled(rphy, &rphy->phy_cfg->chg_det.dp_det);
 698                 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
 699                 /* stage 2 */
 700                 if (is_dcd || tmout) {
 701                         /* stage 4 */
 702                         /* Turn off DCD circuitry */
 703                         rockchip_chg_enable_dcd(rphy, false);
 704                         /* Voltage Source on DP, Probe on DM */
 705                         rockchip_chg_enable_primary_det(rphy, true);
 706                         delay = CHG_PRIMARY_DET_TIME;
 707                         rphy->chg_state = USB_CHG_STATE_DCD_DONE;
 708                 } else {
 709                         /* stage 3 */
 710                         delay = CHG_DCD_POLL_TIME;
 711                 }
 712                 break;
 713         case USB_CHG_STATE_DCD_DONE:
 714                 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.cp_det);
 715                 rockchip_chg_enable_primary_det(rphy, false);
 716                 if (vout) {
 717                         /* Voltage Source on DM, Probe on DP  */
 718                         rockchip_chg_enable_secondary_det(rphy, true);
 719                         delay = CHG_SECONDARY_DET_TIME;
 720                         rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
 721                 } else {
 722                         if (rphy->dcd_retries == CHG_DCD_MAX_RETRIES) {
 723                                 /* floating charger found */
 724                                 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
 725                                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 726                                 delay = 0;
 727                         } else {
 728                                 rphy->chg_type = POWER_SUPPLY_TYPE_USB;
 729                                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 730                                 delay = 0;
 731                         }
 732                 }
 733                 break;
 734         case USB_CHG_STATE_PRIMARY_DONE:
 735                 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.dcp_det);
 736                 /* Turn off voltage source */
 737                 rockchip_chg_enable_secondary_det(rphy, false);
 738                 if (vout)
 739                         rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
 740                 else
 741                         rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
 742                 /* fall through */
 743         case USB_CHG_STATE_SECONDARY_DONE:
 744                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 745                 delay = 0;
 746                 /* fall through */
 747         case USB_CHG_STATE_DETECTED:
 748                 /* put the controller in normal mode */
 749                 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, true);
 750                 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
 751                 dev_info(&rport->phy->dev, "charger = %s\n",
 752                          chg_to_string(rphy->chg_type));
 753                 return;
 754         default:
 755                 return;
 756         }
 757
 758         schedule_delayed_work(&rport->chg_work, delay);
 759 }
 760
 761 /*
 762  * The function manage host-phy port state and suspend/resume phy port
 763  * to save power.
 764  *
 765  * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
 766  * devices is disconnect or not. Besides, we do not need care it is FS/LS
 767  * disconnected or HS disconnected, actually, we just only need get the
 768  * device is disconnected at last through rearm the delayed work,
 769  * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
 770  *
 771  * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
 772  * some clk related APIs, so do not invoke it from interrupt context directly.
 773  */
 774 static void rockchip_usb2phy_sm_work(struct work_struct *work)
 775 {
 776         struct rockchip_usb2phy_port *rport =
 777                 container_of(work, struct rockchip_usb2phy_port, sm_work.work);
 778         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 779         unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
 780                           rport->port_cfg->utmi_hstdet.bitstart + 1;
 781         unsigned int ul, uhd, state;
 782         unsigned int ul_mask, uhd_mask;
 783         int ret;
 784
 785         mutex_lock(&rport->mutex);
 786
 787         ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
 788         if (ret < 0)
 789                 goto next_schedule;
 790
 791         ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset,
 792                           &uhd);
 793         if (ret < 0)
 794                 goto next_schedule;
 795
 796         uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
 797                            rport->port_cfg->utmi_hstdet.bitstart);
 798         ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
 799                           rport->port_cfg->utmi_ls.bitstart);
 800
 801         /* stitch on utmi_ls and utmi_hstdet as phy state */
 802         state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
 803                 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
 804
 805         switch (state) {
 806         case PHY_STATE_HS_ONLINE:
 807                 dev_dbg(&rport->phy->dev, "HS online\n");
 808                 break;
 809         case PHY_STATE_FS_LS_ONLINE:
 810                 /*
 811                  * For FS/LS device, the online state share with connect state
 812                  * from utmi_ls and utmi_hstdet register, so we distinguish
 813                  * them via suspended flag.
 814                  *
 815                  * Plus, there are two cases, one is D- Line pull-up, and D+
 816                  * line pull-down, the state is 4; another is D+ line pull-up,
 817                  * and D- line pull-down, the state is 2.
 818                  */
 819                 if (!rport->suspended) {
 820                         /* D- line pull-up, D+ line pull-down */
 821                         dev_dbg(&rport->phy->dev, "FS/LS online\n");
 822                         break;
 823                 }
 824                 /* fall through */
 825         case PHY_STATE_CONNECT:
 826                 if (rport->suspended) {
 827                         dev_dbg(&rport->phy->dev, "Connected\n");
 828                         rockchip_usb2phy_power_on(rport->phy);
 829                         rport->suspended = false;
 830                 } else {
 831                         /* D+ line pull-up, D- line pull-down */
 832                         dev_dbg(&rport->phy->dev, "FS/LS online\n");
 833                 }
 834                 break;
 835         case PHY_STATE_DISCONNECT:
 836                 if (!rport->suspended) {
 837                         dev_dbg(&rport->phy->dev, "Disconnected\n");
 838                         rockchip_usb2phy_power_off(rport->phy);
 839                         rport->suspended = true;
 840                 }
 841
 842                 /*
 843                  * activate the linestate detection to get the next device
 844                  * plug-in irq.
 845                  */
 846                 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 847                 property_enable(rphy, &rport->port_cfg->ls_det_en, true);
 848
 849                 /*
 850                  * we don't need to rearm the delayed work when the phy port
 851                  * is suspended.
 852                  */
 853                 mutex_unlock(&rport->mutex);
 854                 return;
 855         default:
 856                 dev_dbg(&rport->phy->dev, "unknown phy state\n");
 857                 break;
 858         }
 859
 860 next_schedule:
 861         mutex_unlock(&rport->mutex);
 862         schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
 863 }
 864
 865 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
 866 {
 867         struct rockchip_usb2phy_port *rport = data;
 868         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 869
 870         if (!property_enabled(rphy, &rport->port_cfg->ls_det_st))
 871                 return IRQ_NONE;
 872
 873         mutex_lock(&rport->mutex);
 874
 875         /* disable linestate detect irq and clear its status */
 876         property_enable(rphy, &rport->port_cfg->ls_det_en, false);
 877         property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 878
 879         mutex_unlock(&rport->mutex);
 880
 881         /*
 882          * In this case for host phy port, a new device is plugged in,
 883          * meanwhile, if the phy port is suspended, we need rearm the work to
 884          * resume it and mange its states; otherwise, we do nothing about that.
 885          */
 886         if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST)
 887                 rockchip_usb2phy_sm_work(&rport->sm_work.work);
 888
 889         return IRQ_HANDLED;
 890 }
 891
 892 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
 893 {
 894         struct rockchip_usb2phy_port *rport = data;
 895         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 896
 897         if (!property_enabled(rphy, &rport->port_cfg->bvalid_det_st))
 898                 return IRQ_NONE;
 899
 900         mutex_lock(&rport->mutex);
 901
 902         /* clear bvalid detect irq pending status */
 903         property_enable(rphy, &rport->port_cfg->bvalid_det_clr, true);
 904
 905         mutex_unlock(&rport->mutex);
 906
 907         rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
 908
 909         return IRQ_HANDLED;
 910 }
 911
 912 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
 913                                            struct rockchip_usb2phy_port *rport,
 914                                            struct device_node *child_np)
 915 {
 916         int ret;
 917
 918         rport->port_id = USB2PHY_PORT_HOST;
 919         rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
 920         rport->suspended = true;
 921
 922         mutex_init(&rport->mutex);
 923         INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
 924
 925         rport->ls_irq = of_irq_get_byname(child_np, "linestate");
 926         if (rport->ls_irq < 0) {
 927                 dev_err(rphy->dev, "no linestate irq provided\n");
 928                 return rport->ls_irq;
 929         }
 930
 931         ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
 932                                         rockchip_usb2phy_linestate_irq,
 933                                         IRQF_ONESHOT,
 934                                         "rockchip_usb2phy", rport);
 935         if (ret) {
 936                 dev_err(rphy->dev, "failed to request linestate irq handle\n");
 937                 return ret;
 938         }
 939
 940         return 0;
 941 }
 942
 943 static int rockchip_otg_event(struct notifier_block *nb,
 944                               unsigned long event, void *ptr)
 945 {
 946         struct rockchip_usb2phy_port *rport =
 947                 container_of(nb, struct rockchip_usb2phy_port, event_nb);
 948
 949         schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
 950
 951         return NOTIFY_DONE;
 952 }
 953
 954 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
 955                                           struct rockchip_usb2phy_port *rport,
 956                                           struct device_node *child_np)
 957 {
 958         int ret;
 959
 960         rport->port_id = USB2PHY_PORT_OTG;
 961         rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
 962         rport->state = OTG_STATE_UNDEFINED;
 963
 964         /*
 965          * set suspended flag to true, but actually don't
 966          * put phy in suspend mode, it aims to enable usb
 967          * phy and clock in power_on() called by usb controller
 968          * driver during probe.
 969          */
 970         rport->suspended = true;
 971         rport->vbus_attached = false;
 972
 973         mutex_init(&rport->mutex);
 974
 975         rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
 976         if (rport->mode == USB_DR_MODE_HOST) {
 977                 ret = 0;
 978                 goto out;
 979         }
 980
 981         INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
 982         INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
 983
 984         rport->utmi_avalid =
 985                 of_property_read_bool(child_np, "rockchip,utmi-avalid");
 986
 987         rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
 988         if (rport->bvalid_irq < 0) {
 989                 dev_err(rphy->dev, "no vbus valid irq provided\n");
 990                 ret = rport->bvalid_irq;
 991                 goto out;
 992         }
 993
 994         ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, NULL,
 995                                         rockchip_usb2phy_bvalid_irq,
 996                                         IRQF_ONESHOT,
 997                                         "rockchip_usb2phy_bvalid", rport);
 998         if (ret) {
 999                 dev_err(rphy->dev, "failed to request otg-bvalid irq handle\n");
1000                 goto out;
1001         }
1002
1003         if (!IS_ERR(rphy->edev)) {
1004                 rport->event_nb.notifier_call = rockchip_otg_event;
1005
1006                 ret = extcon_register_notifier(rphy->edev, EXTCON_USB_HOST,
1007                                                &rport->event_nb);
1008                 if (ret)
1009                         dev_err(rphy->dev, "register USB HOST notifier failed\n");
1010         }
1011
1012 out:
1013         return ret;
1014 }
1015
1016 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1017 {
1018         struct device *dev = &pdev->dev;
1019         struct device_node *np = dev->of_node;
1020         struct device_node *child_np;
1021         struct phy_provider *provider;
1022         struct rockchip_usb2phy *rphy;
1023         const struct rockchip_usb2phy_cfg *phy_cfgs;
1024         const struct of_device_id *match;
1025         unsigned int reg;
1026         int index, ret;
1027
1028         rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1029         if (!rphy)
1030                 return -ENOMEM;
1031
1032         match = of_match_device(dev->driver->of_match_table, dev);
1033         if (!match || !match->data) {
1034                 dev_err(dev, "phy configs are not assigned!\n");
1035                 return -EINVAL;
1036         }
1037
1038         if (!dev->parent || !dev->parent->of_node)
1039                 return -EINVAL;
1040
1041         rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1042         if (IS_ERR(rphy->grf))
1043                 return PTR_ERR(rphy->grf);
1044
1045         if (of_property_read_u32(np, "reg", &reg)) {
1046                 dev_err(dev, "the reg property is not assigned in %s node\n",
1047                         np->name);
1048                 return -EINVAL;
1049         }
1050
1051         rphy->dev = dev;
1052         phy_cfgs = match->data;
1053         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1054         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1055         platform_set_drvdata(pdev, rphy);
1056
1057         ret = rockchip_usb2phy_extcon_register(rphy);
1058         if (ret)
1059                 return ret;
1060
1061         /* find out a proper config which can be matched with dt. */
1062         index = 0;
1063         while (phy_cfgs[index].reg) {
1064                 if (phy_cfgs[index].reg == reg) {
1065                         rphy->phy_cfg = &phy_cfgs[index];
1066                         break;
1067                 }
1068
1069                 ++index;
1070         }
1071
1072         if (!rphy->phy_cfg) {
1073                 dev_err(dev, "no phy-config can be matched with %s node\n",
1074                         np->name);
1075                 return -EINVAL;
1076         }
1077
1078         rphy->clk = of_clk_get_by_name(np, "phyclk");
1079         if (!IS_ERR(rphy->clk)) {
1080                 clk_prepare_enable(rphy->clk);
1081         } else {
1082                 dev_info(&pdev->dev, "no phyclk specified\n");
1083                 rphy->clk = NULL;
1084         }
1085
1086         ret = rockchip_usb2phy_clk480m_register(rphy);
1087         if (ret) {
1088                 dev_err(dev, "failed to register 480m output clock\n");
1089                 goto disable_clks;
1090         }
1091
1092         index = 0;
1093         for_each_available_child_of_node(np, child_np) {
1094                 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1095                 struct phy *phy;
1096
1097                 /* This driver aims to support both otg-port and host-port */
1098                 if (of_node_cmp(child_np->name, "host-port") &&
1099                     of_node_cmp(child_np->name, "otg-port"))
1100                         goto next_child;
1101
1102                 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1103                 if (IS_ERR(phy)) {
1104                         dev_err(dev, "failed to create phy\n");
1105                         ret = PTR_ERR(phy);
1106                         goto put_child;
1107                 }
1108
1109                 rport->phy = phy;
1110                 phy_set_drvdata(rport->phy, rport);
1111
1112                 /* initialize otg/host port separately */
1113                 if (!of_node_cmp(child_np->name, "host-port")) {
1114                         ret = rockchip_usb2phy_host_port_init(rphy, rport,
1115                                                               child_np);
1116                         if (ret)
1117                                 goto put_child;
1118                 } else {
1119                         ret = rockchip_usb2phy_otg_port_init(rphy, rport,
1120                                                              child_np);
1121                         if (ret)
1122                                 goto put_child;
1123                 }
1124
1125 next_child:
1126                 /* to prevent out of boundary */
1127                 if (++index >= rphy->phy_cfg->num_ports)
1128                         break;
1129         }
1130
1131         provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1132         return PTR_ERR_OR_ZERO(provider);
1133
1134 put_child:
1135         of_node_put(child_np);
1136 disable_clks:
1137         if (rphy->clk) {
1138                 clk_disable_unprepare(rphy->clk);
1139                 clk_put(rphy->clk);
1140         }
1141         return ret;
1142 }
1143
1144 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
1145         {
1146                 .reg = 0x700,
1147                 .num_ports      = 2,
1148                 .clkout_ctl     = { 0x0724, 15, 15, 1, 0 },
1149                 .port_cfgs      = {
1150                         [USB2PHY_PORT_HOST] = {
1151                                 .phy_sus        = { 0x0728, 15, 0, 0, 0x1d1 },
1152                                 .ls_det_en      = { 0x0680, 4, 4, 0, 1 },
1153                                 .ls_det_st      = { 0x0690, 4, 4, 0, 1 },
1154                                 .ls_det_clr     = { 0x06a0, 4, 4, 0, 1 },
1155                                 .utmi_ls        = { 0x049c, 14, 13, 0, 1 },
1156                                 .utmi_hstdet    = { 0x049c, 12, 12, 0, 1 }
1157                         }
1158                 },
1159         },
1160         { /* sentinel */ }
1161 };
1162
1163 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1164         {
1165                 .reg            = 0xe450,
1166                 .num_ports      = 2,
1167                 .clkout_ctl     = { 0xe450, 4, 4, 1, 0 },
1168                 .port_cfgs      = {
1169                         [USB2PHY_PORT_OTG] = {
1170                                 .phy_sus        = { 0xe454, 1, 0, 2, 1 },
1171                                 .bvalid_det_en  = { 0xe3c0, 3, 3, 0, 1 },
1172                                 .bvalid_det_st  = { 0xe3e0, 3, 3, 0, 1 },
1173                                 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1174                                 .utmi_avalid    = { 0xe2ac, 7, 7, 0, 1 },
1175                                 .utmi_bvalid    = { 0xe2ac, 12, 12, 0, 1 },
1176                         },
1177                         [USB2PHY_PORT_HOST] = {
1178                                 .phy_sus        = { 0xe458, 1, 0, 0x2, 0x1 },
1179                                 .ls_det_en      = { 0xe3c0, 6, 6, 0, 1 },
1180                                 .ls_det_st      = { 0xe3e0, 6, 6, 0, 1 },
1181                                 .ls_det_clr     = { 0xe3d0, 6, 6, 0, 1 },
1182                                 .utmi_ls        = { 0xe2ac, 22, 21, 0, 1 },
1183                                 .utmi_hstdet    = { 0xe2ac, 23, 23, 0, 1 }
1184                         }
1185                 },
1186                 .chg_det = {
1187                         .opmode         = { 0xe454, 3, 0, 5, 1 },
1188                         .cp_det         = { 0xe2ac, 2, 2, 0, 1 },
1189                         .dcp_det        = { 0xe2ac, 1, 1, 0, 1 },
1190                         .dp_det         = { 0xe2ac, 0, 0, 0, 1 },
1191                         .idm_sink_en    = { 0xe450, 8, 8, 0, 1 },
1192                         .idp_sink_en    = { 0xe450, 7, 7, 0, 1 },
1193                         .idp_src_en     = { 0xe450, 9, 9, 0, 1 },
1194                         .rdm_pdwn_en    = { 0xe450, 10, 10, 0, 1 },
1195                         .vdm_src_en     = { 0xe450, 12, 12, 0, 1 },
1196                         .vdp_src_en     = { 0xe450, 11, 11, 0, 1 },
1197                 },
1198         },
1199         {
1200                 .reg            = 0xe460,
1201                 .num_ports      = 2,
1202                 .clkout_ctl     = { 0xe460, 4, 4, 1, 0 },
1203                 .port_cfgs      = {
1204                         [USB2PHY_PORT_OTG] = {
1205                                 .phy_sus        = { 0xe464, 1, 0, 2, 1 },
1206                                 .bvalid_det_en  = { 0xe3c0, 8, 8, 0, 1 },
1207                                 .bvalid_det_st  = { 0xe3e0, 8, 8, 0, 1 },
1208                                 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1209                                 .utmi_avalid    = { 0xe2ac, 10, 10, 0, 1 },
1210                                 .utmi_bvalid    = { 0xe2ac, 16, 16, 0, 1 },
1211                         },
1212                         [USB2PHY_PORT_HOST] = {
1213                                 .phy_sus        = { 0xe468, 1, 0, 0x2, 0x1 },
1214                                 .ls_det_en      = { 0xe3c0, 11, 11, 0, 1 },
1215                                 .ls_det_st      = { 0xe3e0, 11, 11, 0, 1 },
1216                                 .ls_det_clr     = { 0xe3d0, 11, 11, 0, 1 },
1217                                 .utmi_ls        = { 0xe2ac, 26, 25, 0, 1 },
1218                                 .utmi_hstdet    = { 0xe2ac, 27, 27, 0, 1 }
1219                         }
1220                 },
1221         },
1222         { /* sentinel */ }
1223 };
1224
1225 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1226         { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
1227         { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
1228         {}
1229 };
1230 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
1231
1232 static struct platform_driver rockchip_usb2phy_driver = {
1233         .probe          = rockchip_usb2phy_probe,
1234         .driver         = {
1235                 .name   = "rockchip-usb2phy",
1236                 .of_match_table = rockchip_usb2phy_dt_match,
1237         },
1238 };
1239 module_platform_driver(rockchip_usb2phy_driver);
1240
1241 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1242 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
1243 MODULE_LICENSE("GPL v2");