drivers/phy/phy-rockchip-inno-usb2.c

   1 /*
   2  * Rockchip USB2.0 PHY with Innosilicon IP block driver
   3  *
   4  * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/delay.h>
  20 #include <linux/extcon.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/gpio/consumer.h>
  24 #include <linux/jiffies.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/mutex.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/phy/phy.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/power_supply.h>
  35 #include <linux/regmap.h>
  36 #include <linux/mfd/syscon.h>
  37 #include <linux/usb/of.h>
  38 #include <linux/usb/otg.h>
  39
  40 #define BIT_WRITEABLE_SHIFT     16
  41 #define SCHEDULE_DELAY          (60 * HZ)
  42 #define OTG_SCHEDULE_DELAY      (2 * HZ)
  43
  44 enum rockchip_usb2phy_port_id {
  45         USB2PHY_PORT_OTG,
  46         USB2PHY_PORT_HOST,
  47         USB2PHY_NUM_PORTS,
  48 };
  49
  50 enum rockchip_usb2phy_host_state {
  51         PHY_STATE_HS_ONLINE     = 0,
  52         PHY_STATE_DISCONNECT    = 1,
  53         PHY_STATE_CONNECT       = 2,
  54         PHY_STATE_FS_LS_ONLINE  = 4,
  55 };
  56
  57 /**
  58  * Different states involved in USB charger detection.
  59  * USB_CHG_STATE_UNDEFINED      USB charger is not connected or detection
  60  *                              process is not yet started.
  61  * USB_CHG_STATE_WAIT_FOR_DCD   Waiting for Data pins contact.
  62  * USB_CHG_STATE_DCD_DONE       Data pin contact is detected.
  63  * USB_CHG_STATE_PRIMARY_DONE   Primary detection is completed (Detects
  64  *                              between SDP and DCP/CDP).
  65  * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
  66  *                              between DCP and CDP).
  67  * USB_CHG_STATE_DETECTED       USB charger type is determined.
  68  */
  69 enum usb_chg_state {
  70         USB_CHG_STATE_UNDEFINED = 0,
  71         USB_CHG_STATE_WAIT_FOR_DCD,
  72         USB_CHG_STATE_DCD_DONE,
  73         USB_CHG_STATE_PRIMARY_DONE,
  74         USB_CHG_STATE_SECONDARY_DONE,
  75         USB_CHG_STATE_DETECTED,
  76 };
  77
  78 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
  79         EXTCON_USB,
  80         EXTCON_USB_HOST,
  81         EXTCON_CHG_USB_SDP,
  82         EXTCON_CHG_USB_CDP,
  83         EXTCON_CHG_USB_DCP,
  84         EXTCON_CHG_USB_SLOW,
  85         EXTCON_NONE,
  86 };
  87
  88 struct usb2phy_reg {
  89         unsigned int    offset;
  90         unsigned int    bitend;
  91         unsigned int    bitstart;
  92         unsigned int    disable;
  93         unsigned int    enable;
  94 };
  95
  96 /**
  97  * struct rockchip_chg_det_reg: usb charger detect registers
  98  * @cp_det: charging port detected successfully.
  99  * @dcp_det: dedicated charging port detected successfully.
 100  * @dp_det: assert data pin connect successfully.
 101  * @idm_sink_en: open dm sink curren.
 102  * @idp_sink_en: open dp sink current.
 103  * @idp_src_en: open dm source current.
 104  * @rdm_pdwn_en: open dm pull down resistor.
 105  * @vdm_src_en: open dm voltage source.
 106  * @vdp_src_en: open dp voltage source.
 107  * @opmode: utmi operational mode.
 108  */
 109 struct rockchip_chg_det_reg {
 110         struct usb2phy_reg      cp_det;
 111         struct usb2phy_reg      dcp_det;
 112         struct usb2phy_reg      dp_det;
 113         struct usb2phy_reg      idm_sink_en;
 114         struct usb2phy_reg      idp_sink_en;
 115         struct usb2phy_reg      idp_src_en;
 116         struct usb2phy_reg      rdm_pdwn_en;
 117         struct usb2phy_reg      vdm_src_en;
 118         struct usb2phy_reg      vdp_src_en;
 119         struct usb2phy_reg      opmode;
 120 };
 121
 122 /**
 123  * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
 124  * @phy_sus: phy suspend register.
 125  * @bvalid_det_en: vbus valid rise detection enable register.
 126  * @bvalid_det_st: vbus valid rise detection status register.
 127  * @bvalid_det_clr: vbus valid rise detection clear register.
 128  * @ls_det_en: linestate detection enable register.
 129  * @ls_det_st: linestate detection state register.
 130  * @ls_det_clr: linestate detection clear register.
 131  * @utmi_avalid: utmi vbus avalid status register.
 132  * @utmi_bvalid: utmi vbus bvalid status register.
 133  * @utmi_ls: utmi linestate state register.
 134  * @utmi_hstdet: utmi host disconnect register.
 135  */
 136 struct rockchip_usb2phy_port_cfg {
 137         struct usb2phy_reg      phy_sus;
 138         struct usb2phy_reg      bvalid_det_en;
 139         struct usb2phy_reg      bvalid_det_st;
 140         struct usb2phy_reg      bvalid_det_clr;
 141         struct usb2phy_reg      ls_det_en;
 142         struct usb2phy_reg      ls_det_st;
 143         struct usb2phy_reg      ls_det_clr;
 144         struct usb2phy_reg      utmi_avalid;
 145         struct usb2phy_reg      utmi_bvalid;
 146         struct usb2phy_reg      utmi_ls;
 147         struct usb2phy_reg      utmi_hstdet;
 148 };
 149
 150 /**
 151  * struct rockchip_usb2phy_cfg: usb-phy configuration.
 152  * @reg: the address offset of grf for usb-phy config.
 153  * @num_ports: specify how many ports that the phy has.
 154  * @clkout_ctl: keep on/turn off output clk of phy.
 155  * @chg_det: charger detection registers.
 156  */
 157 struct rockchip_usb2phy_cfg {
 158         unsigned int    reg;
 159         unsigned int    num_ports;
 160         struct usb2phy_reg      clkout_ctl;
 161         const struct rockchip_usb2phy_port_cfg  port_cfgs[USB2PHY_NUM_PORTS];
 162         const struct rockchip_chg_det_reg       chg_det;
 163 };
 164
 165 /**
 166  * struct rockchip_usb2phy_port: usb-phy port data.
 167  * @port_id: flag for otg port or host port.
 168  * @suspended: phy suspended flag.
 169  * @utmi_avalid: utmi avalid status usage flag.
 170  *      true    - use avalid to get vbus status
 171  *      flase   - use bvalid to get vbus status
 172  * @vbus_attached: otg device vbus status.
 173  * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
 174  * @ls_irq: IRQ number assigned for linestate detection.
 175  * @mutex: for register updating in sm_work.
 176  * @chg_work: charge detect work.
 177  * @otg_sm_work: OTG state machine work.
 178  * @sm_work: HOST state machine work.
 179  * @phy_cfg: port register configuration, assigned by driver data.
 180  * @event_nb: hold event notification callback.
 181  * @state: define OTG enumeration states before device reset.
 182  * @mode: the dr_mode of the controller.
 183  */
 184 struct rockchip_usb2phy_port {
 185         struct phy      *phy;
 186         unsigned int    port_id;
 187         bool            suspended;
 188         bool            utmi_avalid;
 189         bool            vbus_attached;
 190         int             bvalid_irq;
 191         int             ls_irq;
 192         struct mutex    mutex;
 193         struct          delayed_work chg_work;
 194         struct          delayed_work otg_sm_work;
 195         struct          delayed_work sm_work;
 196         const struct    rockchip_usb2phy_port_cfg *port_cfg;
 197         struct notifier_block   event_nb;
 198         enum usb_otg_state      state;
 199         enum usb_dr_mode        mode;
 200 };
 201
 202 /**
 203  * struct rockchip_usb2phy: usb2.0 phy driver data.
 204  * @grf: General Register Files regmap.
 205  * @clk: clock struct of phy input clk.
 206  * @clk480m: clock struct of phy output clk.
 207  * @clk_hw: clock struct of phy output clk management.
 208  * @chg_state: states involved in USB charger detection.
 209  * @chg_type: USB charger types.
 210  * @dcd_retries: The retry count used to track Data contact
 211  *               detection process.
 212  * @edev: extcon device for notification registration
 213  * @phy_cfg: phy register configuration, assigned by driver data.
 214  * @ports: phy port instance.
 215  */
 216 struct rockchip_usb2phy {
 217         struct device   *dev;
 218         struct regmap   *grf;
 219         struct clk      *clk;
 220         struct clk      *clk480m;
 221         struct clk_hw   clk480m_hw;
 222         enum usb_chg_state      chg_state;
 223         enum power_supply_type  chg_type;
 224         u8                      dcd_retries;
 225         struct extcon_dev       *edev;
 226         const struct rockchip_usb2phy_cfg       *phy_cfg;
 227         struct rockchip_usb2phy_port    ports[USB2PHY_NUM_PORTS];
 228 };
 229
 230 static inline int property_enable(struct rockchip_usb2phy *rphy,
 231                                   const struct usb2phy_reg *reg, bool en)
 232 {
 233         unsigned int val, mask, tmp;
 234
 235         tmp = en ? reg->enable : reg->disable;
 236         mask = GENMASK(reg->bitend, reg->bitstart);
 237         val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
 238
 239         return regmap_write(rphy->grf, reg->offset, val);
 240 }
 241
 242 static inline bool property_enabled(struct rockchip_usb2phy *rphy,
 243                                     const struct usb2phy_reg *reg)
 244 {
 245         int ret;
 246         unsigned int tmp, orig;
 247         unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
 248
 249         ret = regmap_read(rphy->grf, reg->offset, &orig);
 250         if (ret)
 251                 return false;
 252
 253         tmp = (orig & mask) >> reg->bitstart;
 254         return tmp == reg->enable;
 255 }
 256
 257 static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
 258 {
 259         struct rockchip_usb2phy *rphy =
 260                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 261         int ret;
 262
 263         /* turn on 480m clk output if it is off */
 264         if (!property_enabled(rphy, &rphy->phy_cfg->clkout_ctl)) {
 265                 ret = property_enable(rphy, &rphy->phy_cfg->clkout_ctl, true);
 266                 if (ret)
 267                         return ret;
 268
 269                 /* waiting for the clk become stable */
 270                 usleep_range(1200, 1300);
 271         }
 272
 273         return 0;
 274 }
 275
 276 static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw)
 277 {
 278         struct rockchip_usb2phy *rphy =
 279                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 280
 281         /* turn off 480m clk output */
 282         property_enable(rphy, &rphy->phy_cfg->clkout_ctl, false);
 283 }
 284
 285 static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw)
 286 {
 287         struct rockchip_usb2phy *rphy =
 288                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 289
 290         return property_enabled(rphy, &rphy->phy_cfg->clkout_ctl);
 291 }
 292
 293 static unsigned long
 294 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
 295                                      unsigned long parent_rate)
 296 {
 297         return 480000000;
 298 }
 299
 300 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
 301         .prepare = rockchip_usb2phy_clk480m_prepare,
 302         .unprepare = rockchip_usb2phy_clk480m_unprepare,
 303         .is_prepared = rockchip_usb2phy_clk480m_prepared,
 304         .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
 305 };
 306
 307 static void rockchip_usb2phy_clk480m_unregister(void *data)
 308 {
 309         struct rockchip_usb2phy *rphy = data;
 310
 311         of_clk_del_provider(rphy->dev->of_node);
 312         clk_unregister(rphy->clk480m);
 313 }
 314
 315 static int
 316 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
 317 {
 318         struct device_node *node = rphy->dev->of_node;
 319         struct clk_init_data init;
 320         const char *clk_name;
 321         int ret;
 322
 323         init.flags = 0;
 324         init.name = "clk_usbphy_480m";
 325         init.ops = &rockchip_usb2phy_clkout_ops;
 326
 327         /* optional override of the clockname */
 328         of_property_read_string(node, "clock-output-names", &init.name);
 329
 330         if (rphy->clk) {
 331                 clk_name = __clk_get_name(rphy->clk);
 332                 init.parent_names = &clk_name;
 333                 init.num_parents = 1;
 334         } else {
 335                 init.parent_names = NULL;
 336                 init.num_parents = 0;
 337         }
 338
 339         rphy->clk480m_hw.init = &init;
 340
 341         /* register the clock */
 342         rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
 343         if (IS_ERR(rphy->clk480m)) {
 344                 ret = PTR_ERR(rphy->clk480m);
 345                 goto err_ret;
 346         }
 347
 348         ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
 349         if (ret < 0)
 350                 goto err_clk_provider;
 351
 352         ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister,
 353                               rphy);
 354         if (ret < 0)
 355                 goto err_unreg_action;
 356
 357         return 0;
 358
 359 err_unreg_action:
 360         of_clk_del_provider(node);
 361 err_clk_provider:
 362         clk_unregister(rphy->clk480m);
 363 err_ret:
 364         return ret;
 365 }
 366
 367 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
 368 {
 369         int ret;
 370         struct device_node *node = rphy->dev->of_node;
 371         struct extcon_dev *edev;
 372
 373         if (of_property_read_bool(node, "extcon")) {
 374                 edev = extcon_get_edev_by_phandle(rphy->dev, 0);
 375                 if (IS_ERR(edev)) {
 376                         if (PTR_ERR(edev) != -EPROBE_DEFER)
 377                                 dev_err(rphy->dev, "Invalid or missing extcon\n");
 378                         return PTR_ERR(edev);
 379                 }
 380         } else {
 381                 /* Initialize extcon device */
 382                 edev = devm_extcon_dev_allocate(rphy->dev,
 383                                                 rockchip_usb2phy_extcon_cable);
 384
 385                 if (IS_ERR(edev))
 386                         return -ENOMEM;
 387
 388                 ret = devm_extcon_dev_register(rphy->dev, edev);
 389                 if (ret) {
 390                         dev_err(rphy->dev, "failed to register extcon device\n");
 391                         return ret;
 392                 }
 393         }
 394
 395         rphy->edev = edev;
 396
 397         return 0;
 398 }
 399
 400 static int rockchip_usb2phy_init(struct phy *phy)
 401 {
 402         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 403         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 404         int ret = 0;
 405
 406         mutex_lock(&rport->mutex);
 407
 408         if (rport->port_id == USB2PHY_PORT_OTG) {
 409                 if (rport->mode != USB_DR_MODE_HOST) {
 410                         /* clear bvalid status and enable bvalid detect irq */
 411                         ret = property_enable(rphy,
 412                                               &rport->port_cfg->bvalid_det_clr,
 413                                               true);
 414                         if (ret)
 415                                 goto out;
 416
 417                         ret = property_enable(rphy,
 418                                               &rport->port_cfg->bvalid_det_en,
 419                                               true);
 420                         if (ret)
 421                                 goto out;
 422
 423                         schedule_delayed_work(&rport->otg_sm_work,
 424                                               OTG_SCHEDULE_DELAY);
 425                 } else {
 426                         /* If OTG works in host only mode, do nothing. */
 427                         dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
 428                 }
 429         } else if (rport->port_id == USB2PHY_PORT_HOST) {
 430                 /* clear linestate and enable linestate detect irq */
 431                 ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 432                 if (ret)
 433                         goto out;
 434
 435                 ret = property_enable(rphy, &rport->port_cfg->ls_det_en, true);
 436                 if (ret)
 437                         goto out;
 438
 439                 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
 440         }
 441
 442 out:
 443         mutex_unlock(&rport->mutex);
 444         return ret;
 445 }
 446
 447 static int rockchip_usb2phy_power_on(struct phy *phy)
 448 {
 449         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 450         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 451         int ret;
 452
 453         dev_dbg(&rport->phy->dev, "port power on\n");
 454
 455         if (!rport->suspended)
 456                 return 0;
 457
 458         ret = clk_prepare_enable(rphy->clk480m);
 459         if (ret)
 460                 return ret;
 461
 462         ret = property_enable(rphy, &rport->port_cfg->phy_sus, false);
 463         if (ret)
 464                 return ret;
 465
 466         rport->suspended = false;
 467         return 0;
 468 }
 469
 470 static int rockchip_usb2phy_power_off(struct phy *phy)
 471 {
 472         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 473         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 474         int ret;
 475
 476         dev_dbg(&rport->phy->dev, "port power off\n");
 477
 478         if (rport->suspended)
 479                 return 0;
 480
 481         ret = property_enable(rphy, &rport->port_cfg->phy_sus, true);
 482         if (ret)
 483                 return ret;
 484
 485         rport->suspended = true;
 486         clk_disable_unprepare(rphy->clk480m);
 487
 488         return 0;
 489 }
 490
 491 static int rockchip_usb2phy_exit(struct phy *phy)
 492 {
 493         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 494
 495         if (rport->port_id == USB2PHY_PORT_OTG &&
 496             rport->mode != USB_DR_MODE_HOST) {
 497                 cancel_delayed_work_sync(&rport->otg_sm_work);
 498                 cancel_delayed_work_sync(&rport->chg_work);
 499         } else if (rport->port_id == USB2PHY_PORT_HOST)
 500                 cancel_delayed_work_sync(&rport->sm_work);
 501
 502         return 0;
 503 }
 504
 505 static const struct phy_ops rockchip_usb2phy_ops = {
 506         .init           = rockchip_usb2phy_init,
 507         .exit           = rockchip_usb2phy_exit,
 508         .power_on       = rockchip_usb2phy_power_on,
 509         .power_off      = rockchip_usb2phy_power_off,
 510         .owner          = THIS_MODULE,
 511 };
 512
 513 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
 514 {
 515         struct rockchip_usb2phy_port *rport =
 516                 container_of(work, struct rockchip_usb2phy_port,
 517                              otg_sm_work.work);
 518         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 519         static unsigned int cable;
 520         unsigned long delay;
 521         bool vbus_attach, sch_work, notify_charger;
 522
 523         if (rport->utmi_avalid)
 524                 vbus_attach =
 525                         property_enabled(rphy, &rport->port_cfg->utmi_avalid);
 526         else
 527                 vbus_attach =
 528                         property_enabled(rphy, &rport->port_cfg->utmi_bvalid);
 529
 530         sch_work = false;
 531         notify_charger = false;
 532         delay = OTG_SCHEDULE_DELAY;
 533         dev_dbg(&rport->phy->dev, "%s otg sm work\n",
 534                 usb_otg_state_string(rport->state));
 535
 536         switch (rport->state) {
 537         case OTG_STATE_UNDEFINED:
 538                 rport->state = OTG_STATE_B_IDLE;
 539                 if (!vbus_attach)
 540                         rockchip_usb2phy_power_off(rport->phy);
 541                 /* fall through */
 542         case OTG_STATE_B_IDLE:
 543                 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) > 0) {
 544                         dev_dbg(&rport->phy->dev, "usb otg host connect\n");
 545                         rport->state = OTG_STATE_A_HOST;
 546                         rockchip_usb2phy_power_on(rport->phy);
 547                         return;
 548                 } else if (vbus_attach) {
 549                         dev_dbg(&rport->phy->dev, "vbus_attach\n");
 550                         switch (rphy->chg_state) {
 551                         case USB_CHG_STATE_UNDEFINED:
 552                                 schedule_delayed_work(&rport->chg_work, 0);
 553                                 return;
 554                         case USB_CHG_STATE_DETECTED:
 555                                 switch (rphy->chg_type) {
 556                                 case POWER_SUPPLY_TYPE_USB:
 557                                         dev_dbg(&rport->phy->dev, "sdp cable is connected\n");
 558                                         rockchip_usb2phy_power_on(rport->phy);
 559                                         rport->state = OTG_STATE_B_PERIPHERAL;
 560                                         notify_charger = true;
 561                                         sch_work = true;
 562                                         cable = EXTCON_CHG_USB_SDP;
 563                                         break;
 564                                 case POWER_SUPPLY_TYPE_USB_DCP:
 565                                         dev_dbg(&rport->phy->dev, "dcp cable is connected\n");
 566                                         rockchip_usb2phy_power_off(rport->phy);
 567                                         notify_charger = true;
 568                                         sch_work = true;
 569                                         cable = EXTCON_CHG_USB_DCP;
 570                                         break;
 571                                 case POWER_SUPPLY_TYPE_USB_CDP:
 572                                         dev_dbg(&rport->phy->dev, "cdp cable is connected\n");
 573                                         rockchip_usb2phy_power_on(rport->phy);
 574                                         rport->state = OTG_STATE_B_PERIPHERAL;
 575                                         notify_charger = true;
 576                                         sch_work = true;
 577                                         cable = EXTCON_CHG_USB_CDP;
 578                                         break;
 579                                 default:
 580                                         break;
 581                                 }
 582                                 break;
 583                         default:
 584                                 break;
 585                         }
 586                 } else {
 587                         notify_charger = true;
 588                         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
 589                         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
 590                 }
 591
 592                 if (rport->vbus_attached != vbus_attach) {
 593                         rport->vbus_attached = vbus_attach;
 594
 595                         if (notify_charger && rphy->edev) {
 596                                 extcon_set_cable_state_(rphy->edev,
 597                                                         cable, vbus_attach);
 598                                 if (cable == EXTCON_CHG_USB_SDP)
 599                                         extcon_set_state_sync(rphy->edev,
 600                                                               EXTCON_USB,
 601                                                               vbus_attach);
 602                         }
 603                 }
 604                 break;
 605         case OTG_STATE_B_PERIPHERAL:
 606                 if (!vbus_attach) {
 607                         dev_dbg(&rport->phy->dev, "usb disconnect\n");
 608                         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
 609                         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
 610                         rport->state = OTG_STATE_B_IDLE;
 611                         delay = 0;
 612                         rockchip_usb2phy_power_off(rport->phy);
 613                 }
 614                 sch_work = true;
 615                 break;
 616         case OTG_STATE_A_HOST:
 617                 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) == 0) {
 618                         dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
 619                         rport->state = OTG_STATE_B_IDLE;
 620                         rockchip_usb2phy_power_off(rport->phy);
 621                 }
 622                 break;
 623         default:
 624                 break;
 625         }
 626
 627         if (sch_work)
 628                 schedule_delayed_work(&rport->otg_sm_work, delay);
 629 }
 630
 631 static const char *chg_to_string(enum power_supply_type chg_type)
 632 {
 633         switch (chg_type) {
 634         case POWER_SUPPLY_TYPE_USB:
 635                 return "USB_SDP_CHARGER";
 636         case POWER_SUPPLY_TYPE_USB_DCP:
 637                 return "USB_DCP_CHARGER";
 638         case POWER_SUPPLY_TYPE_USB_CDP:
 639                 return "USB_CDP_CHARGER";
 640         default:
 641                 return "INVALID_CHARGER";
 642         }
 643 }
 644
 645 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
 646                                     bool en)
 647 {
 648         property_enable(rphy, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
 649         property_enable(rphy, &rphy->phy_cfg->chg_det.idp_src_en, en);
 650 }
 651
 652 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
 653                                             bool en)
 654 {
 655         property_enable(rphy, &rphy->phy_cfg->chg_det.vdp_src_en, en);
 656         property_enable(rphy, &rphy->phy_cfg->chg_det.idm_sink_en, en);
 657 }
 658
 659 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
 660                                               bool en)
 661 {
 662         property_enable(rphy, &rphy->phy_cfg->chg_det.vdm_src_en, en);
 663         property_enable(rphy, &rphy->phy_cfg->chg_det.idp_sink_en, en);
 664 }
 665
 666 #define CHG_DCD_POLL_TIME       (100 * HZ / 1000)
 667 #define CHG_DCD_MAX_RETRIES     6
 668 #define CHG_PRIMARY_DET_TIME    (40 * HZ / 1000)
 669 #define CHG_SECONDARY_DET_TIME  (40 * HZ / 1000)
 670 static void rockchip_chg_detect_work(struct work_struct *work)
 671 {
 672         struct rockchip_usb2phy_port *rport =
 673                 container_of(work, struct rockchip_usb2phy_port, chg_work.work);
 674         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 675         bool is_dcd, tmout, vout;
 676         unsigned long delay;
 677
 678         dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
 679                 rphy->chg_state);
 680         switch (rphy->chg_state) {
 681         case USB_CHG_STATE_UNDEFINED:
 682                 if (!rport->suspended)
 683                         rockchip_usb2phy_power_off(rport->phy);
 684                 /* put the controller in non-driving mode */
 685                 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, false);
 686                 /* Start DCD processing stage 1 */
 687                 rockchip_chg_enable_dcd(rphy, true);
 688                 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
 689                 rphy->dcd_retries = 0;
 690                 delay = CHG_DCD_POLL_TIME;
 691                 break;
 692         case USB_CHG_STATE_WAIT_FOR_DCD:
 693                 /* get data contact detection status */
 694                 is_dcd = property_enabled(rphy, &rphy->phy_cfg->chg_det.dp_det);
 695                 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
 696                 /* stage 2 */
 697                 if (is_dcd || tmout) {
 698                         /* stage 4 */
 699                         /* Turn off DCD circuitry */
 700                         rockchip_chg_enable_dcd(rphy, false);
 701                         /* Voltage Source on DP, Probe on DM */
 702                         rockchip_chg_enable_primary_det(rphy, true);
 703                         delay = CHG_PRIMARY_DET_TIME;
 704                         rphy->chg_state = USB_CHG_STATE_DCD_DONE;
 705                 } else {
 706                         /* stage 3 */
 707                         delay = CHG_DCD_POLL_TIME;
 708                 }
 709                 break;
 710         case USB_CHG_STATE_DCD_DONE:
 711                 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.cp_det);
 712                 rockchip_chg_enable_primary_det(rphy, false);
 713                 if (vout) {
 714                         /* Voltage Source on DM, Probe on DP  */
 715                         rockchip_chg_enable_secondary_det(rphy, true);
 716                         delay = CHG_SECONDARY_DET_TIME;
 717                         rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
 718                 } else {
 719                         if (rphy->dcd_retries == CHG_DCD_MAX_RETRIES) {
 720                                 /* floating charger found */
 721                                 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
 722                                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 723                                 delay = 0;
 724                         } else {
 725                                 rphy->chg_type = POWER_SUPPLY_TYPE_USB;
 726                                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 727                                 delay = 0;
 728                         }
 729                 }
 730                 break;
 731         case USB_CHG_STATE_PRIMARY_DONE:
 732                 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.dcp_det);
 733                 /* Turn off voltage source */
 734                 rockchip_chg_enable_secondary_det(rphy, false);
 735                 if (vout)
 736                         rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
 737                 else
 738                         rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
 739                 /* fall through */
 740         case USB_CHG_STATE_SECONDARY_DONE:
 741                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 742                 delay = 0;
 743                 /* fall through */
 744         case USB_CHG_STATE_DETECTED:
 745                 /* put the controller in normal mode */
 746                 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, true);
 747                 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
 748                 dev_info(&rport->phy->dev, "charger = %s\n",
 749                          chg_to_string(rphy->chg_type));
 750                 return;
 751         default:
 752                 return;
 753         }
 754
 755         schedule_delayed_work(&rport->chg_work, delay);
 756 }
 757
 758 /*
 759  * The function manage host-phy port state and suspend/resume phy port
 760  * to save power.
 761  *
 762  * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
 763  * devices is disconnect or not. Besides, we do not need care it is FS/LS
 764  * disconnected or HS disconnected, actually, we just only need get the
 765  * device is disconnected at last through rearm the delayed work,
 766  * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
 767  *
 768  * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
 769  * some clk related APIs, so do not invoke it from interrupt context directly.
 770  */
 771 static void rockchip_usb2phy_sm_work(struct work_struct *work)
 772 {
 773         struct rockchip_usb2phy_port *rport =
 774                 container_of(work, struct rockchip_usb2phy_port, sm_work.work);
 775         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 776         unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
 777                           rport->port_cfg->utmi_hstdet.bitstart + 1;
 778         unsigned int ul, uhd, state;
 779         unsigned int ul_mask, uhd_mask;
 780         int ret;
 781
 782         mutex_lock(&rport->mutex);
 783
 784         ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
 785         if (ret < 0)
 786                 goto next_schedule;
 787
 788         ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset,
 789                           &uhd);
 790         if (ret < 0)
 791                 goto next_schedule;
 792
 793         uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
 794                            rport->port_cfg->utmi_hstdet.bitstart);
 795         ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
 796                           rport->port_cfg->utmi_ls.bitstart);
 797
 798         /* stitch on utmi_ls and utmi_hstdet as phy state */
 799         state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
 800                 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
 801
 802         switch (state) {
 803         case PHY_STATE_HS_ONLINE:
 804                 dev_dbg(&rport->phy->dev, "HS online\n");
 805                 break;
 806         case PHY_STATE_FS_LS_ONLINE:
 807                 /*
 808                  * For FS/LS device, the online state share with connect state
 809                  * from utmi_ls and utmi_hstdet register, so we distinguish
 810                  * them via suspended flag.
 811                  *
 812                  * Plus, there are two cases, one is D- Line pull-up, and D+
 813                  * line pull-down, the state is 4; another is D+ line pull-up,
 814                  * and D- line pull-down, the state is 2.
 815                  */
 816                 if (!rport->suspended) {
 817                         /* D- line pull-up, D+ line pull-down */
 818                         dev_dbg(&rport->phy->dev, "FS/LS online\n");
 819                         break;
 820                 }
 821                 /* fall through */
 822         case PHY_STATE_CONNECT:
 823                 if (rport->suspended) {
 824                         dev_dbg(&rport->phy->dev, "Connected\n");
 825                         rockchip_usb2phy_power_on(rport->phy);
 826                         rport->suspended = false;
 827                 } else {
 828                         /* D+ line pull-up, D- line pull-down */
 829                         dev_dbg(&rport->phy->dev, "FS/LS online\n");
 830                 }
 831                 break;
 832         case PHY_STATE_DISCONNECT:
 833                 if (!rport->suspended) {
 834                         dev_dbg(&rport->phy->dev, "Disconnected\n");
 835                         rockchip_usb2phy_power_off(rport->phy);
 836                         rport->suspended = true;
 837                 }
 838
 839                 /*
 840                  * activate the linestate detection to get the next device
 841                  * plug-in irq.
 842                  */
 843                 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 844                 property_enable(rphy, &rport->port_cfg->ls_det_en, true);
 845
 846                 /*
 847                  * we don't need to rearm the delayed work when the phy port
 848                  * is suspended.
 849                  */
 850                 mutex_unlock(&rport->mutex);
 851                 return;
 852         default:
 853                 dev_dbg(&rport->phy->dev, "unknown phy state\n");
 854                 break;
 855         }
 856
 857 next_schedule:
 858         mutex_unlock(&rport->mutex);
 859         schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
 860 }
 861
 862 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
 863 {
 864         struct rockchip_usb2phy_port *rport = data;
 865         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 866
 867         if (!property_enabled(rphy, &rport->port_cfg->ls_det_st))
 868                 return IRQ_NONE;
 869
 870         mutex_lock(&rport->mutex);
 871
 872         /* disable linestate detect irq and clear its status */
 873         property_enable(rphy, &rport->port_cfg->ls_det_en, false);
 874         property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 875
 876         mutex_unlock(&rport->mutex);
 877
 878         /*
 879          * In this case for host phy port, a new device is plugged in,
 880          * meanwhile, if the phy port is suspended, we need rearm the work to
 881          * resume it and mange its states; otherwise, we do nothing about that.
 882          */
 883         if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST)
 884                 rockchip_usb2phy_sm_work(&rport->sm_work.work);
 885
 886         return IRQ_HANDLED;
 887 }
 888
 889 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
 890 {
 891         struct rockchip_usb2phy_port *rport = data;
 892         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 893
 894         if (!property_enabled(rphy, &rport->port_cfg->bvalid_det_st))
 895                 return IRQ_NONE;
 896
 897         mutex_lock(&rport->mutex);
 898
 899         /* clear bvalid detect irq pending status */
 900         property_enable(rphy, &rport->port_cfg->bvalid_det_clr, true);
 901
 902         mutex_unlock(&rport->mutex);
 903
 904         rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
 905
 906         return IRQ_HANDLED;
 907 }
 908
 909 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
 910                                            struct rockchip_usb2phy_port *rport,
 911                                            struct device_node *child_np)
 912 {
 913         int ret;
 914
 915         rport->port_id = USB2PHY_PORT_HOST;
 916         rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
 917         rport->suspended = true;
 918
 919         mutex_init(&rport->mutex);
 920         INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
 921
 922         rport->ls_irq = of_irq_get_byname(child_np, "linestate");
 923         if (rport->ls_irq < 0) {
 924                 dev_err(rphy->dev, "no linestate irq provided\n");
 925                 return rport->ls_irq;
 926         }
 927
 928         ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
 929                                         rockchip_usb2phy_linestate_irq,
 930                                         IRQF_ONESHOT,
 931                                         "rockchip_usb2phy", rport);
 932         if (ret) {
 933                 dev_err(rphy->dev, "failed to request linestate irq handle\n");
 934                 return ret;
 935         }
 936
 937         return 0;
 938 }
 939
 940 static int rockchip_otg_event(struct notifier_block *nb,
 941                               unsigned long event, void *ptr)
 942 {
 943         struct rockchip_usb2phy_port *rport =
 944                 container_of(nb, struct rockchip_usb2phy_port, event_nb);
 945
 946         schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
 947
 948         return NOTIFY_DONE;
 949 }
 950
 951 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
 952                                           struct rockchip_usb2phy_port *rport,
 953                                           struct device_node *child_np)
 954 {
 955         int ret;
 956
 957         rport->port_id = USB2PHY_PORT_OTG;
 958         rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
 959         rport->state = OTG_STATE_UNDEFINED;
 960
 961         /*
 962          * set suspended flag to true, but actually don't
 963          * put phy in suspend mode, it aims to enable usb
 964          * phy and clock in power_on() called by usb controller
 965          * driver during probe.
 966          */
 967         rport->suspended = true;
 968         rport->vbus_attached = false;
 969
 970         mutex_init(&rport->mutex);
 971
 972         rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
 973         if (rport->mode == USB_DR_MODE_HOST) {
 974                 ret = 0;
 975                 goto out;
 976         }
 977
 978         INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
 979         INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
 980
 981         rport->utmi_avalid =
 982                 of_property_read_bool(child_np, "rockchip,utmi-avalid");
 983
 984         rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
 985         if (rport->bvalid_irq < 0) {
 986                 dev_err(rphy->dev, "no vbus valid irq provided\n");
 987                 ret = rport->bvalid_irq;
 988                 goto out;
 989         }
 990
 991         ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, NULL,
 992                                         rockchip_usb2phy_bvalid_irq,
 993                                         IRQF_ONESHOT,
 994                                         "rockchip_usb2phy_bvalid", rport);
 995         if (ret) {
 996                 dev_err(rphy->dev, "failed to request otg-bvalid irq handle\n");
 997                 goto out;
 998         }
 999
1000         if (!IS_ERR(rphy->edev)) {
1001                 rport->event_nb.notifier_call = rockchip_otg_event;
1002
1003                 ret = extcon_register_notifier(rphy->edev, EXTCON_USB_HOST,
1004                                                &rport->event_nb);
1005                 if (ret)
1006                         dev_err(rphy->dev, "register USB HOST notifier failed\n");
1007         }
1008
1009 out:
1010         return ret;
1011 }
1012
1013 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1014 {
1015         struct device *dev = &pdev->dev;
1016         struct device_node *np = dev->of_node;
1017         struct device_node *child_np;
1018         struct phy_provider *provider;
1019         struct rockchip_usb2phy *rphy;
1020         const struct rockchip_usb2phy_cfg *phy_cfgs;
1021         const struct of_device_id *match;
1022         unsigned int reg;
1023         int index, ret;
1024
1025         rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1026         if (!rphy)
1027                 return -ENOMEM;
1028
1029         match = of_match_device(dev->driver->of_match_table, dev);
1030         if (!match || !match->data) {
1031                 dev_err(dev, "phy configs are not assigned!\n");
1032                 return -EINVAL;
1033         }
1034
1035         if (!dev->parent || !dev->parent->of_node)
1036                 return -EINVAL;
1037
1038         rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1039         if (IS_ERR(rphy->grf))
1040                 return PTR_ERR(rphy->grf);
1041
1042         if (of_property_read_u32(np, "reg", &reg)) {
1043                 dev_err(dev, "the reg property is not assigned in %s node\n",
1044                         np->name);
1045                 return -EINVAL;
1046         }
1047
1048         rphy->dev = dev;
1049         phy_cfgs = match->data;
1050         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1051         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1052         platform_set_drvdata(pdev, rphy);
1053
1054         ret = rockchip_usb2phy_extcon_register(rphy);
1055         if (ret)
1056                 return ret;
1057
1058         /* find out a proper config which can be matched with dt. */
1059         index = 0;
1060         while (phy_cfgs[index].reg) {
1061                 if (phy_cfgs[index].reg == reg) {
1062                         rphy->phy_cfg = &phy_cfgs[index];
1063                         break;
1064                 }
1065
1066                 ++index;
1067         }
1068
1069         if (!rphy->phy_cfg) {
1070                 dev_err(dev, "no phy-config can be matched with %s node\n",
1071                         np->name);
1072                 return -EINVAL;
1073         }
1074
1075         rphy->clk = of_clk_get_by_name(np, "phyclk");
1076         if (!IS_ERR(rphy->clk)) {
1077                 clk_prepare_enable(rphy->clk);
1078         } else {
1079                 dev_info(&pdev->dev, "no phyclk specified\n");
1080                 rphy->clk = NULL;
1081         }
1082
1083         ret = rockchip_usb2phy_clk480m_register(rphy);
1084         if (ret) {
1085                 dev_err(dev, "failed to register 480m output clock\n");
1086                 goto disable_clks;
1087         }
1088
1089         index = 0;
1090         for_each_available_child_of_node(np, child_np) {
1091                 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1092                 struct phy *phy;
1093
1094                 /* This driver aims to support both otg-port and host-port */
1095                 if (of_node_cmp(child_np->name, "host-port") &&
1096                     of_node_cmp(child_np->name, "otg-port"))
1097                         goto next_child;
1098
1099                 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1100                 if (IS_ERR(phy)) {
1101                         dev_err(dev, "failed to create phy\n");
1102                         ret = PTR_ERR(phy);
1103                         goto put_child;
1104                 }
1105
1106                 rport->phy = phy;
1107                 phy_set_drvdata(rport->phy, rport);
1108
1109                 /* initialize otg/host port separately */
1110                 if (!of_node_cmp(child_np->name, "host-port")) {
1111                         ret = rockchip_usb2phy_host_port_init(rphy, rport,
1112                                                               child_np);
1113                         if (ret)
1114                                 goto put_child;
1115                 } else {
1116                         ret = rockchip_usb2phy_otg_port_init(rphy, rport,
1117                                                              child_np);
1118                         if (ret)
1119                                 goto put_child;
1120                 }
1121
1122 next_child:
1123                 /* to prevent out of boundary */
1124                 if (++index >= rphy->phy_cfg->num_ports)
1125                         break;
1126         }
1127
1128         provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1129         return PTR_ERR_OR_ZERO(provider);
1130
1131 put_child:
1132         of_node_put(child_np);
1133 disable_clks:
1134         if (rphy->clk) {
1135                 clk_disable_unprepare(rphy->clk);
1136                 clk_put(rphy->clk);
1137         }
1138         return ret;
1139 }
1140
1141 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
1142         {
1143                 .reg = 0x100,
1144                 .num_ports      = 2,
1145                 .clkout_ctl     = { 0x108, 4, 4, 1, 0 },
1146                 .port_cfgs      = {
1147                         [USB2PHY_PORT_OTG] = {
1148                                 .phy_sus        = { 0x0100, 15, 0, 0, 0x1d1 },
1149                                 .bvalid_det_en  = { 0x0110, 2, 2, 0, 1 },
1150                                 .bvalid_det_st  = { 0x0114, 2, 2, 0, 1 },
1151                                 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
1152                                 .ls_det_en      = { 0x0110, 0, 0, 0, 1 },
1153                                 .ls_det_st      = { 0x0114, 0, 0, 0, 1 },
1154                                 .ls_det_clr     = { 0x0118, 0, 0, 0, 1 },
1155                                 .utmi_avalid    = { 0x0120, 10, 10, 0, 1 },
1156                                 .utmi_bvalid    = { 0x0120, 9, 9, 0, 1 },
1157                                 .utmi_ls        = { 0x0120, 5, 4, 0, 1 },
1158                         },
1159                         [USB2PHY_PORT_HOST] = {
1160                                 .phy_sus        = { 0x104, 15, 0, 0, 0x1d1 },
1161                                 .ls_det_en      = { 0x110, 1, 1, 0, 1 },
1162                                 .ls_det_st      = { 0x114, 1, 1, 0, 1 },
1163                                 .ls_det_clr     = { 0x118, 1, 1, 0, 1 },
1164                                 .utmi_ls        = { 0x120, 17, 16, 0, 1 },
1165                                 .utmi_hstdet    = { 0x120, 19, 19, 0, 1 }
1166                         }
1167                 },
1168                 .chg_det = {
1169                         .opmode         = { 0x0100, 3, 0, 5, 1 },
1170                         .cp_det         = { 0x0120, 24, 24, 0, 1 },
1171                         .dcp_det        = { 0x0120, 23, 23, 0, 1 },
1172                         .dp_det         = { 0x0120, 25, 25, 0, 1 },
1173                         .idm_sink_en    = { 0x0108, 8, 8, 0, 1 },
1174                         .idp_sink_en    = { 0x0108, 7, 7, 0, 1 },
1175                         .idp_src_en     = { 0x0108, 9, 9, 0, 1 },
1176                         .rdm_pdwn_en    = { 0x0108, 10, 10, 0, 1 },
1177                         .vdm_src_en     = { 0x0108, 12, 12, 0, 1 },
1178                         .vdp_src_en     = { 0x0108, 11, 11, 0, 1 },
1179                 },
1180         },
1181         { /* sentinel */ }
1182 };
1183
1184 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
1185         {
1186                 .reg = 0x700,
1187                 .num_ports      = 2,
1188                 .clkout_ctl     = { 0x0724, 15, 15, 1, 0 },
1189                 .port_cfgs      = {
1190                         [USB2PHY_PORT_HOST] = {
1191                                 .phy_sus        = { 0x0728, 15, 0, 0, 0x1d1 },
1192                                 .ls_det_en      = { 0x0680, 4, 4, 0, 1 },
1193                                 .ls_det_st      = { 0x0690, 4, 4, 0, 1 },
1194                                 .ls_det_clr     = { 0x06a0, 4, 4, 0, 1 },
1195                                 .utmi_ls        = { 0x049c, 14, 13, 0, 1 },
1196                                 .utmi_hstdet    = { 0x049c, 12, 12, 0, 1 }
1197                         }
1198                 },
1199         },
1200         { /* sentinel */ }
1201 };
1202
1203 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1204         {
1205                 .reg            = 0xe450,
1206                 .num_ports      = 2,
1207                 .clkout_ctl     = { 0xe450, 4, 4, 1, 0 },
1208                 .port_cfgs      = {
1209                         [USB2PHY_PORT_OTG] = {
1210                                 .phy_sus        = { 0xe454, 1, 0, 2, 1 },
1211                                 .bvalid_det_en  = { 0xe3c0, 3, 3, 0, 1 },
1212                                 .bvalid_det_st  = { 0xe3e0, 3, 3, 0, 1 },
1213                                 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1214                                 .utmi_avalid    = { 0xe2ac, 7, 7, 0, 1 },
1215                                 .utmi_bvalid    = { 0xe2ac, 12, 12, 0, 1 },
1216                         },
1217                         [USB2PHY_PORT_HOST] = {
1218                                 .phy_sus        = { 0xe458, 1, 0, 0x2, 0x1 },
1219                                 .ls_det_en      = { 0xe3c0, 6, 6, 0, 1 },
1220                                 .ls_det_st      = { 0xe3e0, 6, 6, 0, 1 },
1221                                 .ls_det_clr     = { 0xe3d0, 6, 6, 0, 1 },
1222                                 .utmi_ls        = { 0xe2ac, 22, 21, 0, 1 },
1223                                 .utmi_hstdet    = { 0xe2ac, 23, 23, 0, 1 }
1224                         }
1225                 },
1226                 .chg_det = {
1227                         .opmode         = { 0xe454, 3, 0, 5, 1 },
1228                         .cp_det         = { 0xe2ac, 2, 2, 0, 1 },
1229                         .dcp_det        = { 0xe2ac, 1, 1, 0, 1 },
1230                         .dp_det         = { 0xe2ac, 0, 0, 0, 1 },
1231                         .idm_sink_en    = { 0xe450, 8, 8, 0, 1 },
1232                         .idp_sink_en    = { 0xe450, 7, 7, 0, 1 },
1233                         .idp_src_en     = { 0xe450, 9, 9, 0, 1 },
1234                         .rdm_pdwn_en    = { 0xe450, 10, 10, 0, 1 },
1235                         .vdm_src_en     = { 0xe450, 12, 12, 0, 1 },
1236                         .vdp_src_en     = { 0xe450, 11, 11, 0, 1 },
1237                 },
1238         },
1239         {
1240                 .reg            = 0xe460,
1241                 .num_ports      = 2,
1242                 .clkout_ctl     = { 0xe460, 4, 4, 1, 0 },
1243                 .port_cfgs      = {
1244                         [USB2PHY_PORT_OTG] = {
1245                                 .phy_sus        = { 0xe464, 1, 0, 2, 1 },
1246                                 .bvalid_det_en  = { 0xe3c0, 8, 8, 0, 1 },
1247                                 .bvalid_det_st  = { 0xe3e0, 8, 8, 0, 1 },
1248                                 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1249                                 .utmi_avalid    = { 0xe2ac, 10, 10, 0, 1 },
1250                                 .utmi_bvalid    = { 0xe2ac, 16, 16, 0, 1 },
1251                         },
1252                         [USB2PHY_PORT_HOST] = {
1253                                 .phy_sus        = { 0xe468, 1, 0, 0x2, 0x1 },
1254                                 .ls_det_en      = { 0xe3c0, 11, 11, 0, 1 },
1255                                 .ls_det_st      = { 0xe3e0, 11, 11, 0, 1 },
1256                                 .ls_det_clr     = { 0xe3d0, 11, 11, 0, 1 },
1257                                 .utmi_ls        = { 0xe2ac, 26, 25, 0, 1 },
1258                                 .utmi_hstdet    = { 0xe2ac, 27, 27, 0, 1 }
1259                         }
1260                 },
1261         },
1262         { /* sentinel */ }
1263 };
1264
1265 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1266         { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
1267         { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
1268         { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
1269         {}
1270 };
1271 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
1272
1273 static struct platform_driver rockchip_usb2phy_driver = {
1274         .probe          = rockchip_usb2phy_probe,
1275         .driver         = {
1276                 .name   = "rockchip-usb2phy",
1277                 .of_match_table = rockchip_usb2phy_dt_match,
1278         },
1279 };
1280 module_platform_driver(rockchip_usb2phy_driver);
1281
1282 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1283 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
1284 MODULE_LICENSE("GPL v2");