drivers/pinctrl/sunxi/pinctrl-sunxi.c

   1 /*
   2  * Allwinner A1X SoCs pinctrl driver.
   3  *
   4  * Copyright (C) 2012 Maxime Ripard
   5  *
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/io.h>
  14 #include <linux/clk.h>
  15 #include <linux/gpio/driver.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/irqchip/chained_irq.h>
  18 #include <linux/export.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/pinctrl/consumer.h>
  24 #include <linux/pinctrl/machine.h>
  25 #include <linux/pinctrl/pinctrl.h>
  26 #include <linux/pinctrl/pinconf-generic.h>
  27 #include <linux/pinctrl/pinmux.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/slab.h>
  30
  31 #include <dt-bindings/pinctrl/sun4i-a10.h>
  32
  33 #include "../core.h"
  34 #include "pinctrl-sunxi.h"
  35
  36 static struct irq_chip sunxi_pinctrl_edge_irq_chip;
  37 static struct irq_chip sunxi_pinctrl_level_irq_chip;
  38
  39 static struct sunxi_pinctrl_group *
  40 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
  41 {
  42         int i;
  43
  44         for (i = 0; i < pctl->ngroups; i++) {
  45                 struct sunxi_pinctrl_group *grp = pctl->groups + i;
  46
  47                 if (!strcmp(grp->name, group))
  48                         return grp;
  49         }
  50
  51         return NULL;
  52 }
  53
  54 static struct sunxi_pinctrl_function *
  55 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
  56                                     const char *name)
  57 {
  58         struct sunxi_pinctrl_function *func = pctl->functions;
  59         int i;
  60
  61         for (i = 0; i < pctl->nfunctions; i++) {
  62                 if (!func[i].name)
  63                         break;
  64
  65                 if (!strcmp(func[i].name, name))
  66                         return func + i;
  67         }
  68
  69         return NULL;
  70 }
  71
  72 static struct sunxi_desc_function *
  73 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
  74                                          const char *pin_name,
  75                                          const char *func_name)
  76 {
  77         int i;
  78
  79         for (i = 0; i < pctl->desc->npins; i++) {
  80                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
  81
  82                 if (!strcmp(pin->pin.name, pin_name)) {
  83                         struct sunxi_desc_function *func = pin->functions;
  84
  85                         while (func->name) {
  86                                 if (!strcmp(func->name, func_name))
  87                                         return func;
  88
  89                                 func++;
  90                         }
  91                 }
  92         }
  93
  94         return NULL;
  95 }
  96
  97 static struct sunxi_desc_function *
  98 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
  99                                         const u16 pin_num,
 100                                         const char *func_name)
 101 {
 102         int i;
 103
 104         for (i = 0; i < pctl->desc->npins; i++) {
 105                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 106
 107                 if (pin->pin.number == pin_num) {
 108                         struct sunxi_desc_function *func = pin->functions;
 109
 110                         while (func->name) {
 111                                 if (!strcmp(func->name, func_name))
 112                                         return func;
 113
 114                                 func++;
 115                         }
 116                 }
 117         }
 118
 119         return NULL;
 120 }
 121
 122 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
 123 {
 124         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 125
 126         return pctl->ngroups;
 127 }
 128
 129 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
 130                                               unsigned group)
 131 {
 132         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 133
 134         return pctl->groups[group].name;
 135 }
 136
 137 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
 138                                       unsigned group,
 139                                       const unsigned **pins,
 140                                       unsigned *num_pins)
 141 {
 142         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 143
 144         *pins = (unsigned *)&pctl->groups[group].pin;
 145         *num_pins = 1;
 146
 147         return 0;
 148 }
 149
 150 static bool sunxi_pctrl_has_bias_prop(struct device_node *node)
 151 {
 152         return of_find_property(node, "bias-pull-up", NULL) ||
 153                 of_find_property(node, "bias-pull-down", NULL) ||
 154                 of_find_property(node, "bias-disable", NULL) ||
 155                 of_find_property(node, "allwinner,pull", NULL);
 156 }
 157
 158 static bool sunxi_pctrl_has_drive_prop(struct device_node *node)
 159 {
 160         return of_find_property(node, "drive-strength", NULL) ||
 161                 of_find_property(node, "allwinner,drive", NULL);
 162 }
 163
 164 static int sunxi_pctrl_parse_bias_prop(struct device_node *node)
 165 {
 166         u32 val;
 167
 168         /* Try the new style binding */
 169         if (of_find_property(node, "bias-pull-up", NULL))
 170                 return PIN_CONFIG_BIAS_PULL_UP;
 171
 172         if (of_find_property(node, "bias-pull-down", NULL))
 173                 return PIN_CONFIG_BIAS_PULL_DOWN;
 174
 175         if (of_find_property(node, "bias-disable", NULL))
 176                 return PIN_CONFIG_BIAS_DISABLE;
 177
 178         /* And fall back to the old binding */
 179         if (of_property_read_u32(node, "allwinner,pull", &val))
 180                 return -EINVAL;
 181
 182         switch (val) {
 183         case SUN4I_PINCTRL_NO_PULL:
 184                 return PIN_CONFIG_BIAS_DISABLE;
 185         case SUN4I_PINCTRL_PULL_UP:
 186                 return PIN_CONFIG_BIAS_PULL_UP;
 187         case SUN4I_PINCTRL_PULL_DOWN:
 188                 return PIN_CONFIG_BIAS_PULL_DOWN;
 189         }
 190
 191         return -EINVAL;
 192 }
 193
 194 static int sunxi_pctrl_parse_drive_prop(struct device_node *node)
 195 {
 196         u32 val;
 197
 198         /* Try the new style binding */
 199         if (!of_property_read_u32(node, "drive-strength", &val)) {
 200                 /* We can't go below 10mA ... */
 201                 if (val < 10)
 202                         return -EINVAL;
 203
 204                 /* ... and only up to 40 mA ... */
 205                 if (val > 40)
 206                         val = 40;
 207
 208                 /* by steps of 10 mA */
 209                 return rounddown(val, 10);
 210         }
 211
 212         /* And then fall back to the old binding */
 213         if (of_property_read_u32(node, "allwinner,drive", &val))
 214                 return -EINVAL;
 215
 216         return (val + 1) * 10;
 217 }
 218
 219 static const char *sunxi_pctrl_parse_function_prop(struct device_node *node)
 220 {
 221         const char *function;
 222         int ret;
 223
 224         /* Try the generic binding */
 225         ret = of_property_read_string(node, "function", &function);
 226         if (!ret)
 227                 return function;
 228
 229         /* And fall back to our legacy one */
 230         ret = of_property_read_string(node, "allwinner,function", &function);
 231         if (!ret)
 232                 return function;
 233
 234         return NULL;
 235 }
 236
 237 static const char *sunxi_pctrl_find_pins_prop(struct device_node *node,
 238                                               int *npins)
 239 {
 240         int count;
 241
 242         /* Try the generic binding */
 243         count = of_property_count_strings(node, "pins");
 244         if (count > 0) {
 245                 *npins = count;
 246                 return "pins";
 247         }
 248
 249         /* And fall back to our legacy one */
 250         count = of_property_count_strings(node, "allwinner,pins");
 251         if (count > 0) {
 252                 *npins = count;
 253                 return "allwinner,pins";
 254         }
 255
 256         return NULL;
 257 }
 258
 259 static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node,
 260                                                    unsigned int *len)
 261 {
 262         unsigned long *pinconfig;
 263         unsigned int configlen = 0, idx = 0;
 264         int ret;
 265
 266         if (sunxi_pctrl_has_drive_prop(node))
 267                 configlen++;
 268         if (sunxi_pctrl_has_bias_prop(node))
 269                 configlen++;
 270
 271         /*
 272          * If we don't have any configuration, bail out
 273          */
 274         if (!configlen)
 275                 return NULL;
 276
 277         pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
 278         if (!pinconfig)
 279                 return ERR_PTR(-ENOMEM);
 280
 281         if (sunxi_pctrl_has_drive_prop(node)) {
 282                 int drive = sunxi_pctrl_parse_drive_prop(node);
 283                 if (drive < 0) {
 284                         ret = drive;
 285                         goto err_free;
 286                 }
 287
 288                 pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
 289                                                           drive);
 290         }
 291
 292         if (sunxi_pctrl_has_bias_prop(node)) {
 293                 int pull = sunxi_pctrl_parse_bias_prop(node);
 294                 int arg = 0;
 295                 if (pull < 0) {
 296                         ret = pull;
 297                         goto err_free;
 298                 }
 299
 300                 if (pull != PIN_CONFIG_BIAS_DISABLE)
 301                         arg = 1; /* hardware uses weak pull resistors */
 302
 303                 pinconfig[idx++] = pinconf_to_config_packed(pull, arg);
 304         }
 305
 306
 307         *len = configlen;
 308         return pinconfig;
 309
 310 err_free:
 311         kfree(pinconfig);
 312         return ERR_PTR(ret);
 313 }
 314
 315 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 316                                       struct device_node *node,
 317                                       struct pinctrl_map **map,
 318                                       unsigned *num_maps)
 319 {
 320         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 321         unsigned long *pinconfig;
 322         struct property *prop;
 323         const char *function, *pin_prop;
 324         const char *group;
 325         int ret, npins, nmaps, configlen = 0, i = 0;
 326
 327         *map = NULL;
 328         *num_maps = 0;
 329
 330         function = sunxi_pctrl_parse_function_prop(node);
 331         if (!function) {
 332                 dev_err(pctl->dev, "missing function property in node %s\n",
 333                         node->name);
 334                 return -EINVAL;
 335         }
 336
 337         pin_prop = sunxi_pctrl_find_pins_prop(node, &npins);
 338         if (!pin_prop) {
 339                 dev_err(pctl->dev, "missing pins property in node %s\n",
 340                         node->name);
 341                 return -EINVAL;
 342         }
 343
 344         /*
 345          * We have two maps for each pin: one for the function, one
 346          * for the configuration (bias, strength, etc).
 347          *
 348          * We might be slightly overshooting, since we might not have
 349          * any configuration.
 350          */
 351         nmaps = npins * 2;
 352         *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
 353         if (!*map)
 354                 return -ENOMEM;
 355
 356         pinconfig = sunxi_pctrl_build_pin_config(node, &configlen);
 357         if (IS_ERR(pinconfig)) {
 358                 ret = PTR_ERR(pinconfig);
 359                 goto err_free_map;
 360         }
 361
 362         of_property_for_each_string(node, pin_prop, prop, group) {
 363                 struct sunxi_pinctrl_group *grp =
 364                         sunxi_pinctrl_find_group_by_name(pctl, group);
 365
 366                 if (!grp) {
 367                         dev_err(pctl->dev, "unknown pin %s", group);
 368                         continue;
 369                 }
 370
 371                 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
 372                                                               grp->name,
 373                                                               function)) {
 374                         dev_err(pctl->dev, "unsupported function %s on pin %s",
 375                                 function, group);
 376                         continue;
 377                 }
 378
 379                 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
 380                 (*map)[i].data.mux.group = group;
 381                 (*map)[i].data.mux.function = function;
 382
 383                 i++;
 384
 385                 if (pinconfig) {
 386                         (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
 387                         (*map)[i].data.configs.group_or_pin = group;
 388                         (*map)[i].data.configs.configs = pinconfig;
 389                         (*map)[i].data.configs.num_configs = configlen;
 390                         i++;
 391                 }
 392         }
 393
 394         *num_maps = i;
 395
 396         /*
 397          * We know have the number of maps we need, we can resize our
 398          * map array
 399          */
 400         *map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL);
 401         if (!*map)
 402                 return -ENOMEM;
 403
 404         return 0;
 405
 406 err_free_map:
 407         kfree(*map);
 408         *map = NULL;
 409         return ret;
 410 }
 411
 412 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
 413                                     struct pinctrl_map *map,
 414                                     unsigned num_maps)
 415 {
 416         int i;
 417
 418         /* pin config is never in the first map */
 419         for (i = 1; i < num_maps; i++) {
 420                 if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP)
 421                         continue;
 422
 423                 /*
 424                  * All the maps share the same pin config,
 425                  * free only the first one we find.
 426                  */
 427                 kfree(map[i].data.configs.configs);
 428                 break;
 429         }
 430
 431         kfree(map);
 432 }
 433
 434 static const struct pinctrl_ops sunxi_pctrl_ops = {
 435         .dt_node_to_map         = sunxi_pctrl_dt_node_to_map,
 436         .dt_free_map            = sunxi_pctrl_dt_free_map,
 437         .get_groups_count       = sunxi_pctrl_get_groups_count,
 438         .get_group_name         = sunxi_pctrl_get_group_name,
 439         .get_group_pins         = sunxi_pctrl_get_group_pins,
 440 };
 441
 442 static int sunxi_pconf_reg(unsigned pin, enum pin_config_param param,
 443                            u32 *offset, u32 *shift, u32 *mask)
 444 {
 445         switch (param) {
 446         case PIN_CONFIG_DRIVE_STRENGTH:
 447                 *offset = sunxi_dlevel_reg(pin);
 448                 *shift = sunxi_dlevel_offset(pin);
 449                 *mask = DLEVEL_PINS_MASK;
 450                 break;
 451
 452         case PIN_CONFIG_BIAS_PULL_UP:
 453         case PIN_CONFIG_BIAS_PULL_DOWN:
 454         case PIN_CONFIG_BIAS_DISABLE:
 455                 *offset = sunxi_pull_reg(pin);
 456                 *shift = sunxi_pull_offset(pin);
 457                 *mask = PULL_PINS_MASK;
 458                 break;
 459
 460         default:
 461                 return -ENOTSUPP;
 462         }
 463
 464         return 0;
 465 }
 466
 467 static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
 468                            unsigned long *config)
 469 {
 470         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 471         enum pin_config_param param = pinconf_to_config_param(*config);
 472         u32 offset, shift, mask, val;
 473         u16 arg;
 474         int ret;
 475
 476         pin -= pctl->desc->pin_base;
 477
 478         ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
 479         if (ret < 0)
 480                 return ret;
 481
 482         val = (readl(pctl->membase + offset) >> shift) & mask;
 483
 484         switch (pinconf_to_config_param(*config)) {
 485         case PIN_CONFIG_DRIVE_STRENGTH:
 486                 arg = (val + 1) * 10;
 487                 break;
 488
 489         case PIN_CONFIG_BIAS_PULL_UP:
 490                 if (val != SUN4I_PINCTRL_PULL_UP)
 491                         return -EINVAL;
 492                 arg = 1; /* hardware is weak pull-up */
 493                 break;
 494
 495         case PIN_CONFIG_BIAS_PULL_DOWN:
 496                 if (val != SUN4I_PINCTRL_PULL_DOWN)
 497                         return -EINVAL;
 498                 arg = 1; /* hardware is weak pull-down */
 499                 break;
 500
 501         case PIN_CONFIG_BIAS_DISABLE:
 502                 if (val != SUN4I_PINCTRL_NO_PULL)
 503                         return -EINVAL;
 504                 arg = 0;
 505                 break;
 506
 507         default:
 508                 /* sunxi_pconf_reg should catch anything unsupported */
 509                 WARN_ON(1);
 510                 return -ENOTSUPP;
 511         }
 512
 513         *config = pinconf_to_config_packed(param, arg);
 514
 515         return 0;
 516 }
 517
 518 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
 519                                  unsigned group,
 520                                  unsigned long *config)
 521 {
 522         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 523         struct sunxi_pinctrl_group *g = &pctl->groups[group];
 524
 525         /* We only support 1 pin per group. Chain it to the pin callback */
 526         return sunxi_pconf_get(pctldev, g->pin, config);
 527 }
 528
 529 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
 530                                  unsigned group,
 531                                  unsigned long *configs,
 532                                  unsigned num_configs)
 533 {
 534         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 535         struct sunxi_pinctrl_group *g = &pctl->groups[group];
 536         unsigned pin = g->pin - pctl->desc->pin_base;
 537         int i;
 538
 539         for (i = 0; i < num_configs; i++) {
 540                 enum pin_config_param param;
 541                 unsigned long flags;
 542                 u32 offset, shift, mask, reg;
 543                 u16 arg, val;
 544                 int ret;
 545
 546                 param = pinconf_to_config_param(configs[i]);
 547                 arg = pinconf_to_config_argument(configs[i]);
 548
 549                 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
 550                 if (ret < 0)
 551                         return ret;
 552
 553                 switch (param) {
 554                 case PIN_CONFIG_DRIVE_STRENGTH:
 555                         if (arg < 10 || arg > 40)
 556                                 return -EINVAL;
 557                         /*
 558                          * We convert from mA to what the register expects:
 559                          *   0: 10mA
 560                          *   1: 20mA
 561                          *   2: 30mA
 562                          *   3: 40mA
 563                          */
 564                         val = arg / 10 - 1;
 565                         break;
 566                 case PIN_CONFIG_BIAS_DISABLE:
 567                         val = 0;
 568                         break;
 569                 case PIN_CONFIG_BIAS_PULL_UP:
 570                         if (arg == 0)
 571                                 return -EINVAL;
 572                         val = 1;
 573                         break;
 574                 case PIN_CONFIG_BIAS_PULL_DOWN:
 575                         if (arg == 0)
 576                                 return -EINVAL;
 577                         val = 2;
 578                         break;
 579                 default:
 580                         /* sunxi_pconf_reg should catch anything unsupported */
 581                         WARN_ON(1);
 582                         return -ENOTSUPP;
 583                 }
 584
 585                 spin_lock_irqsave(&pctl->lock, flags);
 586                 reg = readl(pctl->membase + offset);
 587                 reg &= ~(mask << shift);
 588                 writel(reg | val << shift, pctl->membase + offset);
 589                 spin_unlock_irqrestore(&pctl->lock, flags);
 590         } /* for each config */
 591
 592         return 0;
 593 }
 594
 595 static const struct pinconf_ops sunxi_pconf_ops = {
 596         .is_generic             = true,
 597         .pin_config_get         = sunxi_pconf_get,
 598         .pin_config_group_get   = sunxi_pconf_group_get,
 599         .pin_config_group_set   = sunxi_pconf_group_set,
 600 };
 601
 602 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
 603 {
 604         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 605
 606         return pctl->nfunctions;
 607 }
 608
 609 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
 610                                            unsigned function)
 611 {
 612         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 613
 614         return pctl->functions[function].name;
 615 }
 616
 617 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
 618                                      unsigned function,
 619                                      const char * const **groups,
 620                                      unsigned * const num_groups)
 621 {
 622         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 623
 624         *groups = pctl->functions[function].groups;
 625         *num_groups = pctl->functions[function].ngroups;
 626
 627         return 0;
 628 }
 629
 630 static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
 631                                  unsigned pin,
 632                                  u8 config)
 633 {
 634         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 635         unsigned long flags;
 636         u32 val, mask;
 637
 638         spin_lock_irqsave(&pctl->lock, flags);
 639
 640         pin -= pctl->desc->pin_base;
 641         val = readl(pctl->membase + sunxi_mux_reg(pin));
 642         mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
 643         writel((val & ~mask) | config << sunxi_mux_offset(pin),
 644                 pctl->membase + sunxi_mux_reg(pin));
 645
 646         spin_unlock_irqrestore(&pctl->lock, flags);
 647 }
 648
 649 static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
 650                              unsigned function,
 651                              unsigned group)
 652 {
 653         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 654         struct sunxi_pinctrl_group *g = pctl->groups + group;
 655         struct sunxi_pinctrl_function *func = pctl->functions + function;
 656         struct sunxi_desc_function *desc =
 657                 sunxi_pinctrl_desc_find_function_by_name(pctl,
 658                                                          g->name,
 659                                                          func->name);
 660
 661         if (!desc)
 662                 return -EINVAL;
 663
 664         sunxi_pmx_set(pctldev, g->pin, desc->muxval);
 665
 666         return 0;
 667 }
 668
 669 static int
 670 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 671                         struct pinctrl_gpio_range *range,
 672                         unsigned offset,
 673                         bool input)
 674 {
 675         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 676         struct sunxi_desc_function *desc;
 677         const char *func;
 678
 679         if (input)
 680                 func = "gpio_in";
 681         else
 682                 func = "gpio_out";
 683
 684         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
 685         if (!desc)
 686                 return -EINVAL;
 687
 688         sunxi_pmx_set(pctldev, offset, desc->muxval);
 689
 690         return 0;
 691 }
 692
 693 static const struct pinmux_ops sunxi_pmx_ops = {
 694         .get_functions_count    = sunxi_pmx_get_funcs_cnt,
 695         .get_function_name      = sunxi_pmx_get_func_name,
 696         .get_function_groups    = sunxi_pmx_get_func_groups,
 697         .set_mux                = sunxi_pmx_set_mux,
 698         .gpio_set_direction     = sunxi_pmx_gpio_set_direction,
 699 };
 700
 701 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
 702                                         unsigned offset)
 703 {
 704         return pinctrl_gpio_direction_input(chip->base + offset);
 705 }
 706
 707 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
 708 {
 709         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 710         u32 reg = sunxi_data_reg(offset);
 711         u8 index = sunxi_data_offset(offset);
 712         bool set_mux = pctl->desc->irq_read_needs_mux &&
 713                 gpiochip_line_is_irq(chip, offset);
 714         u32 pin = offset + chip->base;
 715         u32 val;
 716
 717         if (set_mux)
 718                 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
 719
 720         val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
 721
 722         if (set_mux)
 723                 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
 724
 725         return !!val;
 726 }
 727
 728 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
 729                                 unsigned offset, int value)
 730 {
 731         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 732         u32 reg = sunxi_data_reg(offset);
 733         u8 index = sunxi_data_offset(offset);
 734         unsigned long flags;
 735         u32 regval;
 736
 737         spin_lock_irqsave(&pctl->lock, flags);
 738
 739         regval = readl(pctl->membase + reg);
 740
 741         if (value)
 742                 regval |= BIT(index);
 743         else
 744                 regval &= ~(BIT(index));
 745
 746         writel(regval, pctl->membase + reg);
 747
 748         spin_unlock_irqrestore(&pctl->lock, flags);
 749 }
 750
 751 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
 752                                         unsigned offset, int value)
 753 {
 754         sunxi_pinctrl_gpio_set(chip, offset, value);
 755         return pinctrl_gpio_direction_output(chip->base + offset);
 756 }
 757
 758 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
 759                                 const struct of_phandle_args *gpiospec,
 760                                 u32 *flags)
 761 {
 762         int pin, base;
 763
 764         base = PINS_PER_BANK * gpiospec->args[0];
 765         pin = base + gpiospec->args[1];
 766
 767         if (pin > gc->ngpio)
 768                 return -EINVAL;
 769
 770         if (flags)
 771                 *flags = gpiospec->args[2];
 772
 773         return pin;
 774 }
 775
 776 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 777 {
 778         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 779         struct sunxi_desc_function *desc;
 780         unsigned pinnum = pctl->desc->pin_base + offset;
 781         unsigned irqnum;
 782
 783         if (offset >= chip->ngpio)
 784                 return -ENXIO;
 785
 786         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
 787         if (!desc)
 788                 return -EINVAL;
 789
 790         irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
 791
 792         dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n",
 793                 chip->label, offset + chip->base, irqnum);
 794
 795         return irq_find_mapping(pctl->domain, irqnum);
 796 }
 797
 798 static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
 799 {
 800         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 801         struct sunxi_desc_function *func;
 802         int ret;
 803
 804         func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
 805                                         pctl->irq_array[d->hwirq], "irq");
 806         if (!func)
 807                 return -EINVAL;
 808
 809         ret = gpiochip_lock_as_irq(pctl->chip,
 810                         pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
 811         if (ret) {
 812                 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
 813                         irqd_to_hwirq(d));
 814                 return ret;
 815         }
 816
 817         /* Change muxing to INT mode */
 818         sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
 819
 820         return 0;
 821 }
 822
 823 static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
 824 {
 825         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 826
 827         gpiochip_unlock_as_irq(pctl->chip,
 828                               pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
 829 }
 830
 831 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
 832 {
 833         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 834         u32 reg = sunxi_irq_cfg_reg(d->hwirq, pctl->desc->irq_bank_base);
 835         u8 index = sunxi_irq_cfg_offset(d->hwirq);
 836         unsigned long flags;
 837         u32 regval;
 838         u8 mode;
 839
 840         switch (type) {
 841         case IRQ_TYPE_EDGE_RISING:
 842                 mode = IRQ_EDGE_RISING;
 843                 break;
 844         case IRQ_TYPE_EDGE_FALLING:
 845                 mode = IRQ_EDGE_FALLING;
 846                 break;
 847         case IRQ_TYPE_EDGE_BOTH:
 848                 mode = IRQ_EDGE_BOTH;
 849                 break;
 850         case IRQ_TYPE_LEVEL_HIGH:
 851                 mode = IRQ_LEVEL_HIGH;
 852                 break;
 853         case IRQ_TYPE_LEVEL_LOW:
 854                 mode = IRQ_LEVEL_LOW;
 855                 break;
 856         default:
 857                 return -EINVAL;
 858         }
 859
 860         spin_lock_irqsave(&pctl->lock, flags);
 861
 862         if (type & IRQ_TYPE_LEVEL_MASK)
 863                 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip,
 864                                                  handle_fasteoi_irq, NULL);
 865         else
 866                 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip,
 867                                                  handle_edge_irq, NULL);
 868
 869         regval = readl(pctl->membase + reg);
 870         regval &= ~(IRQ_CFG_IRQ_MASK << index);
 871         writel(regval | (mode << index), pctl->membase + reg);
 872
 873         spin_unlock_irqrestore(&pctl->lock, flags);
 874
 875         return 0;
 876 }
 877
 878 static void sunxi_pinctrl_irq_ack(struct irq_data *d)
 879 {
 880         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 881         u32 status_reg = sunxi_irq_status_reg(d->hwirq,
 882                                               pctl->desc->irq_bank_base);
 883         u8 status_idx = sunxi_irq_status_offset(d->hwirq);
 884
 885         /* Clear the IRQ */
 886         writel(1 << status_idx, pctl->membase + status_reg);
 887 }
 888
 889 static void sunxi_pinctrl_irq_mask(struct irq_data *d)
 890 {
 891         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 892         u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);
 893         u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
 894         unsigned long flags;
 895         u32 val;
 896
 897         spin_lock_irqsave(&pctl->lock, flags);
 898
 899         /* Mask the IRQ */
 900         val = readl(pctl->membase + reg);
 901         writel(val & ~(1 << idx), pctl->membase + reg);
 902
 903         spin_unlock_irqrestore(&pctl->lock, flags);
 904 }
 905
 906 static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
 907 {
 908         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 909         u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);
 910         u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
 911         unsigned long flags;
 912         u32 val;
 913
 914         spin_lock_irqsave(&pctl->lock, flags);
 915
 916         /* Unmask the IRQ */
 917         val = readl(pctl->membase + reg);
 918         writel(val | (1 << idx), pctl->membase + reg);
 919
 920         spin_unlock_irqrestore(&pctl->lock, flags);
 921 }
 922
 923 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
 924 {
 925         sunxi_pinctrl_irq_ack(d);
 926         sunxi_pinctrl_irq_unmask(d);
 927 }
 928
 929 static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
 930         .name           = "sunxi_pio_edge",
 931         .irq_ack        = sunxi_pinctrl_irq_ack,
 932         .irq_mask       = sunxi_pinctrl_irq_mask,
 933         .irq_unmask     = sunxi_pinctrl_irq_unmask,
 934         .irq_request_resources = sunxi_pinctrl_irq_request_resources,
 935         .irq_release_resources = sunxi_pinctrl_irq_release_resources,
 936         .irq_set_type   = sunxi_pinctrl_irq_set_type,
 937         .flags          = IRQCHIP_SKIP_SET_WAKE,
 938 };
 939
 940 static struct irq_chip sunxi_pinctrl_level_irq_chip = {
 941         .name           = "sunxi_pio_level",
 942         .irq_eoi        = sunxi_pinctrl_irq_ack,
 943         .irq_mask       = sunxi_pinctrl_irq_mask,
 944         .irq_unmask     = sunxi_pinctrl_irq_unmask,
 945         /* Define irq_enable / disable to avoid spurious irqs for drivers
 946          * using these to suppress irqs while they clear the irq source */
 947         .irq_enable     = sunxi_pinctrl_irq_ack_unmask,
 948         .irq_disable    = sunxi_pinctrl_irq_mask,
 949         .irq_request_resources = sunxi_pinctrl_irq_request_resources,
 950         .irq_release_resources = sunxi_pinctrl_irq_release_resources,
 951         .irq_set_type   = sunxi_pinctrl_irq_set_type,
 952         .flags          = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED |
 953                           IRQCHIP_EOI_IF_HANDLED,
 954 };
 955
 956 static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d,
 957                                       struct device_node *node,
 958                                       const u32 *intspec,
 959                                       unsigned int intsize,
 960                                       unsigned long *out_hwirq,
 961                                       unsigned int *out_type)
 962 {
 963         struct sunxi_pinctrl *pctl = d->host_data;
 964         struct sunxi_desc_function *desc;
 965         int pin, base;
 966
 967         if (intsize < 3)
 968                 return -EINVAL;
 969
 970         base = PINS_PER_BANK * intspec[0];
 971         pin = pctl->desc->pin_base + base + intspec[1];
 972
 973         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");
 974         if (!desc)
 975                 return -EINVAL;
 976
 977         *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum;
 978         *out_type = intspec[2];
 979
 980         return 0;
 981 }
 982
 983 static struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = {
 984         .xlate          = sunxi_pinctrl_irq_of_xlate,
 985 };
 986
 987 static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
 988 {
 989         unsigned int irq = irq_desc_get_irq(desc);
 990         struct irq_chip *chip = irq_desc_get_chip(desc);
 991         struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);
 992         unsigned long bank, reg, val;
 993
 994         for (bank = 0; bank < pctl->desc->irq_banks; bank++)
 995                 if (irq == pctl->irq[bank])
 996                         break;
 997
 998         if (bank == pctl->desc->irq_banks)
 999                 return;
1000
1001         reg = sunxi_irq_status_reg_from_bank(bank, pctl->desc->irq_bank_base);
1002         val = readl(pctl->membase + reg);
1003
1004         if (val) {
1005                 int irqoffset;
1006
1007                 chained_irq_enter(chip, desc);
1008                 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) {
1009                         int pin_irq = irq_find_mapping(pctl->domain,
1010                                                        bank * IRQ_PER_BANK + irqoffset);
1011                         generic_handle_irq(pin_irq);
1012                 }
1013                 chained_irq_exit(chip, desc);
1014         }
1015 }
1016
1017 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
1018                                         const char *name)
1019 {
1020         struct sunxi_pinctrl_function *func = pctl->functions;
1021
1022         while (func->name) {
1023                 /* function already there */
1024                 if (strcmp(func->name, name) == 0) {
1025                         func->ngroups++;
1026                         return -EEXIST;
1027                 }
1028                 func++;
1029         }
1030
1031         func->name = name;
1032         func->ngroups = 1;
1033
1034         pctl->nfunctions++;
1035
1036         return 0;
1037 }
1038
1039 static int sunxi_pinctrl_build_state(struct platform_device *pdev)
1040 {
1041         struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
1042         int i;
1043
1044         pctl->ngroups = pctl->desc->npins;
1045
1046         /* Allocate groups */
1047         pctl->groups = devm_kzalloc(&pdev->dev,
1048                                     pctl->ngroups * sizeof(*pctl->groups),
1049                                     GFP_KERNEL);
1050         if (!pctl->groups)
1051                 return -ENOMEM;
1052
1053         for (i = 0; i < pctl->desc->npins; i++) {
1054                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1055                 struct sunxi_pinctrl_group *group = pctl->groups + i;
1056
1057                 group->name = pin->pin.name;
1058                 group->pin = pin->pin.number;
1059         }
1060
1061         /*
1062          * We suppose that we won't have any more functions than pins,
1063          * we'll reallocate that later anyway
1064          */
1065         pctl->functions = devm_kzalloc(&pdev->dev,
1066                                 pctl->desc->npins * sizeof(*pctl->functions),
1067                                 GFP_KERNEL);
1068         if (!pctl->functions)
1069                 return -ENOMEM;
1070
1071         /* Count functions and their associated groups */
1072         for (i = 0; i < pctl->desc->npins; i++) {
1073                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1074                 struct sunxi_desc_function *func = pin->functions;
1075
1076                 while (func->name) {
1077                         /* Create interrupt mapping while we're at it */
1078                         if (!strcmp(func->name, "irq")) {
1079                                 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
1080                                 pctl->irq_array[irqnum] = pin->pin.number;
1081                         }
1082
1083                         sunxi_pinctrl_add_function(pctl, func->name);
1084                         func++;
1085                 }
1086         }
1087
1088         pctl->functions = krealloc(pctl->functions,
1089                                 pctl->nfunctions * sizeof(*pctl->functions),
1090                                 GFP_KERNEL);
1091
1092         for (i = 0; i < pctl->desc->npins; i++) {
1093                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1094                 struct sunxi_desc_function *func = pin->functions;
1095
1096                 while (func->name) {
1097                         struct sunxi_pinctrl_function *func_item;
1098                         const char **func_grp;
1099
1100                         func_item = sunxi_pinctrl_find_function_by_name(pctl,
1101                                                                         func->name);
1102                         if (!func_item)
1103                                 return -EINVAL;
1104
1105                         if (!func_item->groups) {
1106                                 func_item->groups =
1107                                         devm_kzalloc(&pdev->dev,
1108                                                      func_item->ngroups * sizeof(*func_item->groups),
1109                                                      GFP_KERNEL);
1110                                 if (!func_item->groups)
1111                                         return -ENOMEM;
1112                         }
1113
1114                         func_grp = func_item->groups;
1115                         while (*func_grp)
1116                                 func_grp++;
1117
1118                         *func_grp = pin->pin.name;
1119                         func++;
1120                 }
1121         }
1122
1123         return 0;
1124 }
1125
1126 static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff)
1127 {
1128         unsigned long clock = clk_get_rate(clk);
1129         unsigned int best_diff, best_div;
1130         int i;
1131
1132         best_diff = abs(freq - clock);
1133         best_div = 0;
1134
1135         for (i = 1; i < 8; i++) {
1136                 int cur_diff = abs(freq - (clock >> i));
1137
1138                 if (cur_diff < best_diff) {
1139                         best_diff = cur_diff;
1140                         best_div = i;
1141                 }
1142         }
1143
1144         *diff = best_diff;
1145         return best_div;
1146 }
1147
1148 static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
1149                                         struct device_node *node)
1150 {
1151         unsigned int hosc_diff, losc_diff;
1152         unsigned int hosc_div, losc_div;
1153         struct clk *hosc, *losc;
1154         u8 div, src;
1155         int i, ret;
1156
1157         /* Deal with old DTs that didn't have the oscillators */
1158         if (of_count_phandle_with_args(node, "clocks", "#clock-cells") != 3)
1159                 return 0;
1160
1161         /* If we don't have any setup, bail out */
1162         if (!of_find_property(node, "input-debounce", NULL))
1163                 return 0;
1164
1165         losc = devm_clk_get(pctl->dev, "losc");
1166         if (IS_ERR(losc))
1167                 return PTR_ERR(losc);
1168
1169         hosc = devm_clk_get(pctl->dev, "hosc");
1170         if (IS_ERR(hosc))
1171                 return PTR_ERR(hosc);
1172
1173         for (i = 0; i < pctl->desc->irq_banks; i++) {
1174                 unsigned long debounce_freq;
1175                 u32 debounce;
1176
1177                 ret = of_property_read_u32_index(node, "input-debounce",
1178                                                  i, &debounce);
1179                 if (ret)
1180                         return ret;
1181
1182                 if (!debounce)
1183                         continue;
1184
1185                 debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce);
1186                 losc_div = sunxi_pinctrl_get_debounce_div(losc,
1187                                                           debounce_freq,
1188                                                           &losc_diff);
1189
1190                 hosc_div = sunxi_pinctrl_get_debounce_div(hosc,
1191                                                           debounce_freq,
1192                                                           &hosc_diff);
1193
1194                 if (hosc_diff < losc_diff) {
1195                         div = hosc_div;
1196                         src = 1;
1197                 } else {
1198                         div = losc_div;
1199                         src = 0;
1200                 }
1201
1202                 writel(src | div << 4,
1203                        pctl->membase +
1204                        sunxi_irq_debounce_reg_from_bank(i,
1205                                                         pctl->desc->irq_bank_base));
1206         }
1207
1208         return 0;
1209 }
1210
1211 int sunxi_pinctrl_init(struct platform_device *pdev,
1212                        const struct sunxi_pinctrl_desc *desc)
1213 {
1214         struct device_node *node = pdev->dev.of_node;
1215         struct pinctrl_desc *pctrl_desc;
1216         struct pinctrl_pin_desc *pins;
1217         struct sunxi_pinctrl *pctl;
1218         struct resource *res;
1219         int i, ret, last_pin;
1220         struct clk *clk;
1221
1222         pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1223         if (!pctl)
1224                 return -ENOMEM;
1225         platform_set_drvdata(pdev, pctl);
1226
1227         spin_lock_init(&pctl->lock);
1228
1229         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1230         pctl->membase = devm_ioremap_resource(&pdev->dev, res);
1231         if (IS_ERR(pctl->membase))
1232                 return PTR_ERR(pctl->membase);
1233
1234         pctl->dev = &pdev->dev;
1235         pctl->desc = desc;
1236
1237         pctl->irq_array = devm_kcalloc(&pdev->dev,
1238                                        IRQ_PER_BANK * pctl->desc->irq_banks,
1239                                        sizeof(*pctl->irq_array),
1240                                        GFP_KERNEL);
1241         if (!pctl->irq_array)
1242                 return -ENOMEM;
1243
1244         ret = sunxi_pinctrl_build_state(pdev);
1245         if (ret) {
1246                 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
1247                 return ret;
1248         }
1249
1250         pins = devm_kzalloc(&pdev->dev,
1251                             pctl->desc->npins * sizeof(*pins),
1252                             GFP_KERNEL);
1253         if (!pins)
1254                 return -ENOMEM;
1255
1256         for (i = 0; i < pctl->desc->npins; i++)
1257                 pins[i] = pctl->desc->pins[i].pin;
1258
1259         pctrl_desc = devm_kzalloc(&pdev->dev,
1260                                   sizeof(*pctrl_desc),
1261                                   GFP_KERNEL);
1262         if (!pctrl_desc)
1263                 return -ENOMEM;
1264
1265         pctrl_desc->name = dev_name(&pdev->dev);
1266         pctrl_desc->owner = THIS_MODULE;
1267         pctrl_desc->pins = pins;
1268         pctrl_desc->npins = pctl->desc->npins;
1269         pctrl_desc->confops = &sunxi_pconf_ops;
1270         pctrl_desc->pctlops = &sunxi_pctrl_ops;
1271         pctrl_desc->pmxops =  &sunxi_pmx_ops;
1272
1273         pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
1274         if (IS_ERR(pctl->pctl_dev)) {
1275                 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1276                 return PTR_ERR(pctl->pctl_dev);
1277         }
1278
1279         pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1280         if (!pctl->chip)
1281                 return -ENOMEM;
1282
1283         last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
1284         pctl->chip->owner = THIS_MODULE;
1285         pctl->chip->request = gpiochip_generic_request,
1286         pctl->chip->free = gpiochip_generic_free,
1287         pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input,
1288         pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output,
1289         pctl->chip->get = sunxi_pinctrl_gpio_get,
1290         pctl->chip->set = sunxi_pinctrl_gpio_set,
1291         pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate,
1292         pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq,
1293         pctl->chip->of_gpio_n_cells = 3,
1294         pctl->chip->can_sleep = false,
1295         pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
1296                             pctl->desc->pin_base;
1297         pctl->chip->label = dev_name(&pdev->dev);
1298         pctl->chip->parent = &pdev->dev;
1299         pctl->chip->base = pctl->desc->pin_base;
1300
1301         ret = gpiochip_add_data(pctl->chip, pctl);
1302         if (ret)
1303                 return ret;
1304
1305         for (i = 0; i < pctl->desc->npins; i++) {
1306                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1307
1308                 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1309                                              pin->pin.number - pctl->desc->pin_base,
1310                                              pin->pin.number, 1);
1311                 if (ret)
1312                         goto gpiochip_error;
1313         }
1314
1315         clk = devm_clk_get(&pdev->dev, NULL);
1316         if (IS_ERR(clk)) {
1317                 ret = PTR_ERR(clk);
1318                 goto gpiochip_error;
1319         }
1320
1321         ret = clk_prepare_enable(clk);
1322         if (ret)
1323                 goto gpiochip_error;
1324
1325         pctl->irq = devm_kcalloc(&pdev->dev,
1326                                  pctl->desc->irq_banks,
1327                                  sizeof(*pctl->irq),
1328                                  GFP_KERNEL);
1329         if (!pctl->irq) {
1330                 ret = -ENOMEM;
1331                 goto clk_error;
1332         }
1333
1334         for (i = 0; i < pctl->desc->irq_banks; i++) {
1335                 pctl->irq[i] = platform_get_irq(pdev, i);
1336                 if (pctl->irq[i] < 0) {
1337                         ret = pctl->irq[i];
1338                         goto clk_error;
1339                 }
1340         }
1341
1342         pctl->domain = irq_domain_add_linear(node,
1343                                              pctl->desc->irq_banks * IRQ_PER_BANK,
1344                                              &sunxi_pinctrl_irq_domain_ops,
1345                                              pctl);
1346         if (!pctl->domain) {
1347                 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1348                 ret = -ENOMEM;
1349                 goto clk_error;
1350         }
1351
1352         for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
1353                 int irqno = irq_create_mapping(pctl->domain, i);
1354
1355                 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
1356                                          handle_edge_irq);
1357                 irq_set_chip_data(irqno, pctl);
1358         }
1359
1360         for (i = 0; i < pctl->desc->irq_banks; i++) {
1361                 /* Mask and clear all IRQs before registering a handler */
1362                 writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i,
1363                                                 pctl->desc->irq_bank_base));
1364                 writel(0xffffffff,
1365                        pctl->membase + sunxi_irq_status_reg_from_bank(i,
1366                                                 pctl->desc->irq_bank_base));
1367
1368                 irq_set_chained_handler_and_data(pctl->irq[i],
1369                                                  sunxi_pinctrl_irq_handler,
1370                                                  pctl);
1371         }
1372
1373         sunxi_pinctrl_setup_debounce(pctl, node);
1374
1375         dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
1376
1377         return 0;
1378
1379 clk_error:
1380         clk_disable_unprepare(clk);
1381 gpiochip_error:
1382         gpiochip_remove(pctl->chip);
1383         return ret;
1384 }