2 * Allwinner A1X SoCs pinctrl driver.
4 * Copyright (C) 2012 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/irqdomain.h>
17 #include <linux/irqchip/chained_irq.h>
18 #include <linux/export.h>
20 #include <linux/of_address.h>
21 #include <linux/of_device.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/machine.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/pinctrl/pinmux.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
31 #include <dt-bindings/pinctrl/sun4i-a10.h>
34 #include "pinctrl-sunxi.h"
36 static struct irq_chip sunxi_pinctrl_edge_irq_chip;
37 static struct irq_chip sunxi_pinctrl_level_irq_chip;
39 static struct sunxi_pinctrl_group *
40 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
44 for (i = 0; i < pctl->ngroups; i++) {
45 struct sunxi_pinctrl_group *grp = pctl->groups + i;
47 if (!strcmp(grp->name, group))
54 static struct sunxi_pinctrl_function *
55 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
58 struct sunxi_pinctrl_function *func = pctl->functions;
61 for (i = 0; i < pctl->nfunctions; i++) {
65 if (!strcmp(func[i].name, name))
72 static struct sunxi_desc_function *
73 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
75 const char *func_name)
79 for (i = 0; i < pctl->desc->npins; i++) {
80 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
82 if (!strcmp(pin->pin.name, pin_name)) {
83 struct sunxi_desc_function *func = pin->functions;
86 if (!strcmp(func->name, func_name))
97 static struct sunxi_desc_function *
98 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
100 const char *func_name)
104 for (i = 0; i < pctl->desc->npins; i++) {
105 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
107 if (pin->pin.number == pin_num) {
108 struct sunxi_desc_function *func = pin->functions;
111 if (!strcmp(func->name, func_name))
122 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
124 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
126 return pctl->ngroups;
129 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
132 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
134 return pctl->groups[group].name;
137 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
139 const unsigned **pins,
142 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
144 *pins = (unsigned *)&pctl->groups[group].pin;
150 static bool sunxi_pctrl_has_bias_prop(struct device_node *node)
152 return of_find_property(node, "bias-pull-up", NULL) ||
153 of_find_property(node, "bias-pull-down", NULL) ||
154 of_find_property(node, "bias-disable", NULL) ||
155 of_find_property(node, "allwinner,pull", NULL);
158 static bool sunxi_pctrl_has_drive_prop(struct device_node *node)
160 return of_find_property(node, "drive-strength", NULL) ||
161 of_find_property(node, "allwinner,drive", NULL);
164 static int sunxi_pctrl_parse_bias_prop(struct device_node *node)
168 /* Try the new style binding */
169 if (of_find_property(node, "bias-pull-up", NULL))
170 return PIN_CONFIG_BIAS_PULL_UP;
172 if (of_find_property(node, "bias-pull-down", NULL))
173 return PIN_CONFIG_BIAS_PULL_DOWN;
175 if (of_find_property(node, "bias-disable", NULL))
176 return PIN_CONFIG_BIAS_DISABLE;
178 /* And fall back to the old binding */
179 if (of_property_read_u32(node, "allwinner,pull", &val))
183 case SUN4I_PINCTRL_NO_PULL:
184 return PIN_CONFIG_BIAS_DISABLE;
185 case SUN4I_PINCTRL_PULL_UP:
186 return PIN_CONFIG_BIAS_PULL_UP;
187 case SUN4I_PINCTRL_PULL_DOWN:
188 return PIN_CONFIG_BIAS_PULL_DOWN;
194 static int sunxi_pctrl_parse_drive_prop(struct device_node *node)
198 /* Try the new style binding */
199 if (!of_property_read_u32(node, "drive-strength", &val)) {
200 /* We can't go below 10mA ... */
204 /* ... and only up to 40 mA ... */
208 /* by steps of 10 mA */
209 return rounddown(val, 10);
212 /* And then fall back to the old binding */
213 if (of_property_read_u32(node, "allwinner,drive", &val))
216 return (val + 1) * 10;
219 static const char *sunxi_pctrl_parse_function_prop(struct device_node *node)
221 const char *function;
224 /* Try the generic binding */
225 ret = of_property_read_string(node, "function", &function);
229 /* And fall back to our legacy one */
230 ret = of_property_read_string(node, "allwinner,function", &function);
237 static const char *sunxi_pctrl_find_pins_prop(struct device_node *node,
242 /* Try the generic binding */
243 count = of_property_count_strings(node, "pins");
249 /* And fall back to our legacy one */
250 count = of_property_count_strings(node, "allwinner,pins");
253 return "allwinner,pins";
259 static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node,
262 unsigned long *pinconfig;
263 unsigned int configlen = 0, idx = 0;
266 if (sunxi_pctrl_has_drive_prop(node))
268 if (sunxi_pctrl_has_bias_prop(node))
272 * If we don't have any configuration, bail out
277 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
279 return ERR_PTR(-ENOMEM);
281 if (sunxi_pctrl_has_drive_prop(node)) {
282 int drive = sunxi_pctrl_parse_drive_prop(node);
288 pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
292 if (sunxi_pctrl_has_bias_prop(node)) {
293 int pull = sunxi_pctrl_parse_bias_prop(node);
300 if (pull != PIN_CONFIG_BIAS_DISABLE)
301 arg = 1; /* hardware uses weak pull resistors */
303 pinconfig[idx++] = pinconf_to_config_packed(pull, arg);
315 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
316 struct device_node *node,
317 struct pinctrl_map **map,
320 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
321 unsigned long *pinconfig;
322 struct property *prop;
323 const char *function, *pin_prop;
325 int ret, npins, nmaps, configlen = 0, i = 0;
330 function = sunxi_pctrl_parse_function_prop(node);
332 dev_err(pctl->dev, "missing function property in node %s\n",
337 pin_prop = sunxi_pctrl_find_pins_prop(node, &npins);
339 dev_err(pctl->dev, "missing pins property in node %s\n",
345 * We have two maps for each pin: one for the function, one
346 * for the configuration (bias, strength, etc).
348 * We might be slightly overshooting, since we might not have
352 *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
356 pinconfig = sunxi_pctrl_build_pin_config(node, &configlen);
357 if (IS_ERR(pinconfig)) {
358 ret = PTR_ERR(pinconfig);
362 of_property_for_each_string(node, pin_prop, prop, group) {
363 struct sunxi_pinctrl_group *grp =
364 sunxi_pinctrl_find_group_by_name(pctl, group);
367 dev_err(pctl->dev, "unknown pin %s", group);
371 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
374 dev_err(pctl->dev, "unsupported function %s on pin %s",
379 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
380 (*map)[i].data.mux.group = group;
381 (*map)[i].data.mux.function = function;
386 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
387 (*map)[i].data.configs.group_or_pin = group;
388 (*map)[i].data.configs.configs = pinconfig;
389 (*map)[i].data.configs.num_configs = configlen;
397 * We know have the number of maps we need, we can resize our
400 *map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL);
412 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
413 struct pinctrl_map *map,
418 /* pin config is never in the first map */
419 for (i = 1; i < num_maps; i++) {
420 if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP)
424 * All the maps share the same pin config,
425 * free only the first one we find.
427 kfree(map[i].data.configs.configs);
434 static const struct pinctrl_ops sunxi_pctrl_ops = {
435 .dt_node_to_map = sunxi_pctrl_dt_node_to_map,
436 .dt_free_map = sunxi_pctrl_dt_free_map,
437 .get_groups_count = sunxi_pctrl_get_groups_count,
438 .get_group_name = sunxi_pctrl_get_group_name,
439 .get_group_pins = sunxi_pctrl_get_group_pins,
442 static int sunxi_pconf_reg(unsigned pin, enum pin_config_param param,
443 u32 *offset, u32 *shift, u32 *mask)
446 case PIN_CONFIG_DRIVE_STRENGTH:
447 *offset = sunxi_dlevel_reg(pin);
448 *shift = sunxi_dlevel_offset(pin);
449 *mask = DLEVEL_PINS_MASK;
452 case PIN_CONFIG_BIAS_PULL_UP:
453 case PIN_CONFIG_BIAS_PULL_DOWN:
454 case PIN_CONFIG_BIAS_DISABLE:
455 *offset = sunxi_pull_reg(pin);
456 *shift = sunxi_pull_offset(pin);
457 *mask = PULL_PINS_MASK;
467 static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
468 unsigned long *config)
470 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
471 enum pin_config_param param = pinconf_to_config_param(*config);
472 u32 offset, shift, mask, val;
476 pin -= pctl->desc->pin_base;
478 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
482 val = (readl(pctl->membase + offset) >> shift) & mask;
484 switch (pinconf_to_config_param(*config)) {
485 case PIN_CONFIG_DRIVE_STRENGTH:
486 arg = (val + 1) * 10;
489 case PIN_CONFIG_BIAS_PULL_UP:
490 if (val != SUN4I_PINCTRL_PULL_UP)
492 arg = 1; /* hardware is weak pull-up */
495 case PIN_CONFIG_BIAS_PULL_DOWN:
496 if (val != SUN4I_PINCTRL_PULL_DOWN)
498 arg = 1; /* hardware is weak pull-down */
501 case PIN_CONFIG_BIAS_DISABLE:
502 if (val != SUN4I_PINCTRL_NO_PULL)
508 /* sunxi_pconf_reg should catch anything unsupported */
513 *config = pinconf_to_config_packed(param, arg);
518 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
520 unsigned long *config)
522 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
523 struct sunxi_pinctrl_group *g = &pctl->groups[group];
525 /* We only support 1 pin per group. Chain it to the pin callback */
526 return sunxi_pconf_get(pctldev, g->pin, config);
529 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
531 unsigned long *configs,
532 unsigned num_configs)
534 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
535 struct sunxi_pinctrl_group *g = &pctl->groups[group];
536 unsigned pin = g->pin - pctl->desc->pin_base;
539 for (i = 0; i < num_configs; i++) {
540 enum pin_config_param param;
542 u32 offset, shift, mask, reg;
546 param = pinconf_to_config_param(configs[i]);
547 arg = pinconf_to_config_argument(configs[i]);
549 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
554 case PIN_CONFIG_DRIVE_STRENGTH:
555 if (arg < 10 || arg > 40)
558 * We convert from mA to what the register expects:
566 case PIN_CONFIG_BIAS_DISABLE:
568 case PIN_CONFIG_BIAS_PULL_UP:
573 case PIN_CONFIG_BIAS_PULL_DOWN:
579 /* sunxi_pconf_reg should catch anything unsupported */
584 spin_lock_irqsave(&pctl->lock, flags);
585 reg = readl(pctl->membase + offset);
586 reg &= ~(mask << shift);
587 writel(reg | val << shift, pctl->membase + offset);
588 spin_unlock_irqrestore(&pctl->lock, flags);
589 } /* for each config */
594 static const struct pinconf_ops sunxi_pconf_ops = {
596 .pin_config_get = sunxi_pconf_get,
597 .pin_config_group_get = sunxi_pconf_group_get,
598 .pin_config_group_set = sunxi_pconf_group_set,
601 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
603 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
605 return pctl->nfunctions;
608 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
611 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
613 return pctl->functions[function].name;
616 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
618 const char * const **groups,
619 unsigned * const num_groups)
621 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
623 *groups = pctl->functions[function].groups;
624 *num_groups = pctl->functions[function].ngroups;
629 static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
633 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
637 spin_lock_irqsave(&pctl->lock, flags);
639 pin -= pctl->desc->pin_base;
640 val = readl(pctl->membase + sunxi_mux_reg(pin));
641 mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
642 writel((val & ~mask) | config << sunxi_mux_offset(pin),
643 pctl->membase + sunxi_mux_reg(pin));
645 spin_unlock_irqrestore(&pctl->lock, flags);
648 static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
652 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
653 struct sunxi_pinctrl_group *g = pctl->groups + group;
654 struct sunxi_pinctrl_function *func = pctl->functions + function;
655 struct sunxi_desc_function *desc =
656 sunxi_pinctrl_desc_find_function_by_name(pctl,
663 sunxi_pmx_set(pctldev, g->pin, desc->muxval);
669 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
670 struct pinctrl_gpio_range *range,
674 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
675 struct sunxi_desc_function *desc;
683 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
687 sunxi_pmx_set(pctldev, offset, desc->muxval);
692 static const struct pinmux_ops sunxi_pmx_ops = {
693 .get_functions_count = sunxi_pmx_get_funcs_cnt,
694 .get_function_name = sunxi_pmx_get_func_name,
695 .get_function_groups = sunxi_pmx_get_func_groups,
696 .set_mux = sunxi_pmx_set_mux,
697 .gpio_set_direction = sunxi_pmx_gpio_set_direction,
700 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
703 return pinctrl_gpio_direction_input(chip->base + offset);
706 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
708 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
709 u32 reg = sunxi_data_reg(offset);
710 u8 index = sunxi_data_offset(offset);
711 bool set_mux = pctl->desc->irq_read_needs_mux &&
712 gpiochip_line_is_irq(chip, offset);
713 u32 pin = offset + chip->base;
717 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
719 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
722 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
727 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
728 unsigned offset, int value)
730 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
731 u32 reg = sunxi_data_reg(offset);
732 u8 index = sunxi_data_offset(offset);
736 spin_lock_irqsave(&pctl->lock, flags);
738 regval = readl(pctl->membase + reg);
741 regval |= BIT(index);
743 regval &= ~(BIT(index));
745 writel(regval, pctl->membase + reg);
747 spin_unlock_irqrestore(&pctl->lock, flags);
750 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
751 unsigned offset, int value)
753 sunxi_pinctrl_gpio_set(chip, offset, value);
754 return pinctrl_gpio_direction_output(chip->base + offset);
757 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
758 const struct of_phandle_args *gpiospec,
763 base = PINS_PER_BANK * gpiospec->args[0];
764 pin = base + gpiospec->args[1];
770 *flags = gpiospec->args[2];
775 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
777 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
778 struct sunxi_desc_function *desc;
779 unsigned pinnum = pctl->desc->pin_base + offset;
782 if (offset >= chip->ngpio)
785 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
789 irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
791 dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n",
792 chip->label, offset + chip->base, irqnum);
794 return irq_find_mapping(pctl->domain, irqnum);
797 static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
799 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
800 struct sunxi_desc_function *func;
803 func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
804 pctl->irq_array[d->hwirq], "irq");
808 ret = gpiochip_lock_as_irq(pctl->chip,
809 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
811 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
816 /* Change muxing to INT mode */
817 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
822 static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
824 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
826 gpiochip_unlock_as_irq(pctl->chip,
827 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
830 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
832 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
833 u32 reg = sunxi_irq_cfg_reg(d->hwirq, pctl->desc->irq_bank_base);
834 u8 index = sunxi_irq_cfg_offset(d->hwirq);
840 case IRQ_TYPE_EDGE_RISING:
841 mode = IRQ_EDGE_RISING;
843 case IRQ_TYPE_EDGE_FALLING:
844 mode = IRQ_EDGE_FALLING;
846 case IRQ_TYPE_EDGE_BOTH:
847 mode = IRQ_EDGE_BOTH;
849 case IRQ_TYPE_LEVEL_HIGH:
850 mode = IRQ_LEVEL_HIGH;
852 case IRQ_TYPE_LEVEL_LOW:
853 mode = IRQ_LEVEL_LOW;
859 spin_lock_irqsave(&pctl->lock, flags);
861 if (type & IRQ_TYPE_LEVEL_MASK)
862 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip,
863 handle_fasteoi_irq, NULL);
865 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip,
866 handle_edge_irq, NULL);
868 regval = readl(pctl->membase + reg);
869 regval &= ~(IRQ_CFG_IRQ_MASK << index);
870 writel(regval | (mode << index), pctl->membase + reg);
872 spin_unlock_irqrestore(&pctl->lock, flags);
877 static void sunxi_pinctrl_irq_ack(struct irq_data *d)
879 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
880 u32 status_reg = sunxi_irq_status_reg(d->hwirq,
881 pctl->desc->irq_bank_base);
882 u8 status_idx = sunxi_irq_status_offset(d->hwirq);
885 writel(1 << status_idx, pctl->membase + status_reg);
888 static void sunxi_pinctrl_irq_mask(struct irq_data *d)
890 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
891 u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);
892 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
896 spin_lock_irqsave(&pctl->lock, flags);
899 val = readl(pctl->membase + reg);
900 writel(val & ~(1 << idx), pctl->membase + reg);
902 spin_unlock_irqrestore(&pctl->lock, flags);
905 static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
907 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
908 u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);
909 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
913 spin_lock_irqsave(&pctl->lock, flags);
916 val = readl(pctl->membase + reg);
917 writel(val | (1 << idx), pctl->membase + reg);
919 spin_unlock_irqrestore(&pctl->lock, flags);
922 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
924 sunxi_pinctrl_irq_ack(d);
925 sunxi_pinctrl_irq_unmask(d);
928 static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
929 .name = "sunxi_pio_edge",
930 .irq_ack = sunxi_pinctrl_irq_ack,
931 .irq_mask = sunxi_pinctrl_irq_mask,
932 .irq_unmask = sunxi_pinctrl_irq_unmask,
933 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
934 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
935 .irq_set_type = sunxi_pinctrl_irq_set_type,
936 .flags = IRQCHIP_SKIP_SET_WAKE,
939 static struct irq_chip sunxi_pinctrl_level_irq_chip = {
940 .name = "sunxi_pio_level",
941 .irq_eoi = sunxi_pinctrl_irq_ack,
942 .irq_mask = sunxi_pinctrl_irq_mask,
943 .irq_unmask = sunxi_pinctrl_irq_unmask,
944 /* Define irq_enable / disable to avoid spurious irqs for drivers
945 * using these to suppress irqs while they clear the irq source */
946 .irq_enable = sunxi_pinctrl_irq_ack_unmask,
947 .irq_disable = sunxi_pinctrl_irq_mask,
948 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
949 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
950 .irq_set_type = sunxi_pinctrl_irq_set_type,
951 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED |
952 IRQCHIP_EOI_IF_HANDLED,
955 static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d,
956 struct device_node *node,
958 unsigned int intsize,
959 unsigned long *out_hwirq,
960 unsigned int *out_type)
962 struct sunxi_pinctrl *pctl = d->host_data;
963 struct sunxi_desc_function *desc;
969 base = PINS_PER_BANK * intspec[0];
970 pin = pctl->desc->pin_base + base + intspec[1];
972 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");
976 *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum;
977 *out_type = intspec[2];
982 static struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = {
983 .xlate = sunxi_pinctrl_irq_of_xlate,
986 static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
988 unsigned int irq = irq_desc_get_irq(desc);
989 struct irq_chip *chip = irq_desc_get_chip(desc);
990 struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);
991 unsigned long bank, reg, val;
993 for (bank = 0; bank < pctl->desc->irq_banks; bank++)
994 if (irq == pctl->irq[bank])
997 if (bank == pctl->desc->irq_banks)
1000 reg = sunxi_irq_status_reg_from_bank(bank, pctl->desc->irq_bank_base);
1001 val = readl(pctl->membase + reg);
1006 chained_irq_enter(chip, desc);
1007 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) {
1008 int pin_irq = irq_find_mapping(pctl->domain,
1009 bank * IRQ_PER_BANK + irqoffset);
1010 generic_handle_irq(pin_irq);
1012 chained_irq_exit(chip, desc);
1016 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
1019 struct sunxi_pinctrl_function *func = pctl->functions;
1021 while (func->name) {
1022 /* function already there */
1023 if (strcmp(func->name, name) == 0) {
1038 static int sunxi_pinctrl_build_state(struct platform_device *pdev)
1040 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
1043 pctl->ngroups = pctl->desc->npins;
1045 /* Allocate groups */
1046 pctl->groups = devm_kzalloc(&pdev->dev,
1047 pctl->ngroups * sizeof(*pctl->groups),
1052 for (i = 0; i < pctl->desc->npins; i++) {
1053 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1054 struct sunxi_pinctrl_group *group = pctl->groups + i;
1056 group->name = pin->pin.name;
1057 group->pin = pin->pin.number;
1061 * We suppose that we won't have any more functions than pins,
1062 * we'll reallocate that later anyway
1064 pctl->functions = devm_kzalloc(&pdev->dev,
1065 pctl->desc->npins * sizeof(*pctl->functions),
1067 if (!pctl->functions)
1070 /* Count functions and their associated groups */
1071 for (i = 0; i < pctl->desc->npins; i++) {
1072 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1073 struct sunxi_desc_function *func = pin->functions;
1075 while (func->name) {
1076 /* Create interrupt mapping while we're at it */
1077 if (!strcmp(func->name, "irq")) {
1078 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
1079 pctl->irq_array[irqnum] = pin->pin.number;
1082 sunxi_pinctrl_add_function(pctl, func->name);
1087 pctl->functions = krealloc(pctl->functions,
1088 pctl->nfunctions * sizeof(*pctl->functions),
1091 for (i = 0; i < pctl->desc->npins; i++) {
1092 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1093 struct sunxi_desc_function *func = pin->functions;
1095 while (func->name) {
1096 struct sunxi_pinctrl_function *func_item;
1097 const char **func_grp;
1099 func_item = sunxi_pinctrl_find_function_by_name(pctl,
1104 if (!func_item->groups) {
1106 devm_kzalloc(&pdev->dev,
1107 func_item->ngroups * sizeof(*func_item->groups),
1109 if (!func_item->groups)
1113 func_grp = func_item->groups;
1117 *func_grp = pin->pin.name;
1125 static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff)
1127 unsigned long clock = clk_get_rate(clk);
1128 unsigned int best_diff, best_div;
1131 best_diff = abs(freq - clock);
1134 for (i = 1; i < 8; i++) {
1135 int cur_diff = abs(freq - (clock >> i));
1137 if (cur_diff < best_diff) {
1138 best_diff = cur_diff;
1147 static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
1148 struct device_node *node)
1150 unsigned int hosc_diff, losc_diff;
1151 unsigned int hosc_div, losc_div;
1152 struct clk *hosc, *losc;
1156 /* Deal with old DTs that didn't have the oscillators */
1157 if (of_count_phandle_with_args(node, "clocks", "#clock-cells") != 3)
1160 /* If we don't have any setup, bail out */
1161 if (!of_find_property(node, "input-debounce", NULL))
1164 losc = devm_clk_get(pctl->dev, "losc");
1166 return PTR_ERR(losc);
1168 hosc = devm_clk_get(pctl->dev, "hosc");
1170 return PTR_ERR(hosc);
1172 for (i = 0; i < pctl->desc->irq_banks; i++) {
1173 unsigned long debounce_freq;
1176 ret = of_property_read_u32_index(node, "input-debounce",
1184 debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce);
1185 losc_div = sunxi_pinctrl_get_debounce_div(losc,
1189 hosc_div = sunxi_pinctrl_get_debounce_div(hosc,
1193 if (hosc_diff < losc_diff) {
1201 writel(src | div << 4,
1203 sunxi_irq_debounce_reg_from_bank(i,
1204 pctl->desc->irq_bank_base));
1210 int sunxi_pinctrl_init(struct platform_device *pdev,
1211 const struct sunxi_pinctrl_desc *desc)
1213 struct device_node *node = pdev->dev.of_node;
1214 struct pinctrl_desc *pctrl_desc;
1215 struct pinctrl_pin_desc *pins;
1216 struct sunxi_pinctrl *pctl;
1217 struct resource *res;
1218 int i, ret, last_pin;
1221 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1224 platform_set_drvdata(pdev, pctl);
1226 spin_lock_init(&pctl->lock);
1228 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1229 pctl->membase = devm_ioremap_resource(&pdev->dev, res);
1230 if (IS_ERR(pctl->membase))
1231 return PTR_ERR(pctl->membase);
1233 pctl->dev = &pdev->dev;
1236 pctl->irq_array = devm_kcalloc(&pdev->dev,
1237 IRQ_PER_BANK * pctl->desc->irq_banks,
1238 sizeof(*pctl->irq_array),
1240 if (!pctl->irq_array)
1243 ret = sunxi_pinctrl_build_state(pdev);
1245 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
1249 pins = devm_kzalloc(&pdev->dev,
1250 pctl->desc->npins * sizeof(*pins),
1255 for (i = 0; i < pctl->desc->npins; i++)
1256 pins[i] = pctl->desc->pins[i].pin;
1258 pctrl_desc = devm_kzalloc(&pdev->dev,
1259 sizeof(*pctrl_desc),
1264 pctrl_desc->name = dev_name(&pdev->dev);
1265 pctrl_desc->owner = THIS_MODULE;
1266 pctrl_desc->pins = pins;
1267 pctrl_desc->npins = pctl->desc->npins;
1268 pctrl_desc->confops = &sunxi_pconf_ops;
1269 pctrl_desc->pctlops = &sunxi_pctrl_ops;
1270 pctrl_desc->pmxops = &sunxi_pmx_ops;
1272 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
1273 if (IS_ERR(pctl->pctl_dev)) {
1274 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1275 return PTR_ERR(pctl->pctl_dev);
1278 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1282 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
1283 pctl->chip->owner = THIS_MODULE;
1284 pctl->chip->request = gpiochip_generic_request,
1285 pctl->chip->free = gpiochip_generic_free,
1286 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input,
1287 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output,
1288 pctl->chip->get = sunxi_pinctrl_gpio_get,
1289 pctl->chip->set = sunxi_pinctrl_gpio_set,
1290 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate,
1291 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq,
1292 pctl->chip->of_gpio_n_cells = 3,
1293 pctl->chip->can_sleep = false,
1294 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
1295 pctl->desc->pin_base;
1296 pctl->chip->label = dev_name(&pdev->dev);
1297 pctl->chip->parent = &pdev->dev;
1298 pctl->chip->base = pctl->desc->pin_base;
1300 ret = gpiochip_add_data(pctl->chip, pctl);
1304 for (i = 0; i < pctl->desc->npins; i++) {
1305 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1307 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1308 pin->pin.number - pctl->desc->pin_base,
1309 pin->pin.number, 1);
1311 goto gpiochip_error;
1314 clk = devm_clk_get(&pdev->dev, NULL);
1317 goto gpiochip_error;
1320 ret = clk_prepare_enable(clk);
1322 goto gpiochip_error;
1324 pctl->irq = devm_kcalloc(&pdev->dev,
1325 pctl->desc->irq_banks,
1333 for (i = 0; i < pctl->desc->irq_banks; i++) {
1334 pctl->irq[i] = platform_get_irq(pdev, i);
1335 if (pctl->irq[i] < 0) {
1341 pctl->domain = irq_domain_add_linear(node,
1342 pctl->desc->irq_banks * IRQ_PER_BANK,
1343 &sunxi_pinctrl_irq_domain_ops,
1345 if (!pctl->domain) {
1346 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1351 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
1352 int irqno = irq_create_mapping(pctl->domain, i);
1354 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
1356 irq_set_chip_data(irqno, pctl);
1359 for (i = 0; i < pctl->desc->irq_banks; i++) {
1360 /* Mask and clear all IRQs before registering a handler */
1361 writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i,
1362 pctl->desc->irq_bank_base));
1364 pctl->membase + sunxi_irq_status_reg_from_bank(i,
1365 pctl->desc->irq_bank_base));
1367 irq_set_chained_handler_and_data(pctl->irq[i],
1368 sunxi_pinctrl_irq_handler,
1372 sunxi_pinctrl_setup_debounce(pctl, node);
1374 dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
1379 clk_disable_unprepare(clk);
1381 gpiochip_remove(pctl->chip);