2 * intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism
4 * (C) Copyright 2008-2010,2015 Intel Corporation
5 * Author: Sreedhara DS (sreedhara.ds@intel.com)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
12 * SCU running in ARC processor communicates with other entity running in IA
13 * core through IPC mechanism which in turn messaging between IA core ad SCU.
14 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
15 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
16 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
17 * along with other APIs.
19 #include <linux/delay.h>
20 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/device.h>
24 #include <linux/pci.h>
25 #include <linux/interrupt.h>
26 #include <linux/sfi.h>
27 #include <linux/module.h>
28 #include <asm/intel-mid.h>
29 #include <asm/intel_scu_ipc.h>
31 /* IPC defines the following message types */
32 #define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */
33 #define IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */
34 #define IPCMSG_FW_UPDATE 0xFE /* Firmware update */
35 #define IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */
36 #define IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */
38 /* Command id associated with message IPCMSG_PCNTRL */
39 #define IPC_CMD_PCNTRL_W 0 /* Register write */
40 #define IPC_CMD_PCNTRL_R 1 /* Register read */
41 #define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */
44 * IPC register summary
46 * IPC register blocks are memory mapped at fixed address of PCI BAR 0.
47 * To read or write information to the SCU, driver writes to IPC-1 memory
48 * mapped registers. The following is the IPC mechanism
50 * 1. IA core cDMI interface claims this transaction and converts it to a
51 * Transaction Layer Packet (TLP) message which is sent across the cDMI.
53 * 2. South Complex cDMI block receives this message and writes it to
54 * the IPC-1 register block, causing an interrupt to the SCU
56 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate
57 * message handler is called within firmware.
60 #define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */
61 #define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */
62 #define IPC_IOC 0x100 /* IPC command register IOC bit */
64 #define PCI_DEVICE_ID_LINCROFT 0x082a
65 #define PCI_DEVICE_ID_PENWELL 0x080e
66 #define PCI_DEVICE_ID_CLOVERVIEW 0x08ea
67 #define PCI_DEVICE_ID_TANGIER 0x11a0
69 /* intel scu ipc driver data */
70 struct intel_scu_ipc_pdata_t {
76 static struct intel_scu_ipc_pdata_t intel_scu_ipc_lincroft_pdata = {
77 .i2c_base = 0xff12b000,
82 /* Penwell and Cloverview */
83 static struct intel_scu_ipc_pdata_t intel_scu_ipc_penwell_pdata = {
84 .i2c_base = 0xff12b000,
89 static struct intel_scu_ipc_pdata_t intel_scu_ipc_tangier_pdata = {
90 .i2c_base = 0xff00d000,
95 static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id);
96 static void ipc_remove(struct pci_dev *pdev);
98 struct intel_scu_ipc_dev {
100 void __iomem *ipc_base;
101 void __iomem *i2c_base;
102 struct completion cmd_complete;
106 static struct intel_scu_ipc_dev ipcdev; /* Only one for now */
109 * IPC Read Buffer (Read Only):
110 * 16 byte buffer for receiving data from SCU, if IPC command
111 * processing results in response data
113 #define IPC_READ_BUFFER 0x90
115 #define IPC_I2C_CNTRL_ADDR 0
116 #define I2C_DATA_ADDR 0x04
118 static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
122 * Command Register (Write Only):
123 * A write to this register results in an interrupt to the SCU core processor
125 * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
127 static inline void ipc_command(struct intel_scu_ipc_dev *scu, u32 cmd)
130 reinit_completion(&scu->cmd_complete);
131 writel(cmd | IPC_IOC, scu->ipc_base);
133 writel(cmd, scu->ipc_base);
138 * IPC Write Buffer (Write Only):
139 * 16-byte buffer for sending data associated with IPC command to
140 * SCU. Size of the data is specified in the IPC_COMMAND_REG register
142 static inline void ipc_data_writel(struct intel_scu_ipc_dev *scu, u32 data, u32 offset)
144 writel(data, scu->ipc_base + 0x80 + offset);
148 * Status Register (Read Only):
149 * Driver will read this register to get the ready/busy status of the IPC
150 * block and error status of the IPC command that was just processed by SCU
152 * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
154 static inline u8 ipc_read_status(struct intel_scu_ipc_dev *scu)
156 return __raw_readl(scu->ipc_base + 0x04);
159 /* Read ipc byte data */
160 static inline u8 ipc_data_readb(struct intel_scu_ipc_dev *scu, u32 offset)
162 return readb(scu->ipc_base + IPC_READ_BUFFER + offset);
165 /* Read ipc u32 data */
166 static inline u32 ipc_data_readl(struct intel_scu_ipc_dev *scu, u32 offset)
168 return readl(scu->ipc_base + IPC_READ_BUFFER + offset);
171 /* Wait till scu status is busy */
172 static inline int busy_loop(struct intel_scu_ipc_dev *scu)
174 u32 status = ipc_read_status(scu);
175 u32 loop_count = 100000;
177 /* break if scu doesn't reset busy bit after huge retry */
178 while ((status & BIT(0)) && --loop_count) {
179 udelay(1); /* scu processing time is in few u secods */
180 status = ipc_read_status(scu);
183 if (status & BIT(0)) {
184 dev_err(&scu->pdev->dev, "IPC timed out");
194 /* Wait till ipc ioc interrupt is received or timeout in 3 HZ */
195 static inline int ipc_wait_for_interrupt(struct intel_scu_ipc_dev *scu)
199 if (!wait_for_completion_timeout(&scu->cmd_complete, 3 * HZ)) {
200 struct device *dev = &scu->pdev->dev;
201 dev_err(dev, "IPC timed out\n");
205 status = ipc_read_status(scu);
212 static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev *scu)
214 return scu->irq_mode ? ipc_wait_for_interrupt(scu) : busy_loop(scu);
217 /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
218 static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
220 struct intel_scu_ipc_dev *scu = &ipcdev;
224 u8 cbuf[IPC_WWBUF_SIZE];
225 u32 *wbuf = (u32 *)&cbuf;
227 memset(cbuf, 0, sizeof(cbuf));
229 mutex_lock(&ipclock);
231 if (scu->pdev == NULL) {
232 mutex_unlock(&ipclock);
236 for (nc = 0; nc < count; nc++, offset += 2) {
237 cbuf[offset] = addr[nc];
238 cbuf[offset + 1] = addr[nc] >> 8;
241 if (id == IPC_CMD_PCNTRL_R) {
242 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
243 ipc_data_writel(scu, wbuf[nc], offset);
244 ipc_command(scu, (count * 2) << 16 | id << 12 | 0 << 8 | op);
245 } else if (id == IPC_CMD_PCNTRL_W) {
246 for (nc = 0; nc < count; nc++, offset += 1)
247 cbuf[offset] = data[nc];
248 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
249 ipc_data_writel(scu, wbuf[nc], offset);
250 ipc_command(scu, (count * 3) << 16 | id << 12 | 0 << 8 | op);
251 } else if (id == IPC_CMD_PCNTRL_M) {
252 cbuf[offset] = data[0];
253 cbuf[offset + 1] = data[1];
254 ipc_data_writel(scu, wbuf[0], 0); /* Write wbuff */
255 ipc_command(scu, 4 << 16 | id << 12 | 0 << 8 | op);
258 err = intel_scu_ipc_check_status(scu);
259 if (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
260 /* Workaround: values are read as 0 without memcpy_fromio */
261 memcpy_fromio(cbuf, scu->ipc_base + 0x90, 16);
262 for (nc = 0; nc < count; nc++)
263 data[nc] = ipc_data_readb(scu, nc);
265 mutex_unlock(&ipclock);
270 * intel_scu_ipc_ioread8 - read a word via the SCU
271 * @addr: register on SCU
272 * @data: return pointer for read byte
274 * Read a single register. Returns 0 on success or an error code. All
275 * locking between SCU accesses is handled for the caller.
277 * This function may sleep.
279 int intel_scu_ipc_ioread8(u16 addr, u8 *data)
281 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
283 EXPORT_SYMBOL(intel_scu_ipc_ioread8);
286 * intel_scu_ipc_ioread16 - read a word via the SCU
287 * @addr: register on SCU
288 * @data: return pointer for read word
290 * Read a register pair. Returns 0 on success or an error code. All
291 * locking between SCU accesses is handled for the caller.
293 * This function may sleep.
295 int intel_scu_ipc_ioread16(u16 addr, u16 *data)
297 u16 x[2] = {addr, addr + 1};
298 return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
300 EXPORT_SYMBOL(intel_scu_ipc_ioread16);
303 * intel_scu_ipc_ioread32 - read a dword via the SCU
304 * @addr: register on SCU
305 * @data: return pointer for read dword
307 * Read four registers. Returns 0 on success or an error code. All
308 * locking between SCU accesses is handled for the caller.
310 * This function may sleep.
312 int intel_scu_ipc_ioread32(u16 addr, u32 *data)
314 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
315 return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
317 EXPORT_SYMBOL(intel_scu_ipc_ioread32);
320 * intel_scu_ipc_iowrite8 - write a byte via the SCU
321 * @addr: register on SCU
322 * @data: byte to write
324 * Write a single register. Returns 0 on success or an error code. All
325 * locking between SCU accesses is handled for the caller.
327 * This function may sleep.
329 int intel_scu_ipc_iowrite8(u16 addr, u8 data)
331 return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
333 EXPORT_SYMBOL(intel_scu_ipc_iowrite8);
336 * intel_scu_ipc_iowrite16 - write a word via the SCU
337 * @addr: register on SCU
338 * @data: word to write
340 * Write two registers. Returns 0 on success or an error code. All
341 * locking between SCU accesses is handled for the caller.
343 * This function may sleep.
345 int intel_scu_ipc_iowrite16(u16 addr, u16 data)
347 u16 x[2] = {addr, addr + 1};
348 return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
350 EXPORT_SYMBOL(intel_scu_ipc_iowrite16);
353 * intel_scu_ipc_iowrite32 - write a dword via the SCU
354 * @addr: register on SCU
355 * @data: dword to write
357 * Write four registers. Returns 0 on success or an error code. All
358 * locking between SCU accesses is handled for the caller.
360 * This function may sleep.
362 int intel_scu_ipc_iowrite32(u16 addr, u32 data)
364 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
365 return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
367 EXPORT_SYMBOL(intel_scu_ipc_iowrite32);
370 * intel_scu_ipc_readvv - read a set of registers
371 * @addr: register list
372 * @data: bytes to return
373 * @len: length of array
375 * Read registers. Returns 0 on success or an error code. All
376 * locking between SCU accesses is handled for the caller.
378 * The largest array length permitted by the hardware is 5 items.
380 * This function may sleep.
382 int intel_scu_ipc_readv(u16 *addr, u8 *data, int len)
384 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
386 EXPORT_SYMBOL(intel_scu_ipc_readv);
389 * intel_scu_ipc_writev - write a set of registers
390 * @addr: register list
391 * @data: bytes to write
392 * @len: length of array
394 * Write registers. Returns 0 on success or an error code. All
395 * locking between SCU accesses is handled for the caller.
397 * The largest array length permitted by the hardware is 5 items.
399 * This function may sleep.
402 int intel_scu_ipc_writev(u16 *addr, u8 *data, int len)
404 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
406 EXPORT_SYMBOL(intel_scu_ipc_writev);
409 * intel_scu_ipc_update_register - r/m/w a register
410 * @addr: register address
411 * @bits: bits to update
412 * @mask: mask of bits to update
414 * Read-modify-write power control unit register. The first data argument
415 * must be register value and second is mask value
416 * mask is a bitmap that indicates which bits to update.
417 * 0 = masked. Don't modify this bit, 1 = modify this bit.
418 * returns 0 on success or an error code.
420 * This function may sleep. Locking between SCU accesses is handled
423 int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)
425 u8 data[2] = { bits, mask };
426 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
428 EXPORT_SYMBOL(intel_scu_ipc_update_register);
431 * intel_scu_ipc_simple_command - send a simple command
435 * Issue a simple command to the SCU. Do not use this interface if
436 * you must then access data as any data values may be overwritten
437 * by another SCU access by the time this function returns.
439 * This function may sleep. Locking for SCU accesses is handled for
442 int intel_scu_ipc_simple_command(int cmd, int sub)
444 struct intel_scu_ipc_dev *scu = &ipcdev;
447 mutex_lock(&ipclock);
448 if (scu->pdev == NULL) {
449 mutex_unlock(&ipclock);
452 ipc_command(scu, sub << 12 | cmd);
453 err = intel_scu_ipc_check_status(scu);
454 mutex_unlock(&ipclock);
457 EXPORT_SYMBOL(intel_scu_ipc_simple_command);
460 * intel_scu_ipc_command - command with data
464 * @inlen: input length in dwords
466 * @outlein: output length in dwords
468 * Issue a command to the SCU which involves data transfers. Do the
469 * data copies under the lock but leave it for the caller to interpret
471 int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
472 u32 *out, int outlen)
474 struct intel_scu_ipc_dev *scu = &ipcdev;
477 mutex_lock(&ipclock);
478 if (scu->pdev == NULL) {
479 mutex_unlock(&ipclock);
483 for (i = 0; i < inlen; i++)
484 ipc_data_writel(scu, *in++, 4 * i);
486 ipc_command(scu, (inlen << 16) | (sub << 12) | cmd);
487 err = intel_scu_ipc_check_status(scu);
490 for (i = 0; i < outlen; i++)
491 *out++ = ipc_data_readl(scu, 4 * i);
494 mutex_unlock(&ipclock);
497 EXPORT_SYMBOL(intel_scu_ipc_command);
500 #define IPC_I2C_WRITE 1 /* I2C Write command */
501 #define IPC_I2C_READ 2 /* I2C Read command */
504 * intel_scu_ipc_i2c_cntrl - I2C read/write operations
505 * @addr: I2C address + command bits
506 * @data: data to read/write
508 * Perform an an I2C read/write operation via the SCU. All locking is
509 * handled for the caller. This function may sleep.
511 * Returns an error code or 0 on success.
513 * This has to be in the IPC driver for the locking.
515 int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)
517 struct intel_scu_ipc_dev *scu = &ipcdev;
520 mutex_lock(&ipclock);
521 if (scu->pdev == NULL) {
522 mutex_unlock(&ipclock);
525 cmd = (addr >> 24) & 0xFF;
526 if (cmd == IPC_I2C_READ) {
527 writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);
528 /* Write not getting updated without delay */
530 *data = readl(scu->i2c_base + I2C_DATA_ADDR);
531 } else if (cmd == IPC_I2C_WRITE) {
532 writel(*data, scu->i2c_base + I2C_DATA_ADDR);
534 writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);
536 dev_err(&scu->pdev->dev,
537 "intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd);
539 mutex_unlock(&ipclock);
542 mutex_unlock(&ipclock);
545 EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
548 * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
549 * When ioc bit is set to 1, caller api must wait for interrupt handler called
550 * which in turn unlocks the caller api. Currently this is not used
552 * This is edge triggered so we need take no action to clear anything
554 static irqreturn_t ioc(int irq, void *dev_id)
556 struct intel_scu_ipc_dev *scu = dev_id;
559 complete(&scu->cmd_complete);
565 * ipc_probe - probe an Intel SCU IPC
566 * @dev: the PCI device matching
567 * @id: entry in the match table
569 * Enable and install an intel SCU IPC. This appears in the PCI space
570 * but uses some hard coded addresses as well.
572 static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id)
575 struct intel_scu_ipc_dev *scu = &ipcdev;
576 struct intel_scu_ipc_pdata_t *pdata;
578 if (scu->pdev) /* We support only one SCU */
581 pdata = (struct intel_scu_ipc_pdata_t *)id->driver_data;
583 scu->pdev = pci_dev_get(dev);
584 scu->irq_mode = pdata->irq_mode;
586 err = pcim_enable_device(dev);
590 err = pcim_iomap_regions(dev, 1 << 0, pci_name(dev));
594 init_completion(&scu->cmd_complete);
596 err = devm_request_irq(&dev->dev, dev->irq, ioc, 0, "intel_scu_ipc",
601 scu->ipc_base = pcim_iomap_table(dev)[0];
603 scu->i2c_base = ioremap_nocache(pdata->i2c_base, pdata->i2c_len);
607 intel_scu_devices_create();
609 pci_set_drvdata(dev, scu);
614 * ipc_remove - remove a bound IPC device
617 * In practice the SCU is not removable but this function is also
618 * called for each device on a module unload or cleanup which is the
619 * path that will get used.
621 * Free up the mappings and release the PCI resources
623 static void ipc_remove(struct pci_dev *pdev)
625 struct intel_scu_ipc_dev *scu = pci_get_drvdata(pdev);
627 pci_dev_put(scu->pdev);
629 iounmap(scu->i2c_base);
630 intel_scu_devices_destroy();
633 static const struct pci_device_id pci_ids[] = {
635 PCI_VDEVICE(INTEL, PCI_DEVICE_ID_LINCROFT),
636 (kernel_ulong_t)&intel_scu_ipc_lincroft_pdata,
638 PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL),
639 (kernel_ulong_t)&intel_scu_ipc_penwell_pdata,
641 PCI_VDEVICE(INTEL, PCI_DEVICE_ID_CLOVERVIEW),
642 (kernel_ulong_t)&intel_scu_ipc_penwell_pdata,
644 PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER),
645 (kernel_ulong_t)&intel_scu_ipc_tangier_pdata,
650 MODULE_DEVICE_TABLE(pci, pci_ids);
652 static struct pci_driver ipc_driver = {
653 .name = "intel_scu_ipc",
656 .remove = ipc_remove,
659 static int __init intel_scu_ipc_init(void)
661 int platform; /* Platform type */
663 platform = intel_mid_identify_cpu();
666 return pci_register_driver(&ipc_driver);
669 static void __exit intel_scu_ipc_exit(void)
671 pci_unregister_driver(&ipc_driver);
674 MODULE_AUTHOR("Sreedhara DS <sreedhara.ds@intel.com>");
675 MODULE_DESCRIPTION("Intel SCU IPC driver");
676 MODULE_LICENSE("GPL");
678 module_init(intel_scu_ipc_init);
679 module_exit(intel_scu_ipc_exit);