drivers/reset/reset-socfpga.c

   1 /*
   2  * Socfpga Reset Controller Driver
   3  *
   4  * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
   5  *
   6  * based on
   7  * Allwinner SoCs Reset Controller driver
   8  *
   9  * Copyright 2013 Maxime Ripard
  10  *
  11  * Maxime Ripard <maxime.ripard@free-electrons.com>
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  */
  18
  19 #include <linux/err.h>
  20 #include <linux/io.h>
  21 #include <linux/init.h>
  22 #include <linux/of.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/reset-controller.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/types.h>
  27
  28 #define BANK_INCREMENT          4
  29 #define NR_BANKS                8
  30
  31 struct socfpga_reset_data {
  32         spinlock_t                      lock;
  33         void __iomem                    *membase;
  34         struct reset_controller_dev     rcdev;
  35 };
  36
  37 static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
  38                                 unsigned long id)
  39 {
  40         struct socfpga_reset_data *data = container_of(rcdev,
  41                                                      struct socfpga_reset_data,
  42                                                      rcdev);
  43         int bank = id / BITS_PER_LONG;
  44         int offset = id % BITS_PER_LONG;
  45         unsigned long flags;
  46         u32 reg;
  47
  48         spin_lock_irqsave(&data->lock, flags);
  49
  50         reg = readl(data->membase + (bank * BANK_INCREMENT));
  51         writel(reg | BIT(offset), data->membase + (bank * BANK_INCREMENT));
  52         spin_unlock_irqrestore(&data->lock, flags);
  53
  54         return 0;
  55 }
  56
  57 static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
  58                                   unsigned long id)
  59 {
  60         struct socfpga_reset_data *data = container_of(rcdev,
  61                                                      struct socfpga_reset_data,
  62                                                      rcdev);
  63
  64         int bank = id / BITS_PER_LONG;
  65         int offset = id % BITS_PER_LONG;
  66         unsigned long flags;
  67         u32 reg;
  68
  69         spin_lock_irqsave(&data->lock, flags);
  70
  71         reg = readl(data->membase + (bank * BANK_INCREMENT));
  72         writel(reg & ~BIT(offset), data->membase + (bank * BANK_INCREMENT));
  73
  74         spin_unlock_irqrestore(&data->lock, flags);
  75
  76         return 0;
  77 }
  78
  79 static int socfpga_reset_status(struct reset_controller_dev *rcdev,
  80                                 unsigned long id)
  81 {
  82         struct socfpga_reset_data *data = container_of(rcdev,
  83                                                 struct socfpga_reset_data, rcdev);
  84         int bank = id / BITS_PER_LONG;
  85         int offset = id % BITS_PER_LONG;
  86         u32 reg;
  87
  88         reg = readl(data->membase + (bank * BANK_INCREMENT));
  89
  90         return !(reg & BIT(offset));
  91 }
  92
  93 static const struct reset_control_ops socfpga_reset_ops = {
  94         .assert         = socfpga_reset_assert,
  95         .deassert       = socfpga_reset_deassert,
  96         .status         = socfpga_reset_status,
  97 };
  98
  99 static int socfpga_reset_probe(struct platform_device *pdev)
 100 {
 101         struct socfpga_reset_data *data;
 102         struct resource *res;
 103         struct device *dev = &pdev->dev;
 104         struct device_node *np = dev->of_node;
 105         u32 modrst_offset;
 106
 107         /*
 108          * The binding was mainlined without the required property.
 109          * Do not continue, when we encounter an old DT.
 110          */
 111         if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) {
 112                 dev_err(&pdev->dev, "%s missing #reset-cells property\n",
 113                         pdev->dev.of_node->full_name);
 114                 return -EINVAL;
 115         }
 116
 117         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 118         if (!data)
 119                 return -ENOMEM;
 120
 121         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 122         data->membase = devm_ioremap_resource(&pdev->dev, res);
 123         if (IS_ERR(data->membase))
 124                 return PTR_ERR(data->membase);
 125
 126         if (of_property_read_u32(np, "altr,modrst-offset", &modrst_offset)) {
 127                 dev_warn(dev, "missing altr,modrst-offset property, assuming 0x10!\n");
 128                 modrst_offset = 0x10;
 129         }
 130         data->membase += modrst_offset;
 131
 132         spin_lock_init(&data->lock);
 133
 134         data->rcdev.owner = THIS_MODULE;
 135         data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
 136         data->rcdev.ops = &socfpga_reset_ops;
 137         data->rcdev.of_node = pdev->dev.of_node;
 138
 139         return devm_reset_controller_register(dev, &data->rcdev);
 140 }
 141
 142 static const struct of_device_id socfpga_reset_dt_ids[] = {
 143         { .compatible = "altr,rst-mgr", },
 144         { /* sentinel */ },
 145 };
 146
 147 static struct platform_driver socfpga_reset_driver = {
 148         .probe  = socfpga_reset_probe,
 149         .driver = {
 150                 .name           = "socfpga-reset",
 151                 .of_match_table = socfpga_reset_dt_ids,
 152         },
 153 };
 154 builtin_platform_driver(socfpga_reset_driver);