1 #define DRV_NAME "advansys"
2 #define ASC_VERSION "3.4" /* AdvanSys Driver Version */
5 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
7 * Copyright (c) 1995-2000 Advanced System Products, Inc.
8 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
9 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
10 * All Rights Reserved.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
19 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
20 * changed its name to ConnectCom Solutions, Inc.
21 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/ioport.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <linux/slab.h>
33 #include <linux/proc_fs.h>
34 #include <linux/init.h>
35 #include <linux/blkdev.h>
36 #include <linux/isa.h>
37 #include <linux/eisa.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock.h>
40 #include <linux/dma-mapping.h>
43 #include <asm/system.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <scsi/scsi_device.h>
48 #include <scsi/scsi_tcq.h>
49 #include <scsi/scsi.h>
50 #include <scsi/scsi_host.h>
54 * 1. Although all of the necessary command mapping places have the
55 * appropriate dma_map.. APIs, the driver still processes its internal
56 * queue using bus_to_virt() and virt_to_bus() which are illegal under
57 * the API. The entire queue processing structure will need to be
58 * altered to fix this.
59 * 2. Need to add memory mapping workaround. Test the memory mapping.
60 * If it doesn't work revert to I/O port access. Can a test be done
62 * 3. Handle an interrupt not working. Keep an interrupt counter in
63 * the interrupt handler. In the timeout function if the interrupt
64 * has not occurred then print a message and run in polled mode.
65 * 4. Need to add support for target mode commands, cf. CAM XPT.
66 * 5. check DMA mapping functions for failure
67 * 6. Use scsi_transport_spi
68 * 7. advansys_info is not safe against multiple simultaneous callers
70 * 9. Add module_param to override ISA/VLB ioport array
72 #warning this driver is still not properly converted to the DMA API
74 /* Enable driver /proc statistics. */
75 #define ADVANSYS_STATS
77 /* Enable driver tracing. */
78 /* #define ADVANSYS_DEBUG */
80 #define ASC_LIB_VERSION_MAJOR 1
81 #define ASC_LIB_VERSION_MINOR 24
82 #define ASC_LIB_SERIAL_NUMBER 123
87 * Any instance where a 32-bit long or pointer type is assumed
88 * for precision or HW defined structures, the following define
89 * types must be used. In Linux the char, short, and int types
90 * are all consistent at 8, 16, and 32 bits respectively. Pointers
91 * and long types are 64 bits on Alpha and UltraSPARC.
93 #define ASC_PADDR __u32 /* Physical/Bus address data type. */
94 #define ASC_VADDR __u32 /* Virtual address data type. */
95 #define ASC_DCNT __u32 /* Unsigned Data count type. */
96 #define ASC_SDCNT __s32 /* Signed Data count type. */
99 * These macros are used to convert a virtual address to a
100 * 32-bit value. This currently can be used on Linux Alpha
101 * which uses 64-bit virtual address but a 32-bit bus address.
102 * This is likely to break in the future, but doing this now
103 * will give us time to change the HW and FW to handle 64-bit
106 #define ASC_VADDR_TO_U32 virt_to_bus
107 #define ASC_U32_TO_VADDR bus_to_virt
109 typedef unsigned char uchar;
119 #define UW_ERR (uint)(0xFFFF)
120 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
122 #define PCI_VENDOR_ID_ASP 0x10cd
123 #define PCI_DEVICE_ID_ASP_1200A 0x1100
124 #define PCI_DEVICE_ID_ASP_ABP940 0x1200
125 #define PCI_DEVICE_ID_ASP_ABP940U 0x1300
126 #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
127 #define PCI_DEVICE_ID_38C0800_REV1 0x2500
128 #define PCI_DEVICE_ID_38C1600_REV1 0x2700
131 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
132 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
133 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
136 #define CC_VERY_LONG_SG_LIST 0
137 #define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
139 #define PortAddr unsigned short /* port address size */
140 #define inp(port) inb(port)
141 #define outp(port, byte) outb((byte), (port))
143 #define inpw(port) inw(port)
144 #define outpw(port, word) outw((word), (port))
146 #define ASC_MAX_SG_QUEUE 7
147 #define ASC_MAX_SG_LIST 255
149 #define ASC_CS_TYPE unsigned short
151 #define ASC_IS_ISA (0x0001)
152 #define ASC_IS_ISAPNP (0x0081)
153 #define ASC_IS_EISA (0x0002)
154 #define ASC_IS_PCI (0x0004)
155 #define ASC_IS_PCI_ULTRA (0x0104)
156 #define ASC_IS_PCMCIA (0x0008)
157 #define ASC_IS_MCA (0x0020)
158 #define ASC_IS_VL (0x0040)
159 #define ASC_IS_WIDESCSI_16 (0x0100)
160 #define ASC_IS_WIDESCSI_32 (0x0200)
161 #define ASC_IS_BIG_ENDIAN (0x8000)
163 #define ASC_CHIP_MIN_VER_VL (0x01)
164 #define ASC_CHIP_MAX_VER_VL (0x07)
165 #define ASC_CHIP_MIN_VER_PCI (0x09)
166 #define ASC_CHIP_MAX_VER_PCI (0x0F)
167 #define ASC_CHIP_VER_PCI_BIT (0x08)
168 #define ASC_CHIP_MIN_VER_ISA (0x11)
169 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
170 #define ASC_CHIP_MAX_VER_ISA (0x27)
171 #define ASC_CHIP_VER_ISA_BIT (0x30)
172 #define ASC_CHIP_VER_ISAPNP_BIT (0x20)
173 #define ASC_CHIP_VER_ASYN_BUG (0x21)
174 #define ASC_CHIP_VER_PCI 0x08
175 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
176 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
177 #define ASC_CHIP_MIN_VER_EISA (0x41)
178 #define ASC_CHIP_MAX_VER_EISA (0x47)
179 #define ASC_CHIP_VER_EISA_BIT (0x40)
180 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
181 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
182 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
183 #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
185 #define ASC_SCSI_ID_BITS 3
186 #define ASC_SCSI_TIX_TYPE uchar
187 #define ASC_ALL_DEVICE_BIT_SET 0xFF
188 #define ASC_SCSI_BIT_ID_TYPE uchar
189 #define ASC_MAX_TID 7
190 #define ASC_MAX_LUN 7
191 #define ASC_SCSI_WIDTH_BIT_SET 0xFF
192 #define ASC_MAX_SENSE_LEN 32
193 #define ASC_MIN_SENSE_LEN 14
194 #define ASC_SCSI_RESET_HOLD_TIME_US 60
197 * Narrow boards only support 12-byte commands, while wide boards
198 * extend to 16-byte commands.
200 #define ASC_MAX_CDB_LEN 12
201 #define ADV_MAX_CDB_LEN 16
203 #define MS_SDTR_LEN 0x03
204 #define MS_WDTR_LEN 0x02
206 #define ASC_SG_LIST_PER_Q 7
208 #define QS_READY 0x01
209 #define QS_DISC1 0x02
210 #define QS_DISC2 0x04
212 #define QS_ABORTED 0x40
214 #define QC_NO_CALLBACK 0x01
215 #define QC_SG_SWAP_QUEUE 0x02
216 #define QC_SG_HEAD 0x04
217 #define QC_DATA_IN 0x08
218 #define QC_DATA_OUT 0x10
219 #define QC_URGENT 0x20
220 #define QC_MSG_OUT 0x40
221 #define QC_REQ_SENSE 0x80
222 #define QCSG_SG_XFER_LIST 0x02
223 #define QCSG_SG_XFER_MORE 0x04
224 #define QCSG_SG_XFER_END 0x08
225 #define QD_IN_PROGRESS 0x00
226 #define QD_NO_ERROR 0x01
227 #define QD_ABORTED_BY_HOST 0x02
228 #define QD_WITH_ERROR 0x04
229 #define QD_INVALID_REQUEST 0x80
230 #define QD_INVALID_HOST_NUM 0x81
231 #define QD_INVALID_DEVICE 0x82
232 #define QD_ERR_INTERNAL 0xFF
233 #define QHSTA_NO_ERROR 0x00
234 #define QHSTA_M_SEL_TIMEOUT 0x11
235 #define QHSTA_M_DATA_OVER_RUN 0x12
236 #define QHSTA_M_DATA_UNDER_RUN 0x12
237 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
238 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
239 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
240 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
241 #define QHSTA_D_HOST_ABORT_FAILED 0x23
242 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
243 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
244 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
245 #define QHSTA_M_WTM_TIMEOUT 0x41
246 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
247 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
248 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
249 #define QHSTA_M_TARGET_STATUS_BUSY 0x45
250 #define QHSTA_M_BAD_TAG_CODE 0x46
251 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
252 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
253 #define QHSTA_D_LRAM_CMP_ERROR 0x81
254 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
255 #define ASC_FLAG_SCSIQ_REQ 0x01
256 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
257 #define ASC_FLAG_BIOS_ASYNC_IO 0x04
258 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
259 #define ASC_FLAG_WIN16 0x10
260 #define ASC_FLAG_WIN32 0x20
261 #define ASC_FLAG_ISA_OVER_16MB 0x40
262 #define ASC_FLAG_DOS_VM_CALLBACK 0x80
263 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
264 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
265 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
266 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
267 #define ASC_SCSIQ_CPY_BEG 4
268 #define ASC_SCSIQ_SGHD_CPY_BEG 2
269 #define ASC_SCSIQ_B_FWD 0
270 #define ASC_SCSIQ_B_BWD 1
271 #define ASC_SCSIQ_B_STATUS 2
272 #define ASC_SCSIQ_B_QNO 3
273 #define ASC_SCSIQ_B_CNTL 4
274 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
275 #define ASC_SCSIQ_D_DATA_ADDR 8
276 #define ASC_SCSIQ_D_DATA_CNT 12
277 #define ASC_SCSIQ_B_SENSE_LEN 20
278 #define ASC_SCSIQ_DONE_INFO_BEG 22
279 #define ASC_SCSIQ_D_SRBPTR 22
280 #define ASC_SCSIQ_B_TARGET_IX 26
281 #define ASC_SCSIQ_B_CDB_LEN 28
282 #define ASC_SCSIQ_B_TAG_CODE 29
283 #define ASC_SCSIQ_W_VM_ID 30
284 #define ASC_SCSIQ_DONE_STATUS 32
285 #define ASC_SCSIQ_HOST_STATUS 33
286 #define ASC_SCSIQ_SCSI_STATUS 34
287 #define ASC_SCSIQ_CDB_BEG 36
288 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
289 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
290 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
291 #define ASC_SCSIQ_B_SG_WK_QP 49
292 #define ASC_SCSIQ_B_SG_WK_IX 50
293 #define ASC_SCSIQ_W_ALT_DC1 52
294 #define ASC_SCSIQ_B_LIST_CNT 6
295 #define ASC_SCSIQ_B_CUR_LIST_CNT 7
296 #define ASC_SGQ_B_SG_CNTL 4
297 #define ASC_SGQ_B_SG_HEAD_QP 5
298 #define ASC_SGQ_B_SG_LIST_CNT 6
299 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
300 #define ASC_SGQ_LIST_BEG 8
301 #define ASC_DEF_SCSI1_QNG 4
302 #define ASC_MAX_SCSI1_QNG 4
303 #define ASC_DEF_SCSI2_QNG 16
304 #define ASC_MAX_SCSI2_QNG 32
305 #define ASC_TAG_CODE_MASK 0x23
306 #define ASC_STOP_REQ_RISC_STOP 0x01
307 #define ASC_STOP_ACK_RISC_STOP 0x03
308 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
309 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
310 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
311 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
312 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
313 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
314 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
315 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
316 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
317 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
319 typedef struct asc_scsiq_1 {
328 ASC_PADDR sense_addr;
333 typedef struct asc_scsiq_2 {
342 typedef struct asc_scsiq_3 {
349 typedef struct asc_scsiq_4 {
350 uchar cdb[ASC_MAX_CDB_LEN];
351 uchar y_first_sg_list_qp;
352 uchar y_working_sg_qp;
353 uchar y_working_sg_ix;
356 ushort x_reconnect_rtn;
357 ASC_PADDR x_saved_data_addr;
358 ASC_DCNT x_saved_data_cnt;
361 typedef struct asc_q_done_info {
370 ASC_DCNT remain_bytes;
373 typedef struct asc_sg_list {
378 typedef struct asc_sg_head {
381 ushort entry_to_copy;
383 ASC_SG_LIST sg_list[0];
386 typedef struct asc_scsi_q {
390 ASC_SG_HEAD *sg_head;
391 ushort remain_sg_entry_cnt;
392 ushort next_sg_index;
395 typedef struct asc_scsi_req_q {
399 ASC_SG_HEAD *sg_head;
402 uchar cdb[ASC_MAX_CDB_LEN];
403 uchar sense[ASC_MIN_SENSE_LEN];
406 typedef struct asc_scsi_bios_req_q {
410 ASC_SG_HEAD *sg_head;
413 uchar cdb[ASC_MAX_CDB_LEN];
414 uchar sense[ASC_MIN_SENSE_LEN];
415 } ASC_SCSI_BIOS_REQ_Q;
417 typedef struct asc_risc_q {
426 typedef struct asc_sg_list_q {
432 uchar sg_cur_list_cnt;
435 typedef struct asc_risc_sg_list_q {
439 ASC_SG_LIST sg_list[7];
440 } ASC_RISC_SG_LIST_Q;
442 #define ASCQ_ERR_Q_STATUS 0x0D
443 #define ASCQ_ERR_CUR_QNG 0x17
444 #define ASCQ_ERR_SG_Q_LINKS 0x18
445 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
446 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
447 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
450 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
452 #define ASC_WARN_NO_ERROR 0x0000
453 #define ASC_WARN_IO_PORT_ROTATE 0x0001
454 #define ASC_WARN_EEPROM_CHKSUM 0x0002
455 #define ASC_WARN_IRQ_MODIFIED 0x0004
456 #define ASC_WARN_AUTO_CONFIG 0x0008
457 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
458 #define ASC_WARN_EEPROM_RECOVER 0x0020
459 #define ASC_WARN_CFG_MSW_RECOVER 0x0040
462 * Error code values are set in ASC_DVC_VAR 'err_code'.
464 #define ASC_IERR_WRITE_EEPROM 0x0001
465 #define ASC_IERR_MCODE_CHKSUM 0x0002
466 #define ASC_IERR_SET_PC_ADDR 0x0004
467 #define ASC_IERR_START_STOP_CHIP 0x0008
468 #define ASC_IERR_IRQ_NO 0x0010
469 #define ASC_IERR_SET_IRQ_NO 0x0020
470 #define ASC_IERR_CHIP_VERSION 0x0040
471 #define ASC_IERR_SET_SCSI_ID 0x0080
472 #define ASC_IERR_GET_PHY_ADDR 0x0100
473 #define ASC_IERR_BAD_SIGNATURE 0x0200
474 #define ASC_IERR_NO_BUS_TYPE 0x0400
475 #define ASC_IERR_SCAM 0x0800
476 #define ASC_IERR_SET_SDTR 0x1000
477 #define ASC_IERR_RW_LRAM 0x8000
479 #define ASC_MAX_IRQ_NO 15
480 #define ASC_MIN_IRQ_NO 10
481 #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
482 #define ASC_MIN_TAG_Q_PER_DVC (0x04)
483 #define ASC_MIN_FREE_Q (0x02)
484 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
485 #define ASC_MAX_TOTAL_QNG 240
486 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
487 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
488 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
489 #define ASC_MAX_INRAM_TAG_QNG 16
490 #define ASC_IOADR_GAP 0x10
491 #define ASC_MAX_SYN_XFER_NO 16
492 #define ASC_SYN_MAX_OFFSET 0x0F
493 #define ASC_DEF_SDTR_OFFSET 0x0F
494 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
495 #define SYN_XFER_NS_0 25
496 #define SYN_XFER_NS_1 30
497 #define SYN_XFER_NS_2 35
498 #define SYN_XFER_NS_3 40
499 #define SYN_XFER_NS_4 50
500 #define SYN_XFER_NS_5 60
501 #define SYN_XFER_NS_6 70
502 #define SYN_XFER_NS_7 85
503 #define SYN_ULTRA_XFER_NS_0 12
504 #define SYN_ULTRA_XFER_NS_1 19
505 #define SYN_ULTRA_XFER_NS_2 25
506 #define SYN_ULTRA_XFER_NS_3 32
507 #define SYN_ULTRA_XFER_NS_4 38
508 #define SYN_ULTRA_XFER_NS_5 44
509 #define SYN_ULTRA_XFER_NS_6 50
510 #define SYN_ULTRA_XFER_NS_7 57
511 #define SYN_ULTRA_XFER_NS_8 63
512 #define SYN_ULTRA_XFER_NS_9 69
513 #define SYN_ULTRA_XFER_NS_10 75
514 #define SYN_ULTRA_XFER_NS_11 82
515 #define SYN_ULTRA_XFER_NS_12 88
516 #define SYN_ULTRA_XFER_NS_13 94
517 #define SYN_ULTRA_XFER_NS_14 100
518 #define SYN_ULTRA_XFER_NS_15 107
520 typedef struct ext_msg {
526 uchar sdtr_xfer_period;
527 uchar sdtr_req_ack_offset;
542 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
543 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
544 #define wdtr_width u_ext_msg.wdtr.wdtr_width
545 #define mdp_b3 u_ext_msg.mdp_b3
546 #define mdp_b2 u_ext_msg.mdp_b2
547 #define mdp_b1 u_ext_msg.mdp_b1
548 #define mdp_b0 u_ext_msg.mdp_b0
550 typedef struct asc_dvc_cfg {
551 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
552 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
553 ASC_SCSI_BIT_ID_TYPE disc_enable;
554 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
557 uchar isa_dma_channel;
559 ushort lib_serial_no;
562 ushort mcode_version;
563 uchar max_tag_qng[ASC_MAX_TID + 1];
565 uchar sdtr_period_offset[ASC_MAX_TID + 1];
566 uchar adapter_info[6];
569 #define ASC_DEF_DVC_CNTL 0xFFFF
570 #define ASC_DEF_CHIP_SCSI_ID 7
571 #define ASC_DEF_ISA_DMA_SPEED 4
572 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
573 #define ASC_INIT_STATE_END_GET_CFG 0x0002
574 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
575 #define ASC_INIT_STATE_END_SET_CFG 0x0008
576 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
577 #define ASC_INIT_STATE_END_LOAD_MC 0x0020
578 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
579 #define ASC_INIT_STATE_END_INQUIRY 0x0080
580 #define ASC_INIT_RESET_SCSI_DONE 0x0100
581 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
582 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
583 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
584 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
585 #define ASC_MIN_TAGGED_CMD 7
586 #define ASC_MAX_SCSI_RESET_WAIT 30
588 struct asc_dvc_var; /* Forward Declaration. */
590 typedef struct asc_dvc_var {
596 ASC_SCSI_BIT_ID_TYPE init_sdtr;
597 ASC_SCSI_BIT_ID_TYPE sdtr_done;
598 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
599 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
600 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
601 ASC_SCSI_BIT_ID_TYPE start_motor;
602 uchar scsi_reset_wait;
607 uchar in_critical_cnt;
609 uchar last_q_shortage;
611 uchar cur_dvc_qng[ASC_MAX_TID + 1];
612 uchar max_dvc_qng[ASC_MAX_TID + 1];
613 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
614 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
615 uchar sdtr_period_tbl[ASC_MAX_SYN_XFER_NO];
617 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
620 uchar dos_int13_table[ASC_MAX_TID + 1];
621 ASC_DCNT max_dma_count;
622 ASC_SCSI_BIT_ID_TYPE no_scam;
623 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
624 uchar max_sdtr_index;
625 uchar host_init_sdtr_index;
626 struct asc_board *drv_ptr;
630 typedef struct asc_dvc_inq_info {
631 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
634 typedef struct asc_cap_info {
639 typedef struct asc_cap_info_array {
640 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
641 } ASC_CAP_INFO_ARRAY;
643 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
644 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
645 #define ASC_CNTL_INITIATOR (ushort)0x0001
646 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
647 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
648 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
649 #define ASC_CNTL_NO_SCAM (ushort)0x0010
650 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
651 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
652 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
653 #define ASC_CNTL_RESET_SCSI (ushort)0x0200
654 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
655 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
656 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
657 #define ASC_CNTL_BURST_MODE (ushort)0x2000
658 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
659 #define ASC_EEP_DVC_CFG_BEG_VL 2
660 #define ASC_EEP_MAX_DVC_ADDR_VL 15
661 #define ASC_EEP_DVC_CFG_BEG 32
662 #define ASC_EEP_MAX_DVC_ADDR 45
663 #define ASC_EEP_MAX_RETRY 20
666 * These macros keep the chip SCSI id and ISA DMA speed
667 * bitfields in board order. C bitfields aren't portable
668 * between big and little-endian platforms so they are
672 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
673 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
674 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
675 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
676 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
677 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
679 typedef struct asceep_config {
691 uchar id_speed; /* low order 4 bits is chip scsi id */
692 /* high order 4 bits is isa dma speed */
693 uchar dos_int13_table[ASC_MAX_TID + 1];
694 uchar adapter_info[6];
699 #define ASC_EEP_CMD_READ 0x80
700 #define ASC_EEP_CMD_WRITE 0x40
701 #define ASC_EEP_CMD_WRITE_ABLE 0x30
702 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
703 #define ASC_OVERRUN_BSIZE 0x00000048UL
704 #define ASCV_MSGOUT_BEG 0x0000
705 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
706 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
707 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
708 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
709 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
710 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
711 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
712 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
713 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
714 #define ASCV_BREAK_ADDR (ushort)0x0028
715 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
716 #define ASCV_BREAK_CONTROL (ushort)0x002C
717 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
719 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
720 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
721 #define ASCV_MCODE_SIZE_W (ushort)0x0034
722 #define ASCV_STOP_CODE_B (ushort)0x0036
723 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
724 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
725 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
726 #define ASCV_HALTCODE_W (ushort)0x0040
727 #define ASCV_CHKSUM_W (ushort)0x0042
728 #define ASCV_MC_DATE_W (ushort)0x0044
729 #define ASCV_MC_VER_W (ushort)0x0046
730 #define ASCV_NEXTRDY_B (ushort)0x0048
731 #define ASCV_DONENEXT_B (ushort)0x0049
732 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
733 #define ASCV_SCSIBUSY_B (ushort)0x004B
734 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
735 #define ASCV_CURCDB_B (ushort)0x004D
736 #define ASCV_RCLUN_B (ushort)0x004E
737 #define ASCV_BUSY_QHEAD_B (ushort)0x004F
738 #define ASCV_DISC1_QHEAD_B (ushort)0x0050
739 #define ASCV_DISC_ENABLE_B (ushort)0x0052
740 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
741 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
742 #define ASCV_MCODE_CNTL_B (ushort)0x0056
743 #define ASCV_NULL_TARGET_B (ushort)0x0057
744 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
745 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
746 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
747 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
748 #define ASCV_HOST_FLAG_B (ushort)0x005D
749 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
750 #define ASCV_VER_SERIAL_B (ushort)0x0065
751 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
752 #define ASCV_WTM_FLAG_B (ushort)0x0068
753 #define ASCV_RISC_FLAG_B (ushort)0x006A
754 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
755 #define ASC_HOST_FLAG_IN_ISR 0x01
756 #define ASC_HOST_FLAG_ACK_INT 0x02
757 #define ASC_RISC_FLAG_GEN_INT 0x01
758 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
759 #define IOP_CTRL (0x0F)
760 #define IOP_STATUS (0x0E)
761 #define IOP_INT_ACK IOP_STATUS
762 #define IOP_REG_IFC (0x0D)
763 #define IOP_SYN_OFFSET (0x0B)
764 #define IOP_EXTRA_CONTROL (0x0D)
765 #define IOP_REG_PC (0x0C)
766 #define IOP_RAM_ADDR (0x0A)
767 #define IOP_RAM_DATA (0x08)
768 #define IOP_EEP_DATA (0x06)
769 #define IOP_EEP_CMD (0x07)
770 #define IOP_VERSION (0x03)
771 #define IOP_CONFIG_HIGH (0x04)
772 #define IOP_CONFIG_LOW (0x02)
773 #define IOP_SIG_BYTE (0x01)
774 #define IOP_SIG_WORD (0x00)
775 #define IOP_REG_DC1 (0x0E)
776 #define IOP_REG_DC0 (0x0C)
777 #define IOP_REG_SB (0x0B)
778 #define IOP_REG_DA1 (0x0A)
779 #define IOP_REG_DA0 (0x08)
780 #define IOP_REG_SC (0x09)
781 #define IOP_DMA_SPEED (0x07)
782 #define IOP_REG_FLAG (0x07)
783 #define IOP_FIFO_H (0x06)
784 #define IOP_FIFO_L (0x04)
785 #define IOP_REG_ID (0x05)
786 #define IOP_REG_QP (0x03)
787 #define IOP_REG_IH (0x02)
788 #define IOP_REG_IX (0x01)
789 #define IOP_REG_AX (0x00)
790 #define IFC_REG_LOCK (0x00)
791 #define IFC_REG_UNLOCK (0x09)
792 #define IFC_WR_EN_FILTER (0x10)
793 #define IFC_RD_NO_EEPROM (0x10)
794 #define IFC_SLEW_RATE (0x20)
795 #define IFC_ACT_NEG (0x40)
796 #define IFC_INP_FILTER (0x80)
797 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
798 #define SC_SEL (uchar)(0x80)
799 #define SC_BSY (uchar)(0x40)
800 #define SC_ACK (uchar)(0x20)
801 #define SC_REQ (uchar)(0x10)
802 #define SC_ATN (uchar)(0x08)
803 #define SC_IO (uchar)(0x04)
804 #define SC_CD (uchar)(0x02)
805 #define SC_MSG (uchar)(0x01)
806 #define SEC_SCSI_CTL (uchar)(0x80)
807 #define SEC_ACTIVE_NEGATE (uchar)(0x40)
808 #define SEC_SLEW_RATE (uchar)(0x20)
809 #define SEC_ENABLE_FILTER (uchar)(0x10)
810 #define ASC_HALT_EXTMSG_IN (ushort)0x8000
811 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
812 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
813 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
814 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
815 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
816 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
817 #define ASC_MAX_QNO 0xF8
818 #define ASC_DATA_SEC_BEG (ushort)0x0080
819 #define ASC_DATA_SEC_END (ushort)0x0080
820 #define ASC_CODE_SEC_BEG (ushort)0x0080
821 #define ASC_CODE_SEC_END (ushort)0x0080
822 #define ASC_QADR_BEG (0x4000)
823 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
824 #define ASC_QADR_END (ushort)0x7FFF
825 #define ASC_QLAST_ADR (ushort)0x7FC0
826 #define ASC_QBLK_SIZE 0x40
827 #define ASC_BIOS_DATA_QBEG 0xF8
828 #define ASC_MIN_ACTIVE_QNO 0x01
829 #define ASC_QLINK_END 0xFF
830 #define ASC_EEPROM_WORDS 0x10
831 #define ASC_MAX_MGS_LEN 0x10
832 #define ASC_BIOS_ADDR_DEF 0xDC00
833 #define ASC_BIOS_SIZE 0x3800
834 #define ASC_BIOS_RAM_OFF 0x3800
835 #define ASC_BIOS_RAM_SIZE 0x800
836 #define ASC_BIOS_MIN_ADDR 0xC000
837 #define ASC_BIOS_MAX_ADDR 0xEC00
838 #define ASC_BIOS_BANK_SIZE 0x0400
839 #define ASC_MCODE_START_ADDR 0x0080
840 #define ASC_CFG0_HOST_INT_ON 0x0020
841 #define ASC_CFG0_BIOS_ON 0x0040
842 #define ASC_CFG0_VERA_BURST_ON 0x0080
843 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
844 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
845 #define ASC_CFG1_LRAM_8BITS_ON 0x0800
846 #define ASC_CFG_MSW_CLR_MASK 0x3080
847 #define CSW_TEST1 (ASC_CS_TYPE)0x8000
848 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
849 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
850 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
851 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
852 #define CSW_TEST2 (ASC_CS_TYPE)0x0400
853 #define CSW_TEST3 (ASC_CS_TYPE)0x0200
854 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
855 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
856 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
857 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
858 #define CSW_HALTED (ASC_CS_TYPE)0x0010
859 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
860 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
861 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
862 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
863 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
864 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
865 #define CIW_TEST1 (ASC_CS_TYPE)0x0200
866 #define CIW_TEST2 (ASC_CS_TYPE)0x0400
867 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
868 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
869 #define CC_CHIP_RESET (uchar)0x80
870 #define CC_SCSI_RESET (uchar)0x40
871 #define CC_HALT (uchar)0x20
872 #define CC_SINGLE_STEP (uchar)0x10
873 #define CC_DMA_ABLE (uchar)0x08
874 #define CC_TEST (uchar)0x04
875 #define CC_BANK_ONE (uchar)0x02
876 #define CC_DIAG (uchar)0x01
877 #define ASC_1000_ID0W 0x04C1
878 #define ASC_1000_ID0W_FIX 0x00C1
879 #define ASC_1000_ID1B 0x25
880 #define ASC_EISA_REV_IOP_MASK (0x0C83)
881 #define ASC_EISA_CFG_IOP_MASK (0x0C86)
882 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
883 #define INS_HALTINT (ushort)0x6281
884 #define INS_HALT (ushort)0x6280
885 #define INS_SINT (ushort)0x6200
886 #define INS_RFLAG_WTM (ushort)0x7380
887 #define ASC_MC_SAVE_CODE_WSIZE 0x500
888 #define ASC_MC_SAVE_DATA_WSIZE 0x40
890 typedef struct asc_mc_saved {
891 ushort data[ASC_MC_SAVE_DATA_WSIZE];
892 ushort code[ASC_MC_SAVE_CODE_WSIZE];
895 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
896 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
897 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
898 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
899 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
900 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
901 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
902 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
903 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
904 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
905 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
906 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
907 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
908 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
909 #define AscSynIndexToPeriod(index) (uchar)(asc_dvc->sdtr_period_tbl[ (index) ])
910 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
911 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
912 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
913 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
914 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
915 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
916 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
917 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
918 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
919 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
920 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
921 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
922 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
923 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
924 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
925 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
926 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
927 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
928 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
929 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
930 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
931 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
932 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
933 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
934 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
935 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
936 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
937 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
938 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
939 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
940 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
941 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
942 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
943 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
944 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
945 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
946 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
947 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
948 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
949 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
950 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
951 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
952 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
953 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
954 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
955 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
956 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
957 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
958 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
959 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
960 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
961 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
962 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
964 #define ADV_LIB_VERSION_MAJOR 5
965 #define ADV_LIB_VERSION_MINOR 14
968 * Define Adv Library required special types.
972 * Portable Data Types
974 * Any instance where a 32-bit long or pointer type is assumed
975 * for precision or HW defined structures, the following define
976 * types must be used. In Linux the char, short, and int types
977 * are all consistent at 8, 16, and 32 bits respectively. Pointers
978 * and long types are 64 bits on Alpha and UltraSPARC.
980 #define ADV_PADDR __u32 /* Physical address data type. */
981 #define ADV_VADDR __u32 /* Virtual address data type. */
982 #define ADV_DCNT __u32 /* Unsigned Data count type. */
983 #define ADV_SDCNT __s32 /* Signed Data count type. */
986 * These macros are used to convert a virtual address to a
987 * 32-bit value. This currently can be used on Linux Alpha
988 * which uses 64-bit virtual address but a 32-bit bus address.
989 * This is likely to break in the future, but doing this now
990 * will give us time to change the HW and FW to handle 64-bit
993 #define ADV_VADDR_TO_U32 virt_to_bus
994 #define ADV_U32_TO_VADDR bus_to_virt
996 #define AdvPortAddr void __iomem * /* Virtual memory address size */
999 * Define Adv Library required memory access macros.
1001 #define ADV_MEM_READB(addr) readb(addr)
1002 #define ADV_MEM_READW(addr) readw(addr)
1003 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
1004 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
1005 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
1007 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
1010 * Define total number of simultaneous maximum element scatter-gather
1011 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
1012 * maximum number of outstanding commands per wide host adapter. Each
1013 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
1014 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
1015 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
1016 * structures or 255 scatter-gather elements.
1019 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
1022 * Define Adv Library required maximum number of scatter-gather
1023 * elements per request.
1025 #define ADV_MAX_SG_LIST 255
1027 /* Number of SG blocks needed. */
1028 #define ADV_NUM_SG_BLOCK \
1029 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK)
1031 /* Total contiguous memory needed for SG blocks. */
1032 #define ADV_SG_TOTAL_MEM_SIZE \
1033 (sizeof(ADV_SG_BLOCK) * ADV_NUM_SG_BLOCK)
1035 #define ADV_PAGE_SIZE PAGE_SIZE
1037 #define ADV_NUM_PAGE_CROSSING \
1038 ((ADV_SG_TOTAL_MEM_SIZE + (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
1040 #define ADV_EEP_DVC_CFG_BEGIN (0x00)
1041 #define ADV_EEP_DVC_CFG_END (0x15)
1042 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
1043 #define ADV_EEP_MAX_WORD_ADDR (0x1E)
1045 #define ADV_EEP_DELAY_MS 100
1047 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
1048 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
1050 * For the ASC3550 Bit 13 is Termination Polarity control bit.
1051 * For later ICs Bit 13 controls whether the CIS (Card Information
1052 * Service Section) is loaded from EEPROM.
1054 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
1055 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
1059 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
1060 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
1061 * Function 0 will specify INT B.
1063 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
1064 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
1065 * Function 1 will specify INT A.
1067 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
1069 typedef struct adveep_3550_config {
1070 /* Word Offset, Description */
1072 ushort cfg_lsw; /* 00 power up initialization */
1073 /* bit 13 set - Term Polarity Control */
1074 /* bit 14 set - BIOS Enable */
1075 /* bit 15 set - Big Endian Mode */
1076 ushort cfg_msw; /* 01 unused */
1077 ushort disc_enable; /* 02 disconnect enable */
1078 ushort wdtr_able; /* 03 Wide DTR able */
1079 ushort sdtr_able; /* 04 Synchronous DTR able */
1080 ushort start_motor; /* 05 send start up motor */
1081 ushort tagqng_able; /* 06 tag queuing able */
1082 ushort bios_scan; /* 07 BIOS device control */
1083 ushort scam_tolerant; /* 08 no scam */
1085 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1086 uchar bios_boot_delay; /* power up wait */
1088 uchar scsi_reset_delay; /* 10 reset delay */
1089 uchar bios_id_lun; /* first boot device scsi id & lun */
1090 /* high nibble is lun */
1091 /* low nibble is scsi id */
1093 uchar termination; /* 11 0 - automatic */
1094 /* 1 - low off / high off */
1095 /* 2 - low off / high on */
1096 /* 3 - low on / high on */
1097 /* There is no low on / high off */
1099 uchar reserved1; /* reserved byte (not used) */
1101 ushort bios_ctrl; /* 12 BIOS control bits */
1102 /* bit 0 BIOS don't act as initiator. */
1103 /* bit 1 BIOS > 1 GB support */
1104 /* bit 2 BIOS > 2 Disk Support */
1105 /* bit 3 BIOS don't support removables */
1106 /* bit 4 BIOS support bootable CD */
1107 /* bit 5 BIOS scan enabled */
1108 /* bit 6 BIOS support multiple LUNs */
1109 /* bit 7 BIOS display of message */
1110 /* bit 8 SCAM disabled */
1111 /* bit 9 Reset SCSI bus during init. */
1113 /* bit 11 No verbose initialization. */
1114 /* bit 12 SCSI parity enabled */
1118 ushort ultra_able; /* 13 ULTRA speed able */
1119 ushort reserved2; /* 14 reserved */
1120 uchar max_host_qng; /* 15 maximum host queuing */
1121 uchar max_dvc_qng; /* maximum per device queuing */
1122 ushort dvc_cntl; /* 16 control bit for driver */
1123 ushort bug_fix; /* 17 control bit for bug fix */
1124 ushort serial_number_word1; /* 18 Board serial number word 1 */
1125 ushort serial_number_word2; /* 19 Board serial number word 2 */
1126 ushort serial_number_word3; /* 20 Board serial number word 3 */
1127 ushort check_sum; /* 21 EEP check sum */
1128 uchar oem_name[16]; /* 22 OEM name */
1129 ushort dvc_err_code; /* 30 last device driver error code */
1130 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1131 ushort adv_err_addr; /* 32 last uc error address */
1132 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1133 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1134 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1135 ushort num_of_err; /* 36 number of error */
1136 } ADVEEP_3550_CONFIG;
1138 typedef struct adveep_38C0800_config {
1139 /* Word Offset, Description */
1141 ushort cfg_lsw; /* 00 power up initialization */
1142 /* bit 13 set - Load CIS */
1143 /* bit 14 set - BIOS Enable */
1144 /* bit 15 set - Big Endian Mode */
1145 ushort cfg_msw; /* 01 unused */
1146 ushort disc_enable; /* 02 disconnect enable */
1147 ushort wdtr_able; /* 03 Wide DTR able */
1148 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1149 ushort start_motor; /* 05 send start up motor */
1150 ushort tagqng_able; /* 06 tag queuing able */
1151 ushort bios_scan; /* 07 BIOS device control */
1152 ushort scam_tolerant; /* 08 no scam */
1154 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1155 uchar bios_boot_delay; /* power up wait */
1157 uchar scsi_reset_delay; /* 10 reset delay */
1158 uchar bios_id_lun; /* first boot device scsi id & lun */
1159 /* high nibble is lun */
1160 /* low nibble is scsi id */
1162 uchar termination_se; /* 11 0 - automatic */
1163 /* 1 - low off / high off */
1164 /* 2 - low off / high on */
1165 /* 3 - low on / high on */
1166 /* There is no low on / high off */
1168 uchar termination_lvd; /* 11 0 - automatic */
1169 /* 1 - low off / high off */
1170 /* 2 - low off / high on */
1171 /* 3 - low on / high on */
1172 /* There is no low on / high off */
1174 ushort bios_ctrl; /* 12 BIOS control bits */
1175 /* bit 0 BIOS don't act as initiator. */
1176 /* bit 1 BIOS > 1 GB support */
1177 /* bit 2 BIOS > 2 Disk Support */
1178 /* bit 3 BIOS don't support removables */
1179 /* bit 4 BIOS support bootable CD */
1180 /* bit 5 BIOS scan enabled */
1181 /* bit 6 BIOS support multiple LUNs */
1182 /* bit 7 BIOS display of message */
1183 /* bit 8 SCAM disabled */
1184 /* bit 9 Reset SCSI bus during init. */
1186 /* bit 11 No verbose initialization. */
1187 /* bit 12 SCSI parity enabled */
1191 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1192 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1193 uchar max_host_qng; /* 15 maximum host queueing */
1194 uchar max_dvc_qng; /* maximum per device queuing */
1195 ushort dvc_cntl; /* 16 control bit for driver */
1196 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1197 ushort serial_number_word1; /* 18 Board serial number word 1 */
1198 ushort serial_number_word2; /* 19 Board serial number word 2 */
1199 ushort serial_number_word3; /* 20 Board serial number word 3 */
1200 ushort check_sum; /* 21 EEP check sum */
1201 uchar oem_name[16]; /* 22 OEM name */
1202 ushort dvc_err_code; /* 30 last device driver error code */
1203 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1204 ushort adv_err_addr; /* 32 last uc error address */
1205 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1206 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1207 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1208 ushort reserved36; /* 36 reserved */
1209 ushort reserved37; /* 37 reserved */
1210 ushort reserved38; /* 38 reserved */
1211 ushort reserved39; /* 39 reserved */
1212 ushort reserved40; /* 40 reserved */
1213 ushort reserved41; /* 41 reserved */
1214 ushort reserved42; /* 42 reserved */
1215 ushort reserved43; /* 43 reserved */
1216 ushort reserved44; /* 44 reserved */
1217 ushort reserved45; /* 45 reserved */
1218 ushort reserved46; /* 46 reserved */
1219 ushort reserved47; /* 47 reserved */
1220 ushort reserved48; /* 48 reserved */
1221 ushort reserved49; /* 49 reserved */
1222 ushort reserved50; /* 50 reserved */
1223 ushort reserved51; /* 51 reserved */
1224 ushort reserved52; /* 52 reserved */
1225 ushort reserved53; /* 53 reserved */
1226 ushort reserved54; /* 54 reserved */
1227 ushort reserved55; /* 55 reserved */
1228 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1229 ushort cisprt_msw; /* 57 CIS PTR MSW */
1230 ushort subsysvid; /* 58 SubSystem Vendor ID */
1231 ushort subsysid; /* 59 SubSystem ID */
1232 ushort reserved60; /* 60 reserved */
1233 ushort reserved61; /* 61 reserved */
1234 ushort reserved62; /* 62 reserved */
1235 ushort reserved63; /* 63 reserved */
1236 } ADVEEP_38C0800_CONFIG;
1238 typedef struct adveep_38C1600_config {
1239 /* Word Offset, Description */
1241 ushort cfg_lsw; /* 00 power up initialization */
1242 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
1243 /* clear - Func. 0 INTA, Func. 1 INTB */
1244 /* bit 13 set - Load CIS */
1245 /* bit 14 set - BIOS Enable */
1246 /* bit 15 set - Big Endian Mode */
1247 ushort cfg_msw; /* 01 unused */
1248 ushort disc_enable; /* 02 disconnect enable */
1249 ushort wdtr_able; /* 03 Wide DTR able */
1250 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1251 ushort start_motor; /* 05 send start up motor */
1252 ushort tagqng_able; /* 06 tag queuing able */
1253 ushort bios_scan; /* 07 BIOS device control */
1254 ushort scam_tolerant; /* 08 no scam */
1256 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1257 uchar bios_boot_delay; /* power up wait */
1259 uchar scsi_reset_delay; /* 10 reset delay */
1260 uchar bios_id_lun; /* first boot device scsi id & lun */
1261 /* high nibble is lun */
1262 /* low nibble is scsi id */
1264 uchar termination_se; /* 11 0 - automatic */
1265 /* 1 - low off / high off */
1266 /* 2 - low off / high on */
1267 /* 3 - low on / high on */
1268 /* There is no low on / high off */
1270 uchar termination_lvd; /* 11 0 - automatic */
1271 /* 1 - low off / high off */
1272 /* 2 - low off / high on */
1273 /* 3 - low on / high on */
1274 /* There is no low on / high off */
1276 ushort bios_ctrl; /* 12 BIOS control bits */
1277 /* bit 0 BIOS don't act as initiator. */
1278 /* bit 1 BIOS > 1 GB support */
1279 /* bit 2 BIOS > 2 Disk Support */
1280 /* bit 3 BIOS don't support removables */
1281 /* bit 4 BIOS support bootable CD */
1282 /* bit 5 BIOS scan enabled */
1283 /* bit 6 BIOS support multiple LUNs */
1284 /* bit 7 BIOS display of message */
1285 /* bit 8 SCAM disabled */
1286 /* bit 9 Reset SCSI bus during init. */
1287 /* bit 10 Basic Integrity Checking disabled */
1288 /* bit 11 No verbose initialization. */
1289 /* bit 12 SCSI parity enabled */
1290 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1293 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1294 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1295 uchar max_host_qng; /* 15 maximum host queueing */
1296 uchar max_dvc_qng; /* maximum per device queuing */
1297 ushort dvc_cntl; /* 16 control bit for driver */
1298 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1299 ushort serial_number_word1; /* 18 Board serial number word 1 */
1300 ushort serial_number_word2; /* 19 Board serial number word 2 */
1301 ushort serial_number_word3; /* 20 Board serial number word 3 */
1302 ushort check_sum; /* 21 EEP check sum */
1303 uchar oem_name[16]; /* 22 OEM name */
1304 ushort dvc_err_code; /* 30 last device driver error code */
1305 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1306 ushort adv_err_addr; /* 32 last uc error address */
1307 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1308 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1309 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1310 ushort reserved36; /* 36 reserved */
1311 ushort reserved37; /* 37 reserved */
1312 ushort reserved38; /* 38 reserved */
1313 ushort reserved39; /* 39 reserved */
1314 ushort reserved40; /* 40 reserved */
1315 ushort reserved41; /* 41 reserved */
1316 ushort reserved42; /* 42 reserved */
1317 ushort reserved43; /* 43 reserved */
1318 ushort reserved44; /* 44 reserved */
1319 ushort reserved45; /* 45 reserved */
1320 ushort reserved46; /* 46 reserved */
1321 ushort reserved47; /* 47 reserved */
1322 ushort reserved48; /* 48 reserved */
1323 ushort reserved49; /* 49 reserved */
1324 ushort reserved50; /* 50 reserved */
1325 ushort reserved51; /* 51 reserved */
1326 ushort reserved52; /* 52 reserved */
1327 ushort reserved53; /* 53 reserved */
1328 ushort reserved54; /* 54 reserved */
1329 ushort reserved55; /* 55 reserved */
1330 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1331 ushort cisprt_msw; /* 57 CIS PTR MSW */
1332 ushort subsysvid; /* 58 SubSystem Vendor ID */
1333 ushort subsysid; /* 59 SubSystem ID */
1334 ushort reserved60; /* 60 reserved */
1335 ushort reserved61; /* 61 reserved */
1336 ushort reserved62; /* 62 reserved */
1337 ushort reserved63; /* 63 reserved */
1338 } ADVEEP_38C1600_CONFIG;
1343 #define ASC_EEP_CMD_DONE 0x0200
1346 #define BIOS_CTRL_BIOS 0x0001
1347 #define BIOS_CTRL_EXTENDED_XLAT 0x0002
1348 #define BIOS_CTRL_GT_2_DISK 0x0004
1349 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
1350 #define BIOS_CTRL_BOOTABLE_CD 0x0010
1351 #define BIOS_CTRL_MULTIPLE_LUN 0x0040
1352 #define BIOS_CTRL_DISPLAY_MSG 0x0080
1353 #define BIOS_CTRL_NO_SCAM 0x0100
1354 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
1355 #define BIOS_CTRL_INIT_VERBOSE 0x0800
1356 #define BIOS_CTRL_SCSI_PARITY 0x1000
1357 #define BIOS_CTRL_AIPP_DIS 0x2000
1359 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
1361 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1364 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1365 * a special 16K Adv Library and Microcode version. After the issue is
1366 * resolved, should restore 32K support.
1368 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
1370 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1373 * Byte I/O register address from base of 'iop_base'.
1375 #define IOPB_INTR_STATUS_REG 0x00
1376 #define IOPB_CHIP_ID_1 0x01
1377 #define IOPB_INTR_ENABLES 0x02
1378 #define IOPB_CHIP_TYPE_REV 0x03
1379 #define IOPB_RES_ADDR_4 0x04
1380 #define IOPB_RES_ADDR_5 0x05
1381 #define IOPB_RAM_DATA 0x06
1382 #define IOPB_RES_ADDR_7 0x07
1383 #define IOPB_FLAG_REG 0x08
1384 #define IOPB_RES_ADDR_9 0x09
1385 #define IOPB_RISC_CSR 0x0A
1386 #define IOPB_RES_ADDR_B 0x0B
1387 #define IOPB_RES_ADDR_C 0x0C
1388 #define IOPB_RES_ADDR_D 0x0D
1389 #define IOPB_SOFT_OVER_WR 0x0E
1390 #define IOPB_RES_ADDR_F 0x0F
1391 #define IOPB_MEM_CFG 0x10
1392 #define IOPB_RES_ADDR_11 0x11
1393 #define IOPB_GPIO_DATA 0x12
1394 #define IOPB_RES_ADDR_13 0x13
1395 #define IOPB_FLASH_PAGE 0x14
1396 #define IOPB_RES_ADDR_15 0x15
1397 #define IOPB_GPIO_CNTL 0x16
1398 #define IOPB_RES_ADDR_17 0x17
1399 #define IOPB_FLASH_DATA 0x18
1400 #define IOPB_RES_ADDR_19 0x19
1401 #define IOPB_RES_ADDR_1A 0x1A
1402 #define IOPB_RES_ADDR_1B 0x1B
1403 #define IOPB_RES_ADDR_1C 0x1C
1404 #define IOPB_RES_ADDR_1D 0x1D
1405 #define IOPB_RES_ADDR_1E 0x1E
1406 #define IOPB_RES_ADDR_1F 0x1F
1407 #define IOPB_DMA_CFG0 0x20
1408 #define IOPB_DMA_CFG1 0x21
1409 #define IOPB_TICKLE 0x22
1410 #define IOPB_DMA_REG_WR 0x23
1411 #define IOPB_SDMA_STATUS 0x24
1412 #define IOPB_SCSI_BYTE_CNT 0x25
1413 #define IOPB_HOST_BYTE_CNT 0x26
1414 #define IOPB_BYTE_LEFT_TO_XFER 0x27
1415 #define IOPB_BYTE_TO_XFER_0 0x28
1416 #define IOPB_BYTE_TO_XFER_1 0x29
1417 #define IOPB_BYTE_TO_XFER_2 0x2A
1418 #define IOPB_BYTE_TO_XFER_3 0x2B
1419 #define IOPB_ACC_GRP 0x2C
1420 #define IOPB_RES_ADDR_2D 0x2D
1421 #define IOPB_DEV_ID 0x2E
1422 #define IOPB_RES_ADDR_2F 0x2F
1423 #define IOPB_SCSI_DATA 0x30
1424 #define IOPB_RES_ADDR_31 0x31
1425 #define IOPB_RES_ADDR_32 0x32
1426 #define IOPB_SCSI_DATA_HSHK 0x33
1427 #define IOPB_SCSI_CTRL 0x34
1428 #define IOPB_RES_ADDR_35 0x35
1429 #define IOPB_RES_ADDR_36 0x36
1430 #define IOPB_RES_ADDR_37 0x37
1431 #define IOPB_RAM_BIST 0x38
1432 #define IOPB_PLL_TEST 0x39
1433 #define IOPB_PCI_INT_CFG 0x3A
1434 #define IOPB_RES_ADDR_3B 0x3B
1435 #define IOPB_RFIFO_CNT 0x3C
1436 #define IOPB_RES_ADDR_3D 0x3D
1437 #define IOPB_RES_ADDR_3E 0x3E
1438 #define IOPB_RES_ADDR_3F 0x3F
1441 * Word I/O register address from base of 'iop_base'.
1443 #define IOPW_CHIP_ID_0 0x00 /* CID0 */
1444 #define IOPW_CTRL_REG 0x02 /* CC */
1445 #define IOPW_RAM_ADDR 0x04 /* LA */
1446 #define IOPW_RAM_DATA 0x06 /* LD */
1447 #define IOPW_RES_ADDR_08 0x08
1448 #define IOPW_RISC_CSR 0x0A /* CSR */
1449 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
1450 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
1451 #define IOPW_RES_ADDR_10 0x10
1452 #define IOPW_SEL_MASK 0x12 /* SM */
1453 #define IOPW_RES_ADDR_14 0x14
1454 #define IOPW_FLASH_ADDR 0x16 /* FA */
1455 #define IOPW_RES_ADDR_18 0x18
1456 #define IOPW_EE_CMD 0x1A /* EC */
1457 #define IOPW_EE_DATA 0x1C /* ED */
1458 #define IOPW_SFIFO_CNT 0x1E /* SFC */
1459 #define IOPW_RES_ADDR_20 0x20
1460 #define IOPW_Q_BASE 0x22 /* QB */
1461 #define IOPW_QP 0x24 /* QP */
1462 #define IOPW_IX 0x26 /* IX */
1463 #define IOPW_SP 0x28 /* SP */
1464 #define IOPW_PC 0x2A /* PC */
1465 #define IOPW_RES_ADDR_2C 0x2C
1466 #define IOPW_RES_ADDR_2E 0x2E
1467 #define IOPW_SCSI_DATA 0x30 /* SD */
1468 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
1469 #define IOPW_SCSI_CTRL 0x34 /* SC */
1470 #define IOPW_HSHK_CFG 0x36 /* HCFG */
1471 #define IOPW_SXFR_STATUS 0x36 /* SXS */
1472 #define IOPW_SXFR_CNTL 0x38 /* SXL */
1473 #define IOPW_SXFR_CNTH 0x3A /* SXH */
1474 #define IOPW_RES_ADDR_3C 0x3C
1475 #define IOPW_RFIFO_DATA 0x3E /* RFD */
1478 * Doubleword I/O register address from base of 'iop_base'.
1480 #define IOPDW_RES_ADDR_0 0x00
1481 #define IOPDW_RAM_DATA 0x04
1482 #define IOPDW_RES_ADDR_8 0x08
1483 #define IOPDW_RES_ADDR_C 0x0C
1484 #define IOPDW_RES_ADDR_10 0x10
1485 #define IOPDW_COMMA 0x14
1486 #define IOPDW_COMMB 0x18
1487 #define IOPDW_RES_ADDR_1C 0x1C
1488 #define IOPDW_SDMA_ADDR0 0x20
1489 #define IOPDW_SDMA_ADDR1 0x24
1490 #define IOPDW_SDMA_COUNT 0x28
1491 #define IOPDW_SDMA_ERROR 0x2C
1492 #define IOPDW_RDMA_ADDR0 0x30
1493 #define IOPDW_RDMA_ADDR1 0x34
1494 #define IOPDW_RDMA_COUNT 0x38
1495 #define IOPDW_RDMA_ERROR 0x3C
1497 #define ADV_CHIP_ID_BYTE 0x25
1498 #define ADV_CHIP_ID_WORD 0x04C1
1500 #define ADV_INTR_ENABLE_HOST_INTR 0x01
1501 #define ADV_INTR_ENABLE_SEL_INTR 0x02
1502 #define ADV_INTR_ENABLE_DPR_INTR 0x04
1503 #define ADV_INTR_ENABLE_RTA_INTR 0x08
1504 #define ADV_INTR_ENABLE_RMA_INTR 0x10
1505 #define ADV_INTR_ENABLE_RST_INTR 0x20
1506 #define ADV_INTR_ENABLE_DPE_INTR 0x40
1507 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
1509 #define ADV_INTR_STATUS_INTRA 0x01
1510 #define ADV_INTR_STATUS_INTRB 0x02
1511 #define ADV_INTR_STATUS_INTRC 0x04
1513 #define ADV_RISC_CSR_STOP (0x0000)
1514 #define ADV_RISC_TEST_COND (0x2000)
1515 #define ADV_RISC_CSR_RUN (0x4000)
1516 #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
1518 #define ADV_CTRL_REG_HOST_INTR 0x0100
1519 #define ADV_CTRL_REG_SEL_INTR 0x0200
1520 #define ADV_CTRL_REG_DPR_INTR 0x0400
1521 #define ADV_CTRL_REG_RTA_INTR 0x0800
1522 #define ADV_CTRL_REG_RMA_INTR 0x1000
1523 #define ADV_CTRL_REG_RES_BIT14 0x2000
1524 #define ADV_CTRL_REG_DPE_INTR 0x4000
1525 #define ADV_CTRL_REG_POWER_DONE 0x8000
1526 #define ADV_CTRL_REG_ANY_INTR 0xFF00
1528 #define ADV_CTRL_REG_CMD_RESET 0x00C6
1529 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
1530 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
1531 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
1532 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
1534 #define ADV_TICKLE_NOP 0x00
1535 #define ADV_TICKLE_A 0x01
1536 #define ADV_TICKLE_B 0x02
1537 #define ADV_TICKLE_C 0x03
1539 #define AdvIsIntPending(port) \
1540 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1543 * SCSI_CFG0 Register bit definitions
1545 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
1546 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
1547 #define EVEN_PARITY 0x1000 /* Select Even Parity */
1548 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1549 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
1550 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
1551 #define SCAM_EN 0x0080 /* Enable SCAM selection */
1552 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1553 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1554 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
1555 #define OUR_ID 0x000F /* SCSI ID */
1558 * SCSI_CFG1 Register bit definitions
1560 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
1561 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1562 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
1563 #define FILTER_SEL 0x0C00 /* Filter Period Selection */
1564 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
1565 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1566 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1567 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
1568 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
1569 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
1570 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
1571 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
1572 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
1573 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
1574 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
1577 * Addendum for ASC-38C0800 Chip
1579 * The ASC-38C1600 Chip uses the same definitions except that the
1580 * bus mode override bits [12:10] have been moved to byte register
1581 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1582 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1583 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1584 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1585 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1587 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
1588 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
1589 #define HVD 0x1000 /* HVD Device Detect */
1590 #define LVD 0x0800 /* LVD Device Detect */
1591 #define SE 0x0400 /* SE Device Detect */
1592 #define TERM_LVD 0x00C0 /* LVD Termination Bits */
1593 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
1594 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
1595 #define TERM_SE 0x0030 /* SE Termination Bits */
1596 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
1597 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
1598 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
1599 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
1600 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
1601 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
1602 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
1603 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
1605 #define CABLE_ILLEGAL_A 0x7
1606 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
1608 #define CABLE_ILLEGAL_B 0xB
1609 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
1612 * MEM_CFG Register bit definitions
1614 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
1615 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
1616 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
1617 #define RAM_SZ_2KB 0x00 /* 2 KB */
1618 #define RAM_SZ_4KB 0x04 /* 4 KB */
1619 #define RAM_SZ_8KB 0x08 /* 8 KB */
1620 #define RAM_SZ_16KB 0x0C /* 16 KB */
1621 #define RAM_SZ_32KB 0x10 /* 32 KB */
1622 #define RAM_SZ_64KB 0x14 /* 64 KB */
1625 * DMA_CFG0 Register bit definitions
1627 * This register is only accessible to the host.
1629 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
1630 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
1631 #define FIFO_THRESH_16B 0x00 /* 16 bytes */
1632 #define FIFO_THRESH_32B 0x20 /* 32 bytes */
1633 #define FIFO_THRESH_48B 0x30 /* 48 bytes */
1634 #define FIFO_THRESH_64B 0x40 /* 64 bytes */
1635 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
1636 #define FIFO_THRESH_96B 0x60 /* 96 bytes */
1637 #define FIFO_THRESH_112B 0x70 /* 112 bytes */
1638 #define START_CTL 0x0C /* DMA start conditions */
1639 #define START_CTL_TH 0x00 /* Wait threshold level (default) */
1640 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
1641 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
1642 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
1643 #define READ_CMD 0x03 /* Memory Read Method */
1644 #define READ_CMD_MR 0x00 /* Memory Read */
1645 #define READ_CMD_MRL 0x02 /* Memory Read Long */
1646 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
1649 * ASC-38C0800 RAM BIST Register bit definitions
1651 #define RAM_TEST_MODE 0x80
1652 #define PRE_TEST_MODE 0x40
1653 #define NORMAL_MODE 0x00
1654 #define RAM_TEST_DONE 0x10
1655 #define RAM_TEST_STATUS 0x0F
1656 #define RAM_TEST_HOST_ERROR 0x08
1657 #define RAM_TEST_INTRAM_ERROR 0x04
1658 #define RAM_TEST_RISC_ERROR 0x02
1659 #define RAM_TEST_SCSI_ERROR 0x01
1660 #define RAM_TEST_SUCCESS 0x00
1661 #define PRE_TEST_VALUE 0x05
1662 #define NORMAL_VALUE 0x00
1665 * ASC38C1600 Definitions
1667 * IOPB_PCI_INT_CFG Bit Field Definitions
1670 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
1673 * Bit 1 can be set to change the interrupt for the Function to operate in
1674 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1675 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1676 * mode, otherwise the operating mode is undefined.
1678 #define TOTEMPOLE 0x02
1681 * Bit 0 can be used to change the Int Pin for the Function. The value is
1682 * 0 by default for both Functions with Function 0 using INT A and Function
1683 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1686 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1687 * value specified in the PCI Configuration Space.
1692 * Adv Library Status Definitions
1696 #define ADV_SUCCESS 1
1698 #define ADV_ERROR (-1)
1701 * ADV_DVC_VAR 'warn_code' values
1703 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
1704 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
1705 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
1706 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
1708 #define ADV_MAX_TID 15 /* max. target identifier */
1709 #define ADV_MAX_LUN 7 /* max. logical unit number */
1712 * Error code values are set in ADV_DVC_VAR 'err_code'.
1714 #define ASC_IERR_WRITE_EEPROM 0x0001 /* write EEPROM error */
1715 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
1716 #define ASC_IERR_NO_CARRIER 0x0004 /* No more carrier memory. */
1717 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
1718 #define ASC_IERR_CHIP_VERSION 0x0040 /* wrong chip version */
1719 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
1720 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD attached to LVD connector. */
1721 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
1722 #define ASC_IERR_ILLEGAL_CONNECTION 0x0400 /* Illegal cable connection */
1723 #define ASC_IERR_SINGLE_END_DEVICE 0x0800 /* Single-end used w/differential */
1724 #define ASC_IERR_REVERSED_CABLE 0x1000 /* Narrow flat cable reversed */
1725 #define ASC_IERR_BIST_PRE_TEST 0x2000 /* BIST pre-test error */
1726 #define ASC_IERR_BIST_RAM_TEST 0x4000 /* BIST RAM test error */
1727 #define ASC_IERR_BAD_CHIPTYPE 0x8000 /* Invalid 'chip_type' setting. */
1730 * Fixed locations of microcode operating variables.
1732 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
1733 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
1734 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
1735 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
1736 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
1737 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
1738 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
1739 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
1740 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
1741 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
1742 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
1743 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
1744 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
1745 #define ASC_MC_CHIP_TYPE 0x009A
1746 #define ASC_MC_INTRB_CODE 0x009B
1747 #define ASC_MC_WDTR_ABLE 0x009C
1748 #define ASC_MC_SDTR_ABLE 0x009E
1749 #define ASC_MC_TAGQNG_ABLE 0x00A0
1750 #define ASC_MC_DISC_ENABLE 0x00A2
1751 #define ASC_MC_IDLE_CMD_STATUS 0x00A4
1752 #define ASC_MC_IDLE_CMD 0x00A6
1753 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
1754 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
1755 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
1756 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
1757 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
1758 #define ASC_MC_SDTR_DONE 0x00B6
1759 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
1760 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
1761 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
1762 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
1763 #define ASC_MC_WDTR_DONE 0x0124
1764 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
1765 #define ASC_MC_ICQ 0x0160
1766 #define ASC_MC_IRQ 0x0164
1767 #define ASC_MC_PPR_ABLE 0x017A
1770 * BIOS LRAM variable absolute offsets.
1772 #define BIOS_CODESEG 0x54
1773 #define BIOS_CODELEN 0x56
1774 #define BIOS_SIGNATURE 0x58
1775 #define BIOS_VERSION 0x5A
1778 * Microcode Control Flags
1780 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1781 * and handled by the microcode.
1783 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
1784 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
1787 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1789 #define HSHK_CFG_WIDE_XFR 0x8000
1790 #define HSHK_CFG_RATE 0x0F00
1791 #define HSHK_CFG_OFFSET 0x001F
1793 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
1794 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
1795 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
1796 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
1798 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1799 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
1800 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1801 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
1802 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1804 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
1805 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
1806 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
1807 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
1808 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
1810 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1811 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1813 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
1814 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
1817 * All fields here are accessed by the board microcode and need to be
1820 typedef struct adv_carr_t {
1821 ADV_VADDR carr_va; /* Carrier Virtual Address */
1822 ADV_PADDR carr_pa; /* Carrier Physical Address */
1823 ADV_VADDR areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
1825 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
1827 * next_vpa [3:1] Reserved Bits
1828 * next_vpa [0] Done Flag set in Response Queue.
1834 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1836 #define ASC_NEXT_VPA_MASK 0xFFFFFFF0
1838 #define ASC_RQ_DONE 0x00000001
1839 #define ASC_RQ_GOOD 0x00000002
1840 #define ASC_CQ_STOPPER 0x00000000
1842 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1844 #define ADV_CARRIER_NUM_PAGE_CROSSING \
1845 (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + \
1846 (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
1848 #define ADV_CARRIER_BUFSIZE \
1849 ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
1852 * ASC_SCSI_REQ_Q 'a_flag' definitions
1854 * The Adv Library should limit use to the lower nibble (4 bits) of
1855 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1857 #define ADV_POLL_REQUEST 0x01 /* poll for request completion */
1858 #define ADV_SCSIQ_DONE 0x02 /* request done */
1859 #define ADV_DONT_RETRY 0x08 /* don't do retry */
1861 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
1862 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
1863 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
1866 * Adapter temporary configuration structure
1868 * This structure can be discarded after initialization. Don't add
1869 * fields here needed after initialization.
1871 * Field naming convention:
1873 * *_enable indicates the field enables or disables a feature. The
1874 * value of the field is never reset.
1876 typedef struct adv_dvc_cfg {
1877 ushort disc_enable; /* enable disconnection */
1878 uchar chip_version; /* chip version */
1879 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1880 ushort lib_version; /* Adv Library version number */
1881 ushort control_flag; /* Microcode Control Flag */
1882 ushort mcode_date; /* Microcode date */
1883 ushort mcode_version; /* Microcode version */
1884 ushort serial1; /* EEPROM serial number word 1 */
1885 ushort serial2; /* EEPROM serial number word 2 */
1886 ushort serial3; /* EEPROM serial number word 3 */
1890 struct adv_scsi_req_q;
1893 * Adapter operation variable structure.
1895 * One structure is required per host adapter.
1897 * Field naming convention:
1899 * *_able indicates both whether a feature should be enabled or disabled
1900 * and whether a device isi capable of the feature. At initialization
1901 * this field may be set, but later if a device is found to be incapable
1902 * of the feature, the field is cleared.
1904 typedef struct adv_dvc_var {
1905 AdvPortAddr iop_base; /* I/O port address */
1906 ushort err_code; /* fatal error code */
1907 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
1908 ushort wdtr_able; /* try WDTR for a device */
1909 ushort sdtr_able; /* try SDTR for a device */
1910 ushort ultra_able; /* try SDTR Ultra speed for a device */
1911 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
1912 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
1913 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
1914 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
1915 ushort tagqng_able; /* try tagged queuing with a device */
1916 ushort ppr_able; /* PPR message capable per TID bitmask. */
1917 uchar max_dvc_qng; /* maximum number of tagged commands per device */
1918 ushort start_motor; /* start motor command allowed */
1919 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
1920 uchar chip_no; /* should be assigned by caller */
1921 uchar max_host_qng; /* maximum number of Q'ed command allowed */
1922 uchar irq_no; /* IRQ number */
1923 ushort no_scam; /* scam_tolerant of EEPROM */
1924 struct asc_board *drv_ptr; /* driver pointer to private structure */
1925 uchar chip_scsi_id; /* chip SCSI target ID */
1927 uchar bist_err_code;
1928 ADV_CARR_T *carrier_buf;
1929 ADV_CARR_T *carr_freelist; /* Carrier free list. */
1930 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
1931 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
1932 ushort carr_pending_cnt; /* Count of pending carriers. */
1934 * Note: The following fields will not be used after initialization. The
1935 * driver may discard the buffer after initialization is done.
1937 ADV_DVC_CFG *cfg; /* temporary configuration structure */
1940 #define NO_OF_SG_PER_BLOCK 15
1942 typedef struct asc_sg_block {
1946 uchar sg_cnt; /* Valid entries in block. */
1947 ADV_PADDR sg_ptr; /* Pointer to next sg block. */
1949 ADV_PADDR sg_addr; /* SG element address. */
1950 ADV_DCNT sg_count; /* SG element count. */
1951 } sg_list[NO_OF_SG_PER_BLOCK];
1955 * ADV_SCSI_REQ_Q - microcode request structure
1957 * All fields in this structure up to byte 60 are used by the microcode.
1958 * The microcode makes assumptions about the size and ordering of fields
1959 * in this structure. Do not change the structure definition here without
1960 * coordinating the change with the microcode.
1962 * All fields accessed by microcode must be maintained in little_endian
1965 typedef struct adv_scsi_req_q {
1966 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
1968 uchar target_id; /* Device target identifier. */
1969 uchar target_lun; /* Device target logical unit number. */
1970 ADV_PADDR data_addr; /* Data buffer physical address. */
1971 ADV_DCNT data_cnt; /* Data count. Ucode sets to residual. */
1972 ADV_PADDR sense_addr;
1976 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
1978 uchar done_status; /* Completion status. */
1979 uchar scsi_status; /* SCSI status byte. */
1980 uchar host_status; /* Ucode host status. */
1981 uchar sg_working_ix;
1982 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
1983 ADV_PADDR sg_real_addr; /* SG list physical address. */
1984 ADV_PADDR scsiq_rptr;
1985 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
1986 ADV_VADDR scsiq_ptr;
1989 * End of microcode structure - 60 bytes. The rest of the structure
1990 * is used by the Adv Library and ignored by the microcode.
1993 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
1994 char *vdata_addr; /* Data buffer virtual address. */
1996 uchar pad[2]; /* Pad out to a word boundary. */
2000 * Microcode idle loop commands
2002 #define IDLE_CMD_COMPLETED 0
2003 #define IDLE_CMD_STOP_CHIP 0x0001
2004 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
2005 #define IDLE_CMD_SEND_INT 0x0004
2006 #define IDLE_CMD_ABORT 0x0008
2007 #define IDLE_CMD_DEVICE_RESET 0x0010
2008 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
2009 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
2010 #define IDLE_CMD_SCSIREQ 0x0080
2012 #define IDLE_CMD_STATUS_SUCCESS 0x0001
2013 #define IDLE_CMD_STATUS_FAILURE 0x0002
2016 * AdvSendIdleCmd() flag definitions.
2018 #define ADV_NOWAIT 0x01
2021 * Wait loop time out values.
2023 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
2024 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
2025 #define SCSI_MAX_RETRY 10 /* retry count */
2027 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
2028 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
2029 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
2030 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
2032 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
2034 /* Read byte from a register. */
2035 #define AdvReadByteRegister(iop_base, reg_off) \
2036 (ADV_MEM_READB((iop_base) + (reg_off)))
2038 /* Write byte to a register. */
2039 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
2040 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
2042 /* Read word (2 bytes) from a register. */
2043 #define AdvReadWordRegister(iop_base, reg_off) \
2044 (ADV_MEM_READW((iop_base) + (reg_off)))
2046 /* Write word (2 bytes) to a register. */
2047 #define AdvWriteWordRegister(iop_base, reg_off, word) \
2048 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
2050 /* Write dword (4 bytes) to a register. */
2051 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
2052 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
2054 /* Read byte from LRAM. */
2055 #define AdvReadByteLram(iop_base, addr, byte) \
2057 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2058 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
2061 /* Write byte to LRAM. */
2062 #define AdvWriteByteLram(iop_base, addr, byte) \
2063 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2064 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
2066 /* Read word (2 bytes) from LRAM. */
2067 #define AdvReadWordLram(iop_base, addr, word) \
2069 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2070 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
2073 /* Write word (2 bytes) to LRAM. */
2074 #define AdvWriteWordLram(iop_base, addr, word) \
2075 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2076 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2078 /* Write little-endian double word (4 bytes) to LRAM */
2079 /* Because of unspecified C language ordering don't use auto-increment. */
2080 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
2081 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2082 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2083 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
2084 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
2085 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2086 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2088 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
2089 #define AdvReadWordAutoIncLram(iop_base) \
2090 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2092 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
2093 #define AdvWriteWordAutoIncLram(iop_base, word) \
2094 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2097 * Define macro to check for Condor signature.
2099 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2100 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2102 #define AdvFindSignature(iop_base) \
2103 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2104 ADV_CHIP_ID_BYTE) && \
2105 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2106 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
2109 * Define macro to Return the version number of the chip at 'iop_base'.
2111 * The second parameter 'bus_type' is currently unused.
2113 #define AdvGetChipVersion(iop_base, bus_type) \
2114 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2117 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
2118 * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
2120 * If the request has not yet been sent to the device it will simply be
2121 * aborted from RISC memory. If the request is disconnected it will be
2122 * aborted on reselection by sending an Abort Message to the target ID.
2125 * ADV_TRUE(1) - Queue was successfully aborted.
2126 * ADV_FALSE(0) - Queue was not found on the active queue list.
2128 #define AdvAbortQueue(asc_dvc, scsiq) \
2129 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2133 * Send a Bus Device Reset Message to the specified target ID.
2135 * All outstanding commands will be purged if sending the
2136 * Bus Device Reset Message is successful.
2139 * ADV_TRUE(1) - All requests on the target are purged.
2140 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2143 #define AdvResetDevice(asc_dvc, target_id) \
2144 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2145 (ADV_DCNT) (target_id))
2148 * SCSI Wide Type definition.
2150 #define ADV_SCSI_BIT_ID_TYPE ushort
2153 * AdvInitScsiTarget() 'cntl_flag' options.
2155 #define ADV_SCAN_LUN 0x01
2156 #define ADV_CAPINFO_NOLUN 0x02
2159 * Convert target id to target id bit mask.
2161 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
2164 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2167 #define QD_NO_STATUS 0x00 /* Request not completed yet. */
2168 #define QD_NO_ERROR 0x01
2169 #define QD_ABORTED_BY_HOST 0x02
2170 #define QD_WITH_ERROR 0x04
2172 #define QHSTA_NO_ERROR 0x00
2173 #define QHSTA_M_SEL_TIMEOUT 0x11
2174 #define QHSTA_M_DATA_OVER_RUN 0x12
2175 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2176 #define QHSTA_M_QUEUE_ABORTED 0x15
2177 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
2178 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
2179 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
2180 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
2181 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
2182 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
2183 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
2184 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2185 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
2186 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
2187 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
2188 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
2189 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
2190 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
2191 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
2192 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
2193 #define QHSTA_M_WTM_TIMEOUT 0x41
2194 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
2195 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
2196 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2197 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
2198 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
2199 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
2202 * DvcGetPhyAddr() flag arguments
2204 #define ADV_IS_SCSIQ_FLAG 0x01 /* 'addr' is ASC_SCSI_REQ_Q pointer */
2205 #define ADV_ASCGETSGLIST_VADDR 0x02 /* 'addr' is AscGetSGList() virtual addr */
2206 #define ADV_IS_SENSE_FLAG 0x04 /* 'addr' is sense virtual pointer */
2207 #define ADV_IS_DATA_FLAG 0x08 /* 'addr' is data virtual pointer */
2208 #define ADV_IS_SGLIST_FLAG 0x10 /* 'addr' is sglist virtual pointer */
2209 #define ADV_IS_CARRIER_FLAG 0x20 /* 'addr' is ADV_CARR_T pointer */
2211 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
2212 #define ADV_8BALIGN(addr) (((ulong) (addr) + 0x7) & ~0x7)
2213 #define ADV_16BALIGN(addr) (((ulong) (addr) + 0xF) & ~0xF)
2214 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
2217 * Total contiguous memory needed for driver SG blocks.
2219 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2220 * number of scatter-gather elements the driver supports in a
2224 #define ADV_SG_LIST_MAX_BYTE_SIZE \
2225 (sizeof(ADV_SG_BLOCK) * \
2226 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2228 /* Reference Scsi_Host hostdata */
2229 #define ASC_BOARDP(host) ((asc_board_t *) &((host)->hostdata))
2231 /* asc_board_t flags */
2232 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
2234 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2235 #define ASC_WIDE_BOARD(boardp) ((boardp)->flags & ASC_IS_WIDE_BOARD)
2237 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
2239 #define ASC_INFO_SIZE 128 /* advansys_info() line size */
2241 #ifdef CONFIG_PROC_FS
2242 /* /proc/scsi/advansys/[0...] related definitions */
2243 #define ASC_PRTBUF_SIZE 2048
2244 #define ASC_PRTLINE_SIZE 160
2246 #define ASC_PRT_NEXT() \
2250 if (leftlen == 0) { \
2255 #endif /* CONFIG_PROC_FS */
2257 /* Asc Library return codes */
2260 #define ASC_NOERROR 1
2262 #define ASC_ERROR (-1)
2264 /* struct scsi_cmnd function return codes */
2265 #define STATUS_BYTE(byte) (byte)
2266 #define MSG_BYTE(byte) ((byte) << 8)
2267 #define HOST_BYTE(byte) ((byte) << 16)
2268 #define DRIVER_BYTE(byte) ((byte) << 24)
2270 #ifndef ADVANSYS_STATS
2271 #define ASC_STATS(shost, counter)
2272 #define ASC_STATS_ADD(shost, counter, count)
2273 #else /* ADVANSYS_STATS */
2274 #define ASC_STATS(shost, counter) \
2275 (ASC_BOARDP(shost)->asc_stats.counter++)
2277 #define ASC_STATS_ADD(shost, counter, count) \
2278 (ASC_BOARDP(shost)->asc_stats.counter += (count))
2279 #endif /* ADVANSYS_STATS */
2281 #define ASC_CEILING(val, unit) (((val) + ((unit) - 1))/(unit))
2283 /* If the result wraps when calculating tenths, return 0. */
2284 #define ASC_TENTHS(num, den) \
2285 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2286 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2289 * Display a message to the console.
2291 #define ASC_PRINT(s) \
2293 printk("advansys: "); \
2297 #define ASC_PRINT1(s, a1) \
2299 printk("advansys: "); \
2300 printk((s), (a1)); \
2303 #define ASC_PRINT2(s, a1, a2) \
2305 printk("advansys: "); \
2306 printk((s), (a1), (a2)); \
2309 #define ASC_PRINT3(s, a1, a2, a3) \
2311 printk("advansys: "); \
2312 printk((s), (a1), (a2), (a3)); \
2315 #define ASC_PRINT4(s, a1, a2, a3, a4) \
2317 printk("advansys: "); \
2318 printk((s), (a1), (a2), (a3), (a4)); \
2321 #ifndef ADVANSYS_DEBUG
2323 #define ASC_DBG(lvl, s)
2324 #define ASC_DBG1(lvl, s, a1)
2325 #define ASC_DBG2(lvl, s, a1, a2)
2326 #define ASC_DBG3(lvl, s, a1, a2, a3)
2327 #define ASC_DBG4(lvl, s, a1, a2, a3, a4)
2328 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2329 #define ASC_DBG_PRT_SCSI_CMND(lvl, s)
2330 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2331 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2332 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2333 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2334 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
2335 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
2336 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
2337 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2339 #else /* ADVANSYS_DEBUG */
2342 * Debugging Message Levels:
2344 * 1: High-Level Tracing
2345 * 2-N: Verbose Tracing
2348 #define ASC_DBG(lvl, s) \
2350 if (asc_dbglvl >= (lvl)) { \
2355 #define ASC_DBG1(lvl, s, a1) \
2357 if (asc_dbglvl >= (lvl)) { \
2358 printk((s), (a1)); \
2362 #define ASC_DBG2(lvl, s, a1, a2) \
2364 if (asc_dbglvl >= (lvl)) { \
2365 printk((s), (a1), (a2)); \
2369 #define ASC_DBG3(lvl, s, a1, a2, a3) \
2371 if (asc_dbglvl >= (lvl)) { \
2372 printk((s), (a1), (a2), (a3)); \
2376 #define ASC_DBG4(lvl, s, a1, a2, a3, a4) \
2378 if (asc_dbglvl >= (lvl)) { \
2379 printk((s), (a1), (a2), (a3), (a4)); \
2383 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2385 if (asc_dbglvl >= (lvl)) { \
2386 asc_prt_scsi_host(s); \
2390 #define ASC_DBG_PRT_SCSI_CMND(lvl, s) \
2392 if (asc_dbglvl >= (lvl)) { \
2393 asc_prt_scsi_cmnd(s); \
2397 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2399 if (asc_dbglvl >= (lvl)) { \
2400 asc_prt_asc_scsi_q(scsiqp); \
2404 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2406 if (asc_dbglvl >= (lvl)) { \
2407 asc_prt_asc_qdone_info(qdone); \
2411 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2413 if (asc_dbglvl >= (lvl)) { \
2414 asc_prt_adv_scsi_req_q(scsiqp); \
2418 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2420 if (asc_dbglvl >= (lvl)) { \
2421 asc_prt_hex((name), (start), (length)); \
2425 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2426 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2428 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2429 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2431 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2432 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2433 #endif /* ADVANSYS_DEBUG */
2435 #ifdef ADVANSYS_STATS
2437 /* Per board statistics structure */
2439 /* Driver Entrypoint Statistics */
2440 ADV_DCNT queuecommand; /* # calls to advansys_queuecommand() */
2441 ADV_DCNT reset; /* # calls to advansys_eh_bus_reset() */
2442 ADV_DCNT biosparam; /* # calls to advansys_biosparam() */
2443 ADV_DCNT interrupt; /* # advansys_interrupt() calls */
2444 ADV_DCNT callback; /* # calls to asc/adv_isr_callback() */
2445 ADV_DCNT done; /* # calls to request's scsi_done function */
2446 ADV_DCNT build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
2447 ADV_DCNT adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
2448 ADV_DCNT adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
2449 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2450 ADV_DCNT exe_noerror; /* # ASC_NOERROR returns. */
2451 ADV_DCNT exe_busy; /* # ASC_BUSY returns. */
2452 ADV_DCNT exe_error; /* # ASC_ERROR returns. */
2453 ADV_DCNT exe_unknown; /* # unknown returns. */
2454 /* Data Transfer Statistics */
2455 ADV_DCNT cont_cnt; /* # non-scatter-gather I/O requests received */
2456 ADV_DCNT cont_xfer; /* # contiguous transfer 512-bytes */
2457 ADV_DCNT sg_cnt; /* # scatter-gather I/O requests received */
2458 ADV_DCNT sg_elem; /* # scatter-gather elements */
2459 ADV_DCNT sg_xfer; /* # scatter-gather transfer 512-bytes */
2461 #endif /* ADVANSYS_STATS */
2464 * Adv Library Request Structures
2466 * The following two structures are used to process Wide Board requests.
2468 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
2469 * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
2470 * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
2471 * Mid-Level SCSI request structure.
2473 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
2474 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
2475 * up to 255 scatter-gather elements may be used per request or
2478 * Both structures must be 32 byte aligned.
2480 typedef struct adv_sgblk {
2481 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
2482 uchar align[32]; /* Sgblock structure padding. */
2483 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
2486 typedef struct adv_req {
2487 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
2488 uchar align[32]; /* Request structure padding. */
2489 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
2490 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
2491 struct adv_req *next_reqp; /* Next Request Structure. */
2495 * Structure allocated for each board.
2497 * This structure is allocated by scsi_host_alloc() at the end
2498 * of the 'Scsi_Host' structure starting at the 'hostdata'
2499 * field. It is guaranteed to be allocated from DMA-able memory.
2501 typedef struct asc_board {
2503 int id; /* Board Id */
2504 uint flags; /* Board flags */
2506 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
2507 ADV_DVC_VAR adv_dvc_var; /* Wide board */
2510 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
2511 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
2513 ushort asc_n_io_port; /* Number I/O ports. */
2514 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
2515 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2516 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
2517 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2519 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
2520 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
2521 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
2522 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
2524 ulong last_reset; /* Saved last reset time */
2525 spinlock_t lock; /* Board spinlock */
2526 /* /proc/scsi/advansys/[0...] */
2527 char *prtbuf; /* /proc print buffer */
2528 #ifdef ADVANSYS_STATS
2529 struct asc_stats asc_stats; /* Board statistics */
2530 #endif /* ADVANSYS_STATS */
2532 * The following fields are used only for Narrow Boards.
2534 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
2536 * The following fields are used only for Wide Boards.
2538 void __iomem *ioremap_addr; /* I/O Memory remap address. */
2539 ushort ioport; /* I/O Port address. */
2540 ADV_CARR_T *carrp; /* ADV_CARR_T memory block. */
2541 adv_req_t *orig_reqp; /* adv_req_t memory block. */
2542 adv_req_t *adv_reqp; /* Request structures. */
2543 adv_sgblk_t *adv_sgblkp; /* Scatter-gather structures. */
2544 ushort bios_signature; /* BIOS Signature. */
2545 ushort bios_version; /* BIOS Version. */
2546 ushort bios_codeseg; /* BIOS Code Segment. */
2547 ushort bios_codelen; /* BIOS Code Segment Length. */
2550 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2551 dvc_var.adv_dvc_var)
2552 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2554 /* Number of boards detected in system. */
2555 static int asc_board_count;
2557 /* Overrun buffer used by all narrow boards. */
2558 static uchar overrun_buf[ASC_OVERRUN_BSIZE] = { 0 };
2560 #ifdef ADVANSYS_DEBUG
2561 static int asc_dbglvl = 3;
2564 * asc_prt_scsi_host()
2566 static void asc_prt_scsi_host(struct Scsi_Host *s)
2568 asc_board_t *boardp;
2570 boardp = ASC_BOARDP(s);
2572 printk("Scsi_Host at addr 0x%lx\n", (ulong)s);
2573 printk(" host_busy %u, host_no %d, last_reset %d,\n",
2574 s->host_busy, s->host_no, (unsigned)s->last_reset);
2576 printk(" base 0x%lx, io_port 0x%lx, irq 0x%x,\n",
2577 (ulong)s->base, (ulong)s->io_port, s->irq);
2579 printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2580 s->dma_channel, s->this_id, s->can_queue);
2582 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2583 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
2585 if (ASC_NARROW_BOARD(boardp)) {
2586 asc_prt_asc_dvc_var(&ASC_BOARDP(s)->dvc_var.asc_dvc_var);
2587 asc_prt_asc_dvc_cfg(&ASC_BOARDP(s)->dvc_cfg.asc_dvc_cfg);
2589 asc_prt_adv_dvc_var(&ASC_BOARDP(s)->dvc_var.adv_dvc_var);
2590 asc_prt_adv_dvc_cfg(&ASC_BOARDP(s)->dvc_cfg.adv_dvc_cfg);
2595 * asc_prt_scsi_cmnd()
2597 static void asc_prt_scsi_cmnd(struct scsi_cmnd *s)
2599 printk("struct scsi_cmnd at addr 0x%lx\n", (ulong)s);
2601 printk(" host 0x%lx, device 0x%lx, target %u, lun %u, channel %u,\n",
2602 (ulong)s->device->host, (ulong)s->device, s->device->id,
2603 s->device->lun, s->device->channel);
2605 asc_prt_hex(" CDB", s->cmnd, s->cmd_len);
2607 printk("sc_data_direction %u, resid %d\n",
2608 s->sc_data_direction, s->resid);
2610 printk(" use_sg %u, sglist_len %u\n", s->use_sg, s->sglist_len);
2612 printk(" serial_number 0x%x, retries %d, allowed %d\n",
2613 (unsigned)s->serial_number, s->retries, s->allowed);
2615 printk(" timeout_per_command %d\n", s->timeout_per_command);
2617 printk(" scsi_done 0x%p, done 0x%p, host_scribble 0x%p, result 0x%x\n",
2618 s->scsi_done, s->done, s->host_scribble, s->result);
2620 printk(" tag %u, pid %u\n", (unsigned)s->tag, (unsigned)s->pid);
2624 * asc_prt_asc_dvc_var()
2626 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2628 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2630 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2631 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2633 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2634 (unsigned)h->init_sdtr);
2636 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2637 "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2638 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2639 (unsigned)h->chip_no);
2641 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2642 "%u,\n", (unsigned)h->queue_full_or_busy,
2643 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2645 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2646 "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2647 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2648 (unsigned)h->in_critical_cnt);
2650 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2651 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2652 (unsigned)h->init_state, (unsigned)h->no_scam,
2653 (unsigned)h->pci_fix_asyn_xfer);
2655 printk(" cfg 0x%lx, irq_no 0x%x\n", (ulong)h->cfg, (unsigned)h->irq_no);
2659 * asc_prt_asc_dvc_cfg()
2661 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2663 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2665 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2666 h->can_tagged_qng, h->cmd_qng_enabled);
2667 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2668 h->disc_enable, h->sdtr_enable);
2671 (" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, chip_version %d,\n",
2672 h->chip_scsi_id, h->isa_dma_speed, h->isa_dma_channel,
2676 (" pci_device_id %d, lib_serial_no %u, lib_version %u, mcode_date 0x%x,\n",
2677 to_pci_dev(h->dev)->device, h->lib_serial_no, h->lib_version,
2680 printk(" mcode_version %d, overrun_buf 0x%lx\n",
2681 h->mcode_version, (ulong)h->overrun_buf);
2685 * asc_prt_asc_scsi_q()
2687 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2692 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2695 (" target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
2696 q->q2.target_ix, q->q1.target_lun, (ulong)q->q2.srb_ptr,
2700 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2701 (ulong)le32_to_cpu(q->q1.data_addr),
2702 (ulong)le32_to_cpu(q->q1.data_cnt),
2703 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2705 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2706 (ulong)q->cdbptr, q->q2.cdb_len,
2707 (ulong)q->sg_head, q->q1.sg_queue_cnt);
2711 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2712 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2714 for (i = 0; i < sgp->entry_cnt; i++) {
2715 printk(" [%u]: addr 0x%lx, bytes %lu\n",
2716 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2717 (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2724 * asc_prt_asc_qdone_info()
2726 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2728 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2729 printk(" srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
2730 (ulong)q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
2733 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2734 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2738 * asc_prt_adv_dvc_var()
2740 * Display an ADV_DVC_VAR structure.
2742 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2744 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2746 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2747 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2749 printk(" isr_callback 0x%lx, sdtr_able 0x%x, wdtr_able 0x%x\n",
2750 (ulong)h->isr_callback, (unsigned)h->sdtr_able,
2751 (unsigned)h->wdtr_able);
2753 printk(" start_motor 0x%x, scsi_reset_wait 0x%x, irq_no 0x%x,\n",
2754 (unsigned)h->start_motor,
2755 (unsigned)h->scsi_reset_wait, (unsigned)h->irq_no);
2757 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
2758 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2759 (ulong)h->carr_freelist);
2761 printk(" icq_sp 0x%lx, irq_sp 0x%lx\n",
2762 (ulong)h->icq_sp, (ulong)h->irq_sp);
2764 printk(" no_scam 0x%x, tagqng_able 0x%x\n",
2765 (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2767 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
2768 (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2772 * asc_prt_adv_dvc_cfg()
2774 * Display an ADV_DVC_CFG structure.
2776 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2778 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2780 printk(" disc_enable 0x%x, termination 0x%x\n",
2781 h->disc_enable, h->termination);
2783 printk(" chip_version 0x%x, mcode_date 0x%x\n",
2784 h->chip_version, h->mcode_date);
2786 printk(" mcode_version 0x%x, pci_device_id 0x%x, lib_version %u\n",
2787 h->mcode_version, to_pci_dev(h->dev)->device, h->lib_version);
2789 printk(" control_flag 0x%x\n", h->control_flag);
2793 * asc_prt_adv_scsi_req_q()
2795 * Display an ADV_SCSI_REQ_Q structure.
2797 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2800 struct asc_sg_block *sg_ptr;
2802 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2804 printk(" target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
2805 q->target_id, q->target_lun, (ulong)q->srb_ptr, q->a_flag);
2807 printk(" cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
2808 q->cntl, (ulong)le32_to_cpu(q->data_addr), (ulong)q->vdata_addr);
2810 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2811 (ulong)le32_to_cpu(q->data_cnt),
2812 (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2815 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2816 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2818 printk(" sg_working_ix 0x%x, target_cmd %u\n",
2819 q->sg_working_ix, q->target_cmd);
2821 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2822 (ulong)le32_to_cpu(q->scsiq_rptr),
2823 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2825 /* Display the request's ADV_SG_BLOCK structures. */
2826 if (q->sg_list_ptr != NULL) {
2830 * 'sg_ptr' is a physical address. Convert it to a virtual
2831 * address by indexing 'sg_blk_cnt' into the virtual address
2832 * array 'sg_list_ptr'.
2834 * XXX - Assumes all SG physical blocks are virtually contiguous.
2837 &(((ADV_SG_BLOCK *)(q->sg_list_ptr))[sg_blk_cnt]);
2838 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2839 if (sg_ptr->sg_ptr == 0) {
2848 * asc_prt_adv_sgblock()
2850 * Display an ADV_SG_BLOCK structure.
2852 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2856 printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2857 (ulong)b, sgblockno);
2858 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
2859 b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2860 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2862 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2863 for (i = 0; i < b->sg_cnt; i++) {
2864 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2865 i, (ulong)b->sg_list[i].sg_addr,
2866 (ulong)b->sg_list[i].sg_count);
2873 * Print hexadecimal output in 4 byte groupings 32 bytes
2874 * or 8 double-words per line.
2876 static void asc_prt_hex(char *f, uchar *s, int l)
2883 printk("%s: (%d bytes)\n", f, l);
2885 for (i = 0; i < l; i += 32) {
2887 /* Display a maximum of 8 double-words per line. */
2888 if ((k = (l - i) / 4) >= 8) {
2895 for (j = 0; j < k; j++) {
2896 printk(" %2.2X%2.2X%2.2X%2.2X",
2897 (unsigned)s[i + (j * 4)],
2898 (unsigned)s[i + (j * 4) + 1],
2899 (unsigned)s[i + (j * 4) + 2],
2900 (unsigned)s[i + (j * 4) + 3]);
2908 printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2911 printk(" %2.2X%2.2X",
2912 (unsigned)s[i + (j * 4)],
2913 (unsigned)s[i + (j * 4) + 1]);
2916 printk(" %2.2X%2.2X%2.2X",
2917 (unsigned)s[i + (j * 4) + 1],
2918 (unsigned)s[i + (j * 4) + 2],
2919 (unsigned)s[i + (j * 4) + 3]);
2926 #endif /* ADVANSYS_DEBUG */
2931 * Return suitable for printing on the console with the argument
2932 * adapter's configuration information.
2934 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2935 * otherwise the static 'info' array will be overrun.
2937 static const char *advansys_info(struct Scsi_Host *shost)
2939 static char info[ASC_INFO_SIZE];
2940 asc_board_t *boardp;
2941 ASC_DVC_VAR *asc_dvc_varp;
2942 ADV_DVC_VAR *adv_dvc_varp;
2944 char *widename = NULL;
2946 boardp = ASC_BOARDP(shost);
2947 if (ASC_NARROW_BOARD(boardp)) {
2948 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2949 ASC_DBG(1, "advansys_info: begin\n");
2950 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2951 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2953 busname = "ISA PnP";
2958 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2959 ASC_VERSION, busname,
2960 (ulong)shost->io_port,
2961 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2962 shost->irq, shost->dma_channel);
2964 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2966 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2968 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2969 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2970 == ASC_IS_PCI_ULTRA) {
2971 busname = "PCI Ultra";
2977 ASC_PRINT2("advansys_info: board %d: unknown "
2978 "bus type %d\n", boardp->id,
2979 asc_dvc_varp->bus_type);
2982 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2983 ASC_VERSION, busname, (ulong)shost->io_port,
2984 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2989 * Wide Adapter Information
2991 * Memory-mapped I/O is used instead of I/O space to access
2992 * the adapter, but display the I/O Port range. The Memory
2993 * I/O address is displayed through the driver /proc file.
2995 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2996 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2997 widename = "Ultra-Wide";
2998 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2999 widename = "Ultra2-Wide";
3001 widename = "Ultra3-Wide";
3004 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
3005 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
3006 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, shost->irq);
3008 BUG_ON(strlen(info) >= ASC_INFO_SIZE);
3009 ASC_DBG(1, "advansys_info: end\n");
3013 #ifdef CONFIG_PROC_FS
3017 * If 'cp' is NULL print to the console, otherwise print to a buffer.
3019 * Return 0 if printing to the console, otherwise return the number of
3020 * bytes written to the buffer.
3022 * Note: If any single line is greater than ASC_PRTLINE_SIZE bytes the stack
3023 * will be corrupted. 's[]' is defined to be ASC_PRTLINE_SIZE bytes.
3025 static int asc_prt_line(char *buf, int buflen, char *fmt, ...)
3029 char s[ASC_PRTLINE_SIZE];
3031 va_start(args, fmt);
3032 ret = vsprintf(s, fmt, args);
3033 BUG_ON(ret >= ASC_PRTLINE_SIZE);
3038 ret = min(buflen, ret);
3039 memcpy(buf, s, ret);
3046 * asc_prt_board_devices()
3048 * Print driver information for devices attached to the board.
3050 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3051 * cf. asc_prt_line().
3053 * Return the number of characters copied into 'cp'. No more than
3054 * 'cplen' characters will be copied to 'cp'.
3056 static int asc_prt_board_devices(struct Scsi_Host *shost, char *cp, int cplen)
3058 asc_board_t *boardp;
3065 boardp = ASC_BOARDP(shost);
3069 len = asc_prt_line(cp, leftlen,
3070 "\nDevice Information for AdvanSys SCSI Host %d:\n",
3074 if (ASC_NARROW_BOARD(boardp)) {
3075 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3077 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3080 len = asc_prt_line(cp, leftlen, "Target IDs Detected:");
3082 for (i = 0; i <= ADV_MAX_TID; i++) {
3083 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) {
3084 len = asc_prt_line(cp, leftlen, " %X,", i);
3088 len = asc_prt_line(cp, leftlen, " (%X=Host Adapter)\n", chip_scsi_id);
3095 * Display Wide Board BIOS Information.
3097 static int asc_prt_adv_bios(struct Scsi_Host *shost, char *cp, int cplen)
3099 asc_board_t *boardp;
3103 ushort major, minor, letter;
3105 boardp = ASC_BOARDP(shost);
3109 len = asc_prt_line(cp, leftlen, "\nROM BIOS Version: ");
3113 * If the BIOS saved a valid signature, then fill in
3114 * the BIOS code segment base address.
3116 if (boardp->bios_signature != 0x55AA) {
3117 len = asc_prt_line(cp, leftlen, "Disabled or Pre-3.1\n");
3119 len = asc_prt_line(cp, leftlen,
3120 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
3122 len = asc_prt_line(cp, leftlen,
3123 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
3126 major = (boardp->bios_version >> 12) & 0xF;
3127 minor = (boardp->bios_version >> 8) & 0xF;
3128 letter = (boardp->bios_version & 0xFF);
3130 len = asc_prt_line(cp, leftlen, "%d.%d%c\n",
3132 letter >= 26 ? '?' : letter + 'A');
3136 * Current available ROM BIOS release is 3.1I for UW
3137 * and 3.2I for U2W. This code doesn't differentiate
3138 * UW and U2W boards.
3140 if (major < 3 || (major <= 3 && minor < 1) ||
3141 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
3142 len = asc_prt_line(cp, leftlen,
3143 "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n");
3145 len = asc_prt_line(cp, leftlen,
3146 "ftp://ftp.connectcom.net/pub\n");
3155 * Add serial number to information bar if signature AAh
3156 * is found in at bit 15-9 (7 bits) of word 1.
3158 * Serial Number consists fo 12 alpha-numeric digits.
3160 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
3161 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
3162 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
3163 * 5 - Product revision (A-J) Word0: " "
3165 * Signature Word1: 15-9 (7 bits)
3166 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
3167 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
3169 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
3171 * Note 1: Only production cards will have a serial number.
3173 * Note 2: Signature is most significant 7 bits (0xFE).
3175 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
3177 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
3181 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
3185 * First word - 6 digits.
3189 /* Product type - 1st digit. */
3190 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
3191 /* Product type is P=Prototype */
3196 /* Manufacturing location - 2nd digit. */
3197 *cp++ = 'A' + ((w & 0x1C00) >> 10);
3199 /* Product ID - 3rd, 4th digits. */
3201 *cp++ = '0' + (num / 100);
3203 *cp++ = '0' + (num / 10);
3205 /* Product revision - 5th digit. */
3206 *cp++ = 'A' + (num % 10);
3216 * If bit 15 of third word is set, then the
3217 * last digit of the year is greater than 7.
3219 if (serialnum[2] & 0x8000) {
3220 *cp++ = '8' + ((w & 0x1C0) >> 6);
3222 *cp++ = '0' + ((w & 0x1C0) >> 6);
3225 /* Week of year - 7th, 8th digits. */
3227 *cp++ = '0' + num / 10;
3234 w = serialnum[2] & 0x7FFF;
3236 /* Serial number - 9th digit. */
3237 *cp++ = 'A' + (w / 1000);
3239 /* 10th, 11th, 12th digits. */
3241 *cp++ = '0' + num / 100;
3243 *cp++ = '0' + num / 10;
3247 *cp = '\0'; /* Null Terminate the string. */
3253 * asc_prt_asc_board_eeprom()
3255 * Print board EEPROM configuration.
3257 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3258 * cf. asc_prt_line().
3260 * Return the number of characters copied into 'cp'. No more than
3261 * 'cplen' characters will be copied to 'cp'.
3263 static int asc_prt_asc_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
3265 asc_board_t *boardp;
3266 ASC_DVC_VAR *asc_dvc_varp;
3273 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
3274 #endif /* CONFIG_ISA */
3275 uchar serialstr[13];
3277 boardp = ASC_BOARDP(shost);
3278 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
3279 ep = &boardp->eep_config.asc_eep;
3284 len = asc_prt_line(cp, leftlen,
3285 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3289 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
3292 asc_prt_line(cp, leftlen, " Serial Number: %s\n",
3296 if (ep->adapter_info[5] == 0xBB) {
3297 len = asc_prt_line(cp, leftlen,
3298 " Default Settings Used for EEPROM-less Adapter.\n");
3301 len = asc_prt_line(cp, leftlen,
3302 " Serial Number Signature Not Present.\n");
3307 len = asc_prt_line(cp, leftlen,
3308 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3309 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
3313 len = asc_prt_line(cp, leftlen,
3314 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
3317 len = asc_prt_line(cp, leftlen, " Target ID: ");
3319 for (i = 0; i <= ASC_MAX_TID; i++) {
3320 len = asc_prt_line(cp, leftlen, " %d", i);
3323 len = asc_prt_line(cp, leftlen, "\n");
3326 len = asc_prt_line(cp, leftlen, " Disconnects: ");
3328 for (i = 0; i <= ASC_MAX_TID; i++) {
3329 len = asc_prt_line(cp, leftlen, " %c",
3331 disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3335 len = asc_prt_line(cp, leftlen, "\n");
3338 len = asc_prt_line(cp, leftlen, " Command Queuing: ");
3340 for (i = 0; i <= ASC_MAX_TID; i++) {
3341 len = asc_prt_line(cp, leftlen, " %c",
3343 use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3347 len = asc_prt_line(cp, leftlen, "\n");
3350 len = asc_prt_line(cp, leftlen, " Start Motor: ");
3352 for (i = 0; i <= ASC_MAX_TID; i++) {
3353 len = asc_prt_line(cp, leftlen, " %c",
3355 start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3359 len = asc_prt_line(cp, leftlen, "\n");
3362 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3364 for (i = 0; i <= ASC_MAX_TID; i++) {
3365 len = asc_prt_line(cp, leftlen, " %c",
3367 init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3371 len = asc_prt_line(cp, leftlen, "\n");
3375 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
3376 len = asc_prt_line(cp, leftlen,
3377 " Host ISA DMA speed: %d MB/S\n",
3378 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
3381 #endif /* CONFIG_ISA */
3387 * asc_prt_adv_board_eeprom()
3389 * Print board EEPROM configuration.
3391 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3392 * cf. asc_prt_line().
3394 * Return the number of characters copied into 'cp'. No more than
3395 * 'cplen' characters will be copied to 'cp'.
3397 static int asc_prt_adv_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen)
3399 asc_board_t *boardp;
3400 ADV_DVC_VAR *adv_dvc_varp;
3406 uchar serialstr[13];
3407 ADVEEP_3550_CONFIG *ep_3550 = NULL;
3408 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
3409 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
3412 ushort sdtr_speed = 0;
3414 boardp = ASC_BOARDP(shost);
3415 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3416 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3417 ep_3550 = &boardp->eep_config.adv_3550_eep;
3418 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3419 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
3421 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
3427 len = asc_prt_line(cp, leftlen,
3428 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3432 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3433 wordp = &ep_3550->serial_number_word1;
3434 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3435 wordp = &ep_38C0800->serial_number_word1;
3437 wordp = &ep_38C1600->serial_number_word1;
3440 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE) {
3442 asc_prt_line(cp, leftlen, " Serial Number: %s\n",
3446 len = asc_prt_line(cp, leftlen,
3447 " Serial Number Signature Not Present.\n");
3451 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3452 len = asc_prt_line(cp, leftlen,
3453 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3454 ep_3550->adapter_scsi_id,
3455 ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3457 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3458 len = asc_prt_line(cp, leftlen,
3459 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3460 ep_38C0800->adapter_scsi_id,
3461 ep_38C0800->max_host_qng,
3462 ep_38C0800->max_dvc_qng);
3465 len = asc_prt_line(cp, leftlen,
3466 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3467 ep_38C1600->adapter_scsi_id,
3468 ep_38C1600->max_host_qng,
3469 ep_38C1600->max_dvc_qng);
3472 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3473 word = ep_3550->termination;
3474 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3475 word = ep_38C0800->termination_lvd;
3477 word = ep_38C1600->termination_lvd;
3481 termstr = "Low Off/High Off";
3484 termstr = "Low Off/High On";
3487 termstr = "Low On/High On";
3491 termstr = "Automatic";
3495 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3496 len = asc_prt_line(cp, leftlen,
3497 " termination: %u (%s), bios_ctrl: 0x%x\n",
3498 ep_3550->termination, termstr,
3499 ep_3550->bios_ctrl);
3501 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3502 len = asc_prt_line(cp, leftlen,
3503 " termination: %u (%s), bios_ctrl: 0x%x\n",
3504 ep_38C0800->termination_lvd, termstr,
3505 ep_38C0800->bios_ctrl);
3508 len = asc_prt_line(cp, leftlen,
3509 " termination: %u (%s), bios_ctrl: 0x%x\n",
3510 ep_38C1600->termination_lvd, termstr,
3511 ep_38C1600->bios_ctrl);
3515 len = asc_prt_line(cp, leftlen, " Target ID: ");
3517 for (i = 0; i <= ADV_MAX_TID; i++) {
3518 len = asc_prt_line(cp, leftlen, " %X", i);
3521 len = asc_prt_line(cp, leftlen, "\n");
3524 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3525 word = ep_3550->disc_enable;
3526 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3527 word = ep_38C0800->disc_enable;
3529 word = ep_38C1600->disc_enable;
3531 len = asc_prt_line(cp, leftlen, " Disconnects: ");
3533 for (i = 0; i <= ADV_MAX_TID; i++) {
3534 len = asc_prt_line(cp, leftlen, " %c",
3535 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3538 len = asc_prt_line(cp, leftlen, "\n");
3541 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3542 word = ep_3550->tagqng_able;
3543 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3544 word = ep_38C0800->tagqng_able;
3546 word = ep_38C1600->tagqng_able;
3548 len = asc_prt_line(cp, leftlen, " Command Queuing: ");
3550 for (i = 0; i <= ADV_MAX_TID; i++) {
3551 len = asc_prt_line(cp, leftlen, " %c",
3552 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3555 len = asc_prt_line(cp, leftlen, "\n");
3558 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3559 word = ep_3550->start_motor;
3560 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3561 word = ep_38C0800->start_motor;
3563 word = ep_38C1600->start_motor;
3565 len = asc_prt_line(cp, leftlen, " Start Motor: ");
3567 for (i = 0; i <= ADV_MAX_TID; i++) {
3568 len = asc_prt_line(cp, leftlen, " %c",
3569 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3572 len = asc_prt_line(cp, leftlen, "\n");
3575 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3576 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3578 for (i = 0; i <= ADV_MAX_TID; i++) {
3579 len = asc_prt_line(cp, leftlen, " %c",
3581 sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3585 len = asc_prt_line(cp, leftlen, "\n");
3589 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3590 len = asc_prt_line(cp, leftlen, " Ultra Transfer: ");
3592 for (i = 0; i <= ADV_MAX_TID; i++) {
3593 len = asc_prt_line(cp, leftlen, " %c",
3595 ultra_able & ADV_TID_TO_TIDMASK(i))
3599 len = asc_prt_line(cp, leftlen, "\n");
3603 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3604 word = ep_3550->wdtr_able;
3605 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3606 word = ep_38C0800->wdtr_able;
3608 word = ep_38C1600->wdtr_able;
3610 len = asc_prt_line(cp, leftlen, " Wide Transfer: ");
3612 for (i = 0; i <= ADV_MAX_TID; i++) {
3613 len = asc_prt_line(cp, leftlen, " %c",
3614 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3617 len = asc_prt_line(cp, leftlen, "\n");
3620 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3621 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3622 len = asc_prt_line(cp, leftlen,
3623 " Synchronous Transfer Speed (Mhz):\n ");
3625 for (i = 0; i <= ADV_MAX_TID; i++) {
3629 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3630 } else if (i == 4) {
3631 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3632 } else if (i == 8) {
3633 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3634 } else if (i == 12) {
3635 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3637 switch (sdtr_speed & ADV_MAX_TID) {
3660 len = asc_prt_line(cp, leftlen, "%X:%s ", i, speed_str);
3663 len = asc_prt_line(cp, leftlen, "\n ");
3668 len = asc_prt_line(cp, leftlen, "\n");
3676 * asc_prt_driver_conf()
3678 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3679 * cf. asc_prt_line().
3681 * Return the number of characters copied into 'cp'. No more than
3682 * 'cplen' characters will be copied to 'cp'.
3684 static int asc_prt_driver_conf(struct Scsi_Host *shost, char *cp, int cplen)
3686 asc_board_t *boardp;
3692 boardp = ASC_BOARDP(shost);
3697 len = asc_prt_line(cp, leftlen,
3698 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3702 len = asc_prt_line(cp, leftlen,
3703 " host_busy %u, last_reset %u, max_id %u, max_lun %u, max_channel %u\n",
3704 shost->host_busy, shost->last_reset, shost->max_id,
3705 shost->max_lun, shost->max_channel);
3708 len = asc_prt_line(cp, leftlen,
3709 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3710 shost->unique_id, shost->can_queue, shost->this_id,
3711 shost->sg_tablesize, shost->cmd_per_lun);
3714 len = asc_prt_line(cp, leftlen,
3715 " unchecked_isa_dma %d, use_clustering %d\n",
3716 shost->unchecked_isa_dma, shost->use_clustering);
3719 len = asc_prt_line(cp, leftlen,
3720 " flags 0x%x, last_reset 0x%x, jiffies 0x%x, asc_n_io_port 0x%x\n",
3721 boardp->flags, boardp->last_reset, jiffies,
3722 boardp->asc_n_io_port);
3725 len = asc_prt_line(cp, leftlen, " io_port 0x%x\n", shost->io_port);
3728 if (ASC_NARROW_BOARD(boardp)) {
3729 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3731 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3738 * asc_prt_asc_board_info()
3740 * Print dynamic board configuration information.
3742 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3743 * cf. asc_prt_line().
3745 * Return the number of characters copied into 'cp'. No more than
3746 * 'cplen' characters will be copied to 'cp'.
3748 static int asc_prt_asc_board_info(struct Scsi_Host *shost, char *cp, int cplen)
3750 asc_board_t *boardp;
3758 int renegotiate = 0;
3760 boardp = ASC_BOARDP(shost);
3761 v = &boardp->dvc_var.asc_dvc_var;
3762 c = &boardp->dvc_cfg.asc_dvc_cfg;
3763 chip_scsi_id = c->chip_scsi_id;
3768 len = asc_prt_line(cp, leftlen,
3769 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3773 len = asc_prt_line(cp, leftlen,
3774 " chip_version %u, lib_version 0x%x, lib_serial_no %u, mcode_date 0x%x\n",
3775 c->chip_version, c->lib_version, c->lib_serial_no,
3779 len = asc_prt_line(cp, leftlen,
3780 " mcode_version 0x%x, err_code %u\n",
3781 c->mcode_version, v->err_code);
3784 /* Current number of commands waiting for the host. */
3785 len = asc_prt_line(cp, leftlen,
3786 " Total Command Pending: %d\n", v->cur_total_qng);
3789 len = asc_prt_line(cp, leftlen, " Command Queuing:");
3791 for (i = 0; i <= ASC_MAX_TID; i++) {
3792 if ((chip_scsi_id == i) ||
3793 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3796 len = asc_prt_line(cp, leftlen, " %X:%c",
3799 use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ?
3803 len = asc_prt_line(cp, leftlen, "\n");
3806 /* Current number of commands waiting for a device. */
3807 len = asc_prt_line(cp, leftlen, " Command Queue Pending:");
3809 for (i = 0; i <= ASC_MAX_TID; i++) {
3810 if ((chip_scsi_id == i) ||
3811 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3814 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->cur_dvc_qng[i]);
3817 len = asc_prt_line(cp, leftlen, "\n");
3820 /* Current limit on number of commands that can be sent to a device. */
3821 len = asc_prt_line(cp, leftlen, " Command Queue Limit:");
3823 for (i = 0; i <= ASC_MAX_TID; i++) {
3824 if ((chip_scsi_id == i) ||
3825 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3828 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->max_dvc_qng[i]);
3831 len = asc_prt_line(cp, leftlen, "\n");
3834 /* Indicate whether the device has returned queue full status. */
3835 len = asc_prt_line(cp, leftlen, " Command Queue Full:");
3837 for (i = 0; i <= ASC_MAX_TID; i++) {
3838 if ((chip_scsi_id == i) ||
3839 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3842 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i)) {
3843 len = asc_prt_line(cp, leftlen, " %X:Y-%d",
3844 i, boardp->queue_full_cnt[i]);
3846 len = asc_prt_line(cp, leftlen, " %X:N", i);
3850 len = asc_prt_line(cp, leftlen, "\n");
3853 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:");
3855 for (i = 0; i <= ASC_MAX_TID; i++) {
3856 if ((chip_scsi_id == i) ||
3857 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3860 len = asc_prt_line(cp, leftlen, " %X:%c",
3863 sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3867 len = asc_prt_line(cp, leftlen, "\n");
3870 for (i = 0; i <= ASC_MAX_TID; i++) {
3871 uchar syn_period_ix;
3873 if ((chip_scsi_id == i) ||
3874 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3875 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3879 len = asc_prt_line(cp, leftlen, " %X:", i);
3882 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3883 len = asc_prt_line(cp, leftlen, " Asynchronous");
3887 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3890 len = asc_prt_line(cp, leftlen,
3891 " Transfer Period Factor: %d (%d.%d Mhz),",
3892 v->sdtr_period_tbl[syn_period_ix],
3894 v->sdtr_period_tbl[syn_period_ix],
3901 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
3903 sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3907 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3908 len = asc_prt_line(cp, leftlen, "*\n");
3911 len = asc_prt_line(cp, leftlen, "\n");
3917 len = asc_prt_line(cp, leftlen,
3918 " * = Re-negotiation pending before next command.\n");
3926 * asc_prt_adv_board_info()
3928 * Print dynamic board configuration information.
3930 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
3931 * cf. asc_prt_line().
3933 * Return the number of characters copied into 'cp'. No more than
3934 * 'cplen' characters will be copied to 'cp'.
3936 static int asc_prt_adv_board_info(struct Scsi_Host *shost, char *cp, int cplen)
3938 asc_board_t *boardp;
3945 AdvPortAddr iop_base;
3946 ushort chip_scsi_id;
3950 ushort sdtr_able, wdtr_able;
3951 ushort wdtr_done, sdtr_done;
3953 int renegotiate = 0;
3955 boardp = ASC_BOARDP(shost);
3956 v = &boardp->dvc_var.adv_dvc_var;
3957 c = &boardp->dvc_cfg.adv_dvc_cfg;
3958 iop_base = v->iop_base;
3959 chip_scsi_id = v->chip_scsi_id;
3964 len = asc_prt_line(cp, leftlen,
3965 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3969 len = asc_prt_line(cp, leftlen,
3970 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3972 AdvReadWordRegister(iop_base,
3973 IOPW_SCSI_CFG1) & CABLE_DETECT,
3977 len = asc_prt_line(cp, leftlen,
3978 " chip_version %u, lib_version 0x%x, mcode_date 0x%x, mcode_version 0x%x\n",
3979 c->chip_version, c->lib_version, c->mcode_date,
3983 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3984 len = asc_prt_line(cp, leftlen, " Queuing Enabled:");
3986 for (i = 0; i <= ADV_MAX_TID; i++) {
3987 if ((chip_scsi_id == i) ||
3988 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3992 len = asc_prt_line(cp, leftlen, " %X:%c",
3994 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
3998 len = asc_prt_line(cp, leftlen, "\n");
4001 len = asc_prt_line(cp, leftlen, " Queue Limit:");
4003 for (i = 0; i <= ADV_MAX_TID; i++) {
4004 if ((chip_scsi_id == i) ||
4005 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
4009 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
4012 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
4015 len = asc_prt_line(cp, leftlen, "\n");
4018 len = asc_prt_line(cp, leftlen, " Command Pending:");
4020 for (i = 0; i <= ADV_MAX_TID; i++) {
4021 if ((chip_scsi_id == i) ||
4022 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
4026 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
4029 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
4032 len = asc_prt_line(cp, leftlen, "\n");
4035 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4036 len = asc_prt_line(cp, leftlen, " Wide Enabled:");
4038 for (i = 0; i <= ADV_MAX_TID; i++) {
4039 if ((chip_scsi_id == i) ||
4040 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
4044 len = asc_prt_line(cp, leftlen, " %X:%c",
4046 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
4050 len = asc_prt_line(cp, leftlen, "\n");
4053 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
4054 len = asc_prt_line(cp, leftlen, " Transfer Bit Width:");
4056 for (i = 0; i <= ADV_MAX_TID; i++) {
4057 if ((chip_scsi_id == i) ||
4058 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
4062 AdvReadWordLram(iop_base,
4063 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
4066 len = asc_prt_line(cp, leftlen, " %X:%d",
4067 i, (lramword & 0x8000) ? 16 : 8);
4070 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
4071 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
4072 len = asc_prt_line(cp, leftlen, "*");
4077 len = asc_prt_line(cp, leftlen, "\n");
4080 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4081 len = asc_prt_line(cp, leftlen, " Synchronous Enabled:");
4083 for (i = 0; i <= ADV_MAX_TID; i++) {
4084 if ((chip_scsi_id == i) ||
4085 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
4089 len = asc_prt_line(cp, leftlen, " %X:%c",
4091 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' :
4095 len = asc_prt_line(cp, leftlen, "\n");
4098 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
4099 for (i = 0; i <= ADV_MAX_TID; i++) {
4101 AdvReadWordLram(iop_base,
4102 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
4104 lramword &= ~0x8000;
4106 if ((chip_scsi_id == i) ||
4107 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
4108 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
4112 len = asc_prt_line(cp, leftlen, " %X:", i);
4115 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
4116 len = asc_prt_line(cp, leftlen, " Asynchronous");
4120 asc_prt_line(cp, leftlen,
4121 " Transfer Period Factor: ");
4124 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
4126 asc_prt_line(cp, leftlen, "9 (80.0 Mhz),");
4128 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
4130 asc_prt_line(cp, leftlen, "10 (40.0 Mhz),");
4132 } else { /* 20 Mhz or below. */
4134 period = (((lramword >> 8) * 25) + 50) / 4;
4136 if (period == 0) { /* Should never happen. */
4138 asc_prt_line(cp, leftlen,
4142 len = asc_prt_line(cp, leftlen,
4144 period, 250 / period,
4151 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
4156 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
4157 len = asc_prt_line(cp, leftlen, "*\n");
4160 len = asc_prt_line(cp, leftlen, "\n");
4166 len = asc_prt_line(cp, leftlen,
4167 " * = Re-negotiation pending before next command.\n");
4177 * Copy proc information to a read buffer taking into account the current
4178 * read offset in the file and the remaining space in the read buffer.
4181 asc_proc_copy(off_t advoffset, off_t offset, char *curbuf, int leftlen,
4182 char *cp, int cplen)
4186 ASC_DBG3(2, "asc_proc_copy: offset %d, advoffset %d, cplen %d\n",
4187 (unsigned)offset, (unsigned)advoffset, cplen);
4188 if (offset <= advoffset) {
4189 /* Read offset below current offset, copy everything. */
4190 cnt = min(cplen, leftlen);
4191 ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
4192 (ulong)curbuf, (ulong)cp, cnt);
4193 memcpy(curbuf, cp, cnt);
4194 } else if (offset < advoffset + cplen) {
4195 /* Read offset within current range, partial copy. */
4196 cnt = (advoffset + cplen) - offset;
4197 cp = (cp + cplen) - cnt;
4198 cnt = min(cnt, leftlen);
4199 ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
4200 (ulong)curbuf, (ulong)cp, cnt);
4201 memcpy(curbuf, cp, cnt);
4206 #ifdef ADVANSYS_STATS
4208 * asc_prt_board_stats()
4210 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
4211 * cf. asc_prt_line().
4213 * Return the number of characters copied into 'cp'. No more than
4214 * 'cplen' characters will be copied to 'cp'.
4216 static int asc_prt_board_stats(struct Scsi_Host *shost, char *cp, int cplen)
4221 struct asc_stats *s;
4222 asc_board_t *boardp;
4227 boardp = ASC_BOARDP(shost);
4228 s = &boardp->asc_stats;
4230 len = asc_prt_line(cp, leftlen,
4231 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
4235 len = asc_prt_line(cp, leftlen,
4236 " queuecommand %lu, reset %lu, biosparam %lu, interrupt %lu\n",
4237 s->queuecommand, s->reset, s->biosparam,
4241 len = asc_prt_line(cp, leftlen,
4242 " callback %lu, done %lu, build_error %lu, build_noreq %lu, build_nosg %lu\n",
4243 s->callback, s->done, s->build_error,
4244 s->adv_build_noreq, s->adv_build_nosg);
4247 len = asc_prt_line(cp, leftlen,
4248 " exe_noerror %lu, exe_busy %lu, exe_error %lu, exe_unknown %lu\n",
4249 s->exe_noerror, s->exe_busy, s->exe_error,
4254 * Display data transfer statistics.
4256 if (s->cont_cnt > 0) {
4257 len = asc_prt_line(cp, leftlen, " cont_cnt %lu, ", s->cont_cnt);
4260 len = asc_prt_line(cp, leftlen, "cont_xfer %lu.%01lu kb ",
4262 ASC_TENTHS(s->cont_xfer, 2));
4265 /* Contiguous transfer average size */
4266 len = asc_prt_line(cp, leftlen, "avg_xfer %lu.%01lu kb\n",
4267 (s->cont_xfer / 2) / s->cont_cnt,
4268 ASC_TENTHS((s->cont_xfer / 2), s->cont_cnt));
4272 if (s->sg_cnt > 0) {
4274 len = asc_prt_line(cp, leftlen, " sg_cnt %lu, sg_elem %lu, ",
4275 s->sg_cnt, s->sg_elem);
4278 len = asc_prt_line(cp, leftlen, "sg_xfer %lu.%01lu kb\n",
4279 s->sg_xfer / 2, ASC_TENTHS(s->sg_xfer, 2));
4282 /* Scatter gather transfer statistics */
4283 len = asc_prt_line(cp, leftlen, " avg_num_elem %lu.%01lu, ",
4284 s->sg_elem / s->sg_cnt,
4285 ASC_TENTHS(s->sg_elem, s->sg_cnt));
4288 len = asc_prt_line(cp, leftlen, "avg_elem_size %lu.%01lu kb, ",
4289 (s->sg_xfer / 2) / s->sg_elem,
4290 ASC_TENTHS((s->sg_xfer / 2), s->sg_elem));
4293 len = asc_prt_line(cp, leftlen, "avg_xfer_size %lu.%01lu kb\n",
4294 (s->sg_xfer / 2) / s->sg_cnt,
4295 ASC_TENTHS((s->sg_xfer / 2), s->sg_cnt));
4300 * Display request queuing statistics.
4302 len = asc_prt_line(cp, leftlen,
4303 " Active and Waiting Request Queues (Time Unit: %d HZ):\n",
4309 #endif /* ADVANSYS_STATS */
4312 * advansys_proc_info() - /proc/scsi/advansys/{0,1,2,3,...}
4314 * *buffer: I/O buffer
4315 * **start: if inout == FALSE pointer into buffer where user read should start
4316 * offset: current offset into a /proc/scsi/advansys/[0...] file
4317 * length: length of buffer
4318 * hostno: Scsi_Host host_no
4319 * inout: TRUE - user is writing; FALSE - user is reading
4321 * Return the number of bytes read from or written to a
4322 * /proc/scsi/advansys/[0...] file.
4324 * Note: This function uses the per board buffer 'prtbuf' which is
4325 * allocated when the board is initialized in advansys_detect(). The
4326 * buffer is ASC_PRTBUF_SIZE bytes. The function asc_proc_copy() is
4327 * used to write to the buffer. The way asc_proc_copy() is written
4328 * if 'prtbuf' is too small it will not be overwritten. Instead the
4329 * user just won't get all the available statistics.
4332 advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start,
4333 off_t offset, int length, int inout)
4335 asc_board_t *boardp;
4344 ASC_DBG(1, "advansys_proc_info: begin\n");
4347 * User write not supported.
4349 if (inout == TRUE) {
4354 * User read of /proc/scsi/advansys/[0...] file.
4357 boardp = ASC_BOARDP(shost);
4359 /* Copy read data starting at the beginning of the buffer. */
4367 * Get board configuration information.
4369 * advansys_info() returns the board string from its own static buffer.
4371 cp = (char *)advansys_info(shost);
4374 /* Copy board information. */
4375 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4379 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4386 * Display Wide Board BIOS Information.
4388 if (ASC_WIDE_BOARD(boardp)) {
4389 cp = boardp->prtbuf;
4390 cplen = asc_prt_adv_bios(shost, cp, ASC_PRTBUF_SIZE);
4391 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4392 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp,
4397 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4405 * Display driver information for each device attached to the board.
4407 cp = boardp->prtbuf;
4408 cplen = asc_prt_board_devices(shost, cp, ASC_PRTBUF_SIZE);
4409 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4410 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4414 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4421 * Display EEPROM configuration for the board.
4423 cp = boardp->prtbuf;
4424 if (ASC_NARROW_BOARD(boardp)) {
4425 cplen = asc_prt_asc_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
4427 cplen = asc_prt_adv_board_eeprom(shost, cp, ASC_PRTBUF_SIZE);
4429 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4430 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4434 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4441 * Display driver configuration and information for the board.
4443 cp = boardp->prtbuf;
4444 cplen = asc_prt_driver_conf(shost, cp, ASC_PRTBUF_SIZE);
4445 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4446 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4450 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4456 #ifdef ADVANSYS_STATS
4458 * Display driver statistics for the board.
4460 cp = boardp->prtbuf;
4461 cplen = asc_prt_board_stats(shost, cp, ASC_PRTBUF_SIZE);
4462 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4463 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4467 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4472 #endif /* ADVANSYS_STATS */
4475 * Display Asc Library dynamic configuration information
4478 cp = boardp->prtbuf;
4479 if (ASC_NARROW_BOARD(boardp)) {
4480 cplen = asc_prt_asc_board_info(shost, cp, ASC_PRTBUF_SIZE);
4482 cplen = asc_prt_adv_board_info(shost, cp, ASC_PRTBUF_SIZE);
4484 BUG_ON(cplen >= ASC_PRTBUF_SIZE);
4485 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4489 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4495 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4499 #endif /* CONFIG_PROC_FS */
4501 static void asc_scsi_done(struct scsi_cmnd *scp)
4503 struct asc_board *boardp = ASC_BOARDP(scp->device->host);
4506 dma_unmap_sg(boardp->dev,
4507 (struct scatterlist *)scp->request_buffer,
4508 scp->use_sg, scp->sc_data_direction);
4509 else if (scp->request_bufflen)
4510 dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
4511 scp->request_bufflen, scp->sc_data_direction);
4513 ASC_STATS(scp->device->host, done);
4515 scp->scsi_done(scp);
4518 static void AscSetBank(PortAddr iop_base, uchar bank)
4522 val = AscGetChipControl(iop_base) &
4524 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
4528 } else if (bank == 2) {
4529 val |= CC_DIAG | CC_BANK_ONE;
4531 val &= ~CC_BANK_ONE;
4533 AscSetChipControl(iop_base, val);
4537 static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
4539 AscSetBank(iop_base, 1);
4540 AscWriteChipIH(iop_base, ins_code);
4541 AscSetBank(iop_base, 0);
4545 static int AscStartChip(PortAddr iop_base)
4547 AscSetChipControl(iop_base, 0);
4548 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
4554 static int AscStopChip(PortAddr iop_base)
4559 AscGetChipControl(iop_base) &
4560 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
4561 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
4562 AscSetChipIH(iop_base, INS_HALT);
4563 AscSetChipIH(iop_base, INS_RFLAG_WTM);
4564 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
4570 static int AscIsChipHalted(PortAddr iop_base)
4572 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
4573 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
4580 static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
4585 iop_base = asc_dvc->iop_base;
4586 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
4590 AscStopChip(iop_base);
4591 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
4593 AscSetChipIH(iop_base, INS_RFLAG_WTM);
4594 AscSetChipIH(iop_base, INS_HALT);
4595 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
4596 AscSetChipControl(iop_base, CC_HALT);
4598 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
4599 AscSetChipStatus(iop_base, 0);
4600 return (AscIsChipHalted(iop_base));
4603 static int AscFindSignature(PortAddr iop_base)
4607 ASC_DBG2(1, "AscFindSignature: AscGetChipSignatureByte(0x%x) 0x%x\n",
4608 iop_base, AscGetChipSignatureByte(iop_base));
4609 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
4611 "AscFindSignature: AscGetChipSignatureWord(0x%x) 0x%x\n",
4612 iop_base, AscGetChipSignatureWord(iop_base));
4613 sig_word = AscGetChipSignatureWord(iop_base);
4614 if ((sig_word == (ushort)ASC_1000_ID0W) ||
4615 (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
4622 static void AscEnableInterrupt(PortAddr iop_base)
4626 cfg = AscGetChipCfgLsw(iop_base);
4627 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
4631 static void AscDisableInterrupt(PortAddr iop_base)
4635 cfg = AscGetChipCfgLsw(iop_base);
4636 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
4640 static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
4642 unsigned char byte_data;
4643 unsigned short word_data;
4645 if (isodd_word(addr)) {
4646 AscSetChipLramAddr(iop_base, addr - 1);
4647 word_data = AscGetChipLramData(iop_base);
4648 byte_data = (word_data >> 8) & 0xFF;
4650 AscSetChipLramAddr(iop_base, addr);
4651 word_data = AscGetChipLramData(iop_base);
4652 byte_data = word_data & 0xFF;
4657 static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
4661 AscSetChipLramAddr(iop_base, addr);
4662 word_data = AscGetChipLramData(iop_base);
4666 #if CC_VERY_LONG_SG_LIST
4667 static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr)
4669 ushort val_low, val_high;
4670 ASC_DCNT dword_data;
4672 AscSetChipLramAddr(iop_base, addr);
4673 val_low = AscGetChipLramData(iop_base);
4674 val_high = AscGetChipLramData(iop_base);
4675 dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
4676 return (dword_data);
4678 #endif /* CC_VERY_LONG_SG_LIST */
4681 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
4685 AscSetChipLramAddr(iop_base, s_addr);
4686 for (i = 0; i < words; i++) {
4687 AscSetChipLramData(iop_base, set_wval);
4691 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
4693 AscSetChipLramAddr(iop_base, addr);
4694 AscSetChipLramData(iop_base, word_val);
4698 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
4702 if (isodd_word(addr)) {
4704 word_data = AscReadLramWord(iop_base, addr);
4705 word_data &= 0x00FF;
4706 word_data |= (((ushort)byte_val << 8) & 0xFF00);
4708 word_data = AscReadLramWord(iop_base, addr);
4709 word_data &= 0xFF00;
4710 word_data |= ((ushort)byte_val & 0x00FF);
4712 AscWriteLramWord(iop_base, addr, word_data);
4717 * Copy 2 bytes to LRAM.
4719 * The source data is assumed to be in little-endian order in memory
4720 * and is maintained in little-endian order when written to LRAM.
4723 AscMemWordCopyPtrToLram(PortAddr iop_base,
4724 ushort s_addr, uchar *s_buffer, int words)
4728 AscSetChipLramAddr(iop_base, s_addr);
4729 for (i = 0; i < 2 * words; i += 2) {
4731 * On a little-endian system the second argument below
4732 * produces a little-endian ushort which is written to
4733 * LRAM in little-endian order. On a big-endian system
4734 * the second argument produces a big-endian ushort which
4735 * is "transparently" byte-swapped by outpw() and written
4736 * in little-endian order to LRAM.
4738 outpw(iop_base + IOP_RAM_DATA,
4739 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
4745 * Copy 4 bytes to LRAM.
4747 * The source data is assumed to be in little-endian order in memory
4748 * and is maintained in little-endian order when writen to LRAM.
4751 AscMemDWordCopyPtrToLram(PortAddr iop_base,
4752 ushort s_addr, uchar *s_buffer, int dwords)
4756 AscSetChipLramAddr(iop_base, s_addr);
4757 for (i = 0; i < 4 * dwords; i += 4) {
4758 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
4759 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
4765 * Copy 2 bytes from LRAM.
4767 * The source data is assumed to be in little-endian order in LRAM
4768 * and is maintained in little-endian order when written to memory.
4771 AscMemWordCopyPtrFromLram(PortAddr iop_base,
4772 ushort s_addr, uchar *d_buffer, int words)
4777 AscSetChipLramAddr(iop_base, s_addr);
4778 for (i = 0; i < 2 * words; i += 2) {
4779 word = inpw(iop_base + IOP_RAM_DATA);
4780 d_buffer[i] = word & 0xff;
4781 d_buffer[i + 1] = (word >> 8) & 0xff;
4786 static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
4792 for (i = 0; i < words; i++, s_addr += 2) {
4793 sum += AscReadLramWord(iop_base, s_addr);
4798 static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
4805 iop_base = asc_dvc->iop_base;
4807 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
4808 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
4810 i = ASC_MIN_ACTIVE_QNO;
4811 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
4812 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4814 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4815 (uchar)(asc_dvc->max_total_qng));
4816 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4819 s_addr += ASC_QBLK_SIZE;
4820 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
4821 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4823 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4825 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4828 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4829 (uchar)ASC_QLINK_END);
4830 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4831 (uchar)(asc_dvc->max_total_qng - 1));
4832 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4833 (uchar)asc_dvc->max_total_qng);
4835 s_addr += ASC_QBLK_SIZE;
4836 for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
4837 i++, s_addr += ASC_QBLK_SIZE) {
4838 AscWriteLramByte(iop_base,
4839 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
4840 AscWriteLramByte(iop_base,
4841 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
4842 AscWriteLramByte(iop_base,
4843 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
4849 AscLoadMicroCode(PortAddr iop_base,
4850 ushort s_addr, uchar *mcode_buf, ushort mcode_size)
4853 ushort mcode_word_size;
4854 ushort mcode_chksum;
4856 /* Write the microcode buffer starting at LRAM address 0. */
4857 mcode_word_size = (ushort)(mcode_size >> 1);
4858 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4859 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
4861 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
4862 ASC_DBG1(1, "AscLoadMicroCode: chksum 0x%lx\n", (ulong)chksum);
4863 mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4864 (ushort)ASC_CODE_SEC_BEG,
4865 (ushort)((mcode_size -
4869 ASC_DBG1(1, "AscLoadMicroCode: mcode_chksum 0x%lx\n",
4870 (ulong)mcode_chksum);
4871 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4872 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
4876 /* Microcode buffer is kept after initialization for error recovery. */
4877 static uchar _asc_mcode_buf[] = {
4878 0x01, 0x03, 0x01, 0x19, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4879 0x00, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,
4880 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4881 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4882 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4883 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC3, 0x12, 0x0D, 0x05,
4884 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4885 0xFF, 0x80, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4886 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xFF,
4887 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
4888 0x00, 0x00, 0xE4, 0x88, 0x00, 0x00, 0x00, 0x00, 0x80, 0x73, 0x48, 0x04,
4889 0x36, 0x00, 0x00, 0xA2, 0xC2, 0x00, 0x80, 0x73, 0x03, 0x23, 0x36, 0x40,
4890 0xB6, 0x00, 0x36, 0x00, 0x05, 0xD6, 0x0C, 0xD2, 0x12, 0xDA, 0x00, 0xA2,
4891 0xC2, 0x00, 0x92, 0x80, 0x1E, 0x98, 0x50, 0x00, 0xF5, 0x00, 0x48, 0x98,
4892 0xDF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x4F, 0x00, 0xF5, 0x00,
4893 0x48, 0x98, 0xEF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x80, 0x62,
4894 0x92, 0x80, 0x00, 0x46, 0x15, 0xEE, 0x13, 0xEA, 0x02, 0x01, 0x09, 0xD8,
4895 0xCD, 0x04, 0x4D, 0x00, 0x00, 0xA3, 0xD6, 0x00, 0xA6, 0x97, 0x7F, 0x23,
4896 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84, 0xD2, 0xC1, 0x80, 0x73, 0xCD, 0x04,
4897 0x4D, 0x00, 0x00, 0xA3, 0xDA, 0x01, 0xA6, 0x97, 0xC6, 0x81, 0xC2, 0x88,
4898 0x80, 0x73, 0x80, 0x77, 0x00, 0x01, 0x01, 0xA1, 0xFE, 0x00, 0x4F, 0x00,
4899 0x84, 0x97, 0x07, 0xA6, 0x08, 0x01, 0x00, 0x33, 0x03, 0x00, 0xC2, 0x88,
4900 0x03, 0x03, 0x01, 0xDE, 0xC2, 0x88, 0xCE, 0x00, 0x69, 0x60, 0xCE, 0x00,
4901 0x02, 0x03, 0x4A, 0x60, 0x00, 0xA2, 0x78, 0x01, 0x80, 0x63, 0x07, 0xA6,
4902 0x24, 0x01, 0x78, 0x81, 0x03, 0x03, 0x80, 0x63, 0xE2, 0x00, 0x07, 0xA6,
4903 0x34, 0x01, 0x00, 0x33, 0x04, 0x00, 0xC2, 0x88, 0x03, 0x07, 0x02, 0x01,
4904 0x04, 0xCA, 0x0D, 0x23, 0x68, 0x98, 0x4D, 0x04, 0x04, 0x85, 0x05, 0xD8,
4905 0x0D, 0x23, 0x68, 0x98, 0xCD, 0x04, 0x15, 0x23, 0xF8, 0x88, 0xFB, 0x23,
4906 0x02, 0x61, 0x82, 0x01, 0x80, 0x63, 0x02, 0x03, 0x06, 0xA3, 0x62, 0x01,
4907 0x00, 0x33, 0x0A, 0x00, 0xC2, 0x88, 0x4E, 0x00, 0x07, 0xA3, 0x6E, 0x01,
4908 0x00, 0x33, 0x0B, 0x00, 0xC2, 0x88, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33,
4909 0x1A, 0x00, 0xC2, 0x88, 0x50, 0x04, 0x88, 0x81, 0x06, 0xAB, 0x82, 0x01,
4910 0x88, 0x81, 0x4E, 0x00, 0x07, 0xA3, 0x92, 0x01, 0x50, 0x00, 0x00, 0xA3,
4911 0x3C, 0x01, 0x00, 0x05, 0x7C, 0x81, 0x46, 0x97, 0x02, 0x01, 0x05, 0xC6,
4912 0x04, 0x23, 0xA0, 0x01, 0x15, 0x23, 0xA1, 0x01, 0xBE, 0x81, 0xFD, 0x23,
4913 0x02, 0x61, 0x82, 0x01, 0x0A, 0xDA, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0,
4914 0xB4, 0x01, 0x80, 0x63, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33, 0x1B, 0x00,
4915 0xC2, 0x88, 0x06, 0x23, 0x68, 0x98, 0xCD, 0x04, 0xE6, 0x84, 0x06, 0x01,
4916 0x00, 0xA2, 0xD4, 0x01, 0x57, 0x60, 0x00, 0xA0, 0xDA, 0x01, 0xE6, 0x84,
4917 0x80, 0x23, 0xA0, 0x01, 0xE6, 0x84, 0x80, 0x73, 0x4B, 0x00, 0x06, 0x61,
4918 0x00, 0xA2, 0x00, 0x02, 0x04, 0x01, 0x0C, 0xDE, 0x02, 0x01, 0x03, 0xCC,
4919 0x4F, 0x00, 0x84, 0x97, 0xFC, 0x81, 0x08, 0x23, 0x02, 0x41, 0x82, 0x01,
4920 0x4F, 0x00, 0x62, 0x97, 0x48, 0x04, 0x84, 0x80, 0xF0, 0x97, 0x00, 0x46,
4921 0x56, 0x00, 0x03, 0xC0, 0x01, 0x23, 0xE8, 0x00, 0x81, 0x73, 0x06, 0x29,
4922 0x03, 0x42, 0x06, 0xE2, 0x03, 0xEE, 0x6B, 0xEB, 0x11, 0x23, 0xF8, 0x88,
4923 0x04, 0x98, 0xF0, 0x80, 0x80, 0x73, 0x80, 0x77, 0x07, 0xA4, 0x2A, 0x02,
4924 0x7C, 0x95, 0x06, 0xA6, 0x34, 0x02, 0x03, 0xA6, 0x4C, 0x04, 0x46, 0x82,
4925 0x04, 0x01, 0x03, 0xD8, 0xB4, 0x98, 0x6A, 0x96, 0x46, 0x82, 0xFE, 0x95,
4926 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0xB6, 0x2D, 0x02, 0xA6, 0x6C, 0x02,
4927 0x07, 0xA6, 0x5A, 0x02, 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x62, 0x02,
4928 0xC2, 0x88, 0x7C, 0x95, 0x48, 0x82, 0x60, 0x96, 0x48, 0x82, 0x04, 0x23,
4929 0xA0, 0x01, 0x14, 0x23, 0xA1, 0x01, 0x3C, 0x84, 0x04, 0x01, 0x0C, 0xDC,
4930 0xE0, 0x23, 0x25, 0x61, 0xEF, 0x00, 0x14, 0x01, 0x4F, 0x04, 0xA8, 0x01,
4931 0x6F, 0x00, 0xA5, 0x01, 0x03, 0x23, 0xA4, 0x01, 0x06, 0x23, 0x9C, 0x01,
4932 0x24, 0x2B, 0x1C, 0x01, 0x02, 0xA6, 0xAA, 0x02, 0x07, 0xA6, 0x5A, 0x02,
4933 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x20, 0x04, 0x01, 0xA6, 0xB4, 0x02,
4934 0x00, 0xA6, 0xB4, 0x02, 0x00, 0x33, 0x12, 0x00, 0xC2, 0x88, 0x00, 0x0E,
4935 0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0x8C, 0x02, 0x4D, 0x04, 0x04, 0x01,
4936 0x0B, 0xDC, 0xE7, 0x23, 0x04, 0x61, 0x84, 0x01, 0x10, 0x31, 0x12, 0x35,
4937 0x14, 0x01, 0xEC, 0x00, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0xEA, 0x82,
4938 0x18, 0x23, 0x04, 0x61, 0x18, 0xA0, 0xE2, 0x02, 0x04, 0x01, 0xA2, 0xC8,
4939 0x00, 0x33, 0x1F, 0x00, 0xC2, 0x88, 0x08, 0x31, 0x0A, 0x35, 0x0C, 0x39,
4940 0x0E, 0x3D, 0x7E, 0x98, 0xB6, 0x2D, 0x01, 0xA6, 0x14, 0x03, 0x00, 0xA6,
4941 0x14, 0x03, 0x07, 0xA6, 0x0C, 0x03, 0x06, 0xA6, 0x10, 0x03, 0x03, 0xA6,
4942 0x20, 0x04, 0x02, 0xA6, 0x6C, 0x02, 0x00, 0x33, 0x33, 0x00, 0xC2, 0x88,
4943 0x7C, 0x95, 0xEE, 0x82, 0x60, 0x96, 0xEE, 0x82, 0x82, 0x98, 0x80, 0x42,
4944 0x7E, 0x98, 0x64, 0xE4, 0x04, 0x01, 0x2D, 0xC8, 0x31, 0x05, 0x07, 0x01,
4945 0x00, 0xA2, 0x54, 0x03, 0x00, 0x43, 0x87, 0x01, 0x05, 0x05, 0x86, 0x98,
4946 0x7E, 0x98, 0x00, 0xA6, 0x16, 0x03, 0x07, 0xA6, 0x4C, 0x03, 0x03, 0xA6,
4947 0x3C, 0x04, 0x06, 0xA6, 0x50, 0x03, 0x01, 0xA6, 0x16, 0x03, 0x00, 0x33,
4948 0x25, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x32, 0x83, 0x60, 0x96, 0x32, 0x83,
4949 0x04, 0x01, 0x10, 0xCE, 0x07, 0xC8, 0x05, 0x05, 0xEB, 0x04, 0x00, 0x33,
4950 0x00, 0x20, 0xC0, 0x20, 0x81, 0x62, 0x72, 0x83, 0x00, 0x01, 0x05, 0x05,
4951 0xFF, 0xA2, 0x7A, 0x03, 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x2E, 0x83,
4952 0x05, 0x05, 0x15, 0x01, 0x00, 0xA2, 0x9A, 0x03, 0xEC, 0x00, 0x6E, 0x00,
4953 0x95, 0x01, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0x01, 0xA6, 0x96, 0x03,
4954 0x00, 0xA6, 0x96, 0x03, 0x10, 0x84, 0x80, 0x42, 0x7E, 0x98, 0x01, 0xA6,
4955 0xA4, 0x03, 0x00, 0xA6, 0xBC, 0x03, 0x10, 0x84, 0xA8, 0x98, 0x80, 0x42,
4956 0x01, 0xA6, 0xA4, 0x03, 0x07, 0xA6, 0xB2, 0x03, 0xD4, 0x83, 0x7C, 0x95,
4957 0xA8, 0x83, 0x00, 0x33, 0x2F, 0x00, 0xC2, 0x88, 0xA8, 0x98, 0x80, 0x42,
4958 0x00, 0xA6, 0xBC, 0x03, 0x07, 0xA6, 0xCA, 0x03, 0xD4, 0x83, 0x7C, 0x95,
4959 0xC0, 0x83, 0x00, 0x33, 0x26, 0x00, 0xC2, 0x88, 0x38, 0x2B, 0x80, 0x32,
4960 0x80, 0x36, 0x04, 0x23, 0xA0, 0x01, 0x12, 0x23, 0xA1, 0x01, 0x10, 0x84,
4961 0x07, 0xF0, 0x06, 0xA4, 0xF4, 0x03, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23,
4962 0x83, 0x03, 0x80, 0x63, 0x03, 0xA6, 0x0E, 0x04, 0x07, 0xA6, 0x06, 0x04,
4963 0x06, 0xA6, 0x0A, 0x04, 0x00, 0x33, 0x17, 0x00, 0xC2, 0x88, 0x7C, 0x95,
4964 0xF4, 0x83, 0x60, 0x96, 0xF4, 0x83, 0x20, 0x84, 0x07, 0xF0, 0x06, 0xA4,
4965 0x20, 0x04, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23, 0x83, 0x03, 0x80, 0x63,
4966 0xB6, 0x2D, 0x03, 0xA6, 0x3C, 0x04, 0x07, 0xA6, 0x34, 0x04, 0x06, 0xA6,
4967 0x38, 0x04, 0x00, 0x33, 0x30, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x20, 0x84,
4968 0x60, 0x96, 0x20, 0x84, 0x1D, 0x01, 0x06, 0xCC, 0x00, 0x33, 0x00, 0x84,
4969 0xC0, 0x20, 0x00, 0x23, 0xEA, 0x00, 0x81, 0x62, 0xA2, 0x0D, 0x80, 0x63,
4970 0x07, 0xA6, 0x5A, 0x04, 0x00, 0x33, 0x18, 0x00, 0xC2, 0x88, 0x03, 0x03,
4971 0x80, 0x63, 0xA3, 0x01, 0x07, 0xA4, 0x64, 0x04, 0x23, 0x01, 0x00, 0xA2,
4972 0x86, 0x04, 0x0A, 0xA0, 0x76, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1D, 0x00,
4973 0xC2, 0x88, 0x0B, 0xA0, 0x82, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1E, 0x00,
4974 0xC2, 0x88, 0x42, 0x23, 0xF8, 0x88, 0x00, 0x23, 0x22, 0xA3, 0xE6, 0x04,
4975 0x08, 0x23, 0x22, 0xA3, 0xA2, 0x04, 0x28, 0x23, 0x22, 0xA3, 0xAE, 0x04,
4976 0x02, 0x23, 0x22, 0xA3, 0xC4, 0x04, 0x42, 0x23, 0xF8, 0x88, 0x4A, 0x00,
4977 0x06, 0x61, 0x00, 0xA0, 0xAE, 0x04, 0x45, 0x23, 0xF8, 0x88, 0x04, 0x98,
4978 0x00, 0xA2, 0xC0, 0x04, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x82, 0xC0, 0x20,
4979 0x81, 0x62, 0xE8, 0x81, 0x47, 0x23, 0xF8, 0x88, 0x04, 0x01, 0x0B, 0xDE,
4980 0x04, 0x98, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x81, 0xC0, 0x20, 0x81, 0x62,
4981 0x14, 0x01, 0x00, 0xA0, 0x00, 0x02, 0x43, 0x23, 0xF8, 0x88, 0x04, 0x23,
4982 0xA0, 0x01, 0x44, 0x23, 0xA1, 0x01, 0x80, 0x73, 0x4D, 0x00, 0x03, 0xA3,
4983 0xF4, 0x04, 0x00, 0x33, 0x27, 0x00, 0xC2, 0x88, 0x04, 0x01, 0x04, 0xDC,
4984 0x02, 0x23, 0xA2, 0x01, 0x04, 0x23, 0xA0, 0x01, 0x04, 0x98, 0x26, 0x95,
4985 0x4B, 0x00, 0xF6, 0x00, 0x4F, 0x04, 0x4F, 0x00, 0x00, 0xA3, 0x22, 0x05,
4986 0x00, 0x05, 0x76, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x1C, 0x05, 0x0A, 0x85,
4987 0x46, 0x97, 0xCD, 0x04, 0x24, 0x85, 0x48, 0x04, 0x84, 0x80, 0x02, 0x01,
4988 0x03, 0xDA, 0x80, 0x23, 0x82, 0x01, 0x34, 0x85, 0x02, 0x23, 0xA0, 0x01,
4989 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x40, 0x05, 0x1D, 0x01, 0x04, 0xD6,
4990 0xFF, 0x23, 0x86, 0x41, 0x4B, 0x60, 0xCB, 0x00, 0xFF, 0x23, 0x80, 0x01,
4991 0x49, 0x00, 0x81, 0x01, 0x04, 0x01, 0x02, 0xC8, 0x30, 0x01, 0x80, 0x01,
4992 0xF7, 0x04, 0x03, 0x01, 0x49, 0x04, 0x80, 0x01, 0xC9, 0x00, 0x00, 0x05,
4993 0x00, 0x01, 0xFF, 0xA0, 0x60, 0x05, 0x77, 0x04, 0x01, 0x23, 0xEA, 0x00,
4994 0x5D, 0x00, 0xFE, 0xC7, 0x00, 0x62, 0x00, 0x23, 0xEA, 0x00, 0x00, 0x63,
4995 0x07, 0xA4, 0xF8, 0x05, 0x03, 0x03, 0x02, 0xA0, 0x8E, 0x05, 0xF4, 0x85,
4996 0x00, 0x33, 0x2D, 0x00, 0xC2, 0x88, 0x04, 0xA0, 0xB8, 0x05, 0x80, 0x63,
4997 0x00, 0x23, 0xDF, 0x00, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0xA4, 0x05,
4998 0x1D, 0x01, 0x06, 0xD6, 0x02, 0x23, 0x02, 0x41, 0x82, 0x01, 0x50, 0x00,
4999 0x62, 0x97, 0x04, 0x85, 0x04, 0x23, 0x02, 0x41, 0x82, 0x01, 0x04, 0x85,
5000 0x08, 0xA0, 0xBE, 0x05, 0xF4, 0x85, 0x03, 0xA0, 0xC4, 0x05, 0xF4, 0x85,
5001 0x01, 0xA0, 0xCE, 0x05, 0x88, 0x00, 0x80, 0x63, 0xCC, 0x86, 0x07, 0xA0,
5002 0xEE, 0x05, 0x5F, 0x00, 0x00, 0x2B, 0xDF, 0x08, 0x00, 0xA2, 0xE6, 0x05,
5003 0x80, 0x67, 0x80, 0x63, 0x01, 0xA2, 0x7A, 0x06, 0x7C, 0x85, 0x06, 0x23,
5004 0x68, 0x98, 0x48, 0x23, 0xF8, 0x88, 0x07, 0x23, 0x80, 0x00, 0x06, 0x87,
5005 0x80, 0x63, 0x7C, 0x85, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63, 0x4A, 0x00,
5006 0x06, 0x61, 0x00, 0xA2, 0x36, 0x06, 0x1D, 0x01, 0x16, 0xD4, 0xC0, 0x23,
5007 0x07, 0x41, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x1C, 0x06, 0x00, 0x33,
5008 0x37, 0x00, 0xC2, 0x88, 0x1D, 0x01, 0x01, 0xD6, 0x20, 0x23, 0x63, 0x60,
5009 0x83, 0x03, 0x80, 0x63, 0x02, 0x23, 0xDF, 0x00, 0x07, 0xA6, 0x7C, 0x05,
5010 0xEF, 0x04, 0x6F, 0x00, 0x00, 0x63, 0x4B, 0x00, 0x06, 0x41, 0xCB, 0x00,
5011 0x52, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x4E, 0x06, 0x1D, 0x01, 0x03, 0xCA,
5012 0xC0, 0x23, 0x07, 0x41, 0x00, 0x63, 0x1D, 0x01, 0x04, 0xCC, 0x00, 0x33,
5013 0x00, 0x83, 0xC0, 0x20, 0x81, 0x62, 0x80, 0x23, 0x07, 0x41, 0x00, 0x63,
5014 0x80, 0x67, 0x08, 0x23, 0x83, 0x03, 0x80, 0x63, 0x00, 0x63, 0x01, 0x23,
5015 0xDF, 0x00, 0x06, 0xA6, 0x84, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67,
5016 0x80, 0x63, 0x00, 0x33, 0x00, 0x40, 0xC0, 0x20, 0x81, 0x62, 0x00, 0x63,
5017 0x00, 0x00, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x94, 0x06,
5018 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x00, 0x01, 0xA0, 0x14, 0x07, 0x00, 0x2B,
5019 0x40, 0x0E, 0x80, 0x63, 0x01, 0x00, 0x06, 0xA6, 0xAA, 0x06, 0x07, 0xA6,
5020 0x7C, 0x05, 0x40, 0x0E, 0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0xA2, 0x06,
5021 0x06, 0xA6, 0xBC, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x40, 0x0E,
5022 0x80, 0x63, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63,
5023 0x07, 0xA6, 0xD6, 0x06, 0x00, 0x33, 0x2A, 0x00, 0xC2, 0x88, 0x03, 0x03,
5024 0x80, 0x63, 0x89, 0x00, 0x0A, 0x2B, 0x07, 0xA6, 0xE8, 0x06, 0x00, 0x33,
5025 0x29, 0x00, 0xC2, 0x88, 0x00, 0x43, 0x00, 0xA2, 0xF4, 0x06, 0xC0, 0x0E,
5026 0x80, 0x63, 0xDE, 0x86, 0xC0, 0x0E, 0x00, 0x33, 0x00, 0x80, 0xC0, 0x20,
5027 0x81, 0x62, 0x04, 0x01, 0x02, 0xDA, 0x80, 0x63, 0x7C, 0x85, 0x80, 0x7B,
5028 0x80, 0x63, 0x06, 0xA6, 0x8C, 0x06, 0x00, 0x33, 0x2C, 0x00, 0xC2, 0x88,
5029 0x0C, 0xA2, 0x2E, 0x07, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6,
5030 0x2C, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x33, 0x3D, 0x00, 0xC2, 0x88,
5031 0x00, 0x00, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0x0C, 0xA0, 0x44, 0x07,
5032 0x07, 0xA6, 0x7C, 0x05, 0xBF, 0x23, 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84,
5033 0x00, 0x63, 0xF0, 0x04, 0x01, 0x01, 0xF1, 0x00, 0x00, 0x01, 0xF2, 0x00,
5034 0x01, 0x05, 0x80, 0x01, 0x72, 0x04, 0x71, 0x00, 0x81, 0x01, 0x70, 0x04,
5035 0x80, 0x05, 0x81, 0x05, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04,
5036 0x01, 0x01, 0xF1, 0x00, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04, 0x71, 0x00,
5037 0x81, 0x01, 0x72, 0x00, 0x80, 0x01, 0x71, 0x04, 0x70, 0x00, 0x80, 0x01,
5038 0x70, 0x04, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x00, 0x01,
5039 0xF1, 0x00, 0x70, 0x00, 0x80, 0x01, 0x70, 0x04, 0x71, 0x00, 0x80, 0x01,
5040 0x72, 0x00, 0x81, 0x01, 0x71, 0x04, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04,
5041 0x00, 0x63, 0x00, 0x23, 0xB3, 0x01, 0x83, 0x05, 0xA3, 0x01, 0xA2, 0x01,
5042 0xA1, 0x01, 0x01, 0x23, 0xA0, 0x01, 0x00, 0x01, 0xC8, 0x00, 0x03, 0xA1,
5043 0xC4, 0x07, 0x00, 0x33, 0x07, 0x00, 0xC2, 0x88, 0x80, 0x05, 0x81, 0x05,
5044 0x04, 0x01, 0x11, 0xC8, 0x48, 0x00, 0xB0, 0x01, 0xB1, 0x01, 0x08, 0x23,
5045 0xB2, 0x01, 0x05, 0x01, 0x48, 0x04, 0x00, 0x43, 0x00, 0xA2, 0xE4, 0x07,
5046 0x00, 0x05, 0xDA, 0x87, 0x00, 0x01, 0xC8, 0x00, 0xFF, 0x23, 0x80, 0x01,
5047 0x05, 0x05, 0x00, 0x63, 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04,
5048 0x00, 0x02, 0x80, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04, 0x00, 0x63,
5049 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x00, 0xA0,
5050 0x14, 0x08, 0x16, 0x88, 0x00, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04,
5051 0x00, 0x63, 0xF3, 0x04, 0x00, 0x23, 0xF4, 0x00, 0x74, 0x00, 0x80, 0x43,
5052 0xF4, 0x00, 0xCF, 0x40, 0x00, 0xA2, 0x44, 0x08, 0x74, 0x04, 0x02, 0x01,
5053 0xF7, 0xC9, 0xF6, 0xD9, 0x00, 0x01, 0x01, 0xA1, 0x24, 0x08, 0x04, 0x98,
5054 0x26, 0x95, 0x24, 0x88, 0x73, 0x04, 0x00, 0x63, 0xF3, 0x04, 0x75, 0x04,
5055 0x5A, 0x88, 0x02, 0x01, 0x04, 0xD8, 0x46, 0x97, 0x04, 0x98, 0x26, 0x95,
5056 0x4A, 0x88, 0x75, 0x00, 0x00, 0xA3, 0x64, 0x08, 0x00, 0x05, 0x4E, 0x88,
5057 0x73, 0x04, 0x00, 0x63, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6, 0x76, 0x08,
5058 0x00, 0x33, 0x3E, 0x00, 0xC2, 0x88, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63,
5059 0x00, 0x63, 0x38, 0x2B, 0x9C, 0x88, 0x38, 0x2B, 0x92, 0x88, 0x32, 0x09,
5060 0x31, 0x05, 0x92, 0x98, 0x05, 0x05, 0xB2, 0x09, 0x00, 0x63, 0x00, 0x32,
5061 0x00, 0x36, 0x00, 0x3A, 0x00, 0x3E, 0x00, 0x63, 0x80, 0x32, 0x80, 0x36,
5062 0x80, 0x3A, 0x80, 0x3E, 0xB4, 0x3D, 0x00, 0x63, 0x38, 0x2B, 0x40, 0x32,
5063 0x40, 0x36, 0x40, 0x3A, 0x40, 0x3E, 0x00, 0x63, 0x5A, 0x20, 0xC9, 0x40,
5064 0x00, 0xA0, 0xB4, 0x08, 0x5D, 0x00, 0xFE, 0xC3, 0x00, 0x63, 0x80, 0x73,
5065 0xE6, 0x20, 0x02, 0x23, 0xE8, 0x00, 0x82, 0x73, 0xFF, 0xFD, 0x80, 0x73,
5066 0x13, 0x23, 0xF8, 0x88, 0x66, 0x20, 0xC0, 0x20, 0x04, 0x23, 0xA0, 0x01,
5067 0xA1, 0x23, 0xA1, 0x01, 0x81, 0x62, 0xE2, 0x88, 0x80, 0x73, 0x80, 0x77,
5068 0x68, 0x00, 0x00, 0xA2, 0x80, 0x00, 0x03, 0xC2, 0xF1, 0xC7, 0x41, 0x23,
5069 0xF8, 0x88, 0x11, 0x23, 0xA1, 0x01, 0x04, 0x23, 0xA0, 0x01, 0xE6, 0x84,
5072 static unsigned short _asc_mcode_size = sizeof(_asc_mcode_buf);
5073 static ADV_DCNT _asc_mcode_chksum = 0x012C453FUL;
5075 /* Microcode buffer is kept after initialization for error recovery. */
5076 static unsigned char _adv_asc3550_buf[] = {
5077 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x18, 0xe4, 0x00, 0xfc,
5078 0x01, 0x00, 0x48, 0xe4, 0xbe, 0x18, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00,
5079 0x00, 0xfa, 0xff, 0xff, 0x28, 0x0e, 0x9e, 0xe7, 0xff, 0x00, 0x82, 0xe7,
5080 0x00, 0xea, 0x00, 0xf6, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0, 0x01, 0xf6,
5081 0x01, 0xfa, 0x08, 0x00, 0x03, 0x00, 0x04, 0x00, 0x18, 0xf4, 0x10, 0x00,
5082 0x00, 0xec, 0x85, 0xf0, 0xbc, 0x00, 0xd5, 0xf0, 0x8e, 0x0c, 0x38, 0x54,
5083 0x00, 0xe6, 0x1e, 0xf0, 0x86, 0xf0, 0xb4, 0x00, 0x98, 0x57, 0xd0, 0x01,
5084 0x0c, 0x1c, 0x3e, 0x1c, 0x0c, 0x00, 0xbb, 0x00, 0xaa, 0x18, 0x02, 0x80,
5085 0x32, 0xf0, 0x01, 0xfc, 0x88, 0x0c, 0xc6, 0x12, 0x02, 0x13, 0x18, 0x40,
5086 0x00, 0x57, 0x01, 0xea, 0x3c, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12,
5087 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
5088 0x3e, 0x01, 0xda, 0x0f, 0x22, 0x10, 0x08, 0x12, 0x02, 0x4a, 0xb9, 0x54,
5089 0x03, 0x58, 0x1b, 0x80, 0x30, 0xe4, 0x4b, 0xe4, 0x20, 0x00, 0x32, 0x00,
5090 0x3e, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
5091 0x70, 0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x62, 0x0a,
5092 0x92, 0x0c, 0x2c, 0x10, 0x2e, 0x10, 0x06, 0x13, 0x4c, 0x1c, 0xbb, 0x55,
5093 0x3c, 0x56, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0, 0xb1, 0xf0,
5094 0x03, 0xf7, 0x06, 0xf7, 0x03, 0xfc, 0x0f, 0x00, 0x40, 0x00, 0xbe, 0x00,
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5390 0x05, 0xc6, 0x28, 0x84, 0x05, 0x3f, 0x28, 0x34, 0x5e, 0x02, 0x5b, 0xfe,
5391 0xc0, 0x5d, 0xfe, 0xf8, 0x14, 0xfe, 0x03, 0x17, 0x05, 0x50, 0xb4, 0x0c,
5392 0x50, 0x5e, 0x2b, 0x01, 0x08, 0x26, 0x5c, 0x01, 0xfe, 0xaa, 0x14, 0x02,
5393 0x5c, 0x01, 0x08, 0x25, 0x32, 0x1f, 0x44, 0x30, 0x2e, 0xd6, 0x07, 0x06,
5394 0x21, 0x44, 0x01, 0xfe, 0x8e, 0x13, 0xfe, 0x42, 0x58, 0xfe, 0x82, 0x14,
5395 0xfe, 0xa4, 0x14, 0x87, 0xfe, 0x4a, 0xf4, 0x0b, 0x16, 0x44, 0xfe, 0x4a,
5396 0xf4, 0x06, 0xfe, 0x0c, 0x12, 0x2f, 0x07, 0x9a, 0x85, 0x02, 0x5b, 0x05,
5397 0x3f, 0xb4, 0x0c, 0x3f, 0x5e, 0x2b, 0x01, 0x08, 0x26, 0x5c, 0x01, 0xfe,
5398 0xd8, 0x14, 0x02, 0x5c, 0x13, 0x06, 0x65, 0xfe, 0xca, 0x12, 0x26, 0xfe,
5399 0xe0, 0x12, 0x72, 0xf1, 0x01, 0x08, 0x23, 0x72, 0x03, 0x8f, 0xfe, 0xdc,
5400 0x12, 0x25, 0xfe, 0xdc, 0x12, 0x1f, 0xfe, 0xca, 0x12, 0x5e, 0x2b, 0x01,
5401 0x08, 0xfe, 0xd5, 0x10, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b,
5402 0x1c, 0xfe, 0xff, 0x7f, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x03, 0x13,
5403 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0x1c, 0x3d, 0xfe, 0x30, 0x56,
5404 0xfe, 0x00, 0x5c, 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b,
5405 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0xfe, 0x0b, 0x58,
5406 0x03, 0x0a, 0x50, 0x01, 0x82, 0x0a, 0x3f, 0x01, 0x82, 0x03, 0xfc, 0x1c,
5407 0x10, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4, 0x19, 0x48, 0xfe, 0x00,
5408 0x7d, 0xfe, 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c, 0x63, 0x27,
5409 0x0c, 0x52, 0x18, 0x53, 0xbe, 0x56, 0xbf, 0x57, 0x03, 0xfe, 0x62, 0x08,
5410 0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x74, 0x03, 0x01,
5411 0xfe, 0x14, 0x18, 0xfe, 0x42, 0x48, 0x5f, 0x60, 0x89, 0x01, 0x08, 0x1f,
5412 0xfe, 0xa2, 0x14, 0x30, 0x2e, 0xd8, 0x01, 0x08, 0x1f, 0xfe, 0xa2, 0x14,
5413 0x30, 0x2e, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x05, 0xc6, 0x28, 0xfe,
5414 0xcc, 0x12, 0x49, 0x04, 0x1b, 0xfe, 0xc4, 0x13, 0x23, 0x62, 0x1b, 0xe2,
5415 0x4b, 0xc3, 0x64, 0xfe, 0xe8, 0x13, 0x3b, 0x13, 0x06, 0x17, 0xc3, 0x78,
5416 0xdb, 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xa1, 0xff, 0x02, 0x83,
5417 0x55, 0x62, 0x1a, 0xa4, 0xbb, 0xfe, 0x30, 0x00, 0x8e, 0xe4, 0x17, 0x2c,
5418 0x13, 0x06, 0xfe, 0x56, 0x10, 0x62, 0x0b, 0xe1, 0xbb, 0xfe, 0x64, 0x00,
5419 0x8e, 0xe4, 0x0a, 0xfe, 0x64, 0x00, 0x17, 0x93, 0x13, 0x06, 0xfe, 0x28,
5420 0x10, 0x62, 0x06, 0xfe, 0x60, 0x13, 0xbb, 0xfe, 0xc8, 0x00, 0x8e, 0xe4,
5421 0x0a, 0xfe, 0xc8, 0x00, 0x17, 0x4d, 0x13, 0x06, 0x83, 0xbb, 0xfe, 0x90,
5422 0x01, 0xba, 0xfe, 0x4e, 0x14, 0x89, 0xfe, 0x12, 0x10, 0xfe, 0x43, 0xf4,
5423 0x94, 0xfe, 0x56, 0xf0, 0xfe, 0x60, 0x14, 0xfe, 0x04, 0xf4, 0x6c, 0xfe,
5424 0x43, 0xf4, 0x93, 0xfe, 0xf3, 0x10, 0xf9, 0x01, 0xfe, 0x22, 0x13, 0x1c,
5425 0x3d, 0xfe, 0x10, 0x13, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x69, 0xba,
5426 0xfe, 0x9c, 0x14, 0xb7, 0x69, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe,
5427 0x4d, 0xe4, 0x19, 0xba, 0xfe, 0x9c, 0x14, 0xb7, 0x19, 0x83, 0x60, 0x23,
5428 0xfe, 0x4d, 0xf4, 0x00, 0xdf, 0x89, 0x13, 0x06, 0xfe, 0xb4, 0x56, 0xfe,
5429 0xc3, 0x58, 0x03, 0x60, 0x13, 0x0b, 0x03, 0x15, 0x06, 0x01, 0x08, 0x26,
5430 0xe5, 0x15, 0x0b, 0x01, 0x08, 0x26, 0xe5, 0x15, 0x1a, 0x01, 0x08, 0x26,
5431 0xe5, 0x72, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x03, 0x15, 0x06, 0x01, 0x08,
5432 0x26, 0xa6, 0x15, 0x1a, 0x01, 0x08, 0x26, 0xa6, 0x15, 0x06, 0x01, 0x08,
5433 0x26, 0xa6, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x26, 0xa6, 0x72, 0xfe, 0x89,
5434 0x4a, 0x01, 0x08, 0x03, 0x60, 0x03, 0x1e, 0xcc, 0x07, 0x06, 0xfe, 0x44,
5435 0x13, 0xad, 0x12, 0xcc, 0xfe, 0x49, 0xf4, 0x00, 0x3b, 0x72, 0x9f, 0x5e,
5436 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01, 0xf1, 0x01, 0x08, 0x2f, 0x07, 0xfe,
5437 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1f, 0xfe, 0x5a, 0x15, 0x23, 0x12, 0xcd,
5438 0x01, 0x43, 0x1e, 0xcd, 0x07, 0x06, 0x45, 0x09, 0x4a, 0x06, 0x35, 0x03,
5439 0x0a, 0x42, 0x01, 0x0e, 0xed, 0x88, 0x07, 0x10, 0xa4, 0x0a, 0x80, 0x01,
5440 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03, 0x0a, 0x80, 0x01, 0x0e, 0x88,
5441 0xfe, 0x80, 0xe7, 0x10, 0x07, 0x10, 0x84, 0xfe, 0x45, 0x58, 0x01, 0xe3,
5442 0x88, 0x03, 0x0a, 0x42, 0x01, 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03,
5443 0x0a, 0x42, 0x01, 0x0e, 0xfe, 0x80, 0x80, 0xf2, 0xfe, 0x49, 0xe4, 0x10,
5444 0xa4, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x0a, 0x51, 0x01, 0x82, 0x03, 0x17,
5445 0x10, 0x71, 0x66, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde,
5446 0xfe, 0x24, 0x1c, 0xfe, 0x1d, 0xf7, 0x1d, 0x90, 0xfe, 0xf6, 0x15, 0x01,
5447 0xfe, 0xfc, 0x16, 0xe0, 0x91, 0x1d, 0x66, 0xfe, 0x2c, 0x01, 0xfe, 0x2f,
5448 0x19, 0x03, 0xae, 0x21, 0xfe, 0xe6, 0x15, 0xfe, 0xda, 0x10, 0x17, 0x10,
5449 0x71, 0x05, 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x19, 0xfe, 0x18, 0x58,
5450 0x05, 0xfe, 0x66, 0x01, 0xfe, 0x19, 0x58, 0x91, 0x19, 0xfe, 0x3c, 0x90,
5451 0xfe, 0x30, 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x66, 0xfe, 0x38, 0x00, 0xfe,
5452 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x19, 0x90, 0xfe, 0x40, 0x16, 0xfe, 0xb6,
5453 0x14, 0x34, 0x03, 0xae, 0x21, 0xfe, 0x18, 0x16, 0xfe, 0x9c, 0x10, 0x17,
5454 0x10, 0x71, 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe,
5455 0x1d, 0xf7, 0x38, 0x90, 0xfe, 0x62, 0x16, 0xfe, 0x94, 0x14, 0xfe, 0x10,
5456 0x13, 0x91, 0x38, 0x66, 0x1b, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00,
5457 0x03, 0xae, 0x21, 0xfe, 0x56, 0x16, 0xfe, 0x6c, 0x10, 0x17, 0x10, 0x71,
5458 0xfe, 0x30, 0xbc, 0xfe, 0xb2, 0xbc, 0x91, 0xc5, 0x66, 0x1b, 0xfe, 0x0f,
5459 0x79, 0xfe, 0x1c, 0xf7, 0xc5, 0x90, 0xfe, 0x9a, 0x16, 0xfe, 0x5c, 0x14,
5460 0x34, 0x03, 0xae, 0x21, 0xfe, 0x86, 0x16, 0xfe, 0x42, 0x10, 0xfe, 0x02,
5461 0xf6, 0x10, 0x71, 0xfe, 0x18, 0xfe, 0x54, 0xfe, 0x19, 0xfe, 0x55, 0xfc,
5462 0xfe, 0x1d, 0xf7, 0x4f, 0x90, 0xfe, 0xc0, 0x16, 0xfe, 0x36, 0x14, 0xfe,
5463 0x1c, 0x13, 0x91, 0x4f, 0x47, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe,
5464 0x80, 0xe7, 0x10, 0xfe, 0x81, 0xe7, 0x10, 0x11, 0xfe, 0xdd, 0x00, 0x63,
5465 0x27, 0x03, 0x63, 0x27, 0xfe, 0x12, 0x45, 0x21, 0xfe, 0xb0, 0x16, 0x14,
5466 0x06, 0x37, 0x95, 0xa9, 0x02, 0x29, 0xfe, 0x39, 0xf0, 0xfe, 0x04, 0x17,
5467 0x23, 0x03, 0xfe, 0x7e, 0x18, 0x1c, 0x1a, 0x5d, 0x13, 0x0d, 0x03, 0x71,
5468 0x05, 0xcb, 0x1c, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x78, 0x2c,
5469 0x46, 0x2f, 0x07, 0x2d, 0xfe, 0x3c, 0x13, 0xfe, 0x82, 0x14, 0xfe, 0x42,
5470 0x13, 0x3c, 0x8a, 0x0a, 0x42, 0x01, 0x0e, 0xb0, 0xfe, 0x3e, 0x12, 0xf0,
5471 0xfe, 0x45, 0x48, 0x01, 0xe3, 0xfe, 0x00, 0xcc, 0xb0, 0xfe, 0xf3, 0x13,
5472 0x3d, 0x75, 0x07, 0x10, 0xa3, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x01, 0x6f,
5473 0xfe, 0x16, 0x10, 0x07, 0x7e, 0x85, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12,
5474 0xf6, 0xfe, 0xd6, 0xf0, 0xfe, 0x24, 0x17, 0x17, 0x0b, 0x03, 0xfe, 0x9c,
5475 0xe7, 0x0b, 0x0f, 0xfe, 0x15, 0x00, 0x59, 0x76, 0x27, 0x01, 0xda, 0x17,
5476 0x06, 0x03, 0x3c, 0x8a, 0x09, 0x4a, 0x1d, 0x35, 0x11, 0x2d, 0x01, 0x6f,
5477 0x17, 0x06, 0x03, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x79, 0xc7, 0x68,
5478 0xc8, 0xfe, 0x48, 0x55, 0x34, 0xfe, 0xc9, 0x55, 0x03, 0x1e, 0x98, 0x73,
5479 0x12, 0x98, 0x03, 0x0a, 0x99, 0x01, 0x0e, 0xf0, 0x0a, 0x40, 0x01, 0x0e,
5480 0xfe, 0x49, 0x44, 0x16, 0xfe, 0xf0, 0x17, 0x73, 0x75, 0x03, 0x0a, 0x42,
5481 0x01, 0x0e, 0x07, 0x10, 0x45, 0x0a, 0x51, 0x01, 0x9e, 0x0a, 0x40, 0x01,
5482 0x0e, 0x73, 0x75, 0x03, 0xfe, 0x4e, 0xe4, 0x1a, 0x64, 0xfe, 0x24, 0x18,
5483 0x05, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0x5b, 0xfe, 0x4e, 0xe4, 0xc2,
5484 0x64, 0xfe, 0x36, 0x18, 0x05, 0xfe, 0x92, 0x00, 0xfe, 0x02, 0xe6, 0x1b,
5485 0xdc, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x64, 0xfe, 0x48, 0x18, 0x05,
5486 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x19, 0xfe, 0x08, 0x10, 0x05, 0xfe,
5487 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x2c, 0xfe, 0x4e, 0x45, 0xfe, 0x0c, 0x12,
5488 0xaf, 0xff, 0x04, 0x68, 0x54, 0xde, 0x1c, 0x69, 0x03, 0x07, 0x7a, 0xfe,
5489 0x5a, 0xf0, 0xfe, 0x74, 0x18, 0x24, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10,
5490 0x07, 0x1b, 0xfe, 0x5a, 0xf0, 0xfe, 0x82, 0x18, 0x24, 0xc3, 0xfe, 0x26,
5491 0x10, 0x07, 0x1a, 0x5d, 0x24, 0x2c, 0xdc, 0x07, 0x0b, 0x5d, 0x24, 0x93,
5492 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x5d, 0x24, 0x4d, 0x9f, 0xad, 0x03, 0x14,
5493 0xfe, 0x09, 0x00, 0x01, 0x33, 0xfe, 0x04, 0xfe, 0x7d, 0x05, 0x7f, 0xf9,
5494 0x03, 0x25, 0xfe, 0xca, 0x18, 0xfe, 0x14, 0xf0, 0x08, 0x65, 0xfe, 0xc6,
5495 0x18, 0x03, 0xff, 0x1a, 0x00, 0x00,
5498 static unsigned short _adv_asc3550_size = sizeof(_adv_asc3550_buf); /* 0x13AD */
5499 static ADV_DCNT _adv_asc3550_chksum = 0x04D52DDDUL; /* Expanded little-endian checksum. */
5501 /* Microcode buffer is kept after initialization for error recovery. */
5502 static unsigned char _adv_asc38C0800_buf[] = {
5503 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0xfc, 0x00, 0x16, 0x18, 0xe4,
5504 0x01, 0x00, 0x48, 0xe4, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0xce, 0x19,
5505 0x00, 0xfa, 0xff, 0xff, 0x1c, 0x0f, 0x00, 0xf6, 0x9e, 0xe7, 0xff, 0x00,
5506 0x82, 0xe7, 0x00, 0xea, 0x01, 0xfa, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0,
5507 0x01, 0xf6, 0x03, 0x00, 0x04, 0x00, 0x10, 0x00, 0x1e, 0xf0, 0x85, 0xf0,
5508 0x18, 0xf4, 0x08, 0x00, 0xbc, 0x00, 0x38, 0x54, 0x00, 0xec, 0xd5, 0xf0,
5509 0x82, 0x0d, 0x00, 0xe6, 0x86, 0xf0, 0xb1, 0xf0, 0x98, 0x57, 0x01, 0xfc,
5510 0xb4, 0x00, 0xd4, 0x01, 0x0c, 0x1c, 0x3e, 0x1c, 0x3c, 0x00, 0xbb, 0x00,
5511 0x00, 0x10, 0xba, 0x19, 0x02, 0x80, 0x32, 0xf0, 0x7c, 0x0d, 0x02, 0x13,
5512 0xba, 0x13, 0x18, 0x40, 0x00, 0x57, 0x01, 0xea, 0x02, 0xfc, 0x03, 0xfc,
5513 0x3e, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x74, 0x01, 0x76, 0x01, 0xb9, 0x54,
5514 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
5515 0x3e, 0x01, 0x7a, 0x01, 0xca, 0x08, 0xce, 0x10, 0x16, 0x11, 0x04, 0x12,
5516 0x08, 0x12, 0x02, 0x4a, 0xbb, 0x55, 0x3c, 0x56, 0x03, 0x58, 0x1b, 0x80,
5517 0x30, 0xe4, 0x4b, 0xe4, 0x5d, 0xf0, 0x02, 0xfa, 0x20, 0x00, 0x32, 0x00,
5518 0x40, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
5519 0x70, 0x01, 0x72, 0x01, 0x78, 0x01, 0x7c, 0x01, 0x62, 0x0a, 0x86, 0x0d,
5520 0x06, 0x13, 0x4c, 0x1c, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0,
5521 0x03, 0xf7, 0x0c, 0x00, 0x0f, 0x00, 0x47, 0x00, 0xbe, 0x00, 0x00, 0x01,
5522 0x20, 0x11, 0x5c, 0x16, 0x32, 0x1c, 0x38, 0x1c, 0x4e, 0x1c, 0x10, 0x44,
5523 0x00, 0x4c, 0x04, 0xea, 0x5c, 0xf0, 0xa7, 0xf0, 0x04, 0xf6, 0x03, 0xfa,
5524 0x05, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0xcc, 0x00, 0x20, 0x01,
5525 0x4e, 0x01, 0x4a, 0x0b, 0x42, 0x0c, 0x12, 0x0f, 0x0c, 0x10, 0x22, 0x11,
5526 0x0a, 0x12, 0x04, 0x13, 0x30, 0x1c, 0x02, 0x48, 0x00, 0x4e, 0x42, 0x54,
5527 0x44, 0x55, 0xbd, 0x56, 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0,
5528 0x59, 0xf0, 0xb8, 0xf0, 0x4b, 0xf4, 0x06, 0xf7, 0x0e, 0xf7, 0x04, 0xfc,
5529 0x05, 0xfc, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00, 0x9b, 0x00, 0xa4, 0x00,
5530 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00, 0xe2, 0x03,
5531 0x08, 0x0f, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10, 0x0a, 0x13, 0x0c, 0x13,
5532 0x12, 0x13, 0x24, 0x14, 0x34, 0x14, 0x04, 0x16, 0x08, 0x16, 0xa4, 0x17,
5533 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44,
5534 0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x3a, 0x55, 0x83, 0x55,
5535 0xe5, 0x55, 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0,
5536 0x0c, 0xf0, 0x04, 0xf8, 0x05, 0xf8, 0x07, 0x00, 0x0a, 0x00, 0x1c, 0x00,
5537 0x1e, 0x00, 0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00,
5538 0x22, 0x01, 0x26, 0x01, 0x79, 0x01, 0x7e, 0x01, 0xc4, 0x01, 0xc6, 0x01,
5539 0x80, 0x02, 0x5e, 0x03, 0xee, 0x04, 0x9a, 0x06, 0xf8, 0x07, 0x62, 0x08,
5540 0x68, 0x08, 0x69, 0x08, 0xd6, 0x08, 0xe9, 0x09, 0xfa, 0x0b, 0x2e, 0x0f,
5541 0x12, 0x10, 0x1a, 0x10, 0xed, 0x10, 0xf1, 0x10, 0x2a, 0x11, 0x06, 0x12,
5542 0x0c, 0x12, 0x3e, 0x12, 0x10, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x46, 0x14,
5543 0x76, 0x14, 0x82, 0x14, 0x36, 0x15, 0xca, 0x15, 0x6b, 0x18, 0xbe, 0x18,
5544 0xca, 0x18, 0xe6, 0x19, 0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40,
5545 0x0e, 0x47, 0xfe, 0x9c, 0xf0, 0x2b, 0x02, 0xfe, 0xac, 0x0d, 0xff, 0x10,
5546 0x00, 0x00, 0xd7, 0xfe, 0xe8, 0x19, 0x00, 0xd6, 0xfe, 0x84, 0x01, 0xff,
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5842 0x31, 0xdf, 0x07, 0x06, 0x23, 0x4c, 0x01, 0xf1, 0xfe, 0x42, 0x58, 0xf1,
5843 0xfe, 0xa4, 0x14, 0x8c, 0xfe, 0x4a, 0xf4, 0x0a, 0x17, 0x4c, 0xfe, 0x4a,
5844 0xf4, 0x06, 0xea, 0x32, 0x07, 0xa5, 0x8b, 0x02, 0x72, 0x03, 0x45, 0xc1,
5845 0x0c, 0x45, 0x67, 0x2d, 0x01, 0x0b, 0x26, 0x89, 0x01, 0xfe, 0xcc, 0x15,
5846 0x02, 0x89, 0x0f, 0x06, 0x27, 0xfe, 0xbe, 0x13, 0x26, 0xfe, 0xd4, 0x13,
5847 0x76, 0xfe, 0x89, 0x48, 0x01, 0x0b, 0x21, 0x76, 0x04, 0x7b, 0xfe, 0xd0,
5848 0x13, 0x1c, 0xfe, 0xd0, 0x13, 0x1d, 0xfe, 0xbe, 0x13, 0x67, 0x2d, 0x01,
5849 0x0b, 0xfe, 0xd5, 0x10, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93,
5850 0x1e, 0xfe, 0xff, 0x7f, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x04, 0x0f,
5851 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, 0x1e, 0x43, 0xfe, 0x30, 0x56,
5852 0xfe, 0x00, 0x5c, 0x04, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93,
5853 0x04, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, 0xfe, 0x0b, 0x58,
5854 0x04, 0x09, 0x5c, 0x01, 0x87, 0x09, 0x45, 0x01, 0x87, 0x04, 0xfe, 0x03,
5855 0xa1, 0x1e, 0x11, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4, 0x1f, 0x52,
5856 0xfe, 0x00, 0x7d, 0xfe, 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c,
5857 0x6a, 0x2a, 0x0c, 0x5e, 0x14, 0x5f, 0x57, 0x3f, 0x7d, 0x40, 0x04, 0xdd,
5858 0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x8d, 0x04, 0x01,
5859 0xfe, 0x0c, 0x19, 0xfe, 0x42, 0x48, 0x50, 0x51, 0x91, 0x01, 0x0b, 0x1d,
5860 0xfe, 0x96, 0x15, 0x33, 0x31, 0xe1, 0x01, 0x0b, 0x1d, 0xfe, 0x96, 0x15,
5861 0x33, 0x31, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x03, 0xcd, 0x28, 0xfe,
5862 0xcc, 0x12, 0x53, 0x05, 0x1a, 0xfe, 0xc4, 0x13, 0x21, 0x69, 0x1a, 0xee,
5863 0x55, 0xca, 0x6b, 0xfe, 0xdc, 0x14, 0x4d, 0x0f, 0x06, 0x18, 0xca, 0x7c,
5864 0x30, 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xab, 0xff, 0x02, 0x83,
5865 0x55, 0x69, 0x19, 0xae, 0x98, 0xfe, 0x30, 0x00, 0x96, 0xf2, 0x18, 0x6d,
5866 0x0f, 0x06, 0xfe, 0x56, 0x10, 0x69, 0x0a, 0xed, 0x98, 0xfe, 0x64, 0x00,
5867 0x96, 0xf2, 0x09, 0xfe, 0x64, 0x00, 0x18, 0x9e, 0x0f, 0x06, 0xfe, 0x28,
5868 0x10, 0x69, 0x06, 0xfe, 0x60, 0x13, 0x98, 0xfe, 0xc8, 0x00, 0x96, 0xf2,
5869 0x09, 0xfe, 0xc8, 0x00, 0x18, 0x59, 0x0f, 0x06, 0x88, 0x98, 0xfe, 0x90,
5870 0x01, 0x7a, 0xfe, 0x42, 0x15, 0x91, 0xe4, 0xfe, 0x43, 0xf4, 0x9f, 0xfe,
5871 0x56, 0xf0, 0xfe, 0x54, 0x15, 0xfe, 0x04, 0xf4, 0x71, 0xfe, 0x43, 0xf4,
5872 0x9e, 0xfe, 0xf3, 0x10, 0xfe, 0x40, 0x5c, 0x01, 0xfe, 0x16, 0x14, 0x1e,
5873 0x43, 0xec, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x6e, 0x7a, 0xfe, 0x90,
5874 0x15, 0xc4, 0x6e, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4,
5875 0xcc, 0x7a, 0xfe, 0x90, 0x15, 0xc4, 0xcc, 0x88, 0x51, 0x21, 0xfe, 0x4d,
5876 0xf4, 0x00, 0xe9, 0x91, 0x0f, 0x06, 0xfe, 0xb4, 0x56, 0xfe, 0xc3, 0x58,
5877 0x04, 0x51, 0x0f, 0x0a, 0x04, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xf3, 0x16,
5878 0x0a, 0x01, 0x0b, 0x26, 0xf3, 0x16, 0x19, 0x01, 0x0b, 0x26, 0xf3, 0x76,
5879 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x04, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1,
5880 0x16, 0x19, 0x01, 0x0b, 0x26, 0xb1, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1,
5881 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x26, 0xb1, 0x76, 0xfe, 0x89, 0x4a, 0x01,
5882 0x0b, 0x04, 0x51, 0x04, 0x22, 0xd3, 0x07, 0x06, 0xfe, 0x48, 0x13, 0xb8,
5883 0x13, 0xd3, 0xfe, 0x49, 0xf4, 0x00, 0x4d, 0x76, 0xa9, 0x67, 0xfe, 0x01,
5884 0xec, 0xfe, 0x27, 0x01, 0xfe, 0x89, 0x48, 0xff, 0x02, 0x00, 0x10, 0x27,
5885 0xfe, 0x2e, 0x16, 0x32, 0x07, 0xfe, 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1d,
5886 0xfe, 0x52, 0x16, 0x21, 0x13, 0xd4, 0x01, 0x4b, 0x22, 0xd4, 0x07, 0x06,
5887 0x4e, 0x08, 0x54, 0x06, 0x37, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfb, 0x8e,
5888 0x07, 0x11, 0xae, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0x09, 0x5d, 0x01, 0xa8,
5889 0x04, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0xfe, 0x80, 0xe7, 0x11, 0x07, 0x11,
5890 0x8a, 0xfe, 0x45, 0x58, 0x01, 0xf0, 0x8e, 0x04, 0x09, 0x48, 0x01, 0x0e,
5891 0x8e, 0x09, 0x5d, 0x01, 0xa8, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfe, 0x80,
5892 0x80, 0xfe, 0x80, 0x4c, 0xfe, 0x49, 0xe4, 0x11, 0xae, 0x09, 0x84, 0x01,
5893 0x0e, 0xfe, 0x80, 0x4c, 0x09, 0x5d, 0x01, 0x87, 0x04, 0x18, 0x11, 0x75,
5894 0x6c, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24,
5895 0x1c, 0xfe, 0x1d, 0xf7, 0x1b, 0x97, 0xfe, 0xee, 0x16, 0x01, 0xfe, 0xf4,
5896 0x17, 0xad, 0x9a, 0x1b, 0x6c, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x04,
5897 0xb9, 0x23, 0xfe, 0xde, 0x16, 0xfe, 0xda, 0x10, 0x18, 0x11, 0x75, 0x03,
5898 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x1f, 0xfe, 0x18, 0x58, 0x03, 0xfe,
5899 0x66, 0x01, 0xfe, 0x19, 0x58, 0x9a, 0x1f, 0xfe, 0x3c, 0x90, 0xfe, 0x30,
5900 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x6c, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79,
5901 0xfe, 0x1c, 0xf7, 0x1f, 0x97, 0xfe, 0x38, 0x17, 0xfe, 0xb6, 0x14, 0x35,
5902 0x04, 0xb9, 0x23, 0xfe, 0x10, 0x17, 0xfe, 0x9c, 0x10, 0x18, 0x11, 0x75,
5903 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7,
5904 0x2e, 0x97, 0xfe, 0x5a, 0x17, 0xfe, 0x94, 0x14, 0xec, 0x9a, 0x2e, 0x6c,
5905 0x1a, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00, 0x04, 0xb9, 0x23, 0xfe,
5906 0x4e, 0x17, 0xfe, 0x6c, 0x10, 0x18, 0x11, 0x75, 0xfe, 0x30, 0xbc, 0xfe,
5907 0xb2, 0xbc, 0x9a, 0xcb, 0x6c, 0x1a, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7,
5908 0xcb, 0x97, 0xfe, 0x92, 0x17, 0xfe, 0x5c, 0x14, 0x35, 0x04, 0xb9, 0x23,
5909 0xfe, 0x7e, 0x17, 0xfe, 0x42, 0x10, 0xfe, 0x02, 0xf6, 0x11, 0x75, 0xfe,
5910 0x18, 0xfe, 0x60, 0xfe, 0x19, 0xfe, 0x61, 0xfe, 0x03, 0xa1, 0xfe, 0x1d,
5911 0xf7, 0x5b, 0x97, 0xfe, 0xb8, 0x17, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13,
5912 0x9a, 0x5b, 0x41, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7,
5913 0x11, 0xfe, 0x81, 0xe7, 0x11, 0x12, 0xfe, 0xdd, 0x00, 0x6a, 0x2a, 0x04,
5914 0x6a, 0x2a, 0xfe, 0x12, 0x45, 0x23, 0xfe, 0xa8, 0x17, 0x15, 0x06, 0x39,
5915 0xa0, 0xb4, 0x02, 0x2b, 0xfe, 0x39, 0xf0, 0xfe, 0xfc, 0x17, 0x21, 0x04,
5916 0xfe, 0x7e, 0x18, 0x1e, 0x19, 0x66, 0x0f, 0x0d, 0x04, 0x75, 0x03, 0xd2,
5917 0x1e, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x7c, 0x6f, 0x4f, 0x32,
5918 0x07, 0x2f, 0xfe, 0x3c, 0x13, 0xf1, 0xfe, 0x42, 0x13, 0x42, 0x92, 0x09,
5919 0x48, 0x01, 0x0e, 0xbb, 0xeb, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01,
5920 0xf0, 0xfe, 0x00, 0xcc, 0xbb, 0xfe, 0xf3, 0x13, 0x43, 0x78, 0x07, 0x11,
5921 0xac, 0x09, 0x84, 0x01, 0x0e, 0xfe, 0x80, 0x4c, 0x01, 0x73, 0xfe, 0x16,
5922 0x10, 0x07, 0x82, 0x8b, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12, 0xfe, 0x14,
5923 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x1c, 0x18, 0x18, 0x0a, 0x04, 0xfe, 0x9c,
5924 0xe7, 0x0a, 0x10, 0xfe, 0x15, 0x00, 0x64, 0x79, 0x2a, 0x01, 0xe3, 0x18,
5925 0x06, 0x04, 0x42, 0x92, 0x08, 0x54, 0x1b, 0x37, 0x12, 0x2f, 0x01, 0x73,
5926 0x18, 0x06, 0x04, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x3a, 0xce, 0x3b,
5927 0xcf, 0xfe, 0x48, 0x55, 0x35, 0xfe, 0xc9, 0x55, 0x04, 0x22, 0xa3, 0x77,
5928 0x13, 0xa3, 0x04, 0x09, 0xa4, 0x01, 0x0e, 0xfe, 0x41, 0x48, 0x09, 0x46,
5929 0x01, 0x0e, 0xfe, 0x49, 0x44, 0x17, 0xfe, 0xe8, 0x18, 0x77, 0x78, 0x04,
5930 0x09, 0x48, 0x01, 0x0e, 0x07, 0x11, 0x4e, 0x09, 0x5d, 0x01, 0xa8, 0x09,
5931 0x46, 0x01, 0x0e, 0x77, 0x78, 0x04, 0xfe, 0x4e, 0xe4, 0x19, 0x6b, 0xfe,
5932 0x1c, 0x19, 0x03, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10,
5933 0xfe, 0x4e, 0xe4, 0xc9, 0x6b, 0xfe, 0x2e, 0x19, 0x03, 0xfe, 0x92, 0x00,
5934 0xfe, 0x02, 0xe6, 0x1a, 0xe5, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x6b,
5935 0xfe, 0x40, 0x19, 0x03, 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x1f, 0xfe,
5936 0x08, 0x10, 0x03, 0xfe, 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x6d, 0xfe, 0x4e,
5937 0x45, 0xea, 0xba, 0xff, 0x04, 0x68, 0x54, 0xe7, 0x1e, 0x6e, 0xfe, 0x08,
5938 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c, 0xfe, 0x1a, 0xf4, 0xfe, 0x00,
5939 0x04, 0xea, 0xfe, 0x48, 0xf4, 0x19, 0x7a, 0xfe, 0x74, 0x19, 0x0f, 0x19,
5940 0x04, 0x07, 0x7e, 0xfe, 0x5a, 0xf0, 0xfe, 0x84, 0x19, 0x25, 0xfe, 0x09,
5941 0x00, 0xfe, 0x34, 0x10, 0x07, 0x1a, 0xfe, 0x5a, 0xf0, 0xfe, 0x92, 0x19,
5942 0x25, 0xca, 0xfe, 0x26, 0x10, 0x07, 0x19, 0x66, 0x25, 0x6d, 0xe5, 0x07,
5943 0x0a, 0x66, 0x25, 0x9e, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x66, 0x25, 0x59,
5944 0xa9, 0xb8, 0x04, 0x15, 0xfe, 0x09, 0x00, 0x01, 0x36, 0xfe, 0x04, 0xfe,
5945 0x81, 0x03, 0x83, 0xfe, 0x40, 0x5c, 0x04, 0x1c, 0xf7, 0xfe, 0x14, 0xf0,
5946 0x0b, 0x27, 0xfe, 0xd6, 0x19, 0x1c, 0xf7, 0x7b, 0xf7, 0xfe, 0x82, 0xf0,
5947 0xfe, 0xda, 0x19, 0x04, 0xff, 0xcc, 0x00, 0x00,
5950 static unsigned short _adv_asc38C0800_size = sizeof(_adv_asc38C0800_buf); /* 0x14E1 */
5951 static ADV_DCNT _adv_asc38C0800_chksum = 0x050D3FD8UL; /* Expanded little-endian checksum. */
5953 /* Microcode buffer is kept after initialization for error recovery. */
5954 static unsigned char _adv_asc38C1600_buf[] = {
5955 0x00, 0x00, 0x00, 0xf2, 0x00, 0x16, 0x00, 0xfc, 0x00, 0x10, 0x00, 0xf0,
5956 0x18, 0xe4, 0x01, 0x00, 0x04, 0x1e, 0x48, 0xe4, 0x03, 0xf6, 0xf7, 0x13,
5957 0x2e, 0x1e, 0x02, 0x00, 0x07, 0x17, 0xc0, 0x5f, 0x00, 0xfa, 0xff, 0xff,
5958 0x04, 0x00, 0x00, 0xf6, 0x09, 0xe7, 0x82, 0xe7, 0x85, 0xf0, 0x86, 0xf0,
5959 0x4e, 0x10, 0x9e, 0xe7, 0xff, 0x00, 0x55, 0xf0, 0x01, 0xf6, 0x03, 0x00,
5960 0x98, 0x57, 0x01, 0xe6, 0x00, 0xea, 0x00, 0xec, 0x01, 0xfa, 0x18, 0xf4,
5961 0x08, 0x00, 0xf0, 0x1d, 0x38, 0x54, 0x32, 0xf0, 0x10, 0x00, 0xc2, 0x0e,
5962 0x1e, 0xf0, 0xd5, 0xf0, 0xbc, 0x00, 0x4b, 0xe4, 0x00, 0xe6, 0xb1, 0xf0,
5963 0xb4, 0x00, 0x02, 0x13, 0x3e, 0x1c, 0xc8, 0x47, 0x3e, 0x00, 0xd8, 0x01,
5964 0x06, 0x13, 0x0c, 0x1c, 0x5e, 0x1e, 0x00, 0x57, 0xc8, 0x57, 0x01, 0xfc,
5965 0xbc, 0x0e, 0xa2, 0x12, 0xb9, 0x54, 0x00, 0x80, 0x62, 0x0a, 0x5a, 0x12,
5966 0xc8, 0x15, 0x3e, 0x1e, 0x18, 0x40, 0xbd, 0x56, 0x03, 0xe6, 0x01, 0xea,
5967 0x5c, 0xf0, 0x0f, 0x00, 0x20, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12,
5968 0x04, 0x13, 0xbb, 0x55, 0x3c, 0x56, 0x3e, 0x57, 0x03, 0x58, 0x4a, 0xe4,
5969 0x40, 0x00, 0xb6, 0x00, 0xbb, 0x00, 0xc0, 0x00, 0x00, 0x01, 0x01, 0x01,
5970 0x3e, 0x01, 0x58, 0x0a, 0x44, 0x10, 0x0a, 0x12, 0x4c, 0x1c, 0x4e, 0x1c,
5971 0x02, 0x4a, 0x30, 0xe4, 0x05, 0xe6, 0x0c, 0x00, 0x3c, 0x00, 0x80, 0x00,
5972 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01,
5973 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x7c, 0x01, 0xc6, 0x0e, 0x0c, 0x10,
5974 0xac, 0x12, 0xae, 0x12, 0x16, 0x1a, 0x32, 0x1c, 0x6e, 0x1e, 0x02, 0x48,
5975 0x3a, 0x55, 0xc9, 0x57, 0x02, 0xee, 0x5b, 0xf0, 0x03, 0xf7, 0x06, 0xf7,
5976 0x03, 0xfc, 0x06, 0x00, 0x1e, 0x00, 0xbe, 0x00, 0xe1, 0x00, 0x0c, 0x12,
5977 0x18, 0x1a, 0x70, 0x1a, 0x30, 0x1c, 0x38, 0x1c, 0x10, 0x44, 0x00, 0x4c,
5978 0xb0, 0x57, 0x40, 0x5c, 0x4d, 0xe4, 0x04, 0xea, 0x5d, 0xf0, 0xa7, 0xf0,
5979 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x09, 0x00, 0x19, 0x00, 0x32, 0x00,
5980 0x33, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0x9e, 0x00, 0xcc, 0x00,
5981 0x20, 0x01, 0x4e, 0x01, 0x79, 0x01, 0x3c, 0x09, 0x68, 0x0d, 0x02, 0x10,
5982 0x04, 0x10, 0x3a, 0x10, 0x08, 0x12, 0x0a, 0x13, 0x40, 0x16, 0x50, 0x16,
5983 0x00, 0x17, 0x4a, 0x19, 0x00, 0x4e, 0x00, 0x54, 0x01, 0x58, 0x00, 0xdc,
5984 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xb8, 0xf0, 0x48, 0xf4, 0x0e, 0xf7,
5985 0x0a, 0x00, 0x9b, 0x00, 0x9c, 0x00, 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00,
5986 0xd0, 0x00, 0xe7, 0x00, 0xf0, 0x03, 0x69, 0x08, 0xe9, 0x09, 0x5c, 0x0c,
5987 0xb6, 0x12, 0xbc, 0x19, 0xd8, 0x1b, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c,
5988 0x42, 0x1d, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46,
5989 0x89, 0x48, 0x68, 0x54, 0x83, 0x55, 0x83, 0x59, 0x31, 0xe4, 0x02, 0xe6,
5990 0x07, 0xf0, 0x08, 0xf0, 0x0b, 0xf0, 0x0c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8,
5991 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa, 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00,
5992 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0xe5, 0x00, 0x22, 0x01,
5993 0x26, 0x01, 0x60, 0x01, 0x7a, 0x01, 0x82, 0x01, 0xc8, 0x01, 0xca, 0x01,
5994 0x86, 0x02, 0x6a, 0x03, 0x18, 0x05, 0xb2, 0x07, 0x68, 0x08, 0x10, 0x0d,
5995 0x06, 0x10, 0x0a, 0x10, 0x0e, 0x10, 0x12, 0x10, 0x60, 0x10, 0xed, 0x10,
5996 0xf3, 0x10, 0x06, 0x12, 0x10, 0x12, 0x1e, 0x12, 0x0c, 0x13, 0x0e, 0x13,
5997 0x10, 0x13, 0xfe, 0x9c, 0xf0, 0x35, 0x05, 0xfe, 0xec, 0x0e, 0xff, 0x10,
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6442 0x01, 0xf4, 0x1c, 0x07, 0x02, 0x51, 0xfe, 0x06, 0x83, 0xfe, 0x18, 0x80,
6443 0x61, 0x28, 0x44, 0x15, 0x56, 0x01, 0x85, 0x1c, 0x07, 0x02, 0xfe, 0x38,
6444 0x90, 0xfe, 0xba, 0x90, 0x91, 0xde, 0x7e, 0xdf, 0xfe, 0x48, 0x55, 0x31,
6445 0xfe, 0xc9, 0x55, 0x02, 0x21, 0xb9, 0x88, 0x20, 0xb9, 0x02, 0x0a, 0xba,
6446 0x01, 0x18, 0xfe, 0x41, 0x48, 0x0a, 0x57, 0x01, 0x18, 0xfe, 0x49, 0x44,
6447 0x1b, 0xfe, 0x1e, 0x1d, 0x88, 0x89, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0x09,
6448 0x1a, 0xa4, 0x0a, 0x67, 0x01, 0xa3, 0x0a, 0x57, 0x01, 0x18, 0x88, 0x89,
6449 0x02, 0xfe, 0x4e, 0xe4, 0x1d, 0x7b, 0xfe, 0x52, 0x1d, 0x03, 0xfe, 0x90,
6450 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10, 0xfe, 0x4e, 0xe4, 0xdd, 0x7b,
6451 0xfe, 0x64, 0x1d, 0x03, 0xfe, 0x92, 0x00, 0xd1, 0x12, 0xfe, 0x1a, 0x10,
6452 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x7b, 0xfe, 0x76, 0x1d, 0x03, 0xfe,
6453 0x94, 0x00, 0xd1, 0x24, 0xfe, 0x08, 0x10, 0x03, 0xfe, 0x96, 0x00, 0xd1,
6454 0x63, 0xfe, 0x4e, 0x45, 0x83, 0xca, 0xff, 0x04, 0x68, 0x54, 0xfe, 0xf1,
6455 0x10, 0x23, 0x49, 0xfe, 0x08, 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c,
6456 0xfe, 0x1a, 0xf4, 0xfe, 0x00, 0x04, 0x83, 0xb2, 0x1d, 0x48, 0xfe, 0xaa,
6457 0x1d, 0x13, 0x1d, 0x02, 0x09, 0x92, 0xfe, 0x5a, 0xf0, 0xfe, 0xba, 0x1d,
6458 0x2e, 0x93, 0xfe, 0x34, 0x10, 0x09, 0x12, 0xfe, 0x5a, 0xf0, 0xfe, 0xc8,
6459 0x1d, 0x2e, 0xb4, 0xfe, 0x26, 0x10, 0x09, 0x1d, 0x36, 0x2e, 0x63, 0xfe,
6460 0x1a, 0x10, 0x09, 0x0d, 0x36, 0x2e, 0x94, 0xf2, 0x09, 0x07, 0x36, 0x2e,
6461 0x95, 0xa1, 0xc8, 0x02, 0x1f, 0x93, 0x01, 0x42, 0xfe, 0x04, 0xfe, 0x99,
6462 0x03, 0x9c, 0x8b, 0x02, 0x2a, 0xfe, 0x1c, 0x1e, 0xfe, 0x14, 0xf0, 0x08,
6463 0x2f, 0xfe, 0x0c, 0x1e, 0x2a, 0xfe, 0x1c, 0x1e, 0x8f, 0xfe, 0x1c, 0x1e,
6464 0xfe, 0x82, 0xf0, 0xfe, 0x10, 0x1e, 0x02, 0x0f, 0x3f, 0x04, 0xfe, 0x80,
6465 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x18, 0x80, 0x04, 0xfe, 0x98,
6466 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x02, 0x80, 0x04, 0xfe, 0x82,
6467 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, 0x80, 0x04, 0xfe, 0x86,
6468 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x1b, 0x80, 0x04, 0xfe, 0x9b,
6469 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x04, 0x80, 0x04, 0xfe, 0x84,
6470 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x80, 0x80, 0x04, 0xfe, 0x80,
6471 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x19, 0x81, 0x04,
6472 0xfe, 0x99, 0x83, 0xfe, 0xca, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06,
6473 0x83, 0x04, 0xfe, 0x86, 0x83, 0xfe, 0xce, 0x47, 0x0b, 0x0e, 0x02, 0x0f,
6474 0xfe, 0x2c, 0x90, 0x04, 0xfe, 0xac, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6475 0xfe, 0xae, 0x90, 0x04, 0xfe, 0xae, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6476 0xfe, 0x08, 0x90, 0x04, 0xfe, 0x88, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6477 0xfe, 0x8a, 0x90, 0x04, 0xfe, 0x8a, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6478 0xfe, 0x0c, 0x90, 0x04, 0xfe, 0x8c, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
6479 0xfe, 0x8e, 0x90, 0x04, 0xfe, 0x8e, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f,
6480 0xfe, 0x3c, 0x90, 0x04, 0xfe, 0xbc, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x8b,
6481 0x0f, 0xfe, 0x03, 0x80, 0x04, 0xfe, 0x83, 0x83, 0x33, 0x0b, 0x77, 0x0e,
6482 0xa8, 0x02, 0xff, 0x66, 0x00, 0x00,
6485 static unsigned short _adv_asc38C1600_size = sizeof(_adv_asc38C1600_buf); /* 0x1673 */
6486 static ADV_DCNT _adv_asc38C1600_chksum = 0x0604EF77UL; /* Expanded little-endian checksum. */
6488 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
6494 iop_base = asc_dvc->iop_base;
6495 AscPutRiscVarFreeQHead(iop_base, 1);
6496 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
6497 AscPutVarFreeQHead(iop_base, 1);
6498 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
6499 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
6500 (uchar)((int)asc_dvc->max_total_qng + 1));
6501 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
6502 (uchar)((int)asc_dvc->max_total_qng + 2));
6503 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
6504 asc_dvc->max_total_qng);
6505 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
6506 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6507 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
6508 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
6509 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
6510 AscPutQDoneInProgress(iop_base, 0);
6511 lram_addr = ASC_QADR_BEG;
6512 for (i = 0; i < 32; i++, lram_addr += 2) {
6513 AscWriteLramWord(iop_base, lram_addr, 0);
6517 static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
6525 iop_base = asc_dvc->iop_base;
6527 for (i = 0; i <= ASC_MAX_TID; i++) {
6528 AscPutMCodeInitSDTRAtID(iop_base, i,
6529 asc_dvc->cfg->sdtr_period_offset[i]);
6532 AscInitQLinkVar(asc_dvc);
6533 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
6534 asc_dvc->cfg->disc_enable);
6535 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
6536 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
6538 /* Align overrun buffer on an 8 byte boundary. */
6539 phy_addr = virt_to_bus(asc_dvc->cfg->overrun_buf);
6540 phy_addr = cpu_to_le32((phy_addr + 7) & ~0x7);
6541 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
6542 (uchar *)&phy_addr, 1);
6543 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE - 8);
6544 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
6545 (uchar *)&phy_size, 1);
6547 asc_dvc->cfg->mcode_date =
6548 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
6549 asc_dvc->cfg->mcode_version =
6550 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
6552 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
6553 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
6554 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
6557 if (AscStartChip(iop_base) != 1) {
6558 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
6565 static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
6570 iop_base = asc_dvc->iop_base;
6572 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
6573 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
6574 AscResetChipAndScsiBus(asc_dvc);
6575 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
6577 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
6578 if (asc_dvc->err_code != 0)
6580 if (!AscFindSignature(asc_dvc->iop_base)) {
6581 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
6584 AscDisableInterrupt(iop_base);
6585 warn_code |= AscInitLram(asc_dvc);
6586 if (asc_dvc->err_code != 0)
6588 ASC_DBG1(1, "AscInitAsc1000Driver: _asc_mcode_chksum 0x%lx\n",
6589 (ulong)_asc_mcode_chksum);
6590 if (AscLoadMicroCode(iop_base, 0, _asc_mcode_buf,
6591 _asc_mcode_size) != _asc_mcode_chksum) {
6592 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
6595 warn_code |= AscInitMicroCodeVar(asc_dvc);
6596 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
6597 AscEnableInterrupt(iop_base);
6602 * Load the Microcode
6604 * Write the microcode image to RISC memory starting at address 0.
6606 * The microcode is stored compressed in the following format:
6608 * 254 word (508 byte) table indexed by byte code followed
6609 * by the following byte codes:
6612 * 00: Emit word 0 in table.
6613 * 01: Emit word 1 in table.
6615 * FD: Emit word 253 in table.
6618 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
6619 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
6621 * Returns 0 or an error if the checksum doesn't match
6623 static int AdvLoadMicrocode(AdvPortAddr iop_base, unsigned char *buf, int size,
6624 int memsize, int chksum)
6626 int i, j, end, len = 0;
6629 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
6631 for (i = 253 * 2; i < size; i++) {
6632 if (buf[i] == 0xff) {
6633 unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
6634 for (j = 0; j < buf[i + 1]; j++) {
6635 AdvWriteWordAutoIncLram(iop_base, word);
6639 } else if (buf[i] == 0xfe) {
6640 unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
6641 AdvWriteWordAutoIncLram(iop_base, word);
6645 unsigned char off = buf[i] * 2;
6646 unsigned short word = (buf[off + 1] << 8) | buf[off];
6647 AdvWriteWordAutoIncLram(iop_base, word);
6654 while (len < memsize) {
6655 AdvWriteWordAutoIncLram(iop_base, 0);
6659 /* Verify the microcode checksum. */
6661 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
6663 for (len = 0; len < end; len += 2) {
6664 sum += AdvReadWordAutoIncLram(iop_base);
6668 return ASC_IERR_MCODE_CHKSUM;
6676 * Return the physical address of 'vaddr' and set '*lenp' to the
6677 * number of physically contiguous bytes that follow 'vaddr'.
6678 * 'flag' indicates the type of structure whose physical address
6679 * is being translated.
6681 * Note: Because Linux currently doesn't page the kernel and all
6682 * kernel buffers are physically contiguous, leave '*lenp' unchanged.
6685 DvcGetPhyAddr(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq,
6686 uchar *vaddr, ADV_SDCNT *lenp, int flag)
6688 ADV_PADDR paddr = virt_to_bus(vaddr);
6690 ASC_DBG4(4, "DvcGetPhyAddr: vaddr 0x%p, lenp 0x%p *lenp %lu, paddr 0x%lx\n",
6691 vaddr, lenp, (ulong)*((ulong *)lenp), (ulong)paddr);
6696 static void AdvBuildCarrierFreelist(struct adv_dvc_var *asc_dvc)
6700 ADV_PADDR carr_paddr;
6702 BUG_ON(!asc_dvc->carrier_buf);
6704 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
6705 asc_dvc->carr_freelist = NULL;
6706 if (carrp == asc_dvc->carrier_buf) {
6707 buf_size = ADV_CARRIER_BUFSIZE;
6709 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
6713 /* Get physical address of the carrier 'carrp'. */
6714 ADV_DCNT contig_len = sizeof(ADV_CARR_T);
6715 carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL,
6717 (ADV_SDCNT *)&contig_len,
6718 ADV_IS_CARRIER_FLAG));
6720 buf_size -= sizeof(ADV_CARR_T);
6723 * If the current carrier is not physically contiguous, then
6724 * maybe there was a page crossing. Try the next carrier
6725 * aligned start address.
6727 if (contig_len < sizeof(ADV_CARR_T)) {
6732 carrp->carr_pa = carr_paddr;
6733 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
6736 * Insert the carrier at the beginning of the freelist.
6739 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
6740 asc_dvc->carr_freelist = carrp;
6743 } while (buf_size > 0);
6747 * Send an idle command to the chip and wait for completion.
6749 * Command completion is polled for once per microsecond.
6751 * The function can be called from anywhere including an interrupt handler.
6752 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
6753 * functions to prevent reentrancy.
6756 * ADV_TRUE - command completed successfully
6757 * ADV_FALSE - command failed
6758 * ADV_ERROR - command timed out
6761 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
6762 ushort idle_cmd, ADV_DCNT idle_cmd_parameter)
6766 AdvPortAddr iop_base;
6768 iop_base = asc_dvc->iop_base;
6771 * Clear the idle command status which is set by the microcode
6772 * to a non-zero value to indicate when the command is completed.
6773 * The non-zero result is one of the IDLE_CMD_STATUS_* values
6775 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
6778 * Write the idle command value after the idle command parameter
6779 * has been written to avoid a race condition. If the order is not
6780 * followed, the microcode may process the idle command before the
6781 * parameters have been written to LRAM.
6783 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
6784 cpu_to_le32(idle_cmd_parameter));
6785 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
6788 * Tickle the RISC to tell it to process the idle command.
6790 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
6791 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6793 * Clear the tickle value. In the ASC-3550 the RISC flag
6794 * command 'clr_tickle_b' does not work unless the host
6797 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
6800 /* Wait for up to 100 millisecond for the idle command to timeout. */
6801 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
6802 /* Poll once each microsecond for command completion. */
6803 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
6804 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
6812 BUG(); /* The idle command should never timeout. */
6817 * Reset SCSI Bus and purge all outstanding requests.
6820 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
6821 * ADV_FALSE(0) - Microcode command failed.
6822 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
6823 * may be hung which requires driver recovery.
6825 static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
6830 * Send the SCSI Bus Reset idle start idle command which asserts
6831 * the SCSI Bus Reset signal.
6833 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
6834 if (status != ADV_TRUE) {
6839 * Delay for the specified SCSI Bus Reset hold time.
6841 * The hold time delay is done on the host because the RISC has no
6842 * microsecond accurate timer.
6844 udelay(ASC_SCSI_RESET_HOLD_TIME_US);
6847 * Send the SCSI Bus Reset end idle command which de-asserts
6848 * the SCSI Bus Reset signal and purges any pending requests.
6850 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
6851 if (status != ADV_TRUE) {
6855 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
6861 * Initialize the ASC-3550.
6863 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
6865 * For a non-fatal error return a warning code. If there are no warnings
6866 * then 0 is returned.
6868 * Needed after initialization for error recovery.
6870 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
6872 AdvPortAddr iop_base;
6881 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
6882 ushort wdtr_able = 0, sdtr_able, tagqng_able;
6883 uchar max_cmd[ADV_MAX_TID + 1];
6885 /* If there is already an error, don't continue. */
6886 if (asc_dvc->err_code != 0)
6890 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
6892 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
6893 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
6898 iop_base = asc_dvc->iop_base;
6901 * Save the RISC memory BIOS region before writing the microcode.
6902 * The BIOS may already be loaded and using its RISC LRAM region
6903 * so its region must be saved and restored.
6905 * Note: This code makes the assumption, which is currently true,
6906 * that a chip reset does not clear RISC LRAM.
6908 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
6909 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
6914 * Save current per TID negotiated values.
6916 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
6917 ushort bios_version, major, minor;
6920 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
6921 major = (bios_version >> 12) & 0xF;
6922 minor = (bios_version >> 8) & 0xF;
6923 if (major < 3 || (major == 3 && minor == 1)) {
6924 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
6925 AdvReadWordLram(iop_base, 0x120, wdtr_able);
6927 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6930 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6931 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
6932 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6933 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
6937 asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc3550_buf,
6938 _adv_asc3550_size, ADV_3550_MEMSIZE,
6939 _adv_asc3550_chksum);
6940 if (asc_dvc->err_code)
6944 * Restore the RISC memory BIOS region.
6946 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
6947 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
6952 * Calculate and write the microcode code checksum to the microcode
6953 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
6955 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
6956 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
6958 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
6959 for (word = begin_addr; word < end_addr; word += 2) {
6960 code_sum += AdvReadWordAutoIncLram(iop_base);
6962 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
6965 * Read and save microcode version and date.
6967 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
6968 asc_dvc->cfg->mcode_date);
6969 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
6970 asc_dvc->cfg->mcode_version);
6973 * Set the chip type to indicate the ASC3550.
6975 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
6978 * If the PCI Configuration Command Register "Parity Error Response
6979 * Control" Bit was clear (0), then set the microcode variable
6980 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
6981 * to ignore DMA parity errors.
6983 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
6984 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
6985 word |= CONTROL_FLAG_IGNORE_PERR;
6986 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
6990 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
6991 * threshold of 128 bytes. This register is only accessible to the host.
6993 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
6994 START_CTL_EMFU | READ_CMD_MRM);
6997 * Microcode operating variables for WDTR, SDTR, and command tag
6998 * queuing will be set in slave_configure() based on what a
6999 * device reports it is capable of in Inquiry byte 7.
7001 * If SCSI Bus Resets have been disabled, then directly set
7002 * SDTR and WDTR from the EEPROM configuration. This will allow
7003 * the BIOS and warm boot to work without a SCSI bus hang on
7004 * the Inquiry caused by host and target mismatched DTR values.
7005 * Without the SCSI Bus Reset, before an Inquiry a device can't
7006 * be assumed to be in Asynchronous, Narrow mode.
7008 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
7009 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
7010 asc_dvc->wdtr_able);
7011 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
7012 asc_dvc->sdtr_able);
7016 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
7017 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
7018 * bitmask. These values determine the maximum SDTR speed negotiated
7021 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
7022 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
7023 * without determining here whether the device supports SDTR.
7025 * 4-bit speed SDTR speed name
7026 * =========== ===============
7027 * 0000b (0x0) SDTR disabled
7029 * 0010b (0x2) 10 Mhz
7030 * 0011b (0x3) 20 Mhz (Ultra)
7031 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
7032 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
7033 * 0110b (0x6) Undefined
7035 * 1111b (0xF) Undefined
7038 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7039 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
7040 /* Set Ultra speed for TID 'tid'. */
7041 word |= (0x3 << (4 * (tid % 4)));
7043 /* Set Fast speed for TID 'tid'. */
7044 word |= (0x2 << (4 * (tid % 4)));
7046 if (tid == 3) { /* Check if done with sdtr_speed1. */
7047 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
7049 } else if (tid == 7) { /* Check if done with sdtr_speed2. */
7050 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
7052 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
7053 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
7055 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
7056 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
7062 * Set microcode operating variable for the disconnect per TID bitmask.
7064 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
7065 asc_dvc->cfg->disc_enable);
7068 * Set SCSI_CFG0 Microcode Default Value.
7070 * The microcode will set the SCSI_CFG0 register using this value
7071 * after it is started below.
7073 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
7074 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
7075 asc_dvc->chip_scsi_id);
7078 * Determine SCSI_CFG1 Microcode Default Value.
7080 * The microcode will set the SCSI_CFG1 register using this value
7081 * after it is started below.
7084 /* Read current SCSI_CFG1 Register value. */
7085 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7088 * If all three connectors are in use, return an error.
7090 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
7091 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
7092 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
7097 * If the internal narrow cable is reversed all of the SCSI_CTRL
7098 * register signals will be set. Check for and return an error if
7099 * this condition is found.
7101 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
7102 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
7107 * If this is a differential board and a single-ended device
7108 * is attached to one of the connectors, return an error.
7110 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
7111 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
7116 * If automatic termination control is enabled, then set the
7117 * termination value based on a table listed in a_condor.h.
7119 * If manual termination was specified with an EEPROM setting
7120 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
7121 * is ready to be 'ored' into SCSI_CFG1.
7123 if (asc_dvc->cfg->termination == 0) {
7125 * The software always controls termination by setting TERM_CTL_SEL.
7126 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
7128 asc_dvc->cfg->termination |= TERM_CTL_SEL;
7130 switch (scsi_cfg1 & CABLE_DETECT) {
7131 /* TERM_CTL_H: on, TERM_CTL_L: on */
7138 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
7141 /* TERM_CTL_H: on, TERM_CTL_L: off */
7147 asc_dvc->cfg->termination |= TERM_CTL_H;
7150 /* TERM_CTL_H: off, TERM_CTL_L: off */
7158 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
7160 scsi_cfg1 &= ~TERM_CTL;
7163 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
7164 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
7165 * referenced, because the hardware internally inverts
7166 * the Termination High and Low bits if TERM_POL is set.
7168 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
7171 * Set SCSI_CFG1 Microcode Default Value
7173 * Set filter value and possibly modified termination control
7174 * bits in the Microcode SCSI_CFG1 Register Value.
7176 * The microcode will set the SCSI_CFG1 register using this value
7177 * after it is started below.
7179 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
7180 FLTR_DISABLE | scsi_cfg1);
7183 * Set MEM_CFG Microcode Default Value
7185 * The microcode will set the MEM_CFG register using this value
7186 * after it is started below.
7188 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
7191 * ASC-3550 has 8KB internal memory.
7193 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
7194 BIOS_EN | RAM_SZ_8KB);
7197 * Set SEL_MASK Microcode Default Value
7199 * The microcode will set the SEL_MASK register using this value
7200 * after it is started below.
7202 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
7203 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
7205 AdvBuildCarrierFreelist(asc_dvc);
7208 * Set-up the Host->RISC Initiator Command Queue (ICQ).
7211 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
7212 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7215 asc_dvc->carr_freelist = (ADV_CARR_T *)
7216 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
7219 * The first command issued will be placed in the stopper carrier.
7221 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7224 * Set RISC ICQ physical address start value.
7226 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
7229 * Set-up the RISC->Host Initiator Response Queue (IRQ).
7231 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
7232 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7235 asc_dvc->carr_freelist = (ADV_CARR_T *)
7236 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
7239 * The first command completed by the RISC will be placed in
7242 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
7243 * completed the RISC will set the ASC_RQ_STOPPER bit.
7245 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7248 * Set RISC IRQ physical address start value.
7250 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
7251 asc_dvc->carr_pending_cnt = 0;
7253 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
7254 (ADV_INTR_ENABLE_HOST_INTR |
7255 ADV_INTR_ENABLE_GLOBAL_INTR));
7257 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
7258 AdvWriteWordRegister(iop_base, IOPW_PC, word);
7260 /* finally, finally, gentlemen, start your engine */
7261 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
7264 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
7265 * Resets should be performed. The RISC has to be running
7266 * to issue a SCSI Bus Reset.
7268 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
7270 * If the BIOS Signature is present in memory, restore the
7271 * BIOS Handshake Configuration Table and do not perform
7274 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
7277 * Restore per TID negotiated values.
7279 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7280 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7281 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7283 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7284 AdvWriteByteLram(iop_base,
7285 ASC_MC_NUMBER_OF_MAX_CMD + tid,
7289 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
7290 warn_code = ASC_WARN_BUSRESET_ERROR;
7299 * Initialize the ASC-38C0800.
7301 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
7303 * For a non-fatal error return a warning code. If there are no warnings
7304 * then 0 is returned.
7306 * Needed after initialization for error recovery.
7308 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
7310 AdvPortAddr iop_base;
7320 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
7321 ushort wdtr_able, sdtr_able, tagqng_able;
7322 uchar max_cmd[ADV_MAX_TID + 1];
7324 /* If there is already an error, don't continue. */
7325 if (asc_dvc->err_code != 0)
7329 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
7331 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
7332 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
7337 iop_base = asc_dvc->iop_base;
7340 * Save the RISC memory BIOS region before writing the microcode.
7341 * The BIOS may already be loaded and using its RISC LRAM region
7342 * so its region must be saved and restored.
7344 * Note: This code makes the assumption, which is currently true,
7345 * that a chip reset does not clear RISC LRAM.
7347 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7348 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7353 * Save current per TID negotiated values.
7355 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7356 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7357 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
7358 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7359 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
7364 * RAM BIST (RAM Built-In Self Test)
7366 * Address : I/O base + offset 0x38h register (byte).
7367 * Function: Bit 7-6(RW) : RAM mode
7368 * Normal Mode : 0x00
7369 * Pre-test Mode : 0x40
7370 * RAM Test Mode : 0x80
7372 * Bit 4(RO) : Done bit
7373 * Bit 3-0(RO) : Status
7375 * Int_RAM Error : 0x04
7380 * Note: RAM BIST code should be put right here, before loading the
7381 * microcode and after saving the RISC memory BIOS region.
7387 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
7388 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
7389 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
7390 * to NORMAL_MODE, return an error too.
7392 for (i = 0; i < 2; i++) {
7393 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
7394 mdelay(10); /* Wait for 10ms before reading back. */
7395 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7396 if ((byte & RAM_TEST_DONE) == 0
7397 || (byte & 0x0F) != PRE_TEST_VALUE) {
7398 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7402 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7403 mdelay(10); /* Wait for 10ms before reading back. */
7404 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
7406 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7412 * LRAM Test - It takes about 1.5 ms to run through the test.
7414 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
7415 * If Done bit not set or Status not 0, save register byte, set the
7416 * err_code, and return an error.
7418 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
7419 mdelay(10); /* Wait for 10ms before checking status. */
7421 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7422 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
7423 /* Get here if Done bit not set or Status not 0. */
7424 asc_dvc->bist_err_code = byte; /* for BIOS display message */
7425 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
7429 /* We need to reset back to normal mode after LRAM test passes. */
7430 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7432 asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc38C0800_buf,
7433 _adv_asc38C0800_size, ADV_38C0800_MEMSIZE,
7434 _adv_asc38C0800_chksum);
7435 if (asc_dvc->err_code)
7439 * Restore the RISC memory BIOS region.
7441 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7442 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7447 * Calculate and write the microcode code checksum to the microcode
7448 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
7450 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
7451 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
7453 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
7454 for (word = begin_addr; word < end_addr; word += 2) {
7455 code_sum += AdvReadWordAutoIncLram(iop_base);
7457 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
7460 * Read microcode version and date.
7462 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
7463 asc_dvc->cfg->mcode_date);
7464 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
7465 asc_dvc->cfg->mcode_version);
7468 * Set the chip type to indicate the ASC38C0800.
7470 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
7473 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
7474 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
7475 * cable detection and then we are able to read C_DET[3:0].
7477 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
7478 * Microcode Default Value' section below.
7480 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7481 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
7482 scsi_cfg1 | DIS_TERM_DRV);
7485 * If the PCI Configuration Command Register "Parity Error Response
7486 * Control" Bit was clear (0), then set the microcode variable
7487 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
7488 * to ignore DMA parity errors.
7490 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
7491 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7492 word |= CONTROL_FLAG_IGNORE_PERR;
7493 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7497 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
7498 * bits for the default FIFO threshold.
7500 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
7502 * For DMA Errata #4 set the BC_THRESH_ENB bit.
7504 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
7505 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
7509 * Microcode operating variables for WDTR, SDTR, and command tag
7510 * queuing will be set in slave_configure() based on what a
7511 * device reports it is capable of in Inquiry byte 7.
7513 * If SCSI Bus Resets have been disabled, then directly set
7514 * SDTR and WDTR from the EEPROM configuration. This will allow
7515 * the BIOS and warm boot to work without a SCSI bus hang on
7516 * the Inquiry caused by host and target mismatched DTR values.
7517 * Without the SCSI Bus Reset, before an Inquiry a device can't
7518 * be assumed to be in Asynchronous, Narrow mode.
7520 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
7521 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
7522 asc_dvc->wdtr_able);
7523 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
7524 asc_dvc->sdtr_able);
7528 * Set microcode operating variables for DISC and SDTR_SPEED1,
7529 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
7530 * configuration values.
7532 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
7533 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
7534 * without determining here whether the device supports SDTR.
7536 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
7537 asc_dvc->cfg->disc_enable);
7538 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
7539 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
7540 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
7541 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
7544 * Set SCSI_CFG0 Microcode Default Value.
7546 * The microcode will set the SCSI_CFG0 register using this value
7547 * after it is started below.
7549 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
7550 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
7551 asc_dvc->chip_scsi_id);
7554 * Determine SCSI_CFG1 Microcode Default Value.
7556 * The microcode will set the SCSI_CFG1 register using this value
7557 * after it is started below.
7560 /* Read current SCSI_CFG1 Register value. */
7561 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7564 * If the internal narrow cable is reversed all of the SCSI_CTRL
7565 * register signals will be set. Check for and return an error if
7566 * this condition is found.
7568 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
7569 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
7574 * All kind of combinations of devices attached to one of four
7575 * connectors are acceptable except HVD device attached. For example,
7576 * LVD device can be attached to SE connector while SE device attached
7577 * to LVD connector. If LVD device attached to SE connector, it only
7578 * runs up to Ultra speed.
7580 * If an HVD device is attached to one of LVD connectors, return an
7581 * error. However, there is no way to detect HVD device attached to
7584 if (scsi_cfg1 & HVD) {
7585 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
7590 * If either SE or LVD automatic termination control is enabled, then
7591 * set the termination value based on a table listed in a_condor.h.
7593 * If manual termination was specified with an EEPROM setting then
7594 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
7595 * to be 'ored' into SCSI_CFG1.
7597 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
7598 /* SE automatic termination control is enabled. */
7599 switch (scsi_cfg1 & C_DET_SE) {
7600 /* TERM_SE_HI: on, TERM_SE_LO: on */
7604 asc_dvc->cfg->termination |= TERM_SE;
7607 /* TERM_SE_HI: on, TERM_SE_LO: off */
7609 asc_dvc->cfg->termination |= TERM_SE_HI;
7614 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
7615 /* LVD automatic termination control is enabled. */
7616 switch (scsi_cfg1 & C_DET_LVD) {
7617 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
7621 asc_dvc->cfg->termination |= TERM_LVD;
7624 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
7631 * Clear any set TERM_SE and TERM_LVD bits.
7633 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
7636 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
7638 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
7641 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
7642 * bits and set possibly modified termination control bits in the
7643 * Microcode SCSI_CFG1 Register Value.
7645 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
7648 * Set SCSI_CFG1 Microcode Default Value
7650 * Set possibly modified termination control and reset DIS_TERM_DRV
7651 * bits in the Microcode SCSI_CFG1 Register Value.
7653 * The microcode will set the SCSI_CFG1 register using this value
7654 * after it is started below.
7656 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
7659 * Set MEM_CFG Microcode Default Value
7661 * The microcode will set the MEM_CFG register using this value
7662 * after it is started below.
7664 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
7667 * ASC-38C0800 has 16KB internal memory.
7669 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
7670 BIOS_EN | RAM_SZ_16KB);
7673 * Set SEL_MASK Microcode Default Value
7675 * The microcode will set the SEL_MASK register using this value
7676 * after it is started below.
7678 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
7679 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
7681 AdvBuildCarrierFreelist(asc_dvc);
7684 * Set-up the Host->RISC Initiator Command Queue (ICQ).
7687 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
7688 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7691 asc_dvc->carr_freelist = (ADV_CARR_T *)
7692 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
7695 * The first command issued will be placed in the stopper carrier.
7697 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7700 * Set RISC ICQ physical address start value.
7701 * carr_pa is LE, must be native before write
7703 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
7706 * Set-up the RISC->Host Initiator Response Queue (IRQ).
7708 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
7709 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
7712 asc_dvc->carr_freelist = (ADV_CARR_T *)
7713 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
7716 * The first command completed by the RISC will be placed in
7719 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
7720 * completed the RISC will set the ASC_RQ_STOPPER bit.
7722 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
7725 * Set RISC IRQ physical address start value.
7727 * carr_pa is LE, must be native before write *
7729 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
7730 asc_dvc->carr_pending_cnt = 0;
7732 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
7733 (ADV_INTR_ENABLE_HOST_INTR |
7734 ADV_INTR_ENABLE_GLOBAL_INTR));
7736 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
7737 AdvWriteWordRegister(iop_base, IOPW_PC, word);
7739 /* finally, finally, gentlemen, start your engine */
7740 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
7743 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
7744 * Resets should be performed. The RISC has to be running
7745 * to issue a SCSI Bus Reset.
7747 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
7749 * If the BIOS Signature is present in memory, restore the
7750 * BIOS Handshake Configuration Table and do not perform
7753 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
7756 * Restore per TID negotiated values.
7758 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7759 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7760 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7762 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
7763 AdvWriteByteLram(iop_base,
7764 ASC_MC_NUMBER_OF_MAX_CMD + tid,
7768 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
7769 warn_code = ASC_WARN_BUSRESET_ERROR;
7778 * Initialize the ASC-38C1600.
7780 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
7782 * For a non-fatal error return a warning code. If there are no warnings
7783 * then 0 is returned.
7785 * Needed after initialization for error recovery.
7787 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
7789 AdvPortAddr iop_base;
7799 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
7800 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
7801 uchar max_cmd[ASC_MAX_TID + 1];
7803 /* If there is already an error, don't continue. */
7804 if (asc_dvc->err_code != 0) {
7809 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
7811 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
7812 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
7817 iop_base = asc_dvc->iop_base;
7820 * Save the RISC memory BIOS region before writing the microcode.
7821 * The BIOS may already be loaded and using its RISC LRAM region
7822 * so its region must be saved and restored.
7824 * Note: This code makes the assumption, which is currently true,
7825 * that a chip reset does not clear RISC LRAM.
7827 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7828 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7833 * Save current per TID negotiated values.
7835 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
7836 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
7837 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
7838 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
7839 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
7840 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
7845 * RAM BIST (Built-In Self Test)
7847 * Address : I/O base + offset 0x38h register (byte).
7848 * Function: Bit 7-6(RW) : RAM mode
7849 * Normal Mode : 0x00
7850 * Pre-test Mode : 0x40
7851 * RAM Test Mode : 0x80
7853 * Bit 4(RO) : Done bit
7854 * Bit 3-0(RO) : Status
7856 * Int_RAM Error : 0x04
7861 * Note: RAM BIST code should be put right here, before loading the
7862 * microcode and after saving the RISC memory BIOS region.
7868 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
7869 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
7870 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
7871 * to NORMAL_MODE, return an error too.
7873 for (i = 0; i < 2; i++) {
7874 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
7875 mdelay(10); /* Wait for 10ms before reading back. */
7876 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7877 if ((byte & RAM_TEST_DONE) == 0
7878 || (byte & 0x0F) != PRE_TEST_VALUE) {
7879 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7883 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7884 mdelay(10); /* Wait for 10ms before reading back. */
7885 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
7887 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
7893 * LRAM Test - It takes about 1.5 ms to run through the test.
7895 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
7896 * If Done bit not set or Status not 0, save register byte, set the
7897 * err_code, and return an error.
7899 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
7900 mdelay(10); /* Wait for 10ms before checking status. */
7902 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
7903 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
7904 /* Get here if Done bit not set or Status not 0. */
7905 asc_dvc->bist_err_code = byte; /* for BIOS display message */
7906 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
7910 /* We need to reset back to normal mode after LRAM test passes. */
7911 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
7913 asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc38C1600_buf,
7914 _adv_asc38C1600_size, ADV_38C1600_MEMSIZE,
7915 _adv_asc38C1600_chksum);
7916 if (asc_dvc->err_code)
7920 * Restore the RISC memory BIOS region.
7922 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
7923 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
7928 * Calculate and write the microcode code checksum to the microcode
7929 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
7931 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
7932 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
7934 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
7935 for (word = begin_addr; word < end_addr; word += 2) {
7936 code_sum += AdvReadWordAutoIncLram(iop_base);
7938 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
7941 * Read microcode version and date.
7943 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
7944 asc_dvc->cfg->mcode_date);
7945 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
7946 asc_dvc->cfg->mcode_version);
7949 * Set the chip type to indicate the ASC38C1600.
7951 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
7954 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
7955 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
7956 * cable detection and then we are able to read C_DET[3:0].
7958 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
7959 * Microcode Default Value' section below.
7961 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
7962 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
7963 scsi_cfg1 | DIS_TERM_DRV);
7966 * If the PCI Configuration Command Register "Parity Error Response
7967 * Control" Bit was clear (0), then set the microcode variable
7968 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
7969 * to ignore DMA parity errors.
7971 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
7972 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7973 word |= CONTROL_FLAG_IGNORE_PERR;
7974 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7978 * If the BIOS control flag AIPP (Asynchronous Information
7979 * Phase Protection) disable bit is not set, then set the firmware
7980 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
7981 * AIPP checking and encoding.
7983 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
7984 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7985 word |= CONTROL_FLAG_ENABLE_AIPP;
7986 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
7990 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
7991 * and START_CTL_TH [3:2].
7993 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
7994 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
7997 * Microcode operating variables for WDTR, SDTR, and command tag
7998 * queuing will be set in slave_configure() based on what a
7999 * device reports it is capable of in Inquiry byte 7.
8001 * If SCSI Bus Resets have been disabled, then directly set
8002 * SDTR and WDTR from the EEPROM configuration. This will allow
8003 * the BIOS and warm boot to work without a SCSI bus hang on
8004 * the Inquiry caused by host and target mismatched DTR values.
8005 * Without the SCSI Bus Reset, before an Inquiry a device can't
8006 * be assumed to be in Asynchronous, Narrow mode.
8008 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
8009 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
8010 asc_dvc->wdtr_able);
8011 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
8012 asc_dvc->sdtr_able);
8016 * Set microcode operating variables for DISC and SDTR_SPEED1,
8017 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
8018 * configuration values.
8020 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
8021 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
8022 * without determining here whether the device supports SDTR.
8024 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
8025 asc_dvc->cfg->disc_enable);
8026 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
8027 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
8028 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
8029 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
8032 * Set SCSI_CFG0 Microcode Default Value.
8034 * The microcode will set the SCSI_CFG0 register using this value
8035 * after it is started below.
8037 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
8038 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
8039 asc_dvc->chip_scsi_id);
8042 * Calculate SCSI_CFG1 Microcode Default Value.
8044 * The microcode will set the SCSI_CFG1 register using this value
8045 * after it is started below.
8047 * Each ASC-38C1600 function has only two cable detect bits.
8048 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
8050 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
8053 * If the cable is reversed all of the SCSI_CTRL register signals
8054 * will be set. Check for and return an error if this condition is
8057 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
8058 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
8063 * Each ASC-38C1600 function has two connectors. Only an HVD device
8064 * can not be connected to either connector. An LVD device or SE device
8065 * may be connected to either connecor. If an SE device is connected,
8066 * then at most Ultra speed (20 Mhz) can be used on both connectors.
8068 * If an HVD device is attached, return an error.
8070 if (scsi_cfg1 & HVD) {
8071 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
8076 * Each function in the ASC-38C1600 uses only the SE cable detect and
8077 * termination because there are two connectors for each function. Each
8078 * function may use either LVD or SE mode. Corresponding the SE automatic
8079 * termination control EEPROM bits are used for each function. Each
8080 * function has its own EEPROM. If SE automatic control is enabled for
8081 * the function, then set the termination value based on a table listed
8084 * If manual termination is specified in the EEPROM for the function,
8085 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
8086 * ready to be 'ored' into SCSI_CFG1.
8088 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
8089 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
8090 /* SE automatic termination control is enabled. */
8091 switch (scsi_cfg1 & C_DET_SE) {
8092 /* TERM_SE_HI: on, TERM_SE_LO: on */
8096 asc_dvc->cfg->termination |= TERM_SE;
8100 if (PCI_FUNC(pdev->devfn) == 0) {
8101 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
8103 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
8104 asc_dvc->cfg->termination |= TERM_SE_HI;
8111 * Clear any set TERM_SE bits.
8113 scsi_cfg1 &= ~TERM_SE;
8116 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
8118 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
8121 * Clear Big Endian and Terminator Polarity bits and set possibly
8122 * modified termination control bits in the Microcode SCSI_CFG1
8125 * Big Endian bit is not used even on big endian machines.
8127 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
8130 * Set SCSI_CFG1 Microcode Default Value
8132 * Set possibly modified termination control bits in the Microcode
8133 * SCSI_CFG1 Register Value.
8135 * The microcode will set the SCSI_CFG1 register using this value
8136 * after it is started below.
8138 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
8141 * Set MEM_CFG Microcode Default Value
8143 * The microcode will set the MEM_CFG register using this value
8144 * after it is started below.
8146 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
8149 * ASC-38C1600 has 32KB internal memory.
8151 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
8152 * out a special 16K Adv Library and Microcode version. After the issue
8153 * resolved, we should turn back to the 32K support. Both a_condor.h and
8154 * mcode.sas files also need to be updated.
8156 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
8157 * BIOS_EN | RAM_SZ_32KB);
8159 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
8160 BIOS_EN | RAM_SZ_16KB);
8163 * Set SEL_MASK Microcode Default Value
8165 * The microcode will set the SEL_MASK register using this value
8166 * after it is started below.
8168 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
8169 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
8171 AdvBuildCarrierFreelist(asc_dvc);
8174 * Set-up the Host->RISC Initiator Command Queue (ICQ).
8176 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
8177 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
8180 asc_dvc->carr_freelist = (ADV_CARR_T *)
8181 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
8184 * The first command issued will be placed in the stopper carrier.
8186 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
8189 * Set RISC ICQ physical address start value. Initialize the
8190 * COMMA register to the same value otherwise the RISC will
8191 * prematurely detect a command is available.
8193 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
8194 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
8195 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
8198 * Set-up the RISC->Host Initiator Response Queue (IRQ).
8200 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
8201 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
8204 asc_dvc->carr_freelist = (ADV_CARR_T *)
8205 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
8208 * The first command completed by the RISC will be placed in
8211 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
8212 * completed the RISC will set the ASC_RQ_STOPPER bit.
8214 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
8217 * Set RISC IRQ physical address start value.
8219 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
8220 asc_dvc->carr_pending_cnt = 0;
8222 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
8223 (ADV_INTR_ENABLE_HOST_INTR |
8224 ADV_INTR_ENABLE_GLOBAL_INTR));
8225 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
8226 AdvWriteWordRegister(iop_base, IOPW_PC, word);
8228 /* finally, finally, gentlemen, start your engine */
8229 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
8232 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
8233 * Resets should be performed. The RISC has to be running
8234 * to issue a SCSI Bus Reset.
8236 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
8238 * If the BIOS Signature is present in memory, restore the
8239 * per TID microcode operating variables.
8241 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
8244 * Restore per TID negotiated values.
8246 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8247 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8248 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
8249 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
8251 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
8252 AdvWriteByteLram(iop_base,
8253 ASC_MC_NUMBER_OF_MAX_CMD + tid,
8257 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
8258 warn_code = ASC_WARN_BUSRESET_ERROR;
8267 * Reset chip and SCSI Bus.
8270 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
8271 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
8273 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
8276 ushort wdtr_able, sdtr_able, tagqng_able;
8277 ushort ppr_able = 0;
8278 uchar tid, max_cmd[ADV_MAX_TID + 1];
8279 AdvPortAddr iop_base;
8282 iop_base = asc_dvc->iop_base;
8285 * Save current per TID negotiated values.
8287 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8288 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8289 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8290 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
8292 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
8293 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
8294 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
8299 * Force the AdvInitAsc3550/38C0800Driver() function to
8300 * perform a SCSI Bus Reset by clearing the BIOS signature word.
8301 * The initialization functions assumes a SCSI Bus Reset is not
8302 * needed if the BIOS signature word is present.
8304 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
8305 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
8308 * Stop chip and reset it.
8310 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
8311 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
8313 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
8314 ADV_CTRL_REG_CMD_WR_IO_REG);
8317 * Reset Adv Library error code, if any, and try
8318 * re-initializing the chip.
8320 asc_dvc->err_code = 0;
8321 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8322 status = AdvInitAsc38C1600Driver(asc_dvc);
8323 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8324 status = AdvInitAsc38C0800Driver(asc_dvc);
8326 status = AdvInitAsc3550Driver(asc_dvc);
8329 /* Translate initialization return value to status value. */
8337 * Restore the BIOS signature word.
8339 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
8342 * Restore per TID negotiated values.
8344 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8345 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8346 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8347 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
8349 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
8350 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
8351 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
8359 * adv_async_callback() - Adv Library asynchronous event callback function.
8361 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
8364 case ADV_ASYNC_SCSI_BUS_RESET_DET:
8366 * The firmware detected a SCSI Bus reset.
8369 "adv_async_callback: ADV_ASYNC_SCSI_BUS_RESET_DET\n");
8372 case ADV_ASYNC_RDMA_FAILURE:
8374 * Handle RDMA failure by resetting the SCSI Bus and
8375 * possibly the chip if it is unresponsive. Log the error
8376 * with a unique code.
8378 ASC_DBG(0, "adv_async_callback: ADV_ASYNC_RDMA_FAILURE\n");
8379 AdvResetChipAndSB(adv_dvc_varp);
8382 case ADV_HOST_SCSI_BUS_RESET:
8384 * Host generated SCSI bus reset occurred.
8386 ASC_DBG(0, "adv_async_callback: ADV_HOST_SCSI_BUS_RESET\n");
8390 ASC_DBG1(0, "DvcAsyncCallBack: unknown code 0x%x\n", code);
8396 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
8398 * Callback function for the Wide SCSI Adv Library.
8400 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
8402 asc_board_t *boardp;
8404 adv_sgblk_t *sgblkp;
8405 struct scsi_cmnd *scp;
8406 struct Scsi_Host *shost;
8409 ASC_DBG2(1, "adv_isr_callback: adv_dvc_varp 0x%lx, scsiqp 0x%lx\n",
8410 (ulong)adv_dvc_varp, (ulong)scsiqp);
8411 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
8414 * Get the adv_req_t structure for the command that has been
8415 * completed. The adv_req_t structure actually contains the
8416 * completed ADV_SCSI_REQ_Q structure.
8418 reqp = (adv_req_t *)ADV_U32_TO_VADDR(scsiqp->srb_ptr);
8419 ASC_DBG1(1, "adv_isr_callback: reqp 0x%lx\n", (ulong)reqp);
8421 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
8426 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
8427 * command that has been completed.
8429 * Note: The adv_req_t request structure and adv_sgblk_t structure,
8430 * if any, are dropped, because a board structure pointer can not be
8434 ASC_DBG1(1, "adv_isr_callback: scp 0x%lx\n", (ulong)scp);
8437 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
8440 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
8442 shost = scp->device->host;
8443 ASC_STATS(shost, callback);
8444 ASC_DBG1(1, "adv_isr_callback: shost 0x%lx\n", (ulong)shost);
8446 boardp = ASC_BOARDP(shost);
8447 BUG_ON(adv_dvc_varp != &boardp->dvc_var.adv_dvc_var);
8450 * 'done_status' contains the command's ending status.
8452 switch (scsiqp->done_status) {
8454 ASC_DBG(2, "adv_isr_callback: QD_NO_ERROR\n");
8458 * Check for an underrun condition.
8460 * If there was no error and an underrun condition, then
8461 * then return the number of underrun bytes.
8463 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
8464 if (scp->request_bufflen != 0 && resid_cnt != 0 &&
8465 resid_cnt <= scp->request_bufflen) {
8467 "adv_isr_callback: underrun condition %lu bytes\n",
8469 scp->resid = resid_cnt;
8474 ASC_DBG(2, "adv_isr_callback: QD_WITH_ERROR\n");
8475 switch (scsiqp->host_status) {
8476 case QHSTA_NO_ERROR:
8477 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
8479 "adv_isr_callback: SAM_STAT_CHECK_CONDITION\n");
8480 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
8481 sizeof(scp->sense_buffer));
8483 * Note: The 'status_byte()' macro used by
8484 * target drivers defined in scsi.h shifts the
8485 * status byte returned by host drivers right
8486 * by 1 bit. This is why target drivers also
8487 * use right shifted status byte definitions.
8488 * For instance target drivers use
8489 * CHECK_CONDITION, defined to 0x1, instead of
8490 * the SCSI defined check condition value of
8491 * 0x2. Host drivers are supposed to return
8492 * the status byte as it is defined by SCSI.
8494 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
8495 STATUS_BYTE(scsiqp->scsi_status);
8497 scp->result = STATUS_BYTE(scsiqp->scsi_status);
8502 /* Some other QHSTA error occurred. */
8503 ASC_DBG1(1, "adv_isr_callback: host_status 0x%x\n",
8504 scsiqp->host_status);
8505 scp->result = HOST_BYTE(DID_BAD_TARGET);
8510 case QD_ABORTED_BY_HOST:
8511 ASC_DBG(1, "adv_isr_callback: QD_ABORTED_BY_HOST\n");
8513 HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
8517 ASC_DBG1(1, "adv_isr_callback: done_status 0x%x\n",
8518 scsiqp->done_status);
8520 HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
8525 * If the 'init_tidmask' bit isn't already set for the target and the
8526 * current request finished normally, then set the bit for the target
8527 * to indicate that a device is present.
8529 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
8530 scsiqp->done_status == QD_NO_ERROR &&
8531 scsiqp->host_status == QHSTA_NO_ERROR) {
8532 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
8538 * Free all 'adv_sgblk_t' structures allocated for the request.
8540 while ((sgblkp = reqp->sgblkp) != NULL) {
8541 /* Remove 'sgblkp' from the request list. */
8542 reqp->sgblkp = sgblkp->next_sgblkp;
8544 /* Add 'sgblkp' to the board free list. */
8545 sgblkp->next_sgblkp = boardp->adv_sgblkp;
8546 boardp->adv_sgblkp = sgblkp;
8550 * Free the adv_req_t structure used with the command by adding
8551 * it back to the board free list.
8553 reqp->next_reqp = boardp->adv_reqp;
8554 boardp->adv_reqp = reqp;
8556 ASC_DBG(1, "adv_isr_callback: done\n");
8562 * Adv Library Interrupt Service Routine
8564 * This function is called by a driver's interrupt service routine.
8565 * The function disables and re-enables interrupts.
8567 * When a microcode idle command is completed, the ADV_DVC_VAR
8568 * 'idle_cmd_done' field is set to ADV_TRUE.
8570 * Note: AdvISR() can be called when interrupts are disabled or even
8571 * when there is no hardware interrupt condition present. It will
8572 * always check for completed idle commands and microcode requests.
8573 * This is an important feature that shouldn't be changed because it
8574 * allows commands to be completed from polling mode loops.
8577 * ADV_TRUE(1) - interrupt was pending
8578 * ADV_FALSE(0) - no interrupt was pending
8580 static int AdvISR(ADV_DVC_VAR *asc_dvc)
8582 AdvPortAddr iop_base;
8585 ADV_CARR_T *free_carrp;
8586 ADV_VADDR irq_next_vpa;
8587 ADV_SCSI_REQ_Q *scsiq;
8589 iop_base = asc_dvc->iop_base;
8591 /* Reading the register clears the interrupt. */
8592 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
8594 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
8595 ADV_INTR_STATUS_INTRC)) == 0) {
8600 * Notify the driver of an asynchronous microcode condition by
8601 * calling the adv_async_callback function. The function
8602 * is passed the microcode ASC_MC_INTRB_CODE byte value.
8604 if (int_stat & ADV_INTR_STATUS_INTRB) {
8607 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
8609 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
8610 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8611 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
8612 asc_dvc->carr_pending_cnt != 0) {
8613 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
8615 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
8616 AdvWriteByteRegister(iop_base,
8623 adv_async_callback(asc_dvc, intrb_code);
8627 * Check if the IRQ stopper carrier contains a completed request.
8629 while (((irq_next_vpa =
8630 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
8632 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
8633 * The RISC will have set 'areq_vpa' to a virtual address.
8635 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
8636 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
8637 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
8638 * in AdvExeScsiQueue().
8640 scsiq = (ADV_SCSI_REQ_Q *)
8641 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
8644 * Request finished with good status and the queue was not
8645 * DMAed to host memory by the firmware. Set all status fields
8646 * to indicate good status.
8648 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
8649 scsiq->done_status = QD_NO_ERROR;
8650 scsiq->host_status = scsiq->scsi_status = 0;
8651 scsiq->data_cnt = 0L;
8655 * Advance the stopper pointer to the next carrier
8656 * ignoring the lower four bits. Free the previous
8659 free_carrp = asc_dvc->irq_sp;
8660 asc_dvc->irq_sp = (ADV_CARR_T *)
8661 ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
8663 free_carrp->next_vpa =
8664 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
8665 asc_dvc->carr_freelist = free_carrp;
8666 asc_dvc->carr_pending_cnt--;
8668 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
8671 * Clear request microcode control flag.
8676 * Notify the driver of the completed request by passing
8677 * the ADV_SCSI_REQ_Q pointer to its callback function.
8679 scsiq->a_flag |= ADV_SCSIQ_DONE;
8680 adv_isr_callback(asc_dvc, scsiq);
8682 * Note: After the driver callback function is called, 'scsiq'
8683 * can no longer be referenced.
8685 * Fall through and continue processing other completed
8692 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
8694 if (asc_dvc->err_code == 0) {
8695 asc_dvc->err_code = err_code;
8696 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
8702 static void AscAckInterrupt(PortAddr iop_base)
8710 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
8711 if (loop++ > 0x7FFF) {
8714 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
8716 AscReadLramByte(iop_base,
8717 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
8718 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
8719 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
8720 AscSetChipStatus(iop_base, CIW_INT_ACK);
8722 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
8723 AscSetChipStatus(iop_base, CIW_INT_ACK);
8728 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
8732 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
8734 uchar *period_table;
8739 period_table = asc_dvc->sdtr_period_tbl;
8740 max_index = (int)asc_dvc->max_sdtr_index;
8741 min_index = (int)asc_dvc->host_init_sdtr_index;
8742 if ((syn_time <= period_table[max_index])) {
8743 for (i = min_index; i < (max_index - 1); i++) {
8744 if (syn_time <= period_table[i]) {
8748 return (uchar)max_index;
8750 return (uchar)(max_index + 1);
8755 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
8758 uchar sdtr_period_index;
8761 iop_base = asc_dvc->iop_base;
8762 sdtr_buf.msg_type = EXTENDED_MESSAGE;
8763 sdtr_buf.msg_len = MS_SDTR_LEN;
8764 sdtr_buf.msg_req = EXTENDED_SDTR;
8765 sdtr_buf.xfer_period = sdtr_period;
8766 sdtr_offset &= ASC_SYN_MAX_OFFSET;
8767 sdtr_buf.req_ack_offset = sdtr_offset;
8768 sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
8769 if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
8770 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
8772 sizeof(EXT_MSG) >> 1);
8773 return ((sdtr_period_index << 4) | sdtr_offset);
8775 sdtr_buf.req_ack_offset = 0;
8776 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
8778 sizeof(EXT_MSG) >> 1);
8784 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
8787 uchar sdtr_period_ix;
8789 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
8790 if (sdtr_period_ix > asc_dvc->max_sdtr_index) {
8793 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
8797 static int AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
8799 ASC_SCSI_BIT_ID_TYPE org_id;
8803 AscSetBank(iop_base, 1);
8804 org_id = AscReadChipDvcID(iop_base);
8805 for (i = 0; i <= ASC_MAX_TID; i++) {
8806 if (org_id == (0x01 << i))
8809 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
8810 AscWriteChipDvcID(iop_base, id);
8811 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
8812 AscSetBank(iop_base, 0);
8813 AscSetChipSyn(iop_base, sdtr_data);
8814 if (AscGetChipSyn(iop_base) != sdtr_data) {
8820 AscSetBank(iop_base, 1);
8821 AscWriteChipDvcID(iop_base, org_id);
8822 AscSetBank(iop_base, 0);
8826 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
8828 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
8829 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
8832 static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
8838 ushort int_halt_code;
8839 ASC_SCSI_BIT_ID_TYPE scsi_busy;
8840 ASC_SCSI_BIT_ID_TYPE target_id;
8847 uchar q_cntl, tid_no;
8851 asc_board_t *boardp;
8853 BUG_ON(!asc_dvc->drv_ptr);
8854 boardp = asc_dvc->drv_ptr;
8856 iop_base = asc_dvc->iop_base;
8857 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
8859 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
8860 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
8861 target_ix = AscReadLramByte(iop_base,
8862 (ushort)(halt_q_addr +
8863 (ushort)ASC_SCSIQ_B_TARGET_IX));
8864 q_cntl = AscReadLramByte(iop_base,
8865 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
8866 tid_no = ASC_TIX_TO_TID(target_ix);
8867 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
8868 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8869 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
8873 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
8874 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8875 AscSetChipSDTR(iop_base, 0, tid_no);
8876 boardp->sdtr_data[tid_no] = 0;
8878 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8880 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
8881 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
8882 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8883 boardp->sdtr_data[tid_no] = asyn_sdtr;
8885 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8887 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
8888 AscMemWordCopyPtrFromLram(iop_base,
8891 sizeof(EXT_MSG) >> 1);
8893 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
8894 ext_msg.msg_req == EXTENDED_SDTR &&
8895 ext_msg.msg_len == MS_SDTR_LEN) {
8897 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
8899 sdtr_accept = FALSE;
8900 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
8902 if ((ext_msg.xfer_period <
8903 asc_dvc->sdtr_period_tbl[asc_dvc->
8904 host_init_sdtr_index])
8905 || (ext_msg.xfer_period >
8906 asc_dvc->sdtr_period_tbl[asc_dvc->
8908 sdtr_accept = FALSE;
8909 ext_msg.xfer_period =
8910 asc_dvc->sdtr_period_tbl[asc_dvc->
8911 host_init_sdtr_index];
8915 AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
8916 ext_msg.req_ack_offset);
8917 if ((sdtr_data == 0xFF)) {
8919 q_cntl |= QC_MSG_OUT;
8920 asc_dvc->init_sdtr &= ~target_id;
8921 asc_dvc->sdtr_done &= ~target_id;
8922 AscSetChipSDTR(iop_base, asyn_sdtr,
8924 boardp->sdtr_data[tid_no] = asyn_sdtr;
8927 if (ext_msg.req_ack_offset == 0) {
8929 q_cntl &= ~QC_MSG_OUT;
8930 asc_dvc->init_sdtr &= ~target_id;
8931 asc_dvc->sdtr_done &= ~target_id;
8932 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
8934 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
8936 q_cntl &= ~QC_MSG_OUT;
8937 asc_dvc->sdtr_done |= target_id;
8938 asc_dvc->init_sdtr |= target_id;
8939 asc_dvc->pci_fix_asyn_xfer &=
8942 AscCalSDTRData(asc_dvc,
8943 ext_msg.xfer_period,
8946 AscSetChipSDTR(iop_base, sdtr_data,
8948 boardp->sdtr_data[tid_no] = sdtr_data;
8951 q_cntl |= QC_MSG_OUT;
8952 AscMsgOutSDTR(asc_dvc,
8953 ext_msg.xfer_period,
8954 ext_msg.req_ack_offset);
8955 asc_dvc->pci_fix_asyn_xfer &=
8958 AscCalSDTRData(asc_dvc,
8959 ext_msg.xfer_period,
8962 AscSetChipSDTR(iop_base, sdtr_data,
8964 boardp->sdtr_data[tid_no] = sdtr_data;
8965 asc_dvc->sdtr_done |= target_id;
8966 asc_dvc->init_sdtr |= target_id;
8970 AscWriteLramByte(iop_base,
8971 (ushort)(halt_q_addr +
8972 (ushort)ASC_SCSIQ_B_CNTL),
8974 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8976 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
8977 ext_msg.msg_req == EXTENDED_WDTR &&
8978 ext_msg.msg_len == MS_WDTR_LEN) {
8980 ext_msg.wdtr_width = 0;
8981 AscMemWordCopyPtrToLram(iop_base,
8984 sizeof(EXT_MSG) >> 1);
8985 q_cntl |= QC_MSG_OUT;
8986 AscWriteLramByte(iop_base,
8987 (ushort)(halt_q_addr +
8988 (ushort)ASC_SCSIQ_B_CNTL),
8990 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
8994 ext_msg.msg_type = MESSAGE_REJECT;
8995 AscMemWordCopyPtrToLram(iop_base,
8998 sizeof(EXT_MSG) >> 1);
8999 q_cntl |= QC_MSG_OUT;
9000 AscWriteLramByte(iop_base,
9001 (ushort)(halt_q_addr +
9002 (ushort)ASC_SCSIQ_B_CNTL),
9004 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9007 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
9009 q_cntl |= QC_REQ_SENSE;
9011 if ((asc_dvc->init_sdtr & target_id) != 0) {
9013 asc_dvc->sdtr_done &= ~target_id;
9015 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
9016 q_cntl |= QC_MSG_OUT;
9017 AscMsgOutSDTR(asc_dvc,
9019 sdtr_period_tbl[(sdtr_data >> 4) &
9023 (uchar)(sdtr_data & (uchar)
9024 ASC_SYN_MAX_OFFSET));
9027 AscWriteLramByte(iop_base,
9028 (ushort)(halt_q_addr +
9029 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
9031 tag_code = AscReadLramByte(iop_base,
9032 (ushort)(halt_q_addr + (ushort)
9033 ASC_SCSIQ_B_TAG_CODE));
9035 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
9036 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
9039 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
9040 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
9043 AscWriteLramByte(iop_base,
9044 (ushort)(halt_q_addr +
9045 (ushort)ASC_SCSIQ_B_TAG_CODE),
9048 q_status = AscReadLramByte(iop_base,
9049 (ushort)(halt_q_addr + (ushort)
9050 ASC_SCSIQ_B_STATUS));
9051 q_status |= (QS_READY | QS_BUSY);
9052 AscWriteLramByte(iop_base,
9053 (ushort)(halt_q_addr +
9054 (ushort)ASC_SCSIQ_B_STATUS),
9057 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
9058 scsi_busy &= ~target_id;
9059 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
9061 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9063 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
9065 AscMemWordCopyPtrFromLram(iop_base,
9068 sizeof(EXT_MSG) >> 1);
9070 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
9071 (out_msg.msg_len == MS_SDTR_LEN) &&
9072 (out_msg.msg_req == EXTENDED_SDTR)) {
9074 asc_dvc->init_sdtr &= ~target_id;
9075 asc_dvc->sdtr_done &= ~target_id;
9076 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
9077 boardp->sdtr_data[tid_no] = asyn_sdtr;
9079 q_cntl &= ~QC_MSG_OUT;
9080 AscWriteLramByte(iop_base,
9081 (ushort)(halt_q_addr +
9082 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
9083 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9085 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
9087 scsi_status = AscReadLramByte(iop_base,
9088 (ushort)((ushort)halt_q_addr +
9090 ASC_SCSIQ_SCSI_STATUS));
9092 AscReadLramByte(iop_base,
9093 (ushort)((ushort)ASC_QADR_BEG +
9094 (ushort)target_ix));
9095 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
9097 scsi_busy = AscReadLramByte(iop_base,
9098 (ushort)ASCV_SCSIBUSY_B);
9099 scsi_busy |= target_id;
9100 AscWriteLramByte(iop_base,
9101 (ushort)ASCV_SCSIBUSY_B, scsi_busy);
9102 asc_dvc->queue_full_or_busy |= target_id;
9104 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
9105 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
9107 asc_dvc->max_dvc_qng[tid_no] =
9110 AscWriteLramByte(iop_base,
9112 ASCV_MAX_DVC_QNG_BEG
9118 * Set the device queue depth to the
9119 * number of active requests when the
9120 * QUEUE FULL condition was encountered.
9122 boardp->queue_full |= target_id;
9123 boardp->queue_full_cnt[tid_no] =
9128 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9131 #if CC_VERY_LONG_SG_LIST
9132 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
9136 uchar first_sg_wk_q_no;
9137 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
9138 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
9139 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
9140 ushort sg_list_dwords;
9141 ushort sg_entry_cnt;
9145 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
9146 if (q_no == ASC_QLINK_END)
9149 q_addr = ASC_QNO_TO_QADDR(q_no);
9152 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
9153 * structure pointer using a macro provided by the driver.
9154 * The ASC_SCSI_REQ pointer provides a pointer to the
9155 * host ASC_SG_HEAD structure.
9157 /* Read request's SRB pointer. */
9158 scsiq = (ASC_SCSI_Q *)
9159 ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
9162 ASC_SCSIQ_D_SRBPTR))));
9165 * Get request's first and working SG queue.
9167 sg_wk_q_no = AscReadLramByte(iop_base,
9169 ASC_SCSIQ_B_SG_WK_QP));
9171 first_sg_wk_q_no = AscReadLramByte(iop_base,
9173 ASC_SCSIQ_B_FIRST_SG_WK_QP));
9176 * Reset request's working SG queue back to the
9179 AscWriteLramByte(iop_base,
9181 (ushort)ASC_SCSIQ_B_SG_WK_QP),
9184 sg_head = scsiq->sg_head;
9187 * Set sg_entry_cnt to the number of SG elements
9188 * that will be completed on this interrupt.
9190 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
9191 * SG elements. The data_cnt and data_addr fields which
9192 * add 1 to the SG element capacity are not used when
9193 * restarting SG handling after a halt.
9195 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
9196 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
9199 * Keep track of remaining number of SG elements that
9200 * will need to be handled on the next interrupt.
9202 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
9204 sg_entry_cnt = scsiq->remain_sg_entry_cnt;
9205 scsiq->remain_sg_entry_cnt = 0;
9209 * Copy SG elements into the list of allocated SG queues.
9211 * Last index completed is saved in scsiq->next_sg_index.
9213 next_qp = first_sg_wk_q_no;
9214 q_addr = ASC_QNO_TO_QADDR(next_qp);
9215 scsi_sg_q.sg_head_qp = q_no;
9216 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
9217 for (i = 0; i < sg_head->queue_cnt; i++) {
9218 scsi_sg_q.seq_no = i + 1;
9219 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
9220 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
9221 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
9223 * After very first SG queue RISC FW uses next
9224 * SG queue first element then checks sg_list_cnt
9225 * against zero and then decrements, so set
9226 * sg_list_cnt 1 less than number of SG elements
9229 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
9230 scsi_sg_q.sg_cur_list_cnt =
9231 ASC_SG_LIST_PER_Q - 1;
9234 * This is the last SG queue in the list of
9235 * allocated SG queues. If there are more
9236 * SG elements than will fit in the allocated
9237 * queues, then set the QCSG_SG_XFER_MORE flag.
9239 if (scsiq->remain_sg_entry_cnt != 0) {
9240 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
9242 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
9244 /* equals sg_entry_cnt * 2 */
9245 sg_list_dwords = sg_entry_cnt << 1;
9246 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
9247 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
9251 scsi_sg_q.q_no = next_qp;
9252 AscMemWordCopyPtrToLram(iop_base,
9253 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
9254 (uchar *)&scsi_sg_q,
9255 sizeof(ASC_SG_LIST_Q) >> 1);
9257 AscMemDWordCopyPtrToLram(iop_base,
9258 q_addr + ASC_SGQ_LIST_BEG,
9260 sg_list[scsiq->next_sg_index],
9263 scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
9266 * If the just completed SG queue contained the
9267 * last SG element, then no more SG queues need
9270 if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
9274 next_qp = AscReadLramByte(iop_base,
9277 q_addr = ASC_QNO_TO_QADDR(next_qp);
9281 * Clear the halt condition so the RISC will be restarted
9284 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9287 #endif /* CC_VERY_LONG_SG_LIST */
9293 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
9295 * Calling/Exit State:
9299 * Input an ASC_QDONE_INFO structure from the chip
9302 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
9307 AscSetChipLramAddr(iop_base, s_addr);
9308 for (i = 0; i < 2 * words; i += 2) {
9312 word = inpw(iop_base + IOP_RAM_DATA);
9313 inbuf[i] = word & 0xff;
9314 inbuf[i + 1] = (word >> 8) & 0xff;
9316 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
9320 _AscCopyLramScsiDoneQ(PortAddr iop_base,
9322 ASC_QDONE_INFO *scsiq, ASC_DCNT max_dma_count)
9327 DvcGetQinfo(iop_base,
9328 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
9330 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
9332 _val = AscReadLramWord(iop_base,
9333 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
9334 scsiq->q_status = (uchar)_val;
9335 scsiq->q_no = (uchar)(_val >> 8);
9336 _val = AscReadLramWord(iop_base,
9337 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
9338 scsiq->cntl = (uchar)_val;
9339 sg_queue_cnt = (uchar)(_val >> 8);
9340 _val = AscReadLramWord(iop_base,
9342 (ushort)ASC_SCSIQ_B_SENSE_LEN));
9343 scsiq->sense_len = (uchar)_val;
9344 scsiq->extra_bytes = (uchar)(_val >> 8);
9347 * Read high word of remain bytes from alternate location.
9349 scsiq->remain_bytes = (((ADV_DCNT)AscReadLramWord(iop_base,
9352 ASC_SCSIQ_W_ALT_DC1)))
9355 * Read low word of remain bytes from original location.
9357 scsiq->remain_bytes += AscReadLramWord(iop_base,
9358 (ushort)(q_addr + (ushort)
9359 ASC_SCSIQ_DW_REMAIN_XFER_CNT));
9361 scsiq->remain_bytes &= max_dma_count;
9362 return sg_queue_cnt;
9366 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
9368 * Interrupt callback function for the Narrow SCSI Asc Library.
9370 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
9372 asc_board_t *boardp;
9373 struct scsi_cmnd *scp;
9374 struct Scsi_Host *shost;
9376 ASC_DBG2(1, "asc_isr_callback: asc_dvc_varp 0x%lx, qdonep 0x%lx\n",
9377 (ulong)asc_dvc_varp, (ulong)qdonep);
9378 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
9381 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
9382 * command that has been completed.
9384 scp = (struct scsi_cmnd *)ASC_U32_TO_VADDR(qdonep->d2.srb_ptr);
9385 ASC_DBG1(1, "asc_isr_callback: scp 0x%lx\n", (ulong)scp);
9388 ASC_PRINT("asc_isr_callback: scp is NULL\n");
9391 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
9393 shost = scp->device->host;
9394 ASC_STATS(shost, callback);
9395 ASC_DBG1(1, "asc_isr_callback: shost 0x%lx\n", (ulong)shost);
9397 boardp = ASC_BOARDP(shost);
9398 BUG_ON(asc_dvc_varp != &boardp->dvc_var.asc_dvc_var);
9401 * 'qdonep' contains the command's ending status.
9403 switch (qdonep->d3.done_stat) {
9405 ASC_DBG(2, "asc_isr_callback: QD_NO_ERROR\n");
9409 * Check for an underrun condition.
9411 * If there was no error and an underrun condition, then
9412 * return the number of underrun bytes.
9414 if (scp->request_bufflen != 0 && qdonep->remain_bytes != 0 &&
9415 qdonep->remain_bytes <= scp->request_bufflen) {
9417 "asc_isr_callback: underrun condition %u bytes\n",
9418 (unsigned)qdonep->remain_bytes);
9419 scp->resid = qdonep->remain_bytes;
9424 ASC_DBG(2, "asc_isr_callback: QD_WITH_ERROR\n");
9425 switch (qdonep->d3.host_stat) {
9426 case QHSTA_NO_ERROR:
9427 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
9429 "asc_isr_callback: SAM_STAT_CHECK_CONDITION\n");
9430 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
9431 sizeof(scp->sense_buffer));
9433 * Note: The 'status_byte()' macro used by
9434 * target drivers defined in scsi.h shifts the
9435 * status byte returned by host drivers right
9436 * by 1 bit. This is why target drivers also
9437 * use right shifted status byte definitions.
9438 * For instance target drivers use
9439 * CHECK_CONDITION, defined to 0x1, instead of
9440 * the SCSI defined check condition value of
9441 * 0x2. Host drivers are supposed to return
9442 * the status byte as it is defined by SCSI.
9444 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
9445 STATUS_BYTE(qdonep->d3.scsi_stat);
9447 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
9452 /* QHSTA error occurred */
9453 ASC_DBG1(1, "asc_isr_callback: host_stat 0x%x\n",
9454 qdonep->d3.host_stat);
9455 scp->result = HOST_BYTE(DID_BAD_TARGET);
9460 case QD_ABORTED_BY_HOST:
9461 ASC_DBG(1, "asc_isr_callback: QD_ABORTED_BY_HOST\n");
9463 HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
9465 STATUS_BYTE(qdonep->d3.scsi_stat);
9469 ASC_DBG1(1, "asc_isr_callback: done_stat 0x%x\n",
9470 qdonep->d3.done_stat);
9472 HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
9474 STATUS_BYTE(qdonep->d3.scsi_stat);
9479 * If the 'init_tidmask' bit isn't already set for the target and the
9480 * current request finished normally, then set the bit for the target
9481 * to indicate that a device is present.
9483 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
9484 qdonep->d3.done_stat == QD_NO_ERROR &&
9485 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
9486 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
9494 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
9503 ASC_SCSI_BIT_ID_TYPE scsi_busy;
9504 ASC_SCSI_BIT_ID_TYPE target_id;
9508 uchar cur_target_qng;
9509 ASC_QDONE_INFO scsiq_buf;
9510 ASC_QDONE_INFO *scsiq;
9513 iop_base = asc_dvc->iop_base;
9515 scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
9516 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
9517 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
9518 next_qp = AscReadLramByte(iop_base,
9519 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
9520 if (next_qp != ASC_QLINK_END) {
9521 AscPutVarDoneQTail(iop_base, next_qp);
9522 q_addr = ASC_QNO_TO_QADDR(next_qp);
9523 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
9524 asc_dvc->max_dma_count);
9525 AscWriteLramByte(iop_base,
9527 (ushort)ASC_SCSIQ_B_STATUS),
9529 q_status & (uchar)~(QS_READY |
9531 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
9532 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
9533 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
9535 sg_list_qp = next_qp;
9536 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
9537 sg_list_qp = AscReadLramByte(iop_base,
9541 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
9542 if (sg_list_qp == ASC_QLINK_END) {
9543 AscSetLibErrorCode(asc_dvc,
9544 ASCQ_ERR_SG_Q_LINKS);
9545 scsiq->d3.done_stat = QD_WITH_ERROR;
9546 scsiq->d3.host_stat =
9547 QHSTA_D_QDONE_SG_LIST_CORRUPTED;
9548 goto FATAL_ERR_QDONE;
9550 AscWriteLramByte(iop_base,
9551 (ushort)(sg_q_addr + (ushort)
9552 ASC_SCSIQ_B_STATUS),
9555 n_q_used = sg_queue_cnt + 1;
9556 AscPutVarDoneQTail(iop_base, sg_list_qp);
9558 if (asc_dvc->queue_full_or_busy & target_id) {
9559 cur_target_qng = AscReadLramByte(iop_base,
9565 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
9566 scsi_busy = AscReadLramByte(iop_base, (ushort)
9568 scsi_busy &= ~target_id;
9569 AscWriteLramByte(iop_base,
9570 (ushort)ASCV_SCSIBUSY_B,
9572 asc_dvc->queue_full_or_busy &= ~target_id;
9575 if (asc_dvc->cur_total_qng >= n_q_used) {
9576 asc_dvc->cur_total_qng -= n_q_used;
9577 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
9578 asc_dvc->cur_dvc_qng[tid_no]--;
9581 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
9582 scsiq->d3.done_stat = QD_WITH_ERROR;
9583 goto FATAL_ERR_QDONE;
9585 if ((scsiq->d2.srb_ptr == 0UL) ||
9586 ((scsiq->q_status & QS_ABORTED) != 0)) {
9588 } else if (scsiq->q_status == QS_DONE) {
9589 false_overrun = FALSE;
9590 if (scsiq->extra_bytes != 0) {
9591 scsiq->remain_bytes +=
9592 (ADV_DCNT)scsiq->extra_bytes;
9594 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
9595 if (scsiq->d3.host_stat ==
9596 QHSTA_M_DATA_OVER_RUN) {
9598 cntl & (QC_DATA_IN | QC_DATA_OUT))
9600 scsiq->d3.done_stat =
9602 scsiq->d3.host_stat =
9604 } else if (false_overrun) {
9605 scsiq->d3.done_stat =
9607 scsiq->d3.host_stat =
9610 } else if (scsiq->d3.host_stat ==
9611 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
9612 AscStopChip(iop_base);
9613 AscSetChipControl(iop_base,
9614 (uchar)(CC_SCSI_RESET
9617 AscSetChipControl(iop_base, CC_HALT);
9618 AscSetChipStatus(iop_base,
9619 CIW_CLR_SCSI_RESET_INT);
9620 AscSetChipStatus(iop_base, 0);
9621 AscSetChipControl(iop_base, 0);
9624 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
9625 asc_isr_callback(asc_dvc, scsiq);
9627 if ((AscReadLramByte(iop_base,
9628 (ushort)(q_addr + (ushort)
9631 asc_dvc->unit_not_ready &= ~target_id;
9632 if (scsiq->d3.done_stat != QD_NO_ERROR) {
9633 asc_dvc->start_motor &=
9640 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
9642 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
9643 asc_isr_callback(asc_dvc, scsiq);
9651 static int AscISR(ASC_DVC_VAR *asc_dvc)
9653 ASC_CS_TYPE chipstat;
9655 ushort saved_ram_addr;
9657 uchar saved_ctrl_reg;
9662 iop_base = asc_dvc->iop_base;
9663 int_pending = FALSE;
9665 if (AscIsIntPending(iop_base) == 0)
9668 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
9671 if (asc_dvc->in_critical_cnt != 0) {
9672 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
9675 if (asc_dvc->is_in_int) {
9676 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
9679 asc_dvc->is_in_int = TRUE;
9680 ctrl_reg = AscGetChipControl(iop_base);
9681 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
9682 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
9683 chipstat = AscGetChipStatus(iop_base);
9684 if (chipstat & CSW_SCSI_RESET_LATCH) {
9685 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
9688 asc_dvc->sdtr_done = 0;
9689 saved_ctrl_reg &= (uchar)(~CC_HALT);
9690 while ((AscGetChipStatus(iop_base) &
9691 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
9694 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
9695 AscSetChipControl(iop_base, CC_HALT);
9696 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
9697 AscSetChipStatus(iop_base, 0);
9698 chipstat = AscGetChipStatus(iop_base);
9701 saved_ram_addr = AscGetChipLramAddr(iop_base);
9702 host_flag = AscReadLramByte(iop_base,
9704 (uchar)(~ASC_HOST_FLAG_IN_ISR);
9705 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
9706 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
9707 if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
9708 AscAckInterrupt(iop_base);
9710 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
9711 if (AscIsrChipHalted(asc_dvc) == ERR) {
9712 goto ISR_REPORT_QDONE_FATAL_ERROR;
9714 saved_ctrl_reg &= (uchar)(~CC_HALT);
9717 ISR_REPORT_QDONE_FATAL_ERROR:
9718 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
9720 AscIsrQDone(asc_dvc)) & 0x01) != 0) {
9725 AscIsrQDone(asc_dvc)) == 1) {
9728 } while (status == 0x11);
9730 if ((status & 0x80) != 0)
9734 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
9735 AscSetChipLramAddr(iop_base, saved_ram_addr);
9736 AscSetChipControl(iop_base, saved_ctrl_reg);
9737 asc_dvc->is_in_int = FALSE;
9744 * Reset the bus associated with the command 'scp'.
9746 * This function runs its own thread. Interrupts must be blocked but
9747 * sleeping is allowed and no locking other than for host structures is
9748 * required. Returns SUCCESS or FAILED.
9750 static int advansys_reset(struct scsi_cmnd *scp)
9752 struct Scsi_Host *shost = scp->device->host;
9753 struct asc_board *boardp = ASC_BOARDP(shost);
9754 unsigned long flags;
9758 ASC_DBG1(1, "advansys_reset: 0x%p\n", scp);
9760 ASC_STATS(shost, reset);
9762 scmd_printk(KERN_INFO, scp, "SCSI bus reset started...\n");
9764 if (ASC_NARROW_BOARD(boardp)) {
9765 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
9767 /* Reset the chip and SCSI bus. */
9768 ASC_DBG(1, "advansys_reset: before AscInitAsc1000Driver()\n");
9769 status = AscInitAsc1000Driver(asc_dvc);
9771 /* Refer to ASC_IERR_* defintions for meaning of 'err_code'. */
9772 if (asc_dvc->err_code) {
9773 scmd_printk(KERN_INFO, scp, "SCSI bus reset error: "
9774 "0x%x\n", asc_dvc->err_code);
9776 } else if (status) {
9777 scmd_printk(KERN_INFO, scp, "SCSI bus reset warning: "
9780 scmd_printk(KERN_INFO, scp, "SCSI bus reset "
9784 ASC_DBG(1, "advansys_reset: after AscInitAsc1000Driver()\n");
9785 spin_lock_irqsave(&boardp->lock, flags);
9788 * If the suggest reset bus flags are set, then reset the bus.
9789 * Otherwise only reset the device.
9791 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
9794 * Reset the target's SCSI bus.
9796 ASC_DBG(1, "advansys_reset: before AdvResetChipAndSB()\n");
9797 switch (AdvResetChipAndSB(adv_dvc)) {
9799 scmd_printk(KERN_INFO, scp, "SCSI bus reset "
9804 scmd_printk(KERN_INFO, scp, "SCSI bus reset error\n");
9808 spin_lock_irqsave(&boardp->lock, flags);
9812 /* Save the time of the most recently completed reset. */
9813 boardp->last_reset = jiffies;
9814 spin_unlock_irqrestore(&boardp->lock, flags);
9816 ASC_DBG1(1, "advansys_reset: ret %d\n", ret);
9822 * advansys_biosparam()
9824 * Translate disk drive geometry if the "BIOS greater than 1 GB"
9825 * support is enabled for a drive.
9827 * ip (information pointer) is an int array with the following definition:
9833 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
9834 sector_t capacity, int ip[])
9836 asc_board_t *boardp;
9838 ASC_DBG(1, "advansys_biosparam: begin\n");
9839 ASC_STATS(sdev->host, biosparam);
9840 boardp = ASC_BOARDP(sdev->host);
9841 if (ASC_NARROW_BOARD(boardp)) {
9842 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
9843 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
9851 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
9852 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
9860 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
9861 ASC_DBG(1, "advansys_biosparam: end\n");
9866 * First-level interrupt handler.
9868 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
9870 static irqreturn_t advansys_interrupt(int irq, void *dev_id)
9872 unsigned long flags;
9873 struct Scsi_Host *shost = dev_id;
9874 asc_board_t *boardp = ASC_BOARDP(shost);
9875 irqreturn_t result = IRQ_NONE;
9877 ASC_DBG1(2, "advansys_interrupt: boardp 0x%p\n", boardp);
9878 spin_lock_irqsave(&boardp->lock, flags);
9879 if (ASC_NARROW_BOARD(boardp)) {
9880 if (AscIsIntPending(shost->io_port)) {
9881 result = IRQ_HANDLED;
9882 ASC_STATS(shost, interrupt);
9883 ASC_DBG(1, "advansys_interrupt: before AscISR()\n");
9884 AscISR(&boardp->dvc_var.asc_dvc_var);
9887 ASC_DBG(1, "advansys_interrupt: before AdvISR()\n");
9888 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
9889 result = IRQ_HANDLED;
9890 ASC_STATS(shost, interrupt);
9893 spin_unlock_irqrestore(&boardp->lock, flags);
9895 ASC_DBG(1, "advansys_interrupt: end\n");
9899 static int AscHostReqRiscHalt(PortAddr iop_base)
9903 uchar saved_stop_code;
9905 if (AscIsChipHalted(iop_base))
9907 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
9908 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
9909 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
9911 if (AscIsChipHalted(iop_base)) {
9916 } while (count++ < 20);
9917 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
9922 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
9926 if (AscHostReqRiscHalt(iop_base)) {
9927 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
9928 AscStartChip(iop_base);
9933 static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
9935 char type = sdev->type;
9936 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
9938 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
9940 if (asc_dvc->init_sdtr & tid_bits)
9943 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
9944 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
9946 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
9947 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
9948 (type == TYPE_ROM) || (type == TYPE_TAPE))
9949 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
9951 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
9952 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
9953 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
9957 advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
9959 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
9960 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
9962 if (sdev->lun == 0) {
9963 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
9964 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
9965 asc_dvc->init_sdtr |= tid_bit;
9967 asc_dvc->init_sdtr &= ~tid_bit;
9970 if (orig_init_sdtr != asc_dvc->init_sdtr)
9971 AscAsyncFix(asc_dvc, sdev);
9974 if (sdev->tagged_supported) {
9975 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
9976 if (sdev->lun == 0) {
9977 asc_dvc->cfg->can_tagged_qng |= tid_bit;
9978 asc_dvc->use_tagged_qng |= tid_bit;
9980 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
9981 asc_dvc->max_dvc_qng[sdev->id]);
9984 if (sdev->lun == 0) {
9985 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
9986 asc_dvc->use_tagged_qng &= ~tid_bit;
9988 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
9991 if ((sdev->lun == 0) &&
9992 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
9993 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
9994 asc_dvc->cfg->disc_enable);
9995 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
9996 asc_dvc->use_tagged_qng);
9997 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
9998 asc_dvc->cfg->can_tagged_qng);
10000 asc_dvc->max_dvc_qng[sdev->id] =
10001 asc_dvc->cfg->max_tag_qng[sdev->id];
10002 AscWriteLramByte(asc_dvc->iop_base,
10003 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
10004 asc_dvc->max_dvc_qng[sdev->id]);
10011 * If the EEPROM enabled WDTR for the device and the device supports wide
10012 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
10013 * write the new value to the microcode.
10016 advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
10018 unsigned short cfg_word;
10019 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
10020 if ((cfg_word & tidmask) != 0)
10023 cfg_word |= tidmask;
10024 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
10027 * Clear the microcode SDTR and WDTR negotiation done indicators for
10028 * the target to cause it to negotiate with the new setting set above.
10029 * WDTR when accepted causes the target to enter asynchronous mode, so
10030 * SDTR must be negotiated.
10032 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
10033 cfg_word &= ~tidmask;
10034 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
10035 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
10036 cfg_word &= ~tidmask;
10037 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
10041 * Synchronous Transfers
10043 * If the EEPROM enabled SDTR for the device and the device
10044 * supports synchronous transfers, then turn on the device's
10045 * 'sdtr_able' bit. Write the new value to the microcode.
10048 advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
10050 unsigned short cfg_word;
10051 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
10052 if ((cfg_word & tidmask) != 0)
10055 cfg_word |= tidmask;
10056 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
10059 * Clear the microcode "SDTR negotiation" done indicator for the
10060 * target to cause it to negotiate with the new setting set above.
10062 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
10063 cfg_word &= ~tidmask;
10064 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
10068 * PPR (Parallel Protocol Request) Capable
10070 * If the device supports DT mode, then it must be PPR capable.
10071 * The PPR message will be used in place of the SDTR and WDTR
10072 * messages to negotiate synchronous speed and offset, transfer
10073 * width, and protocol options.
10075 static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
10076 AdvPortAddr iop_base, unsigned short tidmask)
10078 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
10079 adv_dvc->ppr_able |= tidmask;
10080 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
10084 advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
10086 AdvPortAddr iop_base = adv_dvc->iop_base;
10087 unsigned short tidmask = 1 << sdev->id;
10089 if (sdev->lun == 0) {
10091 * Handle WDTR, SDTR, and Tag Queuing. If the feature
10092 * is enabled in the EEPROM and the device supports the
10093 * feature, then enable it in the microcode.
10096 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
10097 advansys_wide_enable_wdtr(iop_base, tidmask);
10098 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
10099 advansys_wide_enable_sdtr(iop_base, tidmask);
10100 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
10101 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
10104 * Tag Queuing is disabled for the BIOS which runs in polled
10105 * mode and would see no benefit from Tag Queuing. Also by
10106 * disabling Tag Queuing in the BIOS devices with Tag Queuing
10107 * bugs will at least work with the BIOS.
10109 if ((adv_dvc->tagqng_able & tidmask) &&
10110 sdev->tagged_supported) {
10111 unsigned short cfg_word;
10112 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
10113 cfg_word |= tidmask;
10114 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
10116 AdvWriteByteLram(iop_base,
10117 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
10118 adv_dvc->max_dvc_qng);
10122 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported) {
10123 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
10124 adv_dvc->max_dvc_qng);
10126 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
10131 * Set the number of commands to queue per device for the
10132 * specified host adapter.
10134 static int advansys_slave_configure(struct scsi_device *sdev)
10136 asc_board_t *boardp = ASC_BOARDP(sdev->host);
10138 if (ASC_NARROW_BOARD(boardp))
10139 advansys_narrow_slave_configure(sdev,
10140 &boardp->dvc_var.asc_dvc_var);
10142 advansys_wide_slave_configure(sdev,
10143 &boardp->dvc_var.adv_dvc_var);
10148 static int asc_build_req(asc_board_t *boardp, struct scsi_cmnd *scp,
10149 struct asc_scsi_q *asc_scsi_q)
10151 memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
10154 * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'.
10156 asc_scsi_q->q2.srb_ptr = ASC_VADDR_TO_U32(scp);
10159 * Build the ASC_SCSI_Q request.
10161 asc_scsi_q->cdbptr = &scp->cmnd[0];
10162 asc_scsi_q->q2.cdb_len = scp->cmd_len;
10163 asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
10164 asc_scsi_q->q1.target_lun = scp->device->lun;
10165 asc_scsi_q->q2.target_ix =
10166 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
10167 asc_scsi_q->q1.sense_addr =
10168 cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
10169 asc_scsi_q->q1.sense_len = sizeof(scp->sense_buffer);
10172 * If there are any outstanding requests for the current target,
10173 * then every 255th request send an ORDERED request. This heuristic
10174 * tries to retain the benefit of request sorting while preventing
10175 * request starvation. 255 is the max number of tags or pending commands
10176 * a device may have outstanding.
10178 * The request count is incremented below for every successfully
10182 if ((boardp->dvc_var.asc_dvc_var.cur_dvc_qng[scp->device->id] > 0) &&
10183 (boardp->reqcnt[scp->device->id] % 255) == 0) {
10184 asc_scsi_q->q2.tag_code = MSG_ORDERED_TAG;
10186 asc_scsi_q->q2.tag_code = MSG_SIMPLE_TAG;
10190 * Build ASC_SCSI_Q for a contiguous buffer or a scatter-gather
10193 if (scp->use_sg == 0) {
10195 * CDB request of single contiguous buffer.
10197 ASC_STATS(scp->device->host, cont_cnt);
10198 scp->SCp.dma_handle = scp->request_bufflen ?
10199 dma_map_single(boardp->dev, scp->request_buffer,
10200 scp->request_bufflen,
10201 scp->sc_data_direction) : 0;
10202 asc_scsi_q->q1.data_addr = cpu_to_le32(scp->SCp.dma_handle);
10203 asc_scsi_q->q1.data_cnt = cpu_to_le32(scp->request_bufflen);
10204 ASC_STATS_ADD(scp->device->host, cont_xfer,
10205 ASC_CEILING(scp->request_bufflen, 512));
10206 asc_scsi_q->q1.sg_queue_cnt = 0;
10207 asc_scsi_q->sg_head = NULL;
10210 * CDB scatter-gather request list.
10214 struct scatterlist *slp;
10215 struct asc_sg_head *asc_sg_head;
10217 slp = (struct scatterlist *)scp->request_buffer;
10218 use_sg = dma_map_sg(boardp->dev, slp, scp->use_sg,
10219 scp->sc_data_direction);
10221 if (use_sg > scp->device->host->sg_tablesize) {
10222 ASC_PRINT3("asc_build_req: board %d: use_sg %d > "
10223 "sg_tablesize %d\n", boardp->id, use_sg,
10224 scp->device->host->sg_tablesize);
10225 dma_unmap_sg(boardp->dev, slp, scp->use_sg,
10226 scp->sc_data_direction);
10227 scp->result = HOST_BYTE(DID_ERROR);
10231 ASC_STATS(scp->device->host, sg_cnt);
10233 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
10234 use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
10235 if (!asc_sg_head) {
10236 dma_unmap_sg(boardp->dev, slp, scp->use_sg,
10237 scp->sc_data_direction);
10238 scp->result = HOST_BYTE(DID_SOFT_ERROR);
10242 asc_scsi_q->q1.cntl |= QC_SG_HEAD;
10243 asc_scsi_q->sg_head = asc_sg_head;
10244 asc_scsi_q->q1.data_cnt = 0;
10245 asc_scsi_q->q1.data_addr = 0;
10246 /* This is a byte value, otherwise it would need to be swapped. */
10247 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
10248 ASC_STATS_ADD(scp->device->host, sg_elem,
10249 asc_sg_head->entry_cnt);
10252 * Convert scatter-gather list into ASC_SG_HEAD list.
10254 for (sgcnt = 0; sgcnt < use_sg; sgcnt++, slp++) {
10255 asc_sg_head->sg_list[sgcnt].addr =
10256 cpu_to_le32(sg_dma_address(slp));
10257 asc_sg_head->sg_list[sgcnt].bytes =
10258 cpu_to_le32(sg_dma_len(slp));
10259 ASC_STATS_ADD(scp->device->host, sg_xfer,
10260 ASC_CEILING(sg_dma_len(slp), 512));
10264 ASC_DBG_PRT_ASC_SCSI_Q(2, &asc_scsi_q);
10265 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
10267 return ASC_NOERROR;
10271 * Build scatter-gather list for Adv Library (Wide Board).
10273 * Additional ADV_SG_BLOCK structures will need to be allocated
10274 * if the total number of scatter-gather elements exceeds
10275 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
10276 * assumed to be physically contiguous.
10279 * ADV_SUCCESS(1) - SG List successfully created
10280 * ADV_ERROR(-1) - SG List creation failed
10283 adv_get_sglist(asc_board_t *boardp, adv_req_t *reqp, struct scsi_cmnd *scp,
10286 adv_sgblk_t *sgblkp;
10287 ADV_SCSI_REQ_Q *scsiqp;
10288 struct scatterlist *slp;
10290 ADV_SG_BLOCK *sg_block, *prev_sg_block;
10291 ADV_PADDR sg_block_paddr;
10294 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
10295 slp = (struct scatterlist *)scp->request_buffer;
10296 sg_elem_cnt = use_sg;
10297 prev_sg_block = NULL;
10298 reqp->sgblkp = NULL;
10302 * Allocate a 'adv_sgblk_t' structure from the board free
10303 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
10304 * (15) scatter-gather elements.
10306 if ((sgblkp = boardp->adv_sgblkp) == NULL) {
10307 ASC_DBG(1, "adv_get_sglist: no free adv_sgblk_t\n");
10308 ASC_STATS(scp->device->host, adv_build_nosg);
10311 * Allocation failed. Free 'adv_sgblk_t' structures
10312 * already allocated for the request.
10314 while ((sgblkp = reqp->sgblkp) != NULL) {
10315 /* Remove 'sgblkp' from the request list. */
10316 reqp->sgblkp = sgblkp->next_sgblkp;
10318 /* Add 'sgblkp' to the board free list. */
10319 sgblkp->next_sgblkp = boardp->adv_sgblkp;
10320 boardp->adv_sgblkp = sgblkp;
10325 /* Complete 'adv_sgblk_t' board allocation. */
10326 boardp->adv_sgblkp = sgblkp->next_sgblkp;
10327 sgblkp->next_sgblkp = NULL;
10330 * Get 8 byte aligned virtual and physical addresses
10331 * for the allocated ADV_SG_BLOCK structure.
10333 sg_block = (ADV_SG_BLOCK *)ADV_8BALIGN(&sgblkp->sg_block);
10334 sg_block_paddr = virt_to_bus(sg_block);
10337 * Check if this is the first 'adv_sgblk_t' for the
10340 if (reqp->sgblkp == NULL) {
10341 /* Request's first scatter-gather block. */
10342 reqp->sgblkp = sgblkp;
10345 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
10346 * address pointers.
10348 scsiqp->sg_list_ptr = sg_block;
10349 scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr);
10351 /* Request's second or later scatter-gather block. */
10352 sgblkp->next_sgblkp = reqp->sgblkp;
10353 reqp->sgblkp = sgblkp;
10356 * Point the previous ADV_SG_BLOCK structure to
10357 * the newly allocated ADV_SG_BLOCK structure.
10359 prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr);
10362 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
10363 sg_block->sg_list[i].sg_addr =
10364 cpu_to_le32(sg_dma_address(slp));
10365 sg_block->sg_list[i].sg_count =
10366 cpu_to_le32(sg_dma_len(slp));
10367 ASC_STATS_ADD(scp->device->host, sg_xfer,
10368 ASC_CEILING(sg_dma_len(slp), 512));
10370 if (--sg_elem_cnt == 0) { /* Last ADV_SG_BLOCK and scatter-gather entry. */
10371 sg_block->sg_cnt = i + 1;
10372 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
10373 return ADV_SUCCESS;
10377 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
10378 prev_sg_block = sg_block;
10383 * Build a request structure for the Adv Library (Wide Board).
10385 * If an adv_req_t can not be allocated to issue the request,
10386 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
10388 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
10389 * microcode for DMA addresses or math operations are byte swapped
10390 * to little-endian order.
10393 adv_build_req(asc_board_t *boardp, struct scsi_cmnd *scp,
10394 ADV_SCSI_REQ_Q **adv_scsiqpp)
10397 ADV_SCSI_REQ_Q *scsiqp;
10402 * Allocate an adv_req_t structure from the board to execute
10405 if (boardp->adv_reqp == NULL) {
10406 ASC_DBG(1, "adv_build_req: no free adv_req_t\n");
10407 ASC_STATS(scp->device->host, adv_build_noreq);
10410 reqp = boardp->adv_reqp;
10411 boardp->adv_reqp = reqp->next_reqp;
10412 reqp->next_reqp = NULL;
10416 * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
10418 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
10421 * Initialize the structure.
10423 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
10426 * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure.
10428 scsiqp->srb_ptr = ASC_VADDR_TO_U32(reqp);
10431 * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure.
10436 * Build the ADV_SCSI_REQ_Q request.
10439 /* Set CDB length and copy it to the request structure. */
10440 scsiqp->cdb_len = scp->cmd_len;
10441 /* Copy first 12 CDB bytes to cdb[]. */
10442 for (i = 0; i < scp->cmd_len && i < 12; i++) {
10443 scsiqp->cdb[i] = scp->cmnd[i];
10445 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
10446 for (; i < scp->cmd_len; i++) {
10447 scsiqp->cdb16[i - 12] = scp->cmnd[i];
10450 scsiqp->target_id = scp->device->id;
10451 scsiqp->target_lun = scp->device->lun;
10453 scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
10454 scsiqp->sense_len = sizeof(scp->sense_buffer);
10457 * Build ADV_SCSI_REQ_Q for a contiguous buffer or a scatter-gather
10461 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
10462 scsiqp->vdata_addr = scp->request_buffer;
10463 scsiqp->data_addr = cpu_to_le32(virt_to_bus(scp->request_buffer));
10465 if (scp->use_sg == 0) {
10467 * CDB request of single contiguous buffer.
10469 reqp->sgblkp = NULL;
10470 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
10471 if (scp->request_bufflen) {
10472 scsiqp->vdata_addr = scp->request_buffer;
10473 scp->SCp.dma_handle =
10474 dma_map_single(boardp->dev, scp->request_buffer,
10475 scp->request_bufflen,
10476 scp->sc_data_direction);
10478 scsiqp->vdata_addr = NULL;
10479 scp->SCp.dma_handle = 0;
10481 scsiqp->data_addr = cpu_to_le32(scp->SCp.dma_handle);
10482 scsiqp->sg_list_ptr = NULL;
10483 scsiqp->sg_real_addr = 0;
10484 ASC_STATS(scp->device->host, cont_cnt);
10485 ASC_STATS_ADD(scp->device->host, cont_xfer,
10486 ASC_CEILING(scp->request_bufflen, 512));
10489 * CDB scatter-gather request list.
10491 struct scatterlist *slp;
10494 slp = (struct scatterlist *)scp->request_buffer;
10495 use_sg = dma_map_sg(boardp->dev, slp, scp->use_sg,
10496 scp->sc_data_direction);
10498 if (use_sg > ADV_MAX_SG_LIST) {
10499 ASC_PRINT3("adv_build_req: board %d: use_sg %d > "
10500 "ADV_MAX_SG_LIST %d\n", boardp->id, use_sg,
10501 scp->device->host->sg_tablesize);
10502 dma_unmap_sg(boardp->dev, slp, scp->use_sg,
10503 scp->sc_data_direction);
10504 scp->result = HOST_BYTE(DID_ERROR);
10507 * Free the 'adv_req_t' structure by adding it back
10508 * to the board free list.
10510 reqp->next_reqp = boardp->adv_reqp;
10511 boardp->adv_reqp = reqp;
10516 ret = adv_get_sglist(boardp, reqp, scp, use_sg);
10517 if (ret != ADV_SUCCESS) {
10519 * Free the adv_req_t structure by adding it back to
10520 * the board free list.
10522 reqp->next_reqp = boardp->adv_reqp;
10523 boardp->adv_reqp = reqp;
10528 ASC_STATS(scp->device->host, sg_cnt);
10529 ASC_STATS_ADD(scp->device->host, sg_elem, use_sg);
10532 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
10533 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
10535 *adv_scsiqpp = scsiqp;
10537 return ASC_NOERROR;
10540 static int AscSgListToQueue(int sg_list)
10544 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
10545 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
10547 return n_sg_list_qs + 1;
10551 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
10555 ASC_SCSI_BIT_ID_TYPE target_id;
10558 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
10559 tid_no = ASC_TIX_TO_TID(target_ix);
10560 if ((asc_dvc->unit_not_ready & target_id) ||
10561 (asc_dvc->queue_full_or_busy & target_id)) {
10565 cur_used_qs = (uint) asc_dvc->cur_total_qng +
10566 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
10568 cur_used_qs = (uint) asc_dvc->cur_total_qng +
10569 (uint) ASC_MIN_FREE_Q;
10571 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
10572 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
10573 if (asc_dvc->cur_dvc_qng[tid_no] >=
10574 asc_dvc->max_dvc_qng[tid_no]) {
10577 return cur_free_qs;
10580 if ((n_qs > asc_dvc->last_q_shortage)
10581 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
10582 asc_dvc->last_q_shortage = n_qs;
10588 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
10594 q_addr = ASC_QNO_TO_QADDR(free_q_head);
10595 q_status = (uchar)AscReadLramByte(iop_base,
10597 ASC_SCSIQ_B_STATUS));
10598 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
10599 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
10601 return ASC_QLINK_END;
10605 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
10609 for (i = 0; i < n_free_q; i++) {
10610 free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
10611 if (free_q_head == ASC_QLINK_END)
10614 return free_q_head;
10619 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
10621 * Calling/Exit State:
10625 * Output an ASC_SCSI_Q structure to the chip
10628 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
10632 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
10633 AscSetChipLramAddr(iop_base, s_addr);
10634 for (i = 0; i < 2 * words; i += 2) {
10635 if (i == 4 || i == 20) {
10638 outpw(iop_base + IOP_RAM_DATA,
10639 ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
10643 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
10648 uchar syn_period_ix;
10652 iop_base = asc_dvc->iop_base;
10653 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
10654 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
10655 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
10656 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10658 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
10659 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
10660 AscMsgOutSDTR(asc_dvc,
10661 asc_dvc->sdtr_period_tbl[syn_period_ix],
10663 scsiq->q1.cntl |= QC_MSG_OUT;
10665 q_addr = ASC_QNO_TO_QADDR(q_no);
10666 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
10667 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
10669 scsiq->q1.status = QS_FREE;
10670 AscMemWordCopyPtrToLram(iop_base,
10671 q_addr + ASC_SCSIQ_CDB_BEG,
10672 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
10674 DvcPutScsiQ(iop_base,
10675 q_addr + ASC_SCSIQ_CPY_BEG,
10676 (uchar *)&scsiq->q1.cntl,
10677 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
10678 AscWriteLramWord(iop_base,
10679 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
10680 (ushort)(((ushort)scsiq->q1.
10681 q_no << 8) | (ushort)QS_READY));
10686 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
10690 ASC_SG_HEAD *sg_head;
10691 ASC_SG_LIST_Q scsi_sg_q;
10692 ASC_DCNT saved_data_addr;
10693 ASC_DCNT saved_data_cnt;
10695 ushort sg_list_dwords;
10697 ushort sg_entry_cnt;
10701 iop_base = asc_dvc->iop_base;
10702 sg_head = scsiq->sg_head;
10703 saved_data_addr = scsiq->q1.data_addr;
10704 saved_data_cnt = scsiq->q1.data_cnt;
10705 scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
10706 scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
10707 #if CC_VERY_LONG_SG_LIST
10709 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
10710 * then not all SG elements will fit in the allocated queues.
10711 * The rest of the SG elements will be copied when the RISC
10712 * completes the SG elements that fit and halts.
10714 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
10716 * Set sg_entry_cnt to be the number of SG elements that
10717 * will fit in the allocated SG queues. It is minus 1, because
10718 * the first SG element is handled above. ASC_MAX_SG_LIST is
10719 * already inflated by 1 to account for this. For example it
10720 * may be 50 which is 1 + 7 queues * 7 SG elements.
10722 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
10725 * Keep track of remaining number of SG elements that will
10726 * need to be handled from a_isr.c.
10728 scsiq->remain_sg_entry_cnt =
10729 sg_head->entry_cnt - ASC_MAX_SG_LIST;
10731 #endif /* CC_VERY_LONG_SG_LIST */
10733 * Set sg_entry_cnt to be the number of SG elements that
10734 * will fit in the allocated SG queues. It is minus 1, because
10735 * the first SG element is handled above.
10737 sg_entry_cnt = sg_head->entry_cnt - 1;
10738 #if CC_VERY_LONG_SG_LIST
10740 #endif /* CC_VERY_LONG_SG_LIST */
10741 if (sg_entry_cnt != 0) {
10742 scsiq->q1.cntl |= QC_SG_HEAD;
10743 q_addr = ASC_QNO_TO_QADDR(q_no);
10745 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
10746 scsi_sg_q.sg_head_qp = q_no;
10747 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
10748 for (i = 0; i < sg_head->queue_cnt; i++) {
10749 scsi_sg_q.seq_no = i + 1;
10750 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
10751 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
10752 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
10754 scsi_sg_q.sg_list_cnt =
10756 scsi_sg_q.sg_cur_list_cnt =
10759 scsi_sg_q.sg_list_cnt =
10760 ASC_SG_LIST_PER_Q - 1;
10761 scsi_sg_q.sg_cur_list_cnt =
10762 ASC_SG_LIST_PER_Q - 1;
10765 #if CC_VERY_LONG_SG_LIST
10767 * This is the last SG queue in the list of
10768 * allocated SG queues. If there are more
10769 * SG elements than will fit in the allocated
10770 * queues, then set the QCSG_SG_XFER_MORE flag.
10772 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
10773 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
10775 #endif /* CC_VERY_LONG_SG_LIST */
10776 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
10777 #if CC_VERY_LONG_SG_LIST
10779 #endif /* CC_VERY_LONG_SG_LIST */
10780 sg_list_dwords = sg_entry_cnt << 1;
10782 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
10783 scsi_sg_q.sg_cur_list_cnt =
10786 scsi_sg_q.sg_list_cnt =
10788 scsi_sg_q.sg_cur_list_cnt =
10793 next_qp = AscReadLramByte(iop_base,
10796 scsi_sg_q.q_no = next_qp;
10797 q_addr = ASC_QNO_TO_QADDR(next_qp);
10798 AscMemWordCopyPtrToLram(iop_base,
10799 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
10800 (uchar *)&scsi_sg_q,
10801 sizeof(ASC_SG_LIST_Q) >> 1);
10802 AscMemDWordCopyPtrToLram(iop_base,
10803 q_addr + ASC_SGQ_LIST_BEG,
10804 (uchar *)&sg_head->
10807 sg_index += ASC_SG_LIST_PER_Q;
10808 scsiq->next_sg_index = sg_index;
10811 scsiq->q1.cntl &= ~QC_SG_HEAD;
10813 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
10814 scsiq->q1.data_addr = saved_data_addr;
10815 scsiq->q1.data_cnt = saved_data_cnt;
10820 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
10829 iop_base = asc_dvc->iop_base;
10830 target_ix = scsiq->q2.target_ix;
10831 tid_no = ASC_TIX_TO_TID(target_ix);
10833 free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
10834 if (n_q_required > 1) {
10835 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
10836 (uchar)n_q_required);
10837 if (next_qp != ASC_QLINK_END) {
10838 asc_dvc->last_q_shortage = 0;
10839 scsiq->sg_head->queue_cnt = n_q_required - 1;
10840 scsiq->q1.q_no = free_q_head;
10841 sta = AscPutReadySgListQueue(asc_dvc, scsiq,
10844 } else if (n_q_required == 1) {
10845 next_qp = AscAllocFreeQueue(iop_base, free_q_head);
10846 if (next_qp != ASC_QLINK_END) {
10847 scsiq->q1.q_no = free_q_head;
10848 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
10852 AscPutVarFreeQHead(iop_base, next_qp);
10853 asc_dvc->cur_total_qng += n_q_required;
10854 asc_dvc->cur_dvc_qng[tid_no]++;
10859 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
10860 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
10879 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
10884 int disable_syn_offset_one_fix;
10887 ushort sg_entry_cnt = 0;
10888 ushort sg_entry_cnt_minus_one = 0;
10895 ASC_SG_HEAD *sg_head;
10898 iop_base = asc_dvc->iop_base;
10899 sg_head = scsiq->sg_head;
10900 if (asc_dvc->err_code != 0)
10902 scsiq->q1.q_no = 0;
10903 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
10904 scsiq->q1.extra_bytes = 0;
10907 target_ix = scsiq->q2.target_ix;
10908 tid_no = ASC_TIX_TO_TID(target_ix);
10910 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
10911 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
10912 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
10913 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10914 AscMsgOutSDTR(asc_dvc,
10916 sdtr_period_tbl[(sdtr_data >> 4) &
10920 (uchar)(sdtr_data & (uchar)
10921 ASC_SYN_MAX_OFFSET));
10922 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
10925 if (asc_dvc->in_critical_cnt != 0) {
10926 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
10929 asc_dvc->in_critical_cnt++;
10930 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10931 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
10932 asc_dvc->in_critical_cnt--;
10935 #if !CC_VERY_LONG_SG_LIST
10936 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
10937 asc_dvc->in_critical_cnt--;
10940 #endif /* !CC_VERY_LONG_SG_LIST */
10941 if (sg_entry_cnt == 1) {
10942 scsiq->q1.data_addr =
10943 (ADV_PADDR)sg_head->sg_list[0].addr;
10944 scsiq->q1.data_cnt =
10945 (ADV_DCNT)sg_head->sg_list[0].bytes;
10946 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
10948 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
10950 scsi_cmd = scsiq->cdbptr[0];
10951 disable_syn_offset_one_fix = FALSE;
10952 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
10953 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
10954 if (scsiq->q1.cntl & QC_SG_HEAD) {
10956 for (i = 0; i < sg_entry_cnt; i++) {
10958 (ADV_DCNT)le32_to_cpu(sg_head->sg_list[i].
10962 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
10964 if (data_cnt != 0UL) {
10965 if (data_cnt < 512UL) {
10966 disable_syn_offset_one_fix = TRUE;
10968 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
10971 _syn_offset_one_disable_cmd[i];
10972 if (disable_cmd == 0xFF) {
10975 if (scsi_cmd == disable_cmd) {
10976 disable_syn_offset_one_fix =
10984 if (disable_syn_offset_one_fix) {
10985 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
10986 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
10987 ASC_TAG_FLAG_DISABLE_DISCONNECT);
10989 scsiq->q2.tag_code &= 0x27;
10991 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10992 if (asc_dvc->bug_fix_cntl) {
10993 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
10994 if ((scsi_cmd == READ_6) ||
10995 (scsi_cmd == READ_10)) {
10997 (ADV_PADDR)le32_to_cpu(sg_head->
10999 [sg_entry_cnt_minus_one].
11001 (ADV_DCNT)le32_to_cpu(sg_head->
11003 [sg_entry_cnt_minus_one].
11006 (uchar)((ushort)addr & 0x0003);
11007 if ((extra_bytes != 0)
11011 ASC_TAG_FLAG_EXTRA_BYTES)
11013 scsiq->q2.tag_code |=
11014 ASC_TAG_FLAG_EXTRA_BYTES;
11015 scsiq->q1.extra_bytes =
11018 le32_to_cpu(sg_head->
11020 [sg_entry_cnt_minus_one].
11023 (ASC_DCNT) extra_bytes;
11026 [sg_entry_cnt_minus_one].
11028 cpu_to_le32(data_cnt);
11033 sg_head->entry_to_copy = sg_head->entry_cnt;
11034 #if CC_VERY_LONG_SG_LIST
11036 * Set the sg_entry_cnt to the maximum possible. The rest of
11037 * the SG elements will be copied when the RISC completes the
11038 * SG elements that fit and halts.
11040 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
11041 sg_entry_cnt = ASC_MAX_SG_LIST;
11043 #endif /* CC_VERY_LONG_SG_LIST */
11044 n_q_required = AscSgListToQueue(sg_entry_cnt);
11045 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
11046 (uint) n_q_required)
11047 || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
11049 AscSendScsiQueue(asc_dvc, scsiq,
11050 n_q_required)) == 1) {
11051 asc_dvc->in_critical_cnt--;
11056 if (asc_dvc->bug_fix_cntl) {
11057 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
11058 if ((scsi_cmd == READ_6) ||
11059 (scsi_cmd == READ_10)) {
11061 le32_to_cpu(scsiq->q1.data_addr) +
11062 le32_to_cpu(scsiq->q1.data_cnt);
11064 (uchar)((ushort)addr & 0x0003);
11065 if ((extra_bytes != 0)
11069 ASC_TAG_FLAG_EXTRA_BYTES)
11072 le32_to_cpu(scsiq->q1.
11074 if (((ushort)data_cnt & 0x01FF)
11076 scsiq->q2.tag_code |=
11077 ASC_TAG_FLAG_EXTRA_BYTES;
11078 data_cnt -= (ASC_DCNT)
11080 scsiq->q1.data_cnt =
11083 scsiq->q1.extra_bytes =
11091 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
11092 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
11093 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
11094 n_q_required)) == 1) {
11095 asc_dvc->in_critical_cnt--;
11100 asc_dvc->in_critical_cnt--;
11105 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
11107 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
11108 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
11109 * RISC to notify it a new command is ready to be executed.
11111 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
11112 * set to SCSI_MAX_RETRY.
11114 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
11115 * for DMA addresses or math operations are byte swapped to little-endian
11119 * ADV_SUCCESS(1) - The request was successfully queued.
11120 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
11121 * request completes.
11122 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
11125 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq)
11127 AdvPortAddr iop_base;
11129 ADV_PADDR req_paddr;
11130 ADV_CARR_T *new_carrp;
11133 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
11135 if (scsiq->target_id > ADV_MAX_TID) {
11136 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
11137 scsiq->done_status = QD_WITH_ERROR;
11141 iop_base = asc_dvc->iop_base;
11144 * Allocate a carrier ensuring at least one carrier always
11145 * remains on the freelist and initialize fields.
11147 if ((new_carrp = asc_dvc->carr_freelist) == NULL) {
11150 asc_dvc->carr_freelist = (ADV_CARR_T *)
11151 ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa));
11152 asc_dvc->carr_pending_cnt++;
11155 * Set the carrier to be a stopper by setting 'next_vpa'
11156 * to the stopper value. The current stopper will be changed
11157 * below to point to the new stopper.
11159 new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
11162 * Clear the ADV_SCSI_REQ_Q done flag.
11164 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
11166 req_size = sizeof(ADV_SCSI_REQ_Q);
11167 req_paddr = DvcGetPhyAddr(asc_dvc, scsiq, (uchar *)scsiq,
11168 (ADV_SDCNT *)&req_size, ADV_IS_SCSIQ_FLAG);
11170 BUG_ON(req_paddr & 31);
11171 BUG_ON(req_size < sizeof(ADV_SCSI_REQ_Q));
11173 /* Wait for assertion before making little-endian */
11174 req_paddr = cpu_to_le32(req_paddr);
11176 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
11177 scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq));
11178 scsiq->scsiq_rptr = req_paddr;
11180 scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp));
11182 * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
11183 * order during initialization.
11185 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
11188 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
11189 * the microcode. The newly allocated stopper will become the new
11192 asc_dvc->icq_sp->areq_vpa = req_paddr;
11195 * Set the 'next_vpa' pointer for the old stopper to be the
11196 * physical address of the new stopper. The RISC can only
11197 * follow physical addresses.
11199 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
11202 * Set the host adapter stopper pointer to point to the new carrier.
11204 asc_dvc->icq_sp = new_carrp;
11206 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
11207 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11209 * Tickle the RISC to tell it to read its Command Queue Head pointer.
11211 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
11212 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
11214 * Clear the tickle value. In the ASC-3550 the RISC flag
11215 * command 'clr_tickle_a' does not work unless the host
11216 * value is cleared.
11218 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
11221 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
11223 * Notify the RISC a carrier is ready by writing the physical
11224 * address of the new carrier stopper to the COMMA register.
11226 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
11227 le32_to_cpu(new_carrp->carr_pa));
11230 return ADV_SUCCESS;
11234 * Execute a single 'Scsi_Cmnd'.
11236 * The function 'done' is called when the request has been completed.
11240 * host - board controlling device
11241 * device - device to send command
11242 * target - target of device
11243 * lun - lun of device
11244 * cmd_len - length of SCSI CDB
11245 * cmnd - buffer for SCSI 8, 10, or 12 byte CDB
11246 * use_sg - if non-zero indicates scatter-gather request with use_sg elements
11248 * if (use_sg == 0) {
11249 * request_buffer - buffer address for request
11250 * request_bufflen - length of request buffer
11252 * request_buffer - pointer to scatterlist structure
11255 * sense_buffer - sense command buffer
11257 * result (4 bytes of an int):
11259 * 0 SCSI Status Byte Code
11260 * 1 SCSI One Byte Message Code
11261 * 2 Host Error Code
11262 * 3 Mid-Level Error Code
11264 * host driver fields:
11265 * SCp - Scsi_Pointer used for command processing status
11266 * scsi_done - used to save caller's done function
11267 * host_scribble - used for pointer to another struct scsi_cmnd
11269 * If this function returns ASC_NOERROR the request will be completed
11270 * from the interrupt handler.
11272 * If this function returns ASC_ERROR the host error code has been set,
11273 * and the called must call asc_scsi_done.
11275 * If ASC_BUSY is returned the request will be returned to the midlayer
11276 * and re-tried later.
11278 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
11281 asc_board_t *boardp = ASC_BOARDP(scp->device->host);
11283 ASC_DBG1(1, "asc_execute_scsi_cmnd: scp 0x%p\n", scp);
11285 if (ASC_NARROW_BOARD(boardp)) {
11286 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
11287 struct asc_scsi_q asc_scsi_q;
11289 /* asc_build_req() can not return ASC_BUSY. */
11290 ret = asc_build_req(boardp, scp, &asc_scsi_q);
11291 if (ret == ASC_ERROR) {
11292 ASC_STATS(scp->device->host, build_error);
11296 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
11297 kfree(asc_scsi_q.sg_head);
11298 err_code = asc_dvc->err_code;
11300 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
11301 ADV_SCSI_REQ_Q *adv_scsiqp;
11303 switch (adv_build_req(boardp, scp, &adv_scsiqp)) {
11305 ASC_DBG(3, "asc_execute_scsi_cmnd: adv_build_req "
11309 ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req "
11312 * The asc_stats fields 'adv_build_noreq' and
11313 * 'adv_build_nosg' count wide board busy conditions.
11314 * They are updated in adv_build_req and
11315 * adv_get_sglist, respectively.
11320 ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req "
11322 ASC_STATS(scp->device->host, build_error);
11326 ret = AdvExeScsiQueue(adv_dvc, adv_scsiqp);
11327 err_code = adv_dvc->err_code;
11332 ASC_STATS(scp->device->host, exe_noerror);
11334 * Increment monotonically increasing per device
11335 * successful request counter. Wrapping doesn't matter.
11337 boardp->reqcnt[scp->device->id]++;
11338 ASC_DBG(1, "asc_execute_scsi_cmnd: ExeScsiQueue(), "
11342 ASC_STATS(scp->device->host, exe_busy);
11345 ASC_PRINT2("asc_execute_scsi_cmnd: board %d: ExeScsiQueue() "
11346 "ASC_ERROR, err_code 0x%x\n", boardp->id, err_code);
11347 ASC_STATS(scp->device->host, exe_error);
11348 scp->result = HOST_BYTE(DID_ERROR);
11351 ASC_PRINT2("asc_execute_scsi_cmnd: board %d: ExeScsiQueue() "
11352 "unknown, err_code 0x%x\n", boardp->id, err_code);
11353 ASC_STATS(scp->device->host, exe_unknown);
11354 scp->result = HOST_BYTE(DID_ERROR);
11358 ASC_DBG(1, "asc_execute_scsi_cmnd: end\n");
11363 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
11365 * This function always returns 0. Command return status is saved
11366 * in the 'scp' result field.
11369 advansys_queuecommand(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
11371 struct Scsi_Host *shost = scp->device->host;
11372 asc_board_t *boardp = ASC_BOARDP(shost);
11373 unsigned long flags;
11374 int asc_res, result = 0;
11376 ASC_STATS(shost, queuecommand);
11377 scp->scsi_done = done;
11380 * host_lock taken by mid-level prior to call, but need
11381 * to protect against own ISR
11383 spin_lock_irqsave(&boardp->lock, flags);
11384 asc_res = asc_execute_scsi_cmnd(scp);
11385 spin_unlock_irqrestore(&boardp->lock, flags);
11391 result = SCSI_MLQUEUE_HOST_BUSY;
11395 asc_scsi_done(scp);
11402 static ushort __devinit AscGetEisaChipCfg(PortAddr iop_base)
11404 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
11405 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
11406 return inpw(eisa_cfg_iop);
11410 * Return the BIOS address of the adapter at the specified
11411 * I/O port and with the specified bus type.
11413 static unsigned short __devinit
11414 AscGetChipBiosAddress(PortAddr iop_base, unsigned short bus_type)
11416 unsigned short cfg_lsw;
11417 unsigned short bios_addr;
11420 * The PCI BIOS is re-located by the motherboard BIOS. Because
11421 * of this the driver can not determine where a PCI BIOS is
11422 * loaded and executes.
11424 if (bus_type & ASC_IS_PCI)
11427 if ((bus_type & ASC_IS_EISA) != 0) {
11428 cfg_lsw = AscGetEisaChipCfg(iop_base);
11430 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
11434 cfg_lsw = AscGetChipCfgLsw(iop_base);
11437 * ISA PnP uses the top bit as the 32K BIOS flag
11439 if (bus_type == ASC_IS_ISAPNP)
11441 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
11445 static uchar __devinit AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
11449 if (AscGetChipScsiID(iop_base) == new_host_id) {
11450 return (new_host_id);
11452 cfg_lsw = AscGetChipCfgLsw(iop_base);
11454 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
11455 AscSetChipCfgLsw(iop_base, cfg_lsw);
11456 return (AscGetChipScsiID(iop_base));
11459 static unsigned char __devinit AscGetChipScsiCtrl(PortAddr iop_base)
11463 AscSetBank(iop_base, 1);
11464 sc = inp(iop_base + IOP_REG_SC);
11465 AscSetBank(iop_base, 0);
11469 static unsigned char __devinit
11470 AscGetChipVersion(PortAddr iop_base, unsigned short bus_type)
11472 if (bus_type & ASC_IS_EISA) {
11474 unsigned char revision;
11475 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
11476 (PortAddr) ASC_EISA_REV_IOP_MASK;
11477 revision = inp(eisa_iop);
11478 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
11480 return AscGetChipVerNo(iop_base);
11483 static void __devinit AscToggleIRQAct(PortAddr iop_base)
11485 AscSetChipStatus(iop_base, CIW_IRQ_ACT);
11486 AscSetChipStatus(iop_base, 0);
11490 static uchar __devinit AscGetChipIRQ(PortAddr iop_base, ushort bus_type)
11495 if ((bus_type & ASC_IS_EISA) != 0) {
11496 cfg_lsw = AscGetEisaChipCfg(iop_base);
11497 chip_irq = (uchar)(((cfg_lsw >> 8) & 0x07) + 10);
11498 if ((chip_irq == 13) || (chip_irq > 15)) {
11503 if ((bus_type & ASC_IS_VL) != 0) {
11504 cfg_lsw = AscGetChipCfgLsw(iop_base);
11505 chip_irq = (uchar)(((cfg_lsw >> 2) & 0x07));
11506 if ((chip_irq == 0) || (chip_irq == 4) || (chip_irq == 7)) {
11509 return ((uchar)(chip_irq + (ASC_MIN_IRQ_NO - 1)));
11511 cfg_lsw = AscGetChipCfgLsw(iop_base);
11512 chip_irq = (uchar)(((cfg_lsw >> 2) & 0x03));
11514 chip_irq += (uchar)2;
11515 return ((uchar)(chip_irq + ASC_MIN_IRQ_NO));
11518 static uchar __devinit
11519 AscSetChipIRQ(PortAddr iop_base, uchar irq_no, ushort bus_type)
11523 if ((bus_type & ASC_IS_VL) != 0) {
11525 if ((irq_no < ASC_MIN_IRQ_NO)
11526 || (irq_no > ASC_MAX_IRQ_NO)) {
11529 irq_no -= (uchar)((ASC_MIN_IRQ_NO - 1));
11532 cfg_lsw = (ushort)(AscGetChipCfgLsw(iop_base) & 0xFFE3);
11533 cfg_lsw |= (ushort)0x0010;
11534 AscSetChipCfgLsw(iop_base, cfg_lsw);
11535 AscToggleIRQAct(iop_base);
11536 cfg_lsw = (ushort)(AscGetChipCfgLsw(iop_base) & 0xFFE0);
11537 cfg_lsw |= (ushort)((irq_no & 0x07) << 2);
11538 AscSetChipCfgLsw(iop_base, cfg_lsw);
11539 AscToggleIRQAct(iop_base);
11540 return (AscGetChipIRQ(iop_base, bus_type));
11542 if ((bus_type & (ASC_IS_ISA)) != 0) {
11544 irq_no -= (uchar)2;
11545 irq_no -= (uchar)ASC_MIN_IRQ_NO;
11546 cfg_lsw = (ushort)(AscGetChipCfgLsw(iop_base) & 0xFFF3);
11547 cfg_lsw |= (ushort)((irq_no & 0x03) << 2);
11548 AscSetChipCfgLsw(iop_base, cfg_lsw);
11549 return (AscGetChipIRQ(iop_base, bus_type));
11555 static void __devinit AscEnableIsaDma(uchar dma_channel)
11557 if (dma_channel < 4) {
11558 outp(0x000B, (ushort)(0xC0 | dma_channel));
11559 outp(0x000A, dma_channel);
11560 } else if (dma_channel < 8) {
11561 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
11562 outp(0x00D4, (ushort)(dma_channel - 4));
11566 #endif /* CONFIG_ISA */
11568 static int AscStopQueueExe(PortAddr iop_base)
11572 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
11573 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
11574 ASC_STOP_REQ_RISC_STOP);
11576 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
11577 ASC_STOP_ACK_RISC_STOP) {
11581 } while (count++ < 20);
11586 static ASC_DCNT __devinit AscGetMaxDmaCount(ushort bus_type)
11588 if (bus_type & ASC_IS_ISA)
11589 return ASC_MAX_ISA_DMA_COUNT;
11590 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
11591 return ASC_MAX_VL_DMA_COUNT;
11592 return ASC_MAX_PCI_DMA_COUNT;
11596 static ushort __devinit AscGetIsaDmaChannel(PortAddr iop_base)
11600 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
11601 if (channel == 0x03)
11603 else if (channel == 0x00)
11605 return (channel + 4);
11608 static ushort __devinit AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
11613 if ((dma_channel >= 5) && (dma_channel <= 7)) {
11614 if (dma_channel == 7)
11617 value = dma_channel - 4;
11618 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
11620 AscSetChipCfgLsw(iop_base, cfg_lsw);
11621 return (AscGetIsaDmaChannel(iop_base));
11626 static uchar __devinit AscGetIsaDmaSpeed(PortAddr iop_base)
11630 AscSetBank(iop_base, 1);
11631 speed_value = AscReadChipDmaSpeed(iop_base);
11632 speed_value &= 0x07;
11633 AscSetBank(iop_base, 0);
11634 return speed_value;
11637 static uchar __devinit AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
11639 speed_value &= 0x07;
11640 AscSetBank(iop_base, 1);
11641 AscWriteChipDmaSpeed(iop_base, speed_value);
11642 AscSetBank(iop_base, 0);
11643 return AscGetIsaDmaSpeed(iop_base);
11645 #endif /* CONFIG_ISA */
11647 static ushort __devinit AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
11652 uchar chip_version;
11654 iop_base = asc_dvc->iop_base;
11656 asc_dvc->err_code = 0;
11657 if ((asc_dvc->bus_type &
11658 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
11659 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
11661 AscSetChipControl(iop_base, CC_HALT);
11662 AscSetChipStatus(iop_base, 0);
11663 asc_dvc->bug_fix_cntl = 0;
11664 asc_dvc->pci_fix_asyn_xfer = 0;
11665 asc_dvc->pci_fix_asyn_xfer_always = 0;
11666 /* asc_dvc->init_state initalized in AscInitGetConfig(). */
11667 asc_dvc->sdtr_done = 0;
11668 asc_dvc->cur_total_qng = 0;
11669 asc_dvc->is_in_int = 0;
11670 asc_dvc->in_critical_cnt = 0;
11671 asc_dvc->last_q_shortage = 0;
11672 asc_dvc->use_tagged_qng = 0;
11673 asc_dvc->no_scam = 0;
11674 asc_dvc->unit_not_ready = 0;
11675 asc_dvc->queue_full_or_busy = 0;
11676 asc_dvc->redo_scam = 0;
11678 asc_dvc->host_init_sdtr_index = 0;
11679 asc_dvc->cfg->can_tagged_qng = 0;
11680 asc_dvc->cfg->cmd_qng_enabled = 0;
11681 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
11682 asc_dvc->init_sdtr = 0;
11683 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
11684 asc_dvc->scsi_reset_wait = 3;
11685 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
11686 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
11687 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
11688 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
11689 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
11690 asc_dvc->cfg->lib_serial_no = ASC_LIB_SERIAL_NUMBER;
11691 asc_dvc->cfg->lib_version = (ASC_LIB_VERSION_MAJOR << 8) |
11692 ASC_LIB_VERSION_MINOR;
11693 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
11694 asc_dvc->cfg->chip_version = chip_version;
11695 asc_dvc->sdtr_period_tbl[0] = SYN_XFER_NS_0;
11696 asc_dvc->sdtr_period_tbl[1] = SYN_XFER_NS_1;
11697 asc_dvc->sdtr_period_tbl[2] = SYN_XFER_NS_2;
11698 asc_dvc->sdtr_period_tbl[3] = SYN_XFER_NS_3;
11699 asc_dvc->sdtr_period_tbl[4] = SYN_XFER_NS_4;
11700 asc_dvc->sdtr_period_tbl[5] = SYN_XFER_NS_5;
11701 asc_dvc->sdtr_period_tbl[6] = SYN_XFER_NS_6;
11702 asc_dvc->sdtr_period_tbl[7] = SYN_XFER_NS_7;
11703 asc_dvc->max_sdtr_index = 7;
11704 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
11705 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
11706 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
11707 asc_dvc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0;
11708 asc_dvc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1;
11709 asc_dvc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2;
11710 asc_dvc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3;
11711 asc_dvc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4;
11712 asc_dvc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5;
11713 asc_dvc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6;
11714 asc_dvc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7;
11715 asc_dvc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8;
11716 asc_dvc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9;
11717 asc_dvc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10;
11718 asc_dvc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11;
11719 asc_dvc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12;
11720 asc_dvc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13;
11721 asc_dvc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14;
11722 asc_dvc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15;
11723 asc_dvc->max_sdtr_index = 15;
11724 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
11725 AscSetExtraControl(iop_base,
11726 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
11727 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
11728 AscSetExtraControl(iop_base,
11729 (SEC_ACTIVE_NEGATE |
11730 SEC_ENABLE_FILTER));
11733 if (asc_dvc->bus_type == ASC_IS_PCI) {
11734 AscSetExtraControl(iop_base,
11735 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
11738 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
11740 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
11741 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
11742 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
11743 asc_dvc->bus_type = ASC_IS_ISAPNP;
11745 asc_dvc->cfg->isa_dma_channel =
11746 (uchar)AscGetIsaDmaChannel(iop_base);
11748 #endif /* CONFIG_ISA */
11749 for (i = 0; i <= ASC_MAX_TID; i++) {
11750 asc_dvc->cur_dvc_qng[i] = 0;
11751 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
11752 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
11753 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
11754 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
11759 static int __devinit AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
11763 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
11764 unsigned char read_back;
11765 AscSetChipEEPCmd(iop_base, cmd_reg);
11767 read_back = AscGetChipEEPCmd(iop_base);
11768 if (read_back == cmd_reg)
11774 static void __devinit AscWaitEEPRead(void)
11779 static ushort __devinit AscReadEEPWord(PortAddr iop_base, uchar addr)
11784 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
11786 cmd_reg = addr | ASC_EEP_CMD_READ;
11787 AscWriteEEPCmdReg(iop_base, cmd_reg);
11789 read_wval = AscGetChipEEPData(iop_base);
11794 static ushort __devinit
11795 AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
11802 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
11805 wbuf = (ushort *)cfg_buf;
11807 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
11808 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11809 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
11812 if (bus_type & ASC_IS_VL) {
11813 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11814 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11816 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11817 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11819 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11820 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
11821 if (s_addr <= uchar_end_in_config) {
11823 * Swap all char fields - must unswap bytes already swapped
11824 * by AscReadEEPWord().
11826 *wbuf = le16_to_cpu(wval);
11828 /* Don't swap word field at the end - cntl field. */
11831 sum += wval; /* Checksum treats all EEPROM data as words. */
11834 * Read the checksum word which will be compared against 'sum'
11835 * by the caller. Word field already swapped.
11837 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
11841 static int __devinit AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
11848 iop_base = asc_dvc->iop_base;
11850 q_addr = ASC_QNO_TO_QADDR(241);
11851 saved_word = AscReadLramWord(iop_base, q_addr);
11852 AscSetChipLramAddr(iop_base, q_addr);
11853 AscSetChipLramData(iop_base, 0x55AA);
11855 AscSetChipLramAddr(iop_base, q_addr);
11856 if (AscGetChipLramData(iop_base) == 0x55AA) {
11858 AscWriteLramWord(iop_base, q_addr, saved_word);
11863 static void __devinit AscWaitEEPWrite(void)
11869 static int __devinit AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
11876 AscSetChipEEPData(iop_base, data_reg);
11878 read_back = AscGetChipEEPData(iop_base);
11879 if (read_back == data_reg) {
11882 if (retry++ > ASC_EEP_MAX_RETRY) {
11888 static ushort __devinit
11889 AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
11893 read_wval = AscReadEEPWord(iop_base, addr);
11894 if (read_wval != word_val) {
11895 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
11897 AscWriteEEPDataReg(iop_base, word_val);
11899 AscWriteEEPCmdReg(iop_base,
11900 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
11902 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
11904 return (AscReadEEPWord(iop_base, addr));
11906 return (read_wval);
11909 static int __devinit
11910 AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
11919 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
11921 wbuf = (ushort *)cfg_buf;
11924 /* Write two config words; AscWriteEEPWord() will swap bytes. */
11925 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11927 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
11931 if (bus_type & ASC_IS_VL) {
11932 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11933 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11935 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11936 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11938 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11939 if (s_addr <= uchar_end_in_config) {
11941 * This is a char field. Swap char fields before they are
11942 * swapped again by AscWriteEEPWord().
11944 word = cpu_to_le16(*wbuf);
11946 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
11950 /* Don't swap word field at the end - cntl field. */
11952 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
11956 sum += *wbuf; /* Checksum calculated from word values. */
11958 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
11960 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
11964 /* Read EEPROM back again. */
11965 wbuf = (ushort *)cfg_buf;
11967 * Read two config words; Byte-swapping done by AscReadEEPWord().
11969 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
11970 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
11974 if (bus_type & ASC_IS_VL) {
11975 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
11976 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
11978 cfg_beg = ASC_EEP_DVC_CFG_BEG;
11979 cfg_end = ASC_EEP_MAX_DVC_ADDR;
11981 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
11982 if (s_addr <= uchar_end_in_config) {
11984 * Swap all char fields. Must unswap bytes already swapped
11985 * by AscReadEEPWord().
11988 le16_to_cpu(AscReadEEPWord
11989 (iop_base, (uchar)s_addr));
11991 /* Don't swap word field at the end - cntl field. */
11992 word = AscReadEEPWord(iop_base, (uchar)s_addr);
11994 if (*wbuf != word) {
11998 /* Read checksum; Byte swapping not needed. */
11999 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
12005 static int __devinit
12006 AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type)
12013 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
12017 if (++retry > ASC_EEP_MAX_RETRY) {
12024 static ushort __devinit AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
12026 ASCEEP_CONFIG eep_config_buf;
12027 ASCEEP_CONFIG *eep_config;
12031 ushort cfg_msw, cfg_lsw;
12035 iop_base = asc_dvc->iop_base;
12037 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
12038 AscStopQueueExe(iop_base);
12039 if ((AscStopChip(iop_base) == FALSE) ||
12040 (AscGetChipScsiCtrl(iop_base) != 0)) {
12041 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
12042 AscResetChipAndScsiBus(asc_dvc);
12043 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
12045 if (AscIsChipHalted(iop_base) == FALSE) {
12046 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
12047 return (warn_code);
12049 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
12050 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
12051 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
12052 return (warn_code);
12054 eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
12055 cfg_msw = AscGetChipCfgMsw(iop_base);
12056 cfg_lsw = AscGetChipCfgLsw(iop_base);
12057 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
12058 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
12059 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
12060 AscSetChipCfgMsw(iop_base, cfg_msw);
12062 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
12063 ASC_DBG1(1, "AscInitFromEEP: chksum 0x%x\n", chksum);
12067 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
12068 warn_code |= ASC_WARN_AUTO_CONFIG;
12069 if (asc_dvc->cfg->chip_version == 3) {
12070 if (eep_config->cfg_lsw != cfg_lsw) {
12071 warn_code |= ASC_WARN_EEPROM_RECOVER;
12072 eep_config->cfg_lsw =
12073 AscGetChipCfgLsw(iop_base);
12075 if (eep_config->cfg_msw != cfg_msw) {
12076 warn_code |= ASC_WARN_EEPROM_RECOVER;
12077 eep_config->cfg_msw =
12078 AscGetChipCfgMsw(iop_base);
12082 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
12083 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
12084 ASC_DBG1(1, "AscInitFromEEP: eep_config->chksum 0x%x\n",
12085 eep_config->chksum);
12086 if (chksum != eep_config->chksum) {
12087 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
12088 ASC_CHIP_VER_PCI_ULTRA_3050) {
12090 "AscInitFromEEP: chksum error ignored; EEPROM-less board\n");
12091 eep_config->init_sdtr = 0xFF;
12092 eep_config->disc_enable = 0xFF;
12093 eep_config->start_motor = 0xFF;
12094 eep_config->use_cmd_qng = 0;
12095 eep_config->max_total_qng = 0xF0;
12096 eep_config->max_tag_qng = 0x20;
12097 eep_config->cntl = 0xBFFF;
12098 ASC_EEP_SET_CHIP_ID(eep_config, 7);
12099 eep_config->no_scam = 0;
12100 eep_config->adapter_info[0] = 0;
12101 eep_config->adapter_info[1] = 0;
12102 eep_config->adapter_info[2] = 0;
12103 eep_config->adapter_info[3] = 0;
12104 eep_config->adapter_info[4] = 0;
12105 /* Indicate EEPROM-less board. */
12106 eep_config->adapter_info[5] = 0xBB;
12109 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
12111 warn_code |= ASC_WARN_EEPROM_CHKSUM;
12114 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
12115 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
12116 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
12117 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
12118 asc_dvc->start_motor = eep_config->start_motor;
12119 asc_dvc->dvc_cntl = eep_config->cntl;
12120 asc_dvc->no_scam = eep_config->no_scam;
12121 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
12122 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
12123 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
12124 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
12125 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
12126 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
12127 if (!AscTestExternalLram(asc_dvc)) {
12128 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
12129 ASC_IS_PCI_ULTRA)) {
12130 eep_config->max_total_qng =
12131 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
12132 eep_config->max_tag_qng =
12133 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
12135 eep_config->cfg_msw |= 0x0800;
12137 AscSetChipCfgMsw(iop_base, cfg_msw);
12138 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
12139 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
12143 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
12144 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
12146 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
12147 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
12149 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
12150 eep_config->max_tag_qng = eep_config->max_total_qng;
12152 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
12153 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
12155 asc_dvc->max_total_qng = eep_config->max_total_qng;
12156 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
12157 eep_config->use_cmd_qng) {
12158 eep_config->disc_enable = eep_config->use_cmd_qng;
12159 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
12161 if (asc_dvc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA)) {
12162 asc_dvc->irq_no = AscGetChipIRQ(iop_base, asc_dvc->bus_type);
12164 ASC_EEP_SET_CHIP_ID(eep_config,
12165 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
12166 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
12167 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
12168 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
12169 asc_dvc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
12172 for (i = 0; i <= ASC_MAX_TID; i++) {
12173 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
12174 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
12175 asc_dvc->cfg->sdtr_period_offset[i] =
12176 (uchar)(ASC_DEF_SDTR_OFFSET |
12177 (asc_dvc->host_init_sdtr_index << 4));
12179 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
12181 if ((i = AscSetEEPConfig(iop_base, eep_config,
12182 asc_dvc->bus_type)) != 0) {
12184 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
12188 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
12191 return (warn_code);
12194 static int __devinit AscInitGetConfig(asc_board_t *boardp)
12196 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
12197 unsigned short warn_code = 0;
12199 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
12200 if (asc_dvc->err_code != 0)
12201 return asc_dvc->err_code;
12203 if (AscFindSignature(asc_dvc->iop_base)) {
12204 warn_code |= AscInitAscDvcVar(asc_dvc);
12205 warn_code |= AscInitFromEEP(asc_dvc);
12206 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
12207 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
12208 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
12210 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
12213 switch (warn_code) {
12214 case 0: /* No error */
12216 case ASC_WARN_IO_PORT_ROTATE:
12217 ASC_PRINT1("AscInitGetConfig: board %d: I/O port address "
12218 "modified\n", boardp->id);
12220 case ASC_WARN_AUTO_CONFIG:
12221 ASC_PRINT1("AscInitGetConfig: board %d: I/O port increment "
12222 "switch enabled\n", boardp->id);
12224 case ASC_WARN_EEPROM_CHKSUM:
12225 ASC_PRINT1("AscInitGetConfig: board %d: EEPROM checksum "
12226 "error\n", boardp->id);
12228 case ASC_WARN_IRQ_MODIFIED:
12229 ASC_PRINT1("AscInitGetConfig: board %d: IRQ modified\n",
12232 case ASC_WARN_CMD_QNG_CONFLICT:
12233 ASC_PRINT1("AscInitGetConfig: board %d: tag queuing enabled "
12234 "w/o disconnects\n", boardp->id);
12237 ASC_PRINT2("AscInitGetConfig: board %d: unknown warning: "
12238 "0x%x\n", boardp->id, warn_code);
12242 if (asc_dvc->err_code != 0) {
12243 ASC_PRINT3("AscInitGetConfig: board %d error: init_state 0x%x, "
12244 "err_code 0x%x\n", boardp->id, asc_dvc->init_state,
12245 asc_dvc->err_code);
12248 return asc_dvc->err_code;
12251 static int __devinit AscInitSetConfig(struct pci_dev *pdev, asc_board_t *boardp)
12253 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
12254 PortAddr iop_base = asc_dvc->iop_base;
12255 unsigned short cfg_msw;
12256 unsigned short warn_code = 0;
12258 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
12259 if (asc_dvc->err_code != 0)
12260 return asc_dvc->err_code;
12261 if (!AscFindSignature(asc_dvc->iop_base)) {
12262 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
12263 return asc_dvc->err_code;
12266 cfg_msw = AscGetChipCfgMsw(iop_base);
12267 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
12268 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
12269 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
12270 AscSetChipCfgMsw(iop_base, cfg_msw);
12272 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
12273 asc_dvc->cfg->cmd_qng_enabled) {
12274 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
12275 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
12277 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
12278 warn_code |= ASC_WARN_AUTO_CONFIG;
12280 if ((asc_dvc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) {
12281 if (AscSetChipIRQ(iop_base, asc_dvc->irq_no, asc_dvc->bus_type)
12282 != asc_dvc->irq_no) {
12283 asc_dvc->err_code |= ASC_IERR_SET_IRQ_NO;
12287 if (asc_dvc->bus_type & ASC_IS_PCI) {
12289 AscSetChipCfgMsw(iop_base, cfg_msw);
12290 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
12292 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
12293 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
12294 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
12295 asc_dvc->bug_fix_cntl |=
12296 ASC_BUG_FIX_ASYN_USE_SYN;
12300 #endif /* CONFIG_PCI */
12301 if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
12302 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
12303 == ASC_CHIP_VER_ASYN_BUG) {
12304 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
12307 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
12308 asc_dvc->cfg->chip_scsi_id) {
12309 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
12312 if (asc_dvc->bus_type & ASC_IS_ISA) {
12313 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
12314 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
12316 #endif /* CONFIG_ISA */
12318 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
12320 switch (warn_code) {
12321 case 0: /* No error. */
12323 case ASC_WARN_IO_PORT_ROTATE:
12324 ASC_PRINT1("AscInitSetConfig: board %d: I/O port address "
12325 "modified\n", boardp->id);
12327 case ASC_WARN_AUTO_CONFIG:
12328 ASC_PRINT1("AscInitSetConfig: board %d: I/O port increment "
12329 "switch enabled\n", boardp->id);
12331 case ASC_WARN_EEPROM_CHKSUM:
12332 ASC_PRINT1("AscInitSetConfig: board %d: EEPROM checksum "
12333 "error\n", boardp->id);
12335 case ASC_WARN_IRQ_MODIFIED:
12336 ASC_PRINT1("AscInitSetConfig: board %d: IRQ modified\n",
12339 case ASC_WARN_CMD_QNG_CONFLICT:
12340 ASC_PRINT1("AscInitSetConfig: board %d: tag queuing w/o "
12345 ASC_PRINT2("AscInitSetConfig: board %d: unknown warning: "
12346 "0x%x\n", boardp->id, warn_code);
12350 if (asc_dvc->err_code != 0) {
12351 ASC_PRINT3("AscInitSetConfig: board %d error: init_state 0x%x, "
12352 "err_code 0x%x\n", boardp->id, asc_dvc->init_state,
12353 asc_dvc->err_code);
12356 return asc_dvc->err_code;
12360 * EEPROM Configuration.
12362 * All drivers should use this structure to set the default EEPROM
12363 * configuration. The BIOS now uses this structure when it is built.
12364 * Additional structure information can be found in a_condor.h where
12365 * the structure is defined.
12367 * The *_Field_IsChar structs are needed to correct for endianness.
12368 * These values are read from the board 16 bits at a time directly
12369 * into the structs. Because some fields are char, the values will be
12370 * in the wrong order. The *_Field_IsChar tells when to flip the
12371 * bytes. Data read and written to PCI memory is automatically swapped
12372 * on big-endian platforms so char fields read as words are actually being
12373 * unswapped on big-endian platforms.
12375 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config __devinitdata = {
12376 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
12377 0x0000, /* cfg_msw */
12378 0xFFFF, /* disc_enable */
12379 0xFFFF, /* wdtr_able */
12380 0xFFFF, /* sdtr_able */
12381 0xFFFF, /* start_motor */
12382 0xFFFF, /* tagqng_able */
12383 0xFFFF, /* bios_scan */
12384 0, /* scam_tolerant */
12385 7, /* adapter_scsi_id */
12386 0, /* bios_boot_delay */
12387 3, /* scsi_reset_delay */
12388 0, /* bios_id_lun */
12389 0, /* termination */
12391 0xFFE7, /* bios_ctrl */
12392 0xFFFF, /* ultra_able */
12394 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
12395 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
12398 0, /* serial_number_word1 */
12399 0, /* serial_number_word2 */
12400 0, /* serial_number_word3 */
12402 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
12403 , /* oem_name[16] */
12404 0, /* dvc_err_code */
12405 0, /* adv_err_code */
12406 0, /* adv_err_addr */
12407 0, /* saved_dvc_err_code */
12408 0, /* saved_adv_err_code */
12409 0, /* saved_adv_err_addr */
12413 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar __devinitdata = {
12416 0, /* -disc_enable */
12419 0, /* start_motor */
12420 0, /* tagqng_able */
12422 0, /* scam_tolerant */
12423 1, /* adapter_scsi_id */
12424 1, /* bios_boot_delay */
12425 1, /* scsi_reset_delay */
12426 1, /* bios_id_lun */
12427 1, /* termination */
12430 0, /* ultra_able */
12432 1, /* max_host_qng */
12433 1, /* max_dvc_qng */
12436 0, /* serial_number_word1 */
12437 0, /* serial_number_word2 */
12438 0, /* serial_number_word3 */
12440 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12441 , /* oem_name[16] */
12442 0, /* dvc_err_code */
12443 0, /* adv_err_code */
12444 0, /* adv_err_addr */
12445 0, /* saved_dvc_err_code */
12446 0, /* saved_adv_err_code */
12447 0, /* saved_adv_err_addr */
12451 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config __devinitdata = {
12452 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
12453 0x0000, /* 01 cfg_msw */
12454 0xFFFF, /* 02 disc_enable */
12455 0xFFFF, /* 03 wdtr_able */
12456 0x4444, /* 04 sdtr_speed1 */
12457 0xFFFF, /* 05 start_motor */
12458 0xFFFF, /* 06 tagqng_able */
12459 0xFFFF, /* 07 bios_scan */
12460 0, /* 08 scam_tolerant */
12461 7, /* 09 adapter_scsi_id */
12462 0, /* bios_boot_delay */
12463 3, /* 10 scsi_reset_delay */
12464 0, /* bios_id_lun */
12465 0, /* 11 termination_se */
12466 0, /* termination_lvd */
12467 0xFFE7, /* 12 bios_ctrl */
12468 0x4444, /* 13 sdtr_speed2 */
12469 0x4444, /* 14 sdtr_speed3 */
12470 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
12471 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
12472 0, /* 16 dvc_cntl */
12473 0x4444, /* 17 sdtr_speed4 */
12474 0, /* 18 serial_number_word1 */
12475 0, /* 19 serial_number_word2 */
12476 0, /* 20 serial_number_word3 */
12477 0, /* 21 check_sum */
12478 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
12479 , /* 22-29 oem_name[16] */
12480 0, /* 30 dvc_err_code */
12481 0, /* 31 adv_err_code */
12482 0, /* 32 adv_err_addr */
12483 0, /* 33 saved_dvc_err_code */
12484 0, /* 34 saved_adv_err_code */
12485 0, /* 35 saved_adv_err_addr */
12486 0, /* 36 reserved */
12487 0, /* 37 reserved */
12488 0, /* 38 reserved */
12489 0, /* 39 reserved */
12490 0, /* 40 reserved */
12491 0, /* 41 reserved */
12492 0, /* 42 reserved */
12493 0, /* 43 reserved */
12494 0, /* 44 reserved */
12495 0, /* 45 reserved */
12496 0, /* 46 reserved */
12497 0, /* 47 reserved */
12498 0, /* 48 reserved */
12499 0, /* 49 reserved */
12500 0, /* 50 reserved */
12501 0, /* 51 reserved */
12502 0, /* 52 reserved */
12503 0, /* 53 reserved */
12504 0, /* 54 reserved */
12505 0, /* 55 reserved */
12506 0, /* 56 cisptr_lsw */
12507 0, /* 57 cisprt_msw */
12508 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
12509 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
12510 0, /* 60 reserved */
12511 0, /* 61 reserved */
12512 0, /* 62 reserved */
12513 0 /* 63 reserved */
12516 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar __devinitdata = {
12517 0, /* 00 cfg_lsw */
12518 0, /* 01 cfg_msw */
12519 0, /* 02 disc_enable */
12520 0, /* 03 wdtr_able */
12521 0, /* 04 sdtr_speed1 */
12522 0, /* 05 start_motor */
12523 0, /* 06 tagqng_able */
12524 0, /* 07 bios_scan */
12525 0, /* 08 scam_tolerant */
12526 1, /* 09 adapter_scsi_id */
12527 1, /* bios_boot_delay */
12528 1, /* 10 scsi_reset_delay */
12529 1, /* bios_id_lun */
12530 1, /* 11 termination_se */
12531 1, /* termination_lvd */
12532 0, /* 12 bios_ctrl */
12533 0, /* 13 sdtr_speed2 */
12534 0, /* 14 sdtr_speed3 */
12535 1, /* 15 max_host_qng */
12536 1, /* max_dvc_qng */
12537 0, /* 16 dvc_cntl */
12538 0, /* 17 sdtr_speed4 */
12539 0, /* 18 serial_number_word1 */
12540 0, /* 19 serial_number_word2 */
12541 0, /* 20 serial_number_word3 */
12542 0, /* 21 check_sum */
12543 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12544 , /* 22-29 oem_name[16] */
12545 0, /* 30 dvc_err_code */
12546 0, /* 31 adv_err_code */
12547 0, /* 32 adv_err_addr */
12548 0, /* 33 saved_dvc_err_code */
12549 0, /* 34 saved_adv_err_code */
12550 0, /* 35 saved_adv_err_addr */
12551 0, /* 36 reserved */
12552 0, /* 37 reserved */
12553 0, /* 38 reserved */
12554 0, /* 39 reserved */
12555 0, /* 40 reserved */
12556 0, /* 41 reserved */
12557 0, /* 42 reserved */
12558 0, /* 43 reserved */
12559 0, /* 44 reserved */
12560 0, /* 45 reserved */
12561 0, /* 46 reserved */
12562 0, /* 47 reserved */
12563 0, /* 48 reserved */
12564 0, /* 49 reserved */
12565 0, /* 50 reserved */
12566 0, /* 51 reserved */
12567 0, /* 52 reserved */
12568 0, /* 53 reserved */
12569 0, /* 54 reserved */
12570 0, /* 55 reserved */
12571 0, /* 56 cisptr_lsw */
12572 0, /* 57 cisprt_msw */
12573 0, /* 58 subsysvid */
12574 0, /* 59 subsysid */
12575 0, /* 60 reserved */
12576 0, /* 61 reserved */
12577 0, /* 62 reserved */
12578 0 /* 63 reserved */
12581 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config __devinitdata = {
12582 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
12583 0x0000, /* 01 cfg_msw */
12584 0xFFFF, /* 02 disc_enable */
12585 0xFFFF, /* 03 wdtr_able */
12586 0x5555, /* 04 sdtr_speed1 */
12587 0xFFFF, /* 05 start_motor */
12588 0xFFFF, /* 06 tagqng_able */
12589 0xFFFF, /* 07 bios_scan */
12590 0, /* 08 scam_tolerant */
12591 7, /* 09 adapter_scsi_id */
12592 0, /* bios_boot_delay */
12593 3, /* 10 scsi_reset_delay */
12594 0, /* bios_id_lun */
12595 0, /* 11 termination_se */
12596 0, /* termination_lvd */
12597 0xFFE7, /* 12 bios_ctrl */
12598 0x5555, /* 13 sdtr_speed2 */
12599 0x5555, /* 14 sdtr_speed3 */
12600 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
12601 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
12602 0, /* 16 dvc_cntl */
12603 0x5555, /* 17 sdtr_speed4 */
12604 0, /* 18 serial_number_word1 */
12605 0, /* 19 serial_number_word2 */
12606 0, /* 20 serial_number_word3 */
12607 0, /* 21 check_sum */
12608 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
12609 , /* 22-29 oem_name[16] */
12610 0, /* 30 dvc_err_code */
12611 0, /* 31 adv_err_code */
12612 0, /* 32 adv_err_addr */
12613 0, /* 33 saved_dvc_err_code */
12614 0, /* 34 saved_adv_err_code */
12615 0, /* 35 saved_adv_err_addr */
12616 0, /* 36 reserved */
12617 0, /* 37 reserved */
12618 0, /* 38 reserved */
12619 0, /* 39 reserved */
12620 0, /* 40 reserved */
12621 0, /* 41 reserved */
12622 0, /* 42 reserved */
12623 0, /* 43 reserved */
12624 0, /* 44 reserved */
12625 0, /* 45 reserved */
12626 0, /* 46 reserved */
12627 0, /* 47 reserved */
12628 0, /* 48 reserved */
12629 0, /* 49 reserved */
12630 0, /* 50 reserved */
12631 0, /* 51 reserved */
12632 0, /* 52 reserved */
12633 0, /* 53 reserved */
12634 0, /* 54 reserved */
12635 0, /* 55 reserved */
12636 0, /* 56 cisptr_lsw */
12637 0, /* 57 cisprt_msw */
12638 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
12639 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
12640 0, /* 60 reserved */
12641 0, /* 61 reserved */
12642 0, /* 62 reserved */
12643 0 /* 63 reserved */
12646 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar __devinitdata = {
12647 0, /* 00 cfg_lsw */
12648 0, /* 01 cfg_msw */
12649 0, /* 02 disc_enable */
12650 0, /* 03 wdtr_able */
12651 0, /* 04 sdtr_speed1 */
12652 0, /* 05 start_motor */
12653 0, /* 06 tagqng_able */
12654 0, /* 07 bios_scan */
12655 0, /* 08 scam_tolerant */
12656 1, /* 09 adapter_scsi_id */
12657 1, /* bios_boot_delay */
12658 1, /* 10 scsi_reset_delay */
12659 1, /* bios_id_lun */
12660 1, /* 11 termination_se */
12661 1, /* termination_lvd */
12662 0, /* 12 bios_ctrl */
12663 0, /* 13 sdtr_speed2 */
12664 0, /* 14 sdtr_speed3 */
12665 1, /* 15 max_host_qng */
12666 1, /* max_dvc_qng */
12667 0, /* 16 dvc_cntl */
12668 0, /* 17 sdtr_speed4 */
12669 0, /* 18 serial_number_word1 */
12670 0, /* 19 serial_number_word2 */
12671 0, /* 20 serial_number_word3 */
12672 0, /* 21 check_sum */
12673 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
12674 , /* 22-29 oem_name[16] */
12675 0, /* 30 dvc_err_code */
12676 0, /* 31 adv_err_code */
12677 0, /* 32 adv_err_addr */
12678 0, /* 33 saved_dvc_err_code */
12679 0, /* 34 saved_adv_err_code */
12680 0, /* 35 saved_adv_err_addr */
12681 0, /* 36 reserved */
12682 0, /* 37 reserved */
12683 0, /* 38 reserved */
12684 0, /* 39 reserved */
12685 0, /* 40 reserved */
12686 0, /* 41 reserved */
12687 0, /* 42 reserved */
12688 0, /* 43 reserved */
12689 0, /* 44 reserved */
12690 0, /* 45 reserved */
12691 0, /* 46 reserved */
12692 0, /* 47 reserved */
12693 0, /* 48 reserved */
12694 0, /* 49 reserved */
12695 0, /* 50 reserved */
12696 0, /* 51 reserved */
12697 0, /* 52 reserved */
12698 0, /* 53 reserved */
12699 0, /* 54 reserved */
12700 0, /* 55 reserved */
12701 0, /* 56 cisptr_lsw */
12702 0, /* 57 cisprt_msw */
12703 0, /* 58 subsysvid */
12704 0, /* 59 subsysid */
12705 0, /* 60 reserved */
12706 0, /* 61 reserved */
12707 0, /* 62 reserved */
12708 0 /* 63 reserved */
12713 * Wait for EEPROM command to complete
12715 static void __devinit AdvWaitEEPCmd(AdvPortAddr iop_base)
12719 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
12720 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
12721 ASC_EEP_CMD_DONE) {
12726 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
12732 * Read the EEPROM from specified location
12734 static ushort __devinit AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
12736 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12737 ASC_EEP_CMD_READ | eep_word_addr);
12738 AdvWaitEEPCmd(iop_base);
12739 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
12743 * Write the EEPROM from 'cfg_buf'.
12746 AdvSet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
12749 ushort addr, chksum;
12750 ushort *charfields;
12752 wbuf = (ushort *)cfg_buf;
12753 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
12756 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12757 AdvWaitEEPCmd(iop_base);
12760 * Write EEPROM from word 0 to word 20.
12762 for (addr = ADV_EEP_DVC_CFG_BEGIN;
12763 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
12766 if (*charfields++) {
12767 word = cpu_to_le16(*wbuf);
12771 chksum += *wbuf; /* Checksum is calculated from word values. */
12772 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12773 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12774 ASC_EEP_CMD_WRITE | addr);
12775 AdvWaitEEPCmd(iop_base);
12776 mdelay(ADV_EEP_DELAY_MS);
12780 * Write EEPROM checksum at word 21.
12782 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
12783 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
12784 AdvWaitEEPCmd(iop_base);
12789 * Write EEPROM OEM name at words 22 to 29.
12791 for (addr = ADV_EEP_DVC_CTL_BEGIN;
12792 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
12795 if (*charfields++) {
12796 word = cpu_to_le16(*wbuf);
12800 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12801 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12802 ASC_EEP_CMD_WRITE | addr);
12803 AdvWaitEEPCmd(iop_base);
12805 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
12806 AdvWaitEEPCmd(iop_base);
12810 * Write the EEPROM from 'cfg_buf'.
12813 AdvSet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
12816 ushort *charfields;
12817 ushort addr, chksum;
12819 wbuf = (ushort *)cfg_buf;
12820 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
12823 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12824 AdvWaitEEPCmd(iop_base);
12827 * Write EEPROM from word 0 to word 20.
12829 for (addr = ADV_EEP_DVC_CFG_BEGIN;
12830 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
12833 if (*charfields++) {
12834 word = cpu_to_le16(*wbuf);
12838 chksum += *wbuf; /* Checksum is calculated from word values. */
12839 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12840 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12841 ASC_EEP_CMD_WRITE | addr);
12842 AdvWaitEEPCmd(iop_base);
12843 mdelay(ADV_EEP_DELAY_MS);
12847 * Write EEPROM checksum at word 21.
12849 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
12850 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
12851 AdvWaitEEPCmd(iop_base);
12856 * Write EEPROM OEM name at words 22 to 29.
12858 for (addr = ADV_EEP_DVC_CTL_BEGIN;
12859 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
12862 if (*charfields++) {
12863 word = cpu_to_le16(*wbuf);
12867 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12868 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12869 ASC_EEP_CMD_WRITE | addr);
12870 AdvWaitEEPCmd(iop_base);
12872 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
12873 AdvWaitEEPCmd(iop_base);
12877 * Write the EEPROM from 'cfg_buf'.
12880 AdvSet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
12883 ushort *charfields;
12884 ushort addr, chksum;
12886 wbuf = (ushort *)cfg_buf;
12887 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
12890 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
12891 AdvWaitEEPCmd(iop_base);
12894 * Write EEPROM from word 0 to word 20.
12896 for (addr = ADV_EEP_DVC_CFG_BEGIN;
12897 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
12900 if (*charfields++) {
12901 word = cpu_to_le16(*wbuf);
12905 chksum += *wbuf; /* Checksum is calculated from word values. */
12906 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12907 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12908 ASC_EEP_CMD_WRITE | addr);
12909 AdvWaitEEPCmd(iop_base);
12910 mdelay(ADV_EEP_DELAY_MS);
12914 * Write EEPROM checksum at word 21.
12916 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
12917 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
12918 AdvWaitEEPCmd(iop_base);
12923 * Write EEPROM OEM name at words 22 to 29.
12925 for (addr = ADV_EEP_DVC_CTL_BEGIN;
12926 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
12929 if (*charfields++) {
12930 word = cpu_to_le16(*wbuf);
12934 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
12935 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
12936 ASC_EEP_CMD_WRITE | addr);
12937 AdvWaitEEPCmd(iop_base);
12939 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
12940 AdvWaitEEPCmd(iop_base);
12944 * Read EEPROM configuration into the specified buffer.
12946 * Return a checksum based on the EEPROM configuration read.
12948 static ushort __devinit
12949 AdvGet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
12951 ushort wval, chksum;
12954 ushort *charfields;
12956 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
12957 wbuf = (ushort *)cfg_buf;
12960 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
12961 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
12962 wval = AdvReadEEPWord(iop_base, eep_addr);
12963 chksum += wval; /* Checksum is calculated from word values. */
12964 if (*charfields++) {
12965 *wbuf = le16_to_cpu(wval);
12970 /* Read checksum word. */
12971 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12975 /* Read rest of EEPROM not covered by the checksum. */
12976 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
12977 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
12978 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
12979 if (*charfields++) {
12980 *wbuf = le16_to_cpu(*wbuf);
12987 * Read EEPROM configuration into the specified buffer.
12989 * Return a checksum based on the EEPROM configuration read.
12991 static ushort __devinit
12992 AdvGet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf)
12994 ushort wval, chksum;
12997 ushort *charfields;
12999 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
13000 wbuf = (ushort *)cfg_buf;
13003 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
13004 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
13005 wval = AdvReadEEPWord(iop_base, eep_addr);
13006 chksum += wval; /* Checksum is calculated from word values. */
13007 if (*charfields++) {
13008 *wbuf = le16_to_cpu(wval);
13013 /* Read checksum word. */
13014 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
13018 /* Read rest of EEPROM not covered by the checksum. */
13019 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
13020 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
13021 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
13022 if (*charfields++) {
13023 *wbuf = le16_to_cpu(*wbuf);
13030 * Read EEPROM configuration into the specified buffer.
13032 * Return a checksum based on the EEPROM configuration read.
13034 static ushort __devinit
13035 AdvGet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf)
13037 ushort wval, chksum;
13040 ushort *charfields;
13042 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
13043 wbuf = (ushort *)cfg_buf;
13046 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
13047 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
13048 wval = AdvReadEEPWord(iop_base, eep_addr);
13049 chksum += wval; /* Checksum is calculated from word values. */
13050 if (*charfields++) {
13051 *wbuf = le16_to_cpu(wval);
13056 /* Read checksum word. */
13057 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
13061 /* Read rest of EEPROM not covered by the checksum. */
13062 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
13063 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
13064 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
13065 if (*charfields++) {
13066 *wbuf = le16_to_cpu(*wbuf);
13073 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
13074 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
13075 * all of this is done.
13077 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
13079 * For a non-fatal error return a warning code. If there are no warnings
13080 * then 0 is returned.
13082 * Note: Chip is stopped on entry.
13084 static int __devinit AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
13086 AdvPortAddr iop_base;
13088 ADVEEP_3550_CONFIG eep_config;
13090 iop_base = asc_dvc->iop_base;
13095 * Read the board's EEPROM configuration.
13097 * Set default values if a bad checksum is found.
13099 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
13100 warn_code |= ASC_WARN_EEPROM_CHKSUM;
13103 * Set EEPROM default values.
13105 memcpy(&eep_config, &Default_3550_EEPROM_Config,
13106 sizeof(ADVEEP_3550_CONFIG));
13109 * Assume the 6 byte board serial number that was read from
13110 * EEPROM is correct even if the EEPROM checksum failed.
13112 eep_config.serial_number_word3 =
13113 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
13115 eep_config.serial_number_word2 =
13116 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
13118 eep_config.serial_number_word1 =
13119 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
13121 AdvSet3550EEPConfig(iop_base, &eep_config);
13124 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
13125 * EEPROM configuration that was read.
13127 * This is the mapping of EEPROM fields to Adv Library fields.
13129 asc_dvc->wdtr_able = eep_config.wdtr_able;
13130 asc_dvc->sdtr_able = eep_config.sdtr_able;
13131 asc_dvc->ultra_able = eep_config.ultra_able;
13132 asc_dvc->tagqng_able = eep_config.tagqng_able;
13133 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
13134 asc_dvc->max_host_qng = eep_config.max_host_qng;
13135 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13136 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
13137 asc_dvc->start_motor = eep_config.start_motor;
13138 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
13139 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
13140 asc_dvc->no_scam = eep_config.scam_tolerant;
13141 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
13142 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
13143 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
13146 * Set the host maximum queuing (max. 253, min. 16) and the per device
13147 * maximum queuing (max. 63, min. 4).
13149 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
13150 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13151 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
13152 /* If the value is zero, assume it is uninitialized. */
13153 if (eep_config.max_host_qng == 0) {
13154 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13156 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
13160 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
13161 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13162 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
13163 /* If the value is zero, assume it is uninitialized. */
13164 if (eep_config.max_dvc_qng == 0) {
13165 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13167 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
13172 * If 'max_dvc_qng' is greater than 'max_host_qng', then
13173 * set 'max_dvc_qng' to 'max_host_qng'.
13175 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
13176 eep_config.max_dvc_qng = eep_config.max_host_qng;
13180 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
13181 * values based on possibly adjusted EEPROM values.
13183 asc_dvc->max_host_qng = eep_config.max_host_qng;
13184 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13187 * If the EEPROM 'termination' field is set to automatic (0), then set
13188 * the ADV_DVC_CFG 'termination' field to automatic also.
13190 * If the termination is specified with a non-zero 'termination'
13191 * value check that a legal value is set and set the ADV_DVC_CFG
13192 * 'termination' field appropriately.
13194 if (eep_config.termination == 0) {
13195 asc_dvc->cfg->termination = 0; /* auto termination */
13197 /* Enable manual control with low off / high off. */
13198 if (eep_config.termination == 1) {
13199 asc_dvc->cfg->termination = TERM_CTL_SEL;
13201 /* Enable manual control with low off / high on. */
13202 } else if (eep_config.termination == 2) {
13203 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
13205 /* Enable manual control with low on / high on. */
13206 } else if (eep_config.termination == 3) {
13207 asc_dvc->cfg->termination =
13208 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
13211 * The EEPROM 'termination' field contains a bad value. Use
13212 * automatic termination instead.
13214 asc_dvc->cfg->termination = 0;
13215 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13223 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
13224 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
13225 * all of this is done.
13227 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
13229 * For a non-fatal error return a warning code. If there are no warnings
13230 * then 0 is returned.
13232 * Note: Chip is stopped on entry.
13234 static int __devinit AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
13236 AdvPortAddr iop_base;
13238 ADVEEP_38C0800_CONFIG eep_config;
13239 uchar tid, termination;
13240 ushort sdtr_speed = 0;
13242 iop_base = asc_dvc->iop_base;
13247 * Read the board's EEPROM configuration.
13249 * Set default values if a bad checksum is found.
13251 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
13252 eep_config.check_sum) {
13253 warn_code |= ASC_WARN_EEPROM_CHKSUM;
13256 * Set EEPROM default values.
13258 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
13259 sizeof(ADVEEP_38C0800_CONFIG));
13262 * Assume the 6 byte board serial number that was read from
13263 * EEPROM is correct even if the EEPROM checksum failed.
13265 eep_config.serial_number_word3 =
13266 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
13268 eep_config.serial_number_word2 =
13269 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
13271 eep_config.serial_number_word1 =
13272 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
13274 AdvSet38C0800EEPConfig(iop_base, &eep_config);
13277 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
13278 * EEPROM configuration that was read.
13280 * This is the mapping of EEPROM fields to Adv Library fields.
13282 asc_dvc->wdtr_able = eep_config.wdtr_able;
13283 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
13284 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
13285 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
13286 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
13287 asc_dvc->tagqng_able = eep_config.tagqng_able;
13288 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
13289 asc_dvc->max_host_qng = eep_config.max_host_qng;
13290 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13291 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
13292 asc_dvc->start_motor = eep_config.start_motor;
13293 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
13294 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
13295 asc_dvc->no_scam = eep_config.scam_tolerant;
13296 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
13297 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
13298 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
13301 * For every Target ID if any of its 'sdtr_speed[1234]' bits
13302 * are set, then set an 'sdtr_able' bit for it.
13304 asc_dvc->sdtr_able = 0;
13305 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
13307 sdtr_speed = asc_dvc->sdtr_speed1;
13308 } else if (tid == 4) {
13309 sdtr_speed = asc_dvc->sdtr_speed2;
13310 } else if (tid == 8) {
13311 sdtr_speed = asc_dvc->sdtr_speed3;
13312 } else if (tid == 12) {
13313 sdtr_speed = asc_dvc->sdtr_speed4;
13315 if (sdtr_speed & ADV_MAX_TID) {
13316 asc_dvc->sdtr_able |= (1 << tid);
13322 * Set the host maximum queuing (max. 253, min. 16) and the per device
13323 * maximum queuing (max. 63, min. 4).
13325 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
13326 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13327 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
13328 /* If the value is zero, assume it is uninitialized. */
13329 if (eep_config.max_host_qng == 0) {
13330 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13332 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
13336 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
13337 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13338 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
13339 /* If the value is zero, assume it is uninitialized. */
13340 if (eep_config.max_dvc_qng == 0) {
13341 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13343 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
13348 * If 'max_dvc_qng' is greater than 'max_host_qng', then
13349 * set 'max_dvc_qng' to 'max_host_qng'.
13351 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
13352 eep_config.max_dvc_qng = eep_config.max_host_qng;
13356 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
13357 * values based on possibly adjusted EEPROM values.
13359 asc_dvc->max_host_qng = eep_config.max_host_qng;
13360 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13363 * If the EEPROM 'termination' field is set to automatic (0), then set
13364 * the ADV_DVC_CFG 'termination' field to automatic also.
13366 * If the termination is specified with a non-zero 'termination'
13367 * value check that a legal value is set and set the ADV_DVC_CFG
13368 * 'termination' field appropriately.
13370 if (eep_config.termination_se == 0) {
13371 termination = 0; /* auto termination for SE */
13373 /* Enable manual control with low off / high off. */
13374 if (eep_config.termination_se == 1) {
13377 /* Enable manual control with low off / high on. */
13378 } else if (eep_config.termination_se == 2) {
13379 termination = TERM_SE_HI;
13381 /* Enable manual control with low on / high on. */
13382 } else if (eep_config.termination_se == 3) {
13383 termination = TERM_SE;
13386 * The EEPROM 'termination_se' field contains a bad value.
13387 * Use automatic termination instead.
13390 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13394 if (eep_config.termination_lvd == 0) {
13395 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
13397 /* Enable manual control with low off / high off. */
13398 if (eep_config.termination_lvd == 1) {
13399 asc_dvc->cfg->termination = termination;
13401 /* Enable manual control with low off / high on. */
13402 } else if (eep_config.termination_lvd == 2) {
13403 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
13405 /* Enable manual control with low on / high on. */
13406 } else if (eep_config.termination_lvd == 3) {
13407 asc_dvc->cfg->termination = termination | TERM_LVD;
13410 * The EEPROM 'termination_lvd' field contains a bad value.
13411 * Use automatic termination instead.
13413 asc_dvc->cfg->termination = termination;
13414 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13422 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
13423 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
13424 * all of this is done.
13426 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
13428 * For a non-fatal error return a warning code. If there are no warnings
13429 * then 0 is returned.
13431 * Note: Chip is stopped on entry.
13433 static int __devinit AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
13435 AdvPortAddr iop_base;
13437 ADVEEP_38C1600_CONFIG eep_config;
13438 uchar tid, termination;
13439 ushort sdtr_speed = 0;
13441 iop_base = asc_dvc->iop_base;
13446 * Read the board's EEPROM configuration.
13448 * Set default values if a bad checksum is found.
13450 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
13451 eep_config.check_sum) {
13452 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
13453 warn_code |= ASC_WARN_EEPROM_CHKSUM;
13456 * Set EEPROM default values.
13458 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
13459 sizeof(ADVEEP_38C1600_CONFIG));
13461 if (PCI_FUNC(pdev->devfn) != 0) {
13464 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
13465 * and old Mac system booting problem. The Expansion
13466 * ROM must be disabled in Function 1 for these systems
13468 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
13470 * Clear the INTAB (bit 11) if the GPIO 0 input
13471 * indicates the Function 1 interrupt line is wired
13474 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
13475 * 1 - Function 1 interrupt line wired to INT A.
13476 * 0 - Function 1 interrupt line wired to INT B.
13478 * Note: Function 0 is always wired to INTA.
13479 * Put all 5 GPIO bits in input mode and then read
13480 * their input values.
13482 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
13483 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
13484 if ((ints & 0x01) == 0)
13485 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
13489 * Assume the 6 byte board serial number that was read from
13490 * EEPROM is correct even if the EEPROM checksum failed.
13492 eep_config.serial_number_word3 =
13493 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
13494 eep_config.serial_number_word2 =
13495 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
13496 eep_config.serial_number_word1 =
13497 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
13499 AdvSet38C1600EEPConfig(iop_base, &eep_config);
13503 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
13504 * EEPROM configuration that was read.
13506 * This is the mapping of EEPROM fields to Adv Library fields.
13508 asc_dvc->wdtr_able = eep_config.wdtr_able;
13509 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
13510 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
13511 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
13512 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
13513 asc_dvc->ppr_able = 0;
13514 asc_dvc->tagqng_able = eep_config.tagqng_able;
13515 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
13516 asc_dvc->max_host_qng = eep_config.max_host_qng;
13517 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13518 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
13519 asc_dvc->start_motor = eep_config.start_motor;
13520 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
13521 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
13522 asc_dvc->no_scam = eep_config.scam_tolerant;
13525 * For every Target ID if any of its 'sdtr_speed[1234]' bits
13526 * are set, then set an 'sdtr_able' bit for it.
13528 asc_dvc->sdtr_able = 0;
13529 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
13531 sdtr_speed = asc_dvc->sdtr_speed1;
13532 } else if (tid == 4) {
13533 sdtr_speed = asc_dvc->sdtr_speed2;
13534 } else if (tid == 8) {
13535 sdtr_speed = asc_dvc->sdtr_speed3;
13536 } else if (tid == 12) {
13537 sdtr_speed = asc_dvc->sdtr_speed4;
13539 if (sdtr_speed & ASC_MAX_TID) {
13540 asc_dvc->sdtr_able |= (1 << tid);
13546 * Set the host maximum queuing (max. 253, min. 16) and the per device
13547 * maximum queuing (max. 63, min. 4).
13549 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
13550 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13551 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
13552 /* If the value is zero, assume it is uninitialized. */
13553 if (eep_config.max_host_qng == 0) {
13554 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
13556 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
13560 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
13561 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13562 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
13563 /* If the value is zero, assume it is uninitialized. */
13564 if (eep_config.max_dvc_qng == 0) {
13565 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
13567 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
13572 * If 'max_dvc_qng' is greater than 'max_host_qng', then
13573 * set 'max_dvc_qng' to 'max_host_qng'.
13575 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
13576 eep_config.max_dvc_qng = eep_config.max_host_qng;
13580 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
13581 * values based on possibly adjusted EEPROM values.
13583 asc_dvc->max_host_qng = eep_config.max_host_qng;
13584 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
13587 * If the EEPROM 'termination' field is set to automatic (0), then set
13588 * the ASC_DVC_CFG 'termination' field to automatic also.
13590 * If the termination is specified with a non-zero 'termination'
13591 * value check that a legal value is set and set the ASC_DVC_CFG
13592 * 'termination' field appropriately.
13594 if (eep_config.termination_se == 0) {
13595 termination = 0; /* auto termination for SE */
13597 /* Enable manual control with low off / high off. */
13598 if (eep_config.termination_se == 1) {
13601 /* Enable manual control with low off / high on. */
13602 } else if (eep_config.termination_se == 2) {
13603 termination = TERM_SE_HI;
13605 /* Enable manual control with low on / high on. */
13606 } else if (eep_config.termination_se == 3) {
13607 termination = TERM_SE;
13610 * The EEPROM 'termination_se' field contains a bad value.
13611 * Use automatic termination instead.
13614 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13618 if (eep_config.termination_lvd == 0) {
13619 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
13621 /* Enable manual control with low off / high off. */
13622 if (eep_config.termination_lvd == 1) {
13623 asc_dvc->cfg->termination = termination;
13625 /* Enable manual control with low off / high on. */
13626 } else if (eep_config.termination_lvd == 2) {
13627 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
13629 /* Enable manual control with low on / high on. */
13630 } else if (eep_config.termination_lvd == 3) {
13631 asc_dvc->cfg->termination = termination | TERM_LVD;
13634 * The EEPROM 'termination_lvd' field contains a bad value.
13635 * Use automatic termination instead.
13637 asc_dvc->cfg->termination = termination;
13638 warn_code |= ASC_WARN_EEPROM_TERMINATION;
13646 * Initialize the ADV_DVC_VAR structure.
13648 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
13650 * For a non-fatal error return a warning code. If there are no warnings
13651 * then 0 is returned.
13653 static int __devinit
13654 AdvInitGetConfig(struct pci_dev *pdev, asc_board_t *boardp)
13656 ADV_DVC_VAR *asc_dvc = &boardp->dvc_var.adv_dvc_var;
13657 unsigned short warn_code = 0;
13658 AdvPortAddr iop_base = asc_dvc->iop_base;
13662 asc_dvc->err_code = 0;
13665 * Save the state of the PCI Configuration Command Register
13666 * "Parity Error Response Control" Bit. If the bit is clear (0),
13667 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
13668 * DMA parity errors.
13670 asc_dvc->cfg->control_flag = 0;
13671 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
13672 if ((cmd & PCI_COMMAND_PARITY) == 0)
13673 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
13675 asc_dvc->cfg->lib_version = (ADV_LIB_VERSION_MAJOR << 8) |
13676 ADV_LIB_VERSION_MINOR;
13677 asc_dvc->cfg->chip_version =
13678 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
13680 ASC_DBG2(1, "AdvInitGetConfig: iopb_chip_id_1: 0x%x 0x%x\n",
13681 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
13682 (ushort)ADV_CHIP_ID_BYTE);
13684 ASC_DBG2(1, "AdvInitGetConfig: iopw_chip_id_0: 0x%x 0x%x\n",
13685 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
13686 (ushort)ADV_CHIP_ID_WORD);
13689 * Reset the chip to start and allow register writes.
13691 if (AdvFindSignature(iop_base) == 0) {
13692 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
13696 * The caller must set 'chip_type' to a valid setting.
13698 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
13699 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
13700 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
13701 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
13708 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
13709 ADV_CTRL_REG_CMD_RESET);
13711 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
13712 ADV_CTRL_REG_CMD_WR_IO_REG);
13714 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
13715 status = AdvInitFrom38C1600EEP(asc_dvc);
13716 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
13717 status = AdvInitFrom38C0800EEP(asc_dvc);
13719 status = AdvInitFrom3550EEP(asc_dvc);
13721 warn_code |= status;
13724 if (warn_code != 0) {
13725 ASC_PRINT2("AdvInitGetConfig: board %d: warning: 0x%x\n",
13726 boardp->id, warn_code);
13729 if (asc_dvc->err_code) {
13730 ASC_PRINT2("AdvInitGetConfig: board %d error: err_code 0x%x\n",
13731 boardp->id, asc_dvc->err_code);
13734 return asc_dvc->err_code;
13738 static struct scsi_host_template advansys_template = {
13739 .proc_name = DRV_NAME,
13740 #ifdef CONFIG_PROC_FS
13741 .proc_info = advansys_proc_info,
13744 .info = advansys_info,
13745 .queuecommand = advansys_queuecommand,
13746 .eh_bus_reset_handler = advansys_reset,
13747 .bios_param = advansys_biosparam,
13748 .slave_configure = advansys_slave_configure,
13750 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
13751 * must be set. The flag will be cleared in advansys_board_found
13752 * for non-ISA adapters.
13754 .unchecked_isa_dma = 1,
13756 * All adapters controlled by this driver are capable of large
13757 * scatter-gather lists. According to the mid-level SCSI documentation
13758 * this obviates any performance gain provided by setting
13759 * 'use_clustering'. But empirically while CPU utilization is increased
13760 * by enabling clustering, I/O throughput increases as well.
13762 .use_clustering = ENABLE_CLUSTERING,
13765 static int __devinit
13766 advansys_wide_init_chip(asc_board_t *boardp, ADV_DVC_VAR *adv_dvc_varp)
13769 adv_req_t *reqp = NULL;
13772 int warn_code, err_code;
13775 * Allocate buffer carrier structures. The total size
13776 * is about 4 KB, so allocate all at once.
13778 boardp->carrp = kmalloc(ADV_CARRIER_BUFSIZE, GFP_KERNEL);
13779 ASC_DBG1(1, "advansys_wide_init_chip: carrp 0x%p\n", boardp->carrp);
13781 if (!boardp->carrp)
13782 goto kmalloc_failed;
13785 * Allocate up to 'max_host_qng' request structures for the Wide
13786 * board. The total size is about 16 KB, so allocate all at once.
13787 * If the allocation fails decrement and try again.
13789 for (req_cnt = adv_dvc_varp->max_host_qng; req_cnt > 0; req_cnt--) {
13790 reqp = kmalloc(sizeof(adv_req_t) * req_cnt, GFP_KERNEL);
13792 ASC_DBG3(1, "advansys_wide_init_chip: reqp 0x%p, req_cnt %d, "
13793 "bytes %lu\n", reqp, req_cnt,
13794 (ulong)sizeof(adv_req_t) * req_cnt);
13801 goto kmalloc_failed;
13803 boardp->orig_reqp = reqp;
13806 * Allocate up to ADV_TOT_SG_BLOCK request structures for
13807 * the Wide board. Each structure is about 136 bytes.
13809 boardp->adv_sgblkp = NULL;
13810 for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
13811 sgp = kmalloc(sizeof(adv_sgblk_t), GFP_KERNEL);
13816 sgp->next_sgblkp = boardp->adv_sgblkp;
13817 boardp->adv_sgblkp = sgp;
13821 ASC_DBG3(1, "advansys_wide_init_chip: sg_cnt %d * %u = %u bytes\n",
13822 sg_cnt, sizeof(adv_sgblk_t),
13823 (unsigned)(sizeof(adv_sgblk_t) * sg_cnt));
13825 if (!boardp->adv_sgblkp)
13826 goto kmalloc_failed;
13828 adv_dvc_varp->carrier_buf = boardp->carrp;
13831 * Point 'adv_reqp' to the request structures and
13832 * link them together.
13835 reqp[req_cnt].next_reqp = NULL;
13836 for (; req_cnt > 0; req_cnt--) {
13837 reqp[req_cnt - 1].next_reqp = &reqp[req_cnt];
13839 boardp->adv_reqp = &reqp[0];
13841 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
13842 ASC_DBG(2, "advansys_wide_init_chip: AdvInitAsc3550Driver()\n");
13843 warn_code = AdvInitAsc3550Driver(adv_dvc_varp);
13844 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
13845 ASC_DBG(2, "advansys_wide_init_chip: AdvInitAsc38C0800Driver()"
13847 warn_code = AdvInitAsc38C0800Driver(adv_dvc_varp);
13849 ASC_DBG(2, "advansys_wide_init_chip: AdvInitAsc38C1600Driver()"
13851 warn_code = AdvInitAsc38C1600Driver(adv_dvc_varp);
13853 err_code = adv_dvc_varp->err_code;
13855 if (warn_code || err_code) {
13856 ASC_PRINT3("advansys_wide_init_chip: board %d error: warn 0x%x,"
13857 " error 0x%x\n", boardp->id, warn_code, err_code);
13863 ASC_PRINT1("advansys_wide_init_chip: board %d error: kmalloc() "
13864 "failed\n", boardp->id);
13865 err_code = ADV_ERROR;
13870 static void advansys_wide_free_mem(asc_board_t *boardp)
13872 kfree(boardp->carrp);
13873 boardp->carrp = NULL;
13874 kfree(boardp->orig_reqp);
13875 boardp->orig_reqp = boardp->adv_reqp = NULL;
13876 while (boardp->adv_sgblkp) {
13877 adv_sgblk_t *sgp = boardp->adv_sgblkp;
13878 boardp->adv_sgblkp = sgp->next_sgblkp;
13883 static struct Scsi_Host *__devinit
13884 advansys_board_found(int iop, struct device *dev, int bus_type)
13886 struct Scsi_Host *shost;
13887 struct pci_dev *pdev = bus_type == ASC_IS_PCI ? to_pci_dev(dev) : NULL;
13888 asc_board_t *boardp;
13889 ASC_DVC_VAR *asc_dvc_varp = NULL;
13890 ADV_DVC_VAR *adv_dvc_varp = NULL;
13892 int warn_code, err_code;
13896 * Register the adapter, get its configuration, and
13899 ASC_DBG(2, "advansys_board_found: scsi_host_alloc()\n");
13900 shost = scsi_host_alloc(&advansys_template, sizeof(asc_board_t));
13904 /* Initialize private per board data */
13905 boardp = ASC_BOARDP(shost);
13906 memset(boardp, 0, sizeof(asc_board_t));
13907 boardp->id = asc_board_count++;
13908 spin_lock_init(&boardp->lock);
13912 * Handle both narrow and wide boards.
13914 * If a Wide board was detected, set the board structure
13915 * wide board flag. Set-up the board structure based on
13919 if (bus_type == ASC_IS_PCI &&
13920 (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
13921 pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
13922 pdev->device == PCI_DEVICE_ID_38C1600_REV1)) {
13923 boardp->flags |= ASC_IS_WIDE_BOARD;
13925 #endif /* CONFIG_PCI */
13927 if (ASC_NARROW_BOARD(boardp)) {
13928 ASC_DBG(1, "advansys_board_found: narrow board\n");
13929 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
13930 asc_dvc_varp->bus_type = bus_type;
13931 asc_dvc_varp->drv_ptr = boardp;
13932 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
13933 asc_dvc_varp->cfg->overrun_buf = &overrun_buf[0];
13934 asc_dvc_varp->iop_base = iop;
13937 ASC_DBG(1, "advansys_board_found: wide board\n");
13938 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
13939 adv_dvc_varp->drv_ptr = boardp;
13940 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
13941 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
13942 ASC_DBG(1, "advansys_board_found: ASC-3550\n");
13943 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
13944 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
13945 ASC_DBG(1, "advansys_board_found: ASC-38C0800\n");
13946 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
13948 ASC_DBG(1, "advansys_board_found: ASC-38C1600\n");
13949 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
13952 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
13953 boardp->ioremap_addr = ioremap(pci_resource_start(pdev, 1),
13954 boardp->asc_n_io_port);
13955 if (!boardp->ioremap_addr) {
13957 ("advansys_board_found: board %d: ioremap(%x, %d) returned NULL\n",
13958 boardp->id, pci_resource_start(pdev, 1),
13959 boardp->asc_n_io_port);
13962 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr
13963 ASC_DBG1(1, "advansys_board_found: iop_base: 0x%lx\n",
13964 adv_dvc_varp->iop_base);
13967 * Even though it isn't used to access wide boards, other
13968 * than for the debug line below, save I/O Port address so
13969 * that it can be reported.
13971 boardp->ioport = iop;
13973 ASC_DBG2(1, "advansys_board_found: iopb_chip_id_1 0x%x, "
13974 "iopw_chip_id_0 0x%x\n", (ushort)inp(iop + 1),
13975 (ushort)inpw(iop));
13976 #endif /* CONFIG_PCI */
13979 #ifdef CONFIG_PROC_FS
13981 * Allocate buffer for printing information from
13982 * /proc/scsi/advansys/[0...].
13984 boardp->prtbuf = kmalloc(ASC_PRTBUF_SIZE, GFP_KERNEL);
13985 if (!boardp->prtbuf) {
13986 ASC_PRINT2("advansys_board_found: board %d: kmalloc(%d) "
13987 "returned NULL\n", boardp->id, ASC_PRTBUF_SIZE);
13990 #endif /* CONFIG_PROC_FS */
13992 if (ASC_NARROW_BOARD(boardp)) {
13994 * Set the board bus type and PCI IRQ before
13995 * calling AscInitGetConfig().
13997 switch (asc_dvc_varp->bus_type) {
14000 shost->unchecked_isa_dma = TRUE;
14004 shost->unchecked_isa_dma = FALSE;
14008 shost->unchecked_isa_dma = FALSE;
14009 share_irq = IRQF_SHARED;
14011 #endif /* CONFIG_ISA */
14014 shost->irq = asc_dvc_varp->irq_no = pdev->irq;
14015 shost->unchecked_isa_dma = FALSE;
14016 share_irq = IRQF_SHARED;
14018 #endif /* CONFIG_PCI */
14021 ("advansys_board_found: board %d: unknown adapter type: %d\n",
14022 boardp->id, asc_dvc_varp->bus_type);
14023 shost->unchecked_isa_dma = TRUE;
14029 * NOTE: AscInitGetConfig() may change the board's
14030 * bus_type value. The bus_type value should no
14031 * longer be used. If the bus_type field must be
14032 * referenced only use the bit-wise AND operator "&".
14034 ASC_DBG(2, "advansys_board_found: AscInitGetConfig()\n");
14035 err_code = AscInitGetConfig(boardp);
14039 * For Wide boards set PCI information before calling
14040 * AdvInitGetConfig().
14042 shost->irq = adv_dvc_varp->irq_no = pdev->irq;
14043 shost->unchecked_isa_dma = FALSE;
14044 share_irq = IRQF_SHARED;
14045 ASC_DBG(2, "advansys_board_found: AdvInitGetConfig()\n");
14047 err_code = AdvInitGetConfig(pdev, boardp);
14048 #endif /* CONFIG_PCI */
14052 goto err_free_proc;
14055 * Save the EEPROM configuration so that it can be displayed
14056 * from /proc/scsi/advansys/[0...].
14058 if (ASC_NARROW_BOARD(boardp)) {
14063 * Set the adapter's target id bit in the 'init_tidmask' field.
14065 boardp->init_tidmask |=
14066 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
14069 * Save EEPROM settings for the board.
14071 ep = &boardp->eep_config.asc_eep;
14073 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
14074 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
14075 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
14076 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
14077 ep->start_motor = asc_dvc_varp->start_motor;
14078 ep->cntl = asc_dvc_varp->dvc_cntl;
14079 ep->no_scam = asc_dvc_varp->no_scam;
14080 ep->max_total_qng = asc_dvc_varp->max_total_qng;
14081 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
14082 /* 'max_tag_qng' is set to the same value for every device. */
14083 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
14084 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
14085 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
14086 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
14087 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
14088 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
14089 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
14092 * Modify board configuration.
14094 ASC_DBG(2, "advansys_board_found: AscInitSetConfig()\n");
14095 err_code = AscInitSetConfig(pdev, boardp);
14097 goto err_free_proc;
14100 * Finish initializing the 'Scsi_Host' structure.
14102 /* AscInitSetConfig() will set the IRQ for non-PCI boards. */
14103 if ((asc_dvc_varp->bus_type & ASC_IS_PCI) == 0) {
14104 shost->irq = asc_dvc_varp->irq_no;
14107 ADVEEP_3550_CONFIG *ep_3550;
14108 ADVEEP_38C0800_CONFIG *ep_38C0800;
14109 ADVEEP_38C1600_CONFIG *ep_38C1600;
14112 * Save Wide EEP Configuration Information.
14114 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
14115 ep_3550 = &boardp->eep_config.adv_3550_eep;
14117 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
14118 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
14119 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
14120 ep_3550->termination = adv_dvc_varp->cfg->termination;
14121 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
14122 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
14123 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
14124 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
14125 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
14126 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
14127 ep_3550->start_motor = adv_dvc_varp->start_motor;
14128 ep_3550->scsi_reset_delay =
14129 adv_dvc_varp->scsi_reset_wait;
14130 ep_3550->serial_number_word1 =
14131 adv_dvc_varp->cfg->serial1;
14132 ep_3550->serial_number_word2 =
14133 adv_dvc_varp->cfg->serial2;
14134 ep_3550->serial_number_word3 =
14135 adv_dvc_varp->cfg->serial3;
14136 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
14137 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
14139 ep_38C0800->adapter_scsi_id =
14140 adv_dvc_varp->chip_scsi_id;
14141 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
14142 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
14143 ep_38C0800->termination_lvd =
14144 adv_dvc_varp->cfg->termination;
14145 ep_38C0800->disc_enable =
14146 adv_dvc_varp->cfg->disc_enable;
14147 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
14148 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
14149 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
14150 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
14151 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
14152 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
14153 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
14154 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
14155 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
14156 ep_38C0800->scsi_reset_delay =
14157 adv_dvc_varp->scsi_reset_wait;
14158 ep_38C0800->serial_number_word1 =
14159 adv_dvc_varp->cfg->serial1;
14160 ep_38C0800->serial_number_word2 =
14161 adv_dvc_varp->cfg->serial2;
14162 ep_38C0800->serial_number_word3 =
14163 adv_dvc_varp->cfg->serial3;
14165 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
14167 ep_38C1600->adapter_scsi_id =
14168 adv_dvc_varp->chip_scsi_id;
14169 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
14170 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
14171 ep_38C1600->termination_lvd =
14172 adv_dvc_varp->cfg->termination;
14173 ep_38C1600->disc_enable =
14174 adv_dvc_varp->cfg->disc_enable;
14175 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
14176 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
14177 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
14178 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
14179 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
14180 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
14181 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
14182 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
14183 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
14184 ep_38C1600->scsi_reset_delay =
14185 adv_dvc_varp->scsi_reset_wait;
14186 ep_38C1600->serial_number_word1 =
14187 adv_dvc_varp->cfg->serial1;
14188 ep_38C1600->serial_number_word2 =
14189 adv_dvc_varp->cfg->serial2;
14190 ep_38C1600->serial_number_word3 =
14191 adv_dvc_varp->cfg->serial3;
14195 * Set the adapter's target id bit in the 'init_tidmask' field.
14197 boardp->init_tidmask |=
14198 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
14202 * Channels are numbered beginning with 0. For AdvanSys one host
14203 * structure supports one channel. Multi-channel boards have a
14204 * separate host structure for each channel.
14206 shost->max_channel = 0;
14207 if (ASC_NARROW_BOARD(boardp)) {
14208 shost->max_id = ASC_MAX_TID + 1;
14209 shost->max_lun = ASC_MAX_LUN + 1;
14210 shost->max_cmd_len = ASC_MAX_CDB_LEN;
14212 shost->io_port = asc_dvc_varp->iop_base;
14213 boardp->asc_n_io_port = ASC_IOADR_GAP;
14214 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
14216 /* Set maximum number of queues the adapter can handle. */
14217 shost->can_queue = asc_dvc_varp->max_total_qng;
14219 shost->max_id = ADV_MAX_TID + 1;
14220 shost->max_lun = ADV_MAX_LUN + 1;
14221 shost->max_cmd_len = ADV_MAX_CDB_LEN;
14224 * Save the I/O Port address and length even though
14225 * I/O ports are not used to access Wide boards.
14226 * Instead the Wide boards are accessed with
14227 * PCI Memory Mapped I/O.
14229 shost->io_port = iop;
14231 shost->this_id = adv_dvc_varp->chip_scsi_id;
14233 /* Set maximum number of queues the adapter can handle. */
14234 shost->can_queue = adv_dvc_varp->max_host_qng;
14238 * Following v1.3.89, 'cmd_per_lun' is no longer needed
14239 * and should be set to zero.
14241 * But because of a bug introduced in v1.3.89 if the driver is
14242 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
14243 * SCSI function 'allocate_device' will panic. To allow the driver
14244 * to work as a module in these kernels set 'cmd_per_lun' to 1.
14246 * Note: This is wrong. cmd_per_lun should be set to the depth
14247 * you want on untagged devices always.
14250 shost->cmd_per_lun = 1;
14252 shost->cmd_per_lun = 0;
14256 * Set the maximum number of scatter-gather elements the
14257 * adapter can handle.
14259 if (ASC_NARROW_BOARD(boardp)) {
14261 * Allow two commands with 'sg_tablesize' scatter-gather
14262 * elements to be executed simultaneously. This value is
14263 * the theoretical hardware limit. It may be decreased
14266 shost->sg_tablesize =
14267 (((asc_dvc_varp->max_total_qng - 2) / 2) *
14268 ASC_SG_LIST_PER_Q) + 1;
14270 shost->sg_tablesize = ADV_MAX_SG_LIST;
14274 * The value of 'sg_tablesize' can not exceed the SCSI
14275 * mid-level driver definition of SG_ALL. SG_ALL also
14276 * must not be exceeded, because it is used to define the
14277 * size of the scatter-gather table in 'struct asc_sg_head'.
14279 if (shost->sg_tablesize > SG_ALL) {
14280 shost->sg_tablesize = SG_ALL;
14283 ASC_DBG1(1, "advansys_board_found: sg_tablesize: %d\n", shost->sg_tablesize);
14285 /* BIOS start address. */
14286 if (ASC_NARROW_BOARD(boardp)) {
14287 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
14288 asc_dvc_varp->bus_type);
14291 * Fill-in BIOS board variables. The Wide BIOS saves
14292 * information in LRAM that is used by the driver.
14294 AdvReadWordLram(adv_dvc_varp->iop_base,
14295 BIOS_SIGNATURE, boardp->bios_signature);
14296 AdvReadWordLram(adv_dvc_varp->iop_base,
14297 BIOS_VERSION, boardp->bios_version);
14298 AdvReadWordLram(adv_dvc_varp->iop_base,
14299 BIOS_CODESEG, boardp->bios_codeseg);
14300 AdvReadWordLram(adv_dvc_varp->iop_base,
14301 BIOS_CODELEN, boardp->bios_codelen);
14304 "advansys_board_found: bios_signature 0x%x, bios_version 0x%x\n",
14305 boardp->bios_signature, boardp->bios_version);
14308 "advansys_board_found: bios_codeseg 0x%x, bios_codelen 0x%x\n",
14309 boardp->bios_codeseg, boardp->bios_codelen);
14312 * If the BIOS saved a valid signature, then fill in
14313 * the BIOS code segment base address.
14315 if (boardp->bios_signature == 0x55AA) {
14317 * Convert x86 realmode code segment to a linear
14318 * address by shifting left 4.
14320 shost->base = ((ulong)boardp->bios_codeseg << 4);
14327 * Register Board Resources - I/O Port, DMA, IRQ
14330 /* Register DMA Channel for Narrow boards. */
14331 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
14333 if (ASC_NARROW_BOARD(boardp)) {
14334 /* Register DMA channel for ISA bus. */
14335 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
14336 shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
14337 ret = request_dma(shost->dma_channel, DRV_NAME);
14340 ("advansys_board_found: board %d: request_dma() %d failed %d\n",
14341 boardp->id, shost->dma_channel, ret);
14342 goto err_free_proc;
14344 AscEnableIsaDma(shost->dma_channel);
14347 #endif /* CONFIG_ISA */
14349 /* Register IRQ Number. */
14350 ASC_DBG1(2, "advansys_board_found: request_irq() %d\n", shost->irq);
14352 ret = request_irq(shost->irq, advansys_interrupt, share_irq,
14356 if (ret == -EBUSY) {
14358 ("advansys_board_found: board %d: request_irq(): IRQ 0x%x already in use.\n",
14359 boardp->id, shost->irq);
14360 } else if (ret == -EINVAL) {
14362 ("advansys_board_found: board %d: request_irq(): IRQ 0x%x not valid.\n",
14363 boardp->id, shost->irq);
14366 ("advansys_board_found: board %d: request_irq(): IRQ 0x%x failed with %d\n",
14367 boardp->id, shost->irq, ret);
14373 * Initialize board RISC chip and enable interrupts.
14375 if (ASC_NARROW_BOARD(boardp)) {
14376 ASC_DBG(2, "advansys_board_found: AscInitAsc1000Driver()\n");
14377 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
14378 err_code = asc_dvc_varp->err_code;
14380 if (warn_code || err_code) {
14382 ("advansys_board_found: board %d error: init_state 0x%x, warn 0x%x, error 0x%x\n",
14384 asc_dvc_varp->init_state, warn_code, err_code);
14387 err_code = advansys_wide_init_chip(boardp, adv_dvc_varp);
14391 goto err_free_wide_mem;
14393 ASC_DBG_PRT_SCSI_HOST(2, shost);
14395 ret = scsi_add_host(shost, dev);
14397 goto err_free_wide_mem;
14399 scsi_scan_host(shost);
14403 advansys_wide_free_mem(boardp);
14404 free_irq(shost->irq, shost);
14406 if (shost->dma_channel != NO_ISA_DMA)
14407 free_dma(shost->dma_channel);
14409 kfree(boardp->prtbuf);
14411 if (boardp->ioremap_addr)
14412 iounmap(boardp->ioremap_addr);
14414 scsi_host_put(shost);
14419 * advansys_release()
14421 * Release resources allocated for a single AdvanSys adapter.
14423 static int advansys_release(struct Scsi_Host *shost)
14425 asc_board_t *boardp;
14427 ASC_DBG(1, "advansys_release: begin\n");
14428 scsi_remove_host(shost);
14429 boardp = ASC_BOARDP(shost);
14430 free_irq(shost->irq, shost);
14431 if (shost->dma_channel != NO_ISA_DMA) {
14432 ASC_DBG(1, "advansys_release: free_dma()\n");
14433 free_dma(shost->dma_channel);
14435 if (ASC_WIDE_BOARD(boardp)) {
14436 iounmap(boardp->ioremap_addr);
14437 advansys_wide_free_mem(boardp);
14439 kfree(boardp->prtbuf);
14440 scsi_host_put(shost);
14441 ASC_DBG(1, "advansys_release: end\n");
14445 #define ASC_IOADR_TABLE_MAX_IX 11
14447 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] __devinitdata = {
14448 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
14449 0x0210, 0x0230, 0x0250, 0x0330
14452 static int __devinit advansys_isa_probe(struct device *dev, unsigned int id)
14454 PortAddr iop_base = _asc_def_iop_base[id];
14455 struct Scsi_Host *shost;
14457 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
14458 ASC_DBG1(1, "advansys_isa_match: I/O port 0x%x busy\n",
14462 ASC_DBG1(1, "advansys_isa_match: probing I/O port 0x%x\n", iop_base);
14463 if (!AscFindSignature(iop_base))
14465 if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
14468 shost = advansys_board_found(iop_base, dev, ASC_IS_ISA);
14472 dev_set_drvdata(dev, shost);
14476 release_region(iop_base, ASC_IOADR_GAP);
14480 static int __devexit advansys_isa_remove(struct device *dev, unsigned int id)
14482 int ioport = _asc_def_iop_base[id];
14483 advansys_release(dev_get_drvdata(dev));
14484 release_region(ioport, ASC_IOADR_GAP);
14488 static struct isa_driver advansys_isa_driver = {
14489 .probe = advansys_isa_probe,
14490 .remove = __devexit_p(advansys_isa_remove),
14492 .owner = THIS_MODULE,
14497 static int __devinit advansys_vlb_probe(struct device *dev, unsigned int id)
14499 PortAddr iop_base = _asc_def_iop_base[id];
14500 struct Scsi_Host *shost;
14502 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
14503 ASC_DBG1(1, "advansys_vlb_match: I/O port 0x%x busy\n",
14507 ASC_DBG1(1, "advansys_vlb_match: probing I/O port 0x%x\n", iop_base);
14508 if (!AscFindSignature(iop_base))
14511 * I don't think this condition can actually happen, but the old
14512 * driver did it, and the chances of finding a VLB setup in 2007
14513 * to do testing with is slight to none.
14515 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
14518 shost = advansys_board_found(iop_base, dev, ASC_IS_VL);
14522 dev_set_drvdata(dev, shost);
14526 release_region(iop_base, ASC_IOADR_GAP);
14530 static struct isa_driver advansys_vlb_driver = {
14531 .probe = advansys_vlb_probe,
14532 .remove = __devexit_p(advansys_isa_remove),
14534 .owner = THIS_MODULE,
14535 .name = "advansys_vlb",
14539 static struct eisa_device_id advansys_eisa_table[] __devinitdata = {
14545 MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
14548 * EISA is a little more tricky than PCI; each EISA device may have two
14549 * channels, and this driver is written to make each channel its own Scsi_Host
14551 struct eisa_scsi_data {
14552 struct Scsi_Host *host[2];
14555 static int __devinit advansys_eisa_probe(struct device *dev)
14559 struct eisa_device *edev = to_eisa_device(dev);
14560 struct eisa_scsi_data *data;
14563 data = kzalloc(sizeof(*data), GFP_KERNEL);
14566 ioport = edev->base_addr + 0xc30;
14569 for (i = 0; i < 2; i++, ioport += 0x20) {
14570 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
14571 printk(KERN_WARNING "Region %x-%x busy\n", ioport,
14572 ioport + ASC_IOADR_GAP - 1);
14575 if (!AscFindSignature(ioport)) {
14576 release_region(ioport, ASC_IOADR_GAP);
14581 * I don't know why we need to do this for EISA chips, but
14582 * not for any others. It looks to be equivalent to
14583 * AscGetChipCfgMsw, but I may have overlooked something,
14584 * so I'm not converting it until I get an EISA board to
14588 data->host[i] = advansys_board_found(ioport, dev, ASC_IS_EISA);
14589 if (data->host[i]) {
14592 release_region(ioport, ASC_IOADR_GAP);
14599 dev_set_drvdata(dev, data);
14606 static __devexit int advansys_eisa_remove(struct device *dev)
14609 struct eisa_scsi_data *data = dev_get_drvdata(dev);
14611 for (i = 0; i < 2; i++) {
14613 struct Scsi_Host *shost = data->host[i];
14616 ioport = shost->io_port;
14617 advansys_release(shost);
14618 release_region(ioport, ASC_IOADR_GAP);
14625 static struct eisa_driver advansys_eisa_driver = {
14626 .id_table = advansys_eisa_table,
14629 .probe = advansys_eisa_probe,
14630 .remove = __devexit_p(advansys_eisa_remove),
14634 /* PCI Devices supported by this driver */
14635 static struct pci_device_id advansys_pci_tbl[] __devinitdata = {
14636 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
14637 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14638 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
14639 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14640 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
14641 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14642 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
14643 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14644 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
14645 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14646 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
14647 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
14651 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
14653 static void __devinit advansys_set_latency(struct pci_dev *pdev)
14655 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
14656 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
14657 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
14660 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
14661 if (latency < 0x20)
14662 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
14666 static int __devinit
14667 advansys_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
14670 struct Scsi_Host *shost;
14672 err = pci_enable_device(pdev);
14675 err = pci_request_regions(pdev, DRV_NAME);
14677 goto disable_device;
14678 pci_set_master(pdev);
14679 advansys_set_latency(pdev);
14681 if (pci_resource_len(pdev, 0) == 0)
14684 ioport = pci_resource_start(pdev, 0);
14685 shost = advansys_board_found(ioport, &pdev->dev, ASC_IS_PCI);
14690 pci_set_drvdata(pdev, shost);
14695 pci_release_regions(pdev);
14697 pci_disable_device(pdev);
14702 static void __devexit advansys_pci_remove(struct pci_dev *pdev)
14704 advansys_release(pci_get_drvdata(pdev));
14705 pci_release_regions(pdev);
14706 pci_disable_device(pdev);
14709 static struct pci_driver advansys_pci_driver = {
14711 .id_table = advansys_pci_tbl,
14712 .probe = advansys_pci_probe,
14713 .remove = __devexit_p(advansys_pci_remove),
14716 static int __init advansys_init(void)
14720 error = isa_register_driver(&advansys_isa_driver,
14721 ASC_IOADR_TABLE_MAX_IX);
14725 error = isa_register_driver(&advansys_vlb_driver,
14726 ASC_IOADR_TABLE_MAX_IX);
14728 goto unregister_isa;
14730 error = eisa_driver_register(&advansys_eisa_driver);
14732 goto unregister_vlb;
14734 error = pci_register_driver(&advansys_pci_driver);
14736 goto unregister_eisa;
14741 eisa_driver_unregister(&advansys_eisa_driver);
14743 isa_unregister_driver(&advansys_vlb_driver);
14745 isa_unregister_driver(&advansys_isa_driver);
14750 static void __exit advansys_exit(void)
14752 pci_unregister_driver(&advansys_pci_driver);
14753 eisa_driver_unregister(&advansys_eisa_driver);
14754 isa_unregister_driver(&advansys_vlb_driver);
14755 isa_unregister_driver(&advansys_isa_driver);
14758 module_init(advansys_init);
14759 module_exit(advansys_exit);
14761 MODULE_LICENSE("GPL");