2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2014-2015 PMC-Sierra, Inc.
4 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
15 * Questions/Comments/Bugfixes to storagedev@pmcs.com
21 #include <scsi/scsicam.h>
28 struct access_method {
29 void (*submit_command)(struct ctlr_info *h,
30 struct CommandList *c);
31 void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
32 bool (*intr_pending)(struct ctlr_info *h);
33 unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
36 struct hpsa_scsi_dev_t {
38 int bus, target, lun; /* as presented to the OS */
39 unsigned char scsi3addr[8]; /* as presented to the HW */
41 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
42 unsigned char device_id[16]; /* from inquiry pg. 0x83 */
43 unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
44 unsigned char model[16]; /* bytes 16-31 of inquiry data */
45 unsigned char raid_level; /* from inquiry page 0xC1 */
46 unsigned char volume_offline; /* discovered via TUR or VPD */
47 u16 queue_depth; /* max queue_depth for this device */
48 atomic_t reset_cmds_out; /* Count of commands to-be affected */
49 atomic_t ioaccel_cmds_out; /* Only used for physical devices
50 * counts commands sent to physical
51 * device via "ioaccel" path.
58 u16 phys_connector[8];
59 int offload_config; /* I/O accel RAID offload configured */
60 int offload_enabled; /* I/O accel RAID offload enabled */
61 int offload_to_be_enabled;
62 int hba_ioaccel_enabled;
63 int offload_to_mirror; /* Send next I/O accelerator RAID
64 * offload request to mirror drive
66 struct raid_map_data raid_map; /* I/O accelerator RAID map */
69 * Pointers from logical drive map indices to the phys drives that
70 * make those logical drives. Note, multiple logical drives may
71 * share physical drives. You can have for instance 5 physical
72 * drives with 3 logical drives each using those same 5 physical
73 * disks. We need these pointers for counting i/o's out to physical
74 * devices in order to honor physical device queue depth limits.
76 struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES];
81 struct reply_queue_buffer {
90 struct bmic_controller_parameters {
92 u8 enable_command_list_verification;
93 u8 backed_out_write_drives;
94 u16 stripes_for_parity;
95 u8 parity_distribution_mode_flags;
96 u16 max_driver_requests;
97 u16 elevator_trend_count;
99 u8 force_scan_complete;
100 u8 scsi_transfer_mode;
104 u8 host_sdb_asic_fix;
105 u8 pdpi_burst_from_host_disabled;
106 char software_name[64];
107 char hardware_name[32];
109 u8 snapshot_priority;
111 u8 post_prompt_timeout;
112 u8 automatic_drive_slamming;
115 u8 cache_nvram_flags;
116 u8 drive_config_flags;
118 u8 temp_warning_level;
119 u8 temp_shutdown_level;
120 u8 temp_condition_reset;
121 u8 max_coalesce_commands;
122 u32 max_coalesce_delay;
133 struct pci_dev *pdev;
137 int nr_cmds; /* Number of commands allowed on this controller */
138 #define HPSA_CMDS_RESERVED_FOR_ABORTS 2
139 #define HPSA_CMDS_RESERVED_FOR_DRIVER 1
140 struct CfgTable __iomem *cfgtable;
141 int interrupts_enabled;
143 atomic_t commands_outstanding;
144 # define PERF_MODE_INT 0
145 # define DOORBELL_INT 1
146 # define SIMPLE_MODE_INT 2
147 # define MEMQ_MODE_INT 3
148 unsigned int intr[MAX_REPLY_QUEUES];
149 unsigned int msix_vector;
150 unsigned int msi_vector;
151 int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
152 struct access_method access;
154 /* queue and queue Info */
159 u8 max_cmd_sg_entries;
161 struct SGDescriptor **cmd_sg_list;
162 struct ioaccel2_sg_element **ioaccel2_cmd_sg_list;
164 /* pointers to command and error info pool */
165 struct CommandList *cmd_pool;
166 dma_addr_t cmd_pool_dhandle;
167 struct io_accel1_cmd *ioaccel_cmd_pool;
168 dma_addr_t ioaccel_cmd_pool_dhandle;
169 struct io_accel2_cmd *ioaccel2_cmd_pool;
170 dma_addr_t ioaccel2_cmd_pool_dhandle;
171 struct ErrorInfo *errinfo_pool;
172 dma_addr_t errinfo_pool_dhandle;
173 unsigned long *cmd_pool_bits;
175 spinlock_t scan_lock;
176 wait_queue_head_t scan_wait_queue;
178 struct Scsi_Host *scsi_host;
179 spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
180 int ndevices; /* number of used elements in .dev[] array. */
181 struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
183 * Performant mode tables.
187 struct TransTable_struct __iomem *transtable;
188 unsigned long transMethod;
190 /* cap concurrent passthrus at some reasonable maximum */
191 #define HPSA_MAX_CONCURRENT_PASSTHRUS (10)
192 atomic_t passthru_cmds_avail;
195 * Performant mode completion buffers
197 size_t reply_queue_size;
198 struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES];
200 u32 *blockFetchTable;
201 u32 *ioaccel1_blockFetchTable;
202 u32 *ioaccel2_blockFetchTable;
203 u32 __iomem *ioaccel2_bft2_regs;
204 unsigned char *hba_inquiry_data;
209 u64 last_intr_timestamp;
211 u64 last_heartbeat_timestamp;
212 u32 heartbeat_sample_interval;
213 atomic_t firmware_flash_in_progress;
214 u32 __percpu *lockup_detected;
215 struct delayed_work monitor_ctlr_work;
216 struct delayed_work rescan_ctlr_work;
217 int remove_in_progress;
218 /* Address of h->q[x] is passed to intr handler to know which queue */
219 u8 q[MAX_REPLY_QUEUES];
220 char intrname[MAX_REPLY_QUEUES][16]; /* "hpsa0-msix00" names */
221 u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
222 #define HPSATMF_BITS_SUPPORTED (1 << 0)
223 #define HPSATMF_PHYS_LUN_RESET (1 << 1)
224 #define HPSATMF_PHYS_NEX_RESET (1 << 2)
225 #define HPSATMF_PHYS_TASK_ABORT (1 << 3)
226 #define HPSATMF_PHYS_TSET_ABORT (1 << 4)
227 #define HPSATMF_PHYS_CLEAR_ACA (1 << 5)
228 #define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
229 #define HPSATMF_PHYS_QRY_TASK (1 << 7)
230 #define HPSATMF_PHYS_QRY_TSET (1 << 8)
231 #define HPSATMF_PHYS_QRY_ASYNC (1 << 9)
232 #define HPSATMF_IOACCEL_ENABLED (1 << 15)
233 #define HPSATMF_MASK_SUPPORTED (1 << 16)
234 #define HPSATMF_LOG_LUN_RESET (1 << 17)
235 #define HPSATMF_LOG_NEX_RESET (1 << 18)
236 #define HPSATMF_LOG_TASK_ABORT (1 << 19)
237 #define HPSATMF_LOG_TSET_ABORT (1 << 20)
238 #define HPSATMF_LOG_CLEAR_ACA (1 << 21)
239 #define HPSATMF_LOG_CLEAR_TSET (1 << 22)
240 #define HPSATMF_LOG_QRY_TASK (1 << 23)
241 #define HPSATMF_LOG_QRY_TSET (1 << 24)
242 #define HPSATMF_LOG_QRY_ASYNC (1 << 25)
244 #define CTLR_STATE_CHANGE_EVENT (1 << 0)
245 #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1)
246 #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4)
247 #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5)
248 #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6)
249 #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30)
250 #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31)
252 #define RESCAN_REQUIRED_EVENT_BITS \
253 (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \
254 CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \
255 CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \
256 CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \
257 CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE)
258 spinlock_t offline_device_lock;
259 struct list_head offline_device_list;
260 int acciopath_status;
262 int raid_offload_debug;
263 int needs_abort_tags_swizzled;
264 struct workqueue_struct *resubmit_wq;
265 struct workqueue_struct *rescan_ctlr_wq;
266 atomic_t abort_cmds_available;
267 wait_queue_head_t abort_cmd_wait_queue;
268 wait_queue_head_t event_sync_wait_queue;
269 struct mutex reset_mutex;
270 u8 reset_in_progress;
273 struct offline_device_entry {
274 unsigned char scsi3addr[8];
275 struct list_head offline_list;
278 #define HPSA_ABORT_MSG 0
279 #define HPSA_DEVICE_RESET_MSG 1
280 #define HPSA_RESET_TYPE_CONTROLLER 0x00
281 #define HPSA_RESET_TYPE_BUS 0x01
282 #define HPSA_RESET_TYPE_TARGET 0x03
283 #define HPSA_RESET_TYPE_LUN 0x04
284 #define HPSA_PHYS_TARGET_RESET 0x99 /* not defined by cciss spec */
285 #define HPSA_MSG_SEND_RETRY_LIMIT 10
286 #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
288 /* Maximum time in seconds driver will wait for command completions
289 * when polling before giving up.
291 #define HPSA_MAX_POLL_TIME_SECS (20)
293 /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
294 * how many times to retry TEST UNIT READY on a device
295 * while waiting for it to become ready before giving up.
296 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
297 * between sending TURs while waiting for a device
300 #define HPSA_TUR_RETRY_LIMIT (20)
301 #define HPSA_MAX_WAIT_INTERVAL_SECS (30)
303 /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
304 * to become ready, in seconds, before giving up on it.
305 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
306 * between polling the board to see if it is ready, in
307 * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
308 * HPSA_BOARD_READY_ITERATIONS are derived from those.
310 #define HPSA_BOARD_READY_WAIT_SECS (120)
311 #define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
312 #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
313 #define HPSA_BOARD_READY_POLL_INTERVAL \
314 ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
315 #define HPSA_BOARD_READY_ITERATIONS \
316 ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
317 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
318 #define HPSA_BOARD_NOT_READY_ITERATIONS \
319 ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
320 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
321 #define HPSA_POST_RESET_PAUSE_MSECS (3000)
322 #define HPSA_POST_RESET_NOOP_RETRIES (12)
324 /* Defining the diffent access_menthods */
326 * Memory mapped FIFO interface (SMART 53xx cards)
328 #define SA5_DOORBELL 0x20
329 #define SA5_REQUEST_PORT_OFFSET 0x40
330 #define SA5_REQUEST_PORT64_LO_OFFSET 0xC0
331 #define SA5_REQUEST_PORT64_HI_OFFSET 0xC4
332 #define SA5_REPLY_INTR_MASK_OFFSET 0x34
333 #define SA5_REPLY_PORT_OFFSET 0x44
334 #define SA5_INTR_STATUS 0x30
335 #define SA5_SCRATCHPAD_OFFSET 0xB0
337 #define SA5_CTCFG_OFFSET 0xB4
338 #define SA5_CTMEM_OFFSET 0xB8
340 #define SA5_INTR_OFF 0x08
341 #define SA5B_INTR_OFF 0x04
342 #define SA5_INTR_PENDING 0x08
343 #define SA5B_INTR_PENDING 0x04
344 #define FIFO_EMPTY 0xffffffff
345 #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
347 #define HPSA_ERROR_BIT 0x02
349 /* Performant mode flags */
350 #define SA5_PERF_INTR_PENDING 0x04
351 #define SA5_PERF_INTR_OFF 0x05
352 #define SA5_OUTDB_STATUS_PERF_BIT 0x01
353 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
354 #define SA5_OUTDB_CLEAR 0xA0
355 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
356 #define SA5_OUTDB_STATUS 0x9C
359 #define HPSA_INTR_ON 1
360 #define HPSA_INTR_OFF 0
363 * Inbound Post Queue offsets for IO Accelerator Mode 2
365 #define IOACCEL2_INBOUND_POSTQ_32 0x48
366 #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0
367 #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4
370 Send the command to the hardware
372 static void SA5_submit_command(struct ctlr_info *h,
373 struct CommandList *c)
375 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
376 (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
379 static void SA5_submit_command_no_read(struct ctlr_info *h,
380 struct CommandList *c)
382 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
385 static void SA5_submit_command_ioaccel2(struct ctlr_info *h,
386 struct CommandList *c)
388 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
392 * This card is the opposite of the other cards.
393 * 0 turns interrupts on...
394 * 0x08 turns them off...
396 static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
398 if (val) { /* Turn interrupts on */
399 h->interrupts_enabled = 1;
400 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
401 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
402 } else { /* Turn them off */
403 h->interrupts_enabled = 0;
405 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
406 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
410 static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
412 if (val) { /* turn on interrupts */
413 h->interrupts_enabled = 1;
414 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
415 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
417 h->interrupts_enabled = 0;
418 writel(SA5_PERF_INTR_OFF,
419 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
420 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
424 static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
426 struct reply_queue_buffer *rq = &h->reply_queue[q];
427 unsigned long register_value = FIFO_EMPTY;
429 /* msi auto clears the interrupt pending bit. */
430 if (unlikely(!(h->msi_vector || h->msix_vector))) {
431 /* flush the controller write of the reply queue by reading
432 * outbound doorbell status register.
434 (void) readl(h->vaddr + SA5_OUTDB_STATUS);
435 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
436 /* Do a read in order to flush the write to the controller
439 (void) readl(h->vaddr + SA5_OUTDB_STATUS);
442 if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) {
443 register_value = rq->head[rq->current_entry];
445 atomic_dec(&h->commands_outstanding);
447 register_value = FIFO_EMPTY;
449 /* Check for wraparound */
450 if (rq->current_entry == h->max_commands) {
451 rq->current_entry = 0;
454 return register_value;
458 * returns value read from hardware.
459 * returns FIFO_EMPTY if there is nothing to read
461 static unsigned long SA5_completed(struct ctlr_info *h,
462 __attribute__((unused)) u8 q)
464 unsigned long register_value
465 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
467 if (register_value != FIFO_EMPTY)
468 atomic_dec(&h->commands_outstanding);
471 if (register_value != FIFO_EMPTY)
472 dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
475 dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
478 return register_value;
481 * Returns true if an interrupt is pending..
483 static bool SA5_intr_pending(struct ctlr_info *h)
485 unsigned long register_value =
486 readl(h->vaddr + SA5_INTR_STATUS);
487 return register_value & SA5_INTR_PENDING;
490 static bool SA5_performant_intr_pending(struct ctlr_info *h)
492 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
497 /* Read outbound doorbell to flush */
498 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
499 return register_value & SA5_OUTDB_STATUS_PERF_BIT;
502 #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100
504 static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h)
506 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
508 return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ?
512 #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0
513 #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8
514 #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC
515 #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL
517 static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)
520 struct reply_queue_buffer *rq = &h->reply_queue[q];
522 BUG_ON(q >= h->nreply_queues);
524 register_value = rq->head[rq->current_entry];
525 if (register_value != IOACCEL_MODE1_REPLY_UNUSED) {
526 rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED;
527 if (++rq->current_entry == rq->size)
528 rq->current_entry = 0;
532 * Don't really need to write the new index after each command,
533 * but with current driver design this is easiest.
536 writel((q << 24) | rq->current_entry, h->vaddr +
537 IOACCEL_MODE1_CONSUMER_INDEX);
538 atomic_dec(&h->commands_outstanding);
540 return (unsigned long) register_value;
543 static struct access_method SA5_access = {
550 static struct access_method SA5_ioaccel_mode1_access = {
552 SA5_performant_intr_mask,
553 SA5_ioaccel_mode1_intr_pending,
554 SA5_ioaccel_mode1_completed,
557 static struct access_method SA5_ioaccel_mode2_access = {
558 SA5_submit_command_ioaccel2,
559 SA5_performant_intr_mask,
560 SA5_performant_intr_pending,
561 SA5_performant_completed,
564 static struct access_method SA5_performant_access = {
566 SA5_performant_intr_mask,
567 SA5_performant_intr_pending,
568 SA5_performant_completed,
571 static struct access_method SA5_performant_access_no_read = {
572 SA5_submit_command_no_read,
573 SA5_performant_intr_mask,
574 SA5_performant_intr_pending,
575 SA5_performant_completed,
581 struct access_method *access;