drivers/scsi/isci/host.c

   1 /*
   2  * This file is provided under a dual BSD/GPLv2 license.  When using or
   3  * redistributing this file, you may do so under either license.
   4  *
   5  * GPL LICENSE SUMMARY
   6  *
   7  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * BSD LICENSE
  25  *
  26  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  27  * All rights reserved.
  28  *
  29  * Redistribution and use in source and binary forms, with or without
  30  * modification, are permitted provided that the following conditions
  31  * are met:
  32  *
  33  *   * Redistributions of source code must retain the above copyright
  34  *     notice, this list of conditions and the following disclaimer.
  35  *   * Redistributions in binary form must reproduce the above copyright
  36  *     notice, this list of conditions and the following disclaimer in
  37  *     the documentation and/or other materials provided with the
  38  *     distribution.
  39  *   * Neither the name of Intel Corporation nor the names of its
  40  *     contributors may be used to endorse or promote products derived
  41  *     from this software without specific prior written permission.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  */
  55 #include <linux/device.h>
  56 #include <scsi/sas.h>
  57 #include "host.h"
  58 #include "isci.h"
  59 #include "port.h"
  60 #include "host.h"
  61 #include "probe_roms.h"
  62 #include "remote_device.h"
  63 #include "request.h"
  64 #include "scu_completion_codes.h"
  65 #include "scu_event_codes.h"
  66 #include "registers.h"
  67 #include "scu_remote_node_context.h"
  68 #include "scu_task_context.h"
  69 #include "scu_unsolicited_frame.h"
  70 #include "timers.h"
  71
  72 #define SCU_CONTEXT_RAM_INIT_STALL_TIME      200
  73
  74 /**
  75  * smu_dcc_get_max_ports() -
  76  *
  77  * This macro returns the maximum number of logical ports supported by the
  78  * hardware. The caller passes in the value read from the device context
  79  * capacity register and this macro will mash and shift the value appropriately.
  80  */
  81 #define smu_dcc_get_max_ports(dcc_value) \
  82         (\
  83                 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \
  84                  >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT) + 1 \
  85         )
  86
  87 /**
  88  * smu_dcc_get_max_task_context() -
  89  *
  90  * This macro returns the maximum number of task contexts supported by the
  91  * hardware. The caller passes in the value read from the device context
  92  * capacity register and this macro will mash and shift the value appropriately.
  93  */
  94 #define smu_dcc_get_max_task_context(dcc_value) \
  95         (\
  96                 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \
  97                  >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT) + 1 \
  98         )
  99
 100 /**
 101  * smu_dcc_get_max_remote_node_context() -
 102  *
 103  * This macro returns the maximum number of remote node contexts supported by
 104  * the hardware. The caller passes in the value read from the device context
 105  * capacity register and this macro will mash and shift the value appropriately.
 106  */
 107 #define smu_dcc_get_max_remote_node_context(dcc_value) \
 108         (\
 109                 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \
 110                  >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT) + 1 \
 111         )
 112
 113
 114 #define SCIC_SDS_CONTROLLER_MIN_TIMER_COUNT  3
 115 #define SCIC_SDS_CONTROLLER_MAX_TIMER_COUNT  3
 116
 117 /**
 118  *
 119  *
 120  * The number of milliseconds to wait for a phy to start.
 121  */
 122 #define SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT      100
 123
 124 /**
 125  *
 126  *
 127  * The number of milliseconds to wait while a given phy is consuming power
 128  * before allowing another set of phys to consume power. Ultimately, this will
 129  * be specified by OEM parameter.
 130  */
 131 #define SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL 500
 132
 133 /**
 134  * NORMALIZE_PUT_POINTER() -
 135  *
 136  * This macro will normalize the completion queue put pointer so its value can
 137  * be used as an array inde
 138  */
 139 #define NORMALIZE_PUT_POINTER(x) \
 140         ((x) & SMU_COMPLETION_QUEUE_PUT_POINTER_MASK)
 141
 142
 143 /**
 144  * NORMALIZE_EVENT_POINTER() -
 145  *
 146  * This macro will normalize the completion queue event entry so its value can
 147  * be used as an index.
 148  */
 149 #define NORMALIZE_EVENT_POINTER(x) \
 150         (\
 151                 ((x) & SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK) \
 152                 >> SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT \
 153         )
 154
 155 /**
 156  * INCREMENT_COMPLETION_QUEUE_GET() -
 157  *
 158  * This macro will increment the controllers completion queue index value and
 159  * possibly toggle the cycle bit if the completion queue index wraps back to 0.
 160  */
 161 #define INCREMENT_COMPLETION_QUEUE_GET(controller, index, cycle) \
 162         INCREMENT_QUEUE_GET(\
 163                 (index), \
 164                 (cycle), \
 165                 (controller)->completion_queue_entries, \
 166                 SMU_CQGR_CYCLE_BIT \
 167                 )
 168
 169 /**
 170  * INCREMENT_EVENT_QUEUE_GET() -
 171  *
 172  * This macro will increment the controllers event queue index value and
 173  * possibly toggle the event cycle bit if the event queue index wraps back to 0.
 174  */
 175 #define INCREMENT_EVENT_QUEUE_GET(controller, index, cycle) \
 176         INCREMENT_QUEUE_GET(\
 177                 (index), \
 178                 (cycle), \
 179                 (controller)->completion_event_entries, \
 180                 SMU_CQGR_EVENT_CYCLE_BIT \
 181                 )
 182
 183
 184 /**
 185  * NORMALIZE_GET_POINTER() -
 186  *
 187  * This macro will normalize the completion queue get pointer so its value can
 188  * be used as an index into an array
 189  */
 190 #define NORMALIZE_GET_POINTER(x) \
 191         ((x) & SMU_COMPLETION_QUEUE_GET_POINTER_MASK)
 192
 193 /**
 194  * NORMALIZE_GET_POINTER_CYCLE_BIT() -
 195  *
 196  * This macro will normalize the completion queue cycle pointer so it matches
 197  * the completion queue cycle bit
 198  */
 199 #define NORMALIZE_GET_POINTER_CYCLE_BIT(x) \
 200         ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT))
 201
 202 /**
 203  * COMPLETION_QUEUE_CYCLE_BIT() -
 204  *
 205  * This macro will return the cycle bit of the completion queue entry
 206  */
 207 #define COMPLETION_QUEUE_CYCLE_BIT(x) ((x) & 0x80000000)
 208
 209 static bool scic_sds_controller_completion_queue_has_entries(
 210         struct scic_sds_controller *scic)
 211 {
 212         u32 get_value = scic->completion_queue_get;
 213         u32 get_index = get_value & SMU_COMPLETION_QUEUE_GET_POINTER_MASK;
 214
 215         if (NORMALIZE_GET_POINTER_CYCLE_BIT(get_value) ==
 216             COMPLETION_QUEUE_CYCLE_BIT(scic->completion_queue[get_index]))
 217                 return true;
 218
 219         return false;
 220 }
 221
 222 static bool scic_sds_controller_isr(struct scic_sds_controller *scic)
 223 {
 224         if (scic_sds_controller_completion_queue_has_entries(scic)) {
 225                 return true;
 226         } else {
 227                 /*
 228                  * we have a spurious interrupt it could be that we have already
 229                  * emptied the completion queue from a previous interrupt */
 230                 writel(SMU_ISR_COMPLETION, &scic->smu_registers->interrupt_status);
 231
 232                 /*
 233                  * There is a race in the hardware that could cause us not to be notified
 234                  * of an interrupt completion if we do not take this step.  We will mask
 235                  * then unmask the interrupts so if there is another interrupt pending
 236                  * the clearing of the interrupt source we get the next interrupt message. */
 237                 writel(0xFF000000, &scic->smu_registers->interrupt_mask);
 238                 writel(0, &scic->smu_registers->interrupt_mask);
 239         }
 240
 241         return false;
 242 }
 243
 244 irqreturn_t isci_msix_isr(int vec, void *data)
 245 {
 246         struct isci_host *ihost = data;
 247
 248         if (scic_sds_controller_isr(&ihost->sci))
 249                 tasklet_schedule(&ihost->completion_tasklet);
 250
 251         return IRQ_HANDLED;
 252 }
 253
 254 static bool scic_sds_controller_error_isr(struct scic_sds_controller *scic)
 255 {
 256         u32 interrupt_status;
 257
 258         interrupt_status =
 259                 readl(&scic->smu_registers->interrupt_status);
 260         interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND);
 261
 262         if (interrupt_status != 0) {
 263                 /*
 264                  * There is an error interrupt pending so let it through and handle
 265                  * in the callback */
 266                 return true;
 267         }
 268
 269         /*
 270          * There is a race in the hardware that could cause us not to be notified
 271          * of an interrupt completion if we do not take this step.  We will mask
 272          * then unmask the error interrupts so if there was another interrupt
 273          * pending we will be notified.
 274          * Could we write the value of (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)? */
 275         writel(0xff, &scic->smu_registers->interrupt_mask);
 276         writel(0, &scic->smu_registers->interrupt_mask);
 277
 278         return false;
 279 }
 280
 281 static void scic_sds_controller_task_completion(struct scic_sds_controller *scic,
 282                                                 u32 completion_entry)
 283 {
 284         u32 index;
 285         struct scic_sds_request *io_request;
 286
 287         index = SCU_GET_COMPLETION_INDEX(completion_entry);
 288         io_request = scic->io_request_table[index];
 289
 290         /* Make sure that we really want to process this IO request */
 291         if (
 292                 (io_request != NULL)
 293                 && (io_request->io_tag != SCI_CONTROLLER_INVALID_IO_TAG)
 294                 && (
 295                         scic_sds_io_tag_get_sequence(io_request->io_tag)
 296                         == scic->io_request_sequence[index]
 297                         )
 298                 ) {
 299                 /* Yep this is a valid io request pass it along to the io request handler */
 300                 scic_sds_io_request_tc_completion(io_request, completion_entry);
 301         }
 302 }
 303
 304 static void scic_sds_controller_sdma_completion(struct scic_sds_controller *scic,
 305                                                 u32 completion_entry)
 306 {
 307         u32 index;
 308         struct scic_sds_request *io_request;
 309         struct scic_sds_remote_device *device;
 310
 311         index = SCU_GET_COMPLETION_INDEX(completion_entry);
 312
 313         switch (scu_get_command_request_type(completion_entry)) {
 314         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_TC:
 315         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_TC:
 316                 io_request = scic->io_request_table[index];
 317                 dev_warn(scic_to_dev(scic),
 318                          "%s: SCIC SDS Completion type SDMA %x for io request "
 319                          "%p\n",
 320                          __func__,
 321                          completion_entry,
 322                          io_request);
 323                 /* @todo For a post TC operation we need to fail the IO
 324                  * request
 325                  */
 326                 break;
 327
 328         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_RNC:
 329         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_OTHER_RNC:
 330         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_RNC:
 331                 device = scic->device_table[index];
 332                 dev_warn(scic_to_dev(scic),
 333                          "%s: SCIC SDS Completion type SDMA %x for remote "
 334                          "device %p\n",
 335                          __func__,
 336                          completion_entry,
 337                          device);
 338                 /* @todo For a port RNC operation we need to fail the
 339                  * device
 340                  */
 341                 break;
 342
 343         default:
 344                 dev_warn(scic_to_dev(scic),
 345                          "%s: SCIC SDS Completion unknown SDMA completion "
 346                          "type %x\n",
 347                          __func__,
 348                          completion_entry);
 349                 break;
 350
 351         }
 352 }
 353
 354 static void scic_sds_controller_unsolicited_frame(struct scic_sds_controller *scic,
 355                                                   u32 completion_entry)
 356 {
 357         u32 index;
 358         u32 frame_index;
 359
 360         struct isci_host *ihost = scic_to_ihost(scic);
 361         struct scu_unsolicited_frame_header *frame_header;
 362         struct scic_sds_phy *phy;
 363         struct scic_sds_remote_device *device;
 364
 365         enum sci_status result = SCI_FAILURE;
 366
 367         frame_index = SCU_GET_FRAME_INDEX(completion_entry);
 368
 369         frame_header = scic->uf_control.buffers.array[frame_index].header;
 370         scic->uf_control.buffers.array[frame_index].state = UNSOLICITED_FRAME_IN_USE;
 371
 372         if (SCU_GET_FRAME_ERROR(completion_entry)) {
 373                 /*
 374                  * / @todo If the IAF frame or SIGNATURE FIS frame has an error will
 375                  * /       this cause a problem? We expect the phy initialization will
 376                  * /       fail if there is an error in the frame. */
 377                 scic_sds_controller_release_frame(scic, frame_index);
 378                 return;
 379         }
 380
 381         if (frame_header->is_address_frame) {
 382                 index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry);
 383                 phy = &ihost->phys[index].sci;
 384                 result = scic_sds_phy_frame_handler(phy, frame_index);
 385         } else {
 386
 387                 index = SCU_GET_COMPLETION_INDEX(completion_entry);
 388
 389                 if (index == SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
 390                         /*
 391                          * This is a signature fis or a frame from a direct attached SATA
 392                          * device that has not yet been created.  In either case forwared
 393                          * the frame to the PE and let it take care of the frame data. */
 394                         index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry);
 395                         phy = &ihost->phys[index].sci;
 396                         result = scic_sds_phy_frame_handler(phy, frame_index);
 397                 } else {
 398                         if (index < scic->remote_node_entries)
 399                                 device = scic->device_table[index];
 400                         else
 401                                 device = NULL;
 402
 403                         if (device != NULL)
 404                                 result = scic_sds_remote_device_frame_handler(device, frame_index);
 405                         else
 406                                 scic_sds_controller_release_frame(scic, frame_index);
 407                 }
 408         }
 409
 410         if (result != SCI_SUCCESS) {
 411                 /*
 412                  * / @todo Is there any reason to report some additional error message
 413                  * /       when we get this failure notifiction? */
 414         }
 415 }
 416
 417 static void scic_sds_controller_event_completion(struct scic_sds_controller *scic,
 418                                                  u32 completion_entry)
 419 {
 420         struct isci_host *ihost = scic_to_ihost(scic);
 421         struct scic_sds_request *io_request;
 422         struct scic_sds_remote_device *device;
 423         struct scic_sds_phy *phy;
 424         u32 index;
 425
 426         index = SCU_GET_COMPLETION_INDEX(completion_entry);
 427
 428         switch (scu_get_event_type(completion_entry)) {
 429         case SCU_EVENT_TYPE_SMU_COMMAND_ERROR:
 430                 /* / @todo The driver did something wrong and we need to fix the condtion. */
 431                 dev_err(scic_to_dev(scic),
 432                         "%s: SCIC Controller 0x%p received SMU command error "
 433                         "0x%x\n",
 434                         __func__,
 435                         scic,
 436                         completion_entry);
 437                 break;
 438
 439         case SCU_EVENT_TYPE_SMU_PCQ_ERROR:
 440         case SCU_EVENT_TYPE_SMU_ERROR:
 441         case SCU_EVENT_TYPE_FATAL_MEMORY_ERROR:
 442                 /*
 443                  * / @todo This is a hardware failure and its likely that we want to
 444                  * /       reset the controller. */
 445                 dev_err(scic_to_dev(scic),
 446                         "%s: SCIC Controller 0x%p received fatal controller "
 447                         "event  0x%x\n",
 448                         __func__,
 449                         scic,
 450                         completion_entry);
 451                 break;
 452
 453         case SCU_EVENT_TYPE_TRANSPORT_ERROR:
 454                 io_request = scic->io_request_table[index];
 455                 scic_sds_io_request_event_handler(io_request, completion_entry);
 456                 break;
 457
 458         case SCU_EVENT_TYPE_PTX_SCHEDULE_EVENT:
 459                 switch (scu_get_event_specifier(completion_entry)) {
 460                 case SCU_EVENT_SPECIFIC_SMP_RESPONSE_NO_PE:
 461                 case SCU_EVENT_SPECIFIC_TASK_TIMEOUT:
 462                         io_request = scic->io_request_table[index];
 463                         if (io_request != NULL)
 464                                 scic_sds_io_request_event_handler(io_request, completion_entry);
 465                         else
 466                                 dev_warn(scic_to_dev(scic),
 467                                          "%s: SCIC Controller 0x%p received "
 468                                          "event 0x%x for io request object "
 469                                          "that doesnt exist.\n",
 470                                          __func__,
 471                                          scic,
 472                                          completion_entry);
 473
 474                         break;
 475
 476                 case SCU_EVENT_SPECIFIC_IT_NEXUS_TIMEOUT:
 477                         device = scic->device_table[index];
 478                         if (device != NULL)
 479                                 scic_sds_remote_device_event_handler(device, completion_entry);
 480                         else
 481                                 dev_warn(scic_to_dev(scic),
 482                                          "%s: SCIC Controller 0x%p received "
 483                                          "event 0x%x for remote device object "
 484                                          "that doesnt exist.\n",
 485                                          __func__,
 486                                          scic,
 487                                          completion_entry);
 488
 489                         break;
 490                 }
 491                 break;
 492
 493         case SCU_EVENT_TYPE_BROADCAST_CHANGE:
 494         /*
 495          * direct the broadcast change event to the phy first and then let
 496          * the phy redirect the broadcast change to the port object */
 497         case SCU_EVENT_TYPE_ERR_CNT_EVENT:
 498         /*
 499          * direct error counter event to the phy object since that is where
 500          * we get the event notification.  This is a type 4 event. */
 501         case SCU_EVENT_TYPE_OSSP_EVENT:
 502                 index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry);
 503                 phy = &ihost->phys[index].sci;
 504                 scic_sds_phy_event_handler(phy, completion_entry);
 505                 break;
 506
 507         case SCU_EVENT_TYPE_RNC_SUSPEND_TX:
 508         case SCU_EVENT_TYPE_RNC_SUSPEND_TX_RX:
 509         case SCU_EVENT_TYPE_RNC_OPS_MISC:
 510                 if (index < scic->remote_node_entries) {
 511                         device = scic->device_table[index];
 512
 513                         if (device != NULL)
 514                                 scic_sds_remote_device_event_handler(device, completion_entry);
 515                 } else
 516                         dev_err(scic_to_dev(scic),
 517                                 "%s: SCIC Controller 0x%p received event 0x%x "
 518                                 "for remote device object 0x%0x that doesnt "
 519                                 "exist.\n",
 520                                 __func__,
 521                                 scic,
 522                                 completion_entry,
 523                                 index);
 524
 525                 break;
 526
 527         default:
 528                 dev_warn(scic_to_dev(scic),
 529                          "%s: SCIC Controller received unknown event code %x\n",
 530                          __func__,
 531                          completion_entry);
 532                 break;
 533         }
 534 }
 535
 536
 537
 538 static void scic_sds_controller_process_completions(struct scic_sds_controller *scic)
 539 {
 540         u32 completion_count = 0;
 541         u32 completion_entry;
 542         u32 get_index;
 543         u32 get_cycle;
 544         u32 event_index;
 545         u32 event_cycle;
 546
 547         dev_dbg(scic_to_dev(scic),
 548                 "%s: completion queue begining get:0x%08x\n",
 549                 __func__,
 550                 scic->completion_queue_get);
 551
 552         /* Get the component parts of the completion queue */
 553         get_index = NORMALIZE_GET_POINTER(scic->completion_queue_get);
 554         get_cycle = SMU_CQGR_CYCLE_BIT & scic->completion_queue_get;
 555
 556         event_index = NORMALIZE_EVENT_POINTER(scic->completion_queue_get);
 557         event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & scic->completion_queue_get;
 558
 559         while (
 560                 NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle)
 561                 == COMPLETION_QUEUE_CYCLE_BIT(scic->completion_queue[get_index])
 562                 ) {
 563                 completion_count++;
 564
 565                 completion_entry = scic->completion_queue[get_index];
 566                 INCREMENT_COMPLETION_QUEUE_GET(scic, get_index, get_cycle);
 567
 568                 dev_dbg(scic_to_dev(scic),
 569                         "%s: completion queue entry:0x%08x\n",
 570                         __func__,
 571                         completion_entry);
 572
 573                 switch (SCU_GET_COMPLETION_TYPE(completion_entry)) {
 574                 case SCU_COMPLETION_TYPE_TASK:
 575                         scic_sds_controller_task_completion(scic, completion_entry);
 576                         break;
 577
 578                 case SCU_COMPLETION_TYPE_SDMA:
 579                         scic_sds_controller_sdma_completion(scic, completion_entry);
 580                         break;
 581
 582                 case SCU_COMPLETION_TYPE_UFI:
 583                         scic_sds_controller_unsolicited_frame(scic, completion_entry);
 584                         break;
 585
 586                 case SCU_COMPLETION_TYPE_EVENT:
 587                         INCREMENT_EVENT_QUEUE_GET(scic, event_index, event_cycle);
 588                         scic_sds_controller_event_completion(scic, completion_entry);
 589                         break;
 590
 591                 case SCU_COMPLETION_TYPE_NOTIFY:
 592                         /*
 593                          * Presently we do the same thing with a notify event that we do with the
 594                          * other event codes. */
 595                         INCREMENT_EVENT_QUEUE_GET(scic, event_index, event_cycle);
 596                         scic_sds_controller_event_completion(scic, completion_entry);
 597                         break;
 598
 599                 default:
 600                         dev_warn(scic_to_dev(scic),
 601                                  "%s: SCIC Controller received unknown "
 602                                  "completion type %x\n",
 603                                  __func__,
 604                                  completion_entry);
 605                         break;
 606                 }
 607         }
 608
 609         /* Update the get register if we completed one or more entries */
 610         if (completion_count > 0) {
 611                 scic->completion_queue_get =
 612                         SMU_CQGR_GEN_BIT(ENABLE) |
 613                         SMU_CQGR_GEN_BIT(EVENT_ENABLE) |
 614                         event_cycle |
 615                         SMU_CQGR_GEN_VAL(EVENT_POINTER, event_index) |
 616                         get_cycle |
 617                         SMU_CQGR_GEN_VAL(POINTER, get_index);
 618
 619                 writel(scic->completion_queue_get,
 620                        &scic->smu_registers->completion_queue_get);
 621
 622         }
 623
 624         dev_dbg(scic_to_dev(scic),
 625                 "%s: completion queue ending get:0x%08x\n",
 626                 __func__,
 627                 scic->completion_queue_get);
 628
 629 }
 630
 631 static void scic_sds_controller_error_handler(struct scic_sds_controller *scic)
 632 {
 633         u32 interrupt_status;
 634
 635         interrupt_status =
 636                 readl(&scic->smu_registers->interrupt_status);
 637
 638         if ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) &&
 639             scic_sds_controller_completion_queue_has_entries(scic)) {
 640
 641                 scic_sds_controller_process_completions(scic);
 642                 writel(SMU_ISR_QUEUE_SUSPEND, &scic->smu_registers->interrupt_status);
 643         } else {
 644                 dev_err(scic_to_dev(scic), "%s: status: %#x\n", __func__,
 645                         interrupt_status);
 646
 647                 sci_base_state_machine_change_state(&scic->state_machine,
 648                                                     SCI_BASE_CONTROLLER_STATE_FAILED);
 649
 650                 return;
 651         }
 652
 653         /* If we dont process any completions I am not sure that we want to do this.
 654          * We are in the middle of a hardware fault and should probably be reset.
 655          */
 656         writel(0, &scic->smu_registers->interrupt_mask);
 657 }
 658
 659 irqreturn_t isci_intx_isr(int vec, void *data)
 660 {
 661         irqreturn_t ret = IRQ_NONE;
 662         struct isci_host *ihost = data;
 663         struct scic_sds_controller *scic = &ihost->sci;
 664
 665         if (scic_sds_controller_isr(scic)) {
 666                 writel(SMU_ISR_COMPLETION, &scic->smu_registers->interrupt_status);
 667                 tasklet_schedule(&ihost->completion_tasklet);
 668                 ret = IRQ_HANDLED;
 669         } else if (scic_sds_controller_error_isr(scic)) {
 670                 spin_lock(&ihost->scic_lock);
 671                 scic_sds_controller_error_handler(scic);
 672                 spin_unlock(&ihost->scic_lock);
 673                 ret = IRQ_HANDLED;
 674         }
 675
 676         return ret;
 677 }
 678
 679 irqreturn_t isci_error_isr(int vec, void *data)
 680 {
 681         struct isci_host *ihost = data;
 682
 683         if (scic_sds_controller_error_isr(&ihost->sci))
 684                 scic_sds_controller_error_handler(&ihost->sci);
 685
 686         return IRQ_HANDLED;
 687 }
 688
 689 /**
 690  * isci_host_start_complete() - This function is called by the core library,
 691  *    through the ISCI Module, to indicate controller start status.
 692  * @isci_host: This parameter specifies the ISCI host object
 693  * @completion_status: This parameter specifies the completion status from the
 694  *    core library.
 695  *
 696  */
 697 static void isci_host_start_complete(struct isci_host *ihost, enum sci_status completion_status)
 698 {
 699         if (completion_status != SCI_SUCCESS)
 700                 dev_info(&ihost->pdev->dev,
 701                         "controller start timed out, continuing...\n");
 702         isci_host_change_state(ihost, isci_ready);
 703         clear_bit(IHOST_START_PENDING, &ihost->flags);
 704         wake_up(&ihost->eventq);
 705 }
 706
 707 int isci_host_scan_finished(struct Scsi_Host *shost, unsigned long time)
 708 {
 709         struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha;
 710
 711         if (test_bit(IHOST_START_PENDING, &ihost->flags))
 712                 return 0;
 713
 714         /* todo: use sas_flush_discovery once it is upstream */
 715         scsi_flush_work(shost);
 716
 717         scsi_flush_work(shost);
 718
 719         dev_dbg(&ihost->pdev->dev,
 720                 "%s: ihost->status = %d, time = %ld\n",
 721                  __func__, isci_host_get_state(ihost), time);
 722
 723         return 1;
 724
 725 }
 726
 727 /**
 728  * scic_controller_get_suggested_start_timeout() - This method returns the
 729  *    suggested scic_controller_start() timeout amount.  The user is free to
 730  *    use any timeout value, but this method provides the suggested minimum
 731  *    start timeout value.  The returned value is based upon empirical
 732  *    information determined as a result of interoperability testing.
 733  * @controller: the handle to the controller object for which to return the
 734  *    suggested start timeout.
 735  *
 736  * This method returns the number of milliseconds for the suggested start
 737  * operation timeout.
 738  */
 739 static u32 scic_controller_get_suggested_start_timeout(
 740         struct scic_sds_controller *sc)
 741 {
 742         /* Validate the user supplied parameters. */
 743         if (sc == NULL)
 744                 return 0;
 745
 746         /*
 747          * The suggested minimum timeout value for a controller start operation:
 748          *
 749          *     Signature FIS Timeout
 750          *   + Phy Start Timeout
 751          *   + Number of Phy Spin Up Intervals
 752          *   ---------------------------------
 753          *   Number of milliseconds for the controller start operation.
 754          *
 755          * NOTE: The number of phy spin up intervals will be equivalent
 756          *       to the number of phys divided by the number phys allowed
 757          *       per interval - 1 (once OEM parameters are supported).
 758          *       Currently we assume only 1 phy per interval. */
 759
 760         return SCIC_SDS_SIGNATURE_FIS_TIMEOUT
 761                 + SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT
 762                 + ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
 763 }
 764
 765 static void scic_controller_enable_interrupts(
 766         struct scic_sds_controller *scic)
 767 {
 768         BUG_ON(scic->smu_registers == NULL);
 769         writel(0, &scic->smu_registers->interrupt_mask);
 770 }
 771
 772 void scic_controller_disable_interrupts(
 773         struct scic_sds_controller *scic)
 774 {
 775         BUG_ON(scic->smu_registers == NULL);
 776         writel(0xffffffff, &scic->smu_registers->interrupt_mask);
 777 }
 778
 779 static void scic_sds_controller_enable_port_task_scheduler(
 780         struct scic_sds_controller *scic)
 781 {
 782         u32 port_task_scheduler_value;
 783
 784         port_task_scheduler_value =
 785                 readl(&scic->scu_registers->peg0.ptsg.control);
 786         port_task_scheduler_value |=
 787                 (SCU_PTSGCR_GEN_BIT(ETM_ENABLE) |
 788                  SCU_PTSGCR_GEN_BIT(PTSG_ENABLE));
 789         writel(port_task_scheduler_value,
 790                &scic->scu_registers->peg0.ptsg.control);
 791 }
 792
 793 static void scic_sds_controller_assign_task_entries(struct scic_sds_controller *scic)
 794 {
 795         u32 task_assignment;
 796
 797         /*
 798          * Assign all the TCs to function 0
 799          * TODO: Do we actually need to read this register to write it back?
 800          */
 801
 802         task_assignment =
 803                 readl(&scic->smu_registers->task_context_assignment[0]);
 804
 805         task_assignment |= (SMU_TCA_GEN_VAL(STARTING, 0)) |
 806                 (SMU_TCA_GEN_VAL(ENDING,  scic->task_context_entries - 1)) |
 807                 (SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE));
 808
 809         writel(task_assignment,
 810                 &scic->smu_registers->task_context_assignment[0]);
 811
 812 }
 813
 814 static void scic_sds_controller_initialize_completion_queue(struct scic_sds_controller *scic)
 815 {
 816         u32 index;
 817         u32 completion_queue_control_value;
 818         u32 completion_queue_get_value;
 819         u32 completion_queue_put_value;
 820
 821         scic->completion_queue_get = 0;
 822
 823         completion_queue_control_value = (
 824                 SMU_CQC_QUEUE_LIMIT_SET(scic->completion_queue_entries - 1)
 825                 | SMU_CQC_EVENT_LIMIT_SET(scic->completion_event_entries - 1)
 826                 );
 827
 828         writel(completion_queue_control_value,
 829                &scic->smu_registers->completion_queue_control);
 830
 831
 832         /* Set the completion queue get pointer and enable the queue */
 833         completion_queue_get_value = (
 834                 (SMU_CQGR_GEN_VAL(POINTER, 0))
 835                 | (SMU_CQGR_GEN_VAL(EVENT_POINTER, 0))
 836                 | (SMU_CQGR_GEN_BIT(ENABLE))
 837                 | (SMU_CQGR_GEN_BIT(EVENT_ENABLE))
 838                 );
 839
 840         writel(completion_queue_get_value,
 841                &scic->smu_registers->completion_queue_get);
 842
 843         /* Set the completion queue put pointer */
 844         completion_queue_put_value = (
 845                 (SMU_CQPR_GEN_VAL(POINTER, 0))
 846                 | (SMU_CQPR_GEN_VAL(EVENT_POINTER, 0))
 847                 );
 848
 849         writel(completion_queue_put_value,
 850                &scic->smu_registers->completion_queue_put);
 851
 852         /* Initialize the cycle bit of the completion queue entries */
 853         for (index = 0; index < scic->completion_queue_entries; index++) {
 854                 /*
 855                  * If get.cycle_bit != completion_queue.cycle_bit
 856                  * its not a valid completion queue entry
 857                  * so at system start all entries are invalid */
 858                 scic->completion_queue[index] = 0x80000000;
 859         }
 860 }
 861
 862 static void scic_sds_controller_initialize_unsolicited_frame_queue(struct scic_sds_controller *scic)
 863 {
 864         u32 frame_queue_control_value;
 865         u32 frame_queue_get_value;
 866         u32 frame_queue_put_value;
 867
 868         /* Write the queue size */
 869         frame_queue_control_value =
 870                 SCU_UFQC_GEN_VAL(QUEUE_SIZE,
 871                                  scic->uf_control.address_table.count);
 872
 873         writel(frame_queue_control_value,
 874                &scic->scu_registers->sdma.unsolicited_frame_queue_control);
 875
 876         /* Setup the get pointer for the unsolicited frame queue */
 877         frame_queue_get_value = (
 878                 SCU_UFQGP_GEN_VAL(POINTER, 0)
 879                 |  SCU_UFQGP_GEN_BIT(ENABLE_BIT)
 880                 );
 881
 882         writel(frame_queue_get_value,
 883                &scic->scu_registers->sdma.unsolicited_frame_get_pointer);
 884         /* Setup the put pointer for the unsolicited frame queue */
 885         frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0);
 886         writel(frame_queue_put_value,
 887                &scic->scu_registers->sdma.unsolicited_frame_put_pointer);
 888 }
 889
 890 /**
 891  * This method will attempt to transition into the ready state for the
 892  *    controller and indicate that the controller start operation has completed
 893  *    if all criteria are met.
 894  * @scic: This parameter indicates the controller object for which
 895  *    to transition to ready.
 896  * @status: This parameter indicates the status value to be pass into the call
 897  *    to scic_cb_controller_start_complete().
 898  *
 899  * none.
 900  */
 901 static void scic_sds_controller_transition_to_ready(
 902         struct scic_sds_controller *scic,
 903         enum sci_status status)
 904 {
 905         struct isci_host *ihost = scic_to_ihost(scic);
 906
 907         if (scic->state_machine.current_state_id ==
 908             SCI_BASE_CONTROLLER_STATE_STARTING) {
 909                 /*
 910                  * We move into the ready state, because some of the phys/ports
 911                  * may be up and operational.
 912                  */
 913                 sci_base_state_machine_change_state(&scic->state_machine,
 914                                                     SCI_BASE_CONTROLLER_STATE_READY);
 915
 916                 isci_host_start_complete(ihost, status);
 917         }
 918 }
 919
 920 static void scic_sds_controller_phy_timer_stop(struct scic_sds_controller *scic)
 921 {
 922         isci_timer_stop(scic->phy_startup_timer);
 923
 924         scic->phy_startup_timer_pending = false;
 925 }
 926
 927 static void scic_sds_controller_phy_timer_start(struct scic_sds_controller *scic)
 928 {
 929         isci_timer_start(scic->phy_startup_timer,
 930                          SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT);
 931
 932         scic->phy_startup_timer_pending = true;
 933 }
 934
 935 /**
 936  * scic_sds_controller_start_next_phy - start phy
 937  * @scic: controller
 938  *
 939  * If all the phys have been started, then attempt to transition the
 940  * controller to the READY state and inform the user
 941  * (scic_cb_controller_start_complete()).
 942  */
 943 static enum sci_status scic_sds_controller_start_next_phy(struct scic_sds_controller *scic)
 944 {
 945         struct isci_host *ihost = scic_to_ihost(scic);
 946         struct scic_sds_oem_params *oem = &scic->oem_parameters.sds1;
 947         struct scic_sds_phy *sci_phy;
 948         enum sci_status status;
 949
 950         status = SCI_SUCCESS;
 951
 952         if (scic->phy_startup_timer_pending)
 953                 return status;
 954
 955         if (scic->next_phy_to_start >= SCI_MAX_PHYS) {
 956                 bool is_controller_start_complete = true;
 957                 u32 state;
 958                 u8 index;
 959
 960                 for (index = 0; index < SCI_MAX_PHYS; index++) {
 961                         sci_phy = &ihost->phys[index].sci;
 962                         state = sci_phy->state_machine.current_state_id;
 963
 964                         if (!scic_sds_phy_get_port(sci_phy))
 965                                 continue;
 966
 967                         /* The controller start operation is complete iff:
 968                          * - all links have been given an opportunity to start
 969                          * - have no indication of a connected device
 970                          * - have an indication of a connected device and it has
 971                          *   finished the link training process.
 972                          */
 973                         if ((sci_phy->is_in_link_training == false &&
 974                              state == SCI_BASE_PHY_STATE_INITIAL) ||
 975                             (sci_phy->is_in_link_training == false &&
 976                              state == SCI_BASE_PHY_STATE_STOPPED) ||
 977                             (sci_phy->is_in_link_training == true &&
 978                              state == SCI_BASE_PHY_STATE_STARTING)) {
 979                                 is_controller_start_complete = false;
 980                                 break;
 981                         }
 982                 }
 983
 984                 /*
 985                  * The controller has successfully finished the start process.
 986                  * Inform the SCI Core user and transition to the READY state. */
 987                 if (is_controller_start_complete == true) {
 988                         scic_sds_controller_transition_to_ready(scic, SCI_SUCCESS);
 989                         scic_sds_controller_phy_timer_stop(scic);
 990                 }
 991         } else {
 992                 sci_phy = &ihost->phys[scic->next_phy_to_start].sci;
 993
 994                 if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
 995                         if (scic_sds_phy_get_port(sci_phy) == NULL) {
 996                                 scic->next_phy_to_start++;
 997
 998                                 /* Caution recursion ahead be forwarned
 999                                  *
1000                                  * The PHY was never added to a PORT in MPC mode
1001                                  * so start the next phy in sequence This phy
1002                                  * will never go link up and will not draw power
1003                                  * the OEM parameters either configured the phy
1004                                  * incorrectly for the PORT or it was never
1005                                  * assigned to a PORT
1006                                  */
1007                                 return scic_sds_controller_start_next_phy(scic);
1008                         }
1009                 }
1010
1011                 status = scic_sds_phy_start(sci_phy);
1012
1013                 if (status == SCI_SUCCESS) {
1014                         scic_sds_controller_phy_timer_start(scic);
1015                 } else {
1016                         dev_warn(scic_to_dev(scic),
1017                                  "%s: Controller stop operation failed "
1018                                  "to stop phy %d because of status "
1019                                  "%d.\n",
1020                                  __func__,
1021                                  ihost->phys[scic->next_phy_to_start].sci.phy_index,
1022                                  status);
1023                 }
1024
1025                 scic->next_phy_to_start++;
1026         }
1027
1028         return status;
1029 }
1030
1031 static void scic_sds_controller_phy_startup_timeout_handler(void *_scic)
1032 {
1033         struct scic_sds_controller *scic = _scic;
1034         enum sci_status status;
1035
1036         scic->phy_startup_timer_pending = false;
1037         status = SCI_FAILURE;
1038         while (status != SCI_SUCCESS)
1039                 status = scic_sds_controller_start_next_phy(scic);
1040 }
1041
1042 static enum sci_status scic_controller_start(struct scic_sds_controller *scic,
1043                                              u32 timeout)
1044 {
1045         struct isci_host *ihost = scic_to_ihost(scic);
1046         enum sci_status result;
1047         u16 index;
1048
1049         if (scic->state_machine.current_state_id !=
1050             SCI_BASE_CONTROLLER_STATE_INITIALIZED) {
1051                 dev_warn(scic_to_dev(scic),
1052                          "SCIC Controller start operation requested in "
1053                          "invalid state\n");
1054                 return SCI_FAILURE_INVALID_STATE;
1055         }
1056
1057         /* Build the TCi free pool */
1058         sci_pool_initialize(scic->tci_pool);
1059         for (index = 0; index < scic->task_context_entries; index++)
1060                 sci_pool_put(scic->tci_pool, index);
1061
1062         /* Build the RNi free pool */
1063         scic_sds_remote_node_table_initialize(
1064                         &scic->available_remote_nodes,
1065                         scic->remote_node_entries);
1066
1067         /*
1068          * Before anything else lets make sure we will not be
1069          * interrupted by the hardware.
1070          */
1071         scic_controller_disable_interrupts(scic);
1072
1073         /* Enable the port task scheduler */
1074         scic_sds_controller_enable_port_task_scheduler(scic);
1075
1076         /* Assign all the task entries to scic physical function */
1077         scic_sds_controller_assign_task_entries(scic);
1078
1079         /* Now initialize the completion queue */
1080         scic_sds_controller_initialize_completion_queue(scic);
1081
1082         /* Initialize the unsolicited frame queue for use */
1083         scic_sds_controller_initialize_unsolicited_frame_queue(scic);
1084
1085         /* Start all of the ports on this controller */
1086         for (index = 0; index < scic->logical_port_entries; index++) {
1087                 struct scic_sds_port *sci_port = &ihost->ports[index].sci;
1088
1089                 result = sci_port->state_handlers->start_handler(sci_port);
1090                 if (result)
1091                         return result;
1092         }
1093
1094         scic_sds_controller_start_next_phy(scic);
1095
1096         isci_timer_start(scic->timeout_timer, timeout);
1097
1098         sci_base_state_machine_change_state(&scic->state_machine,
1099                                             SCI_BASE_CONTROLLER_STATE_STARTING);
1100
1101         return SCI_SUCCESS;
1102 }
1103
1104 void isci_host_scan_start(struct Scsi_Host *shost)
1105 {
1106         struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha;
1107         unsigned long tmo = scic_controller_get_suggested_start_timeout(&ihost->sci);
1108
1109         set_bit(IHOST_START_PENDING, &ihost->flags);
1110
1111         spin_lock_irq(&ihost->scic_lock);
1112         scic_controller_start(&ihost->sci, tmo);
1113         scic_controller_enable_interrupts(&ihost->sci);
1114         spin_unlock_irq(&ihost->scic_lock);
1115 }
1116
1117 static void isci_host_stop_complete(struct isci_host *ihost, enum sci_status completion_status)
1118 {
1119         isci_host_change_state(ihost, isci_stopped);
1120         scic_controller_disable_interrupts(&ihost->sci);
1121         clear_bit(IHOST_STOP_PENDING, &ihost->flags);
1122         wake_up(&ihost->eventq);
1123 }
1124
1125 static void scic_sds_controller_completion_handler(struct scic_sds_controller *scic)
1126 {
1127         /* Empty out the completion queue */
1128         if (scic_sds_controller_completion_queue_has_entries(scic))
1129                 scic_sds_controller_process_completions(scic);
1130
1131         /* Clear the interrupt and enable all interrupts again */
1132         writel(SMU_ISR_COMPLETION, &scic->smu_registers->interrupt_status);
1133         /* Could we write the value of SMU_ISR_COMPLETION? */
1134         writel(0xFF000000, &scic->smu_registers->interrupt_mask);
1135         writel(0, &scic->smu_registers->interrupt_mask);
1136 }
1137
1138 /**
1139  * isci_host_completion_routine() - This function is the delayed service
1140  *    routine that calls the sci core library's completion handler. It's
1141  *    scheduled as a tasklet from the interrupt service routine when interrupts
1142  *    in use, or set as the timeout function in polled mode.
1143  * @data: This parameter specifies the ISCI host object
1144  *
1145  */
1146 static void isci_host_completion_routine(unsigned long data)
1147 {
1148         struct isci_host *isci_host = (struct isci_host *)data;
1149         struct list_head    completed_request_list;
1150         struct list_head    errored_request_list;
1151         struct list_head    *current_position;
1152         struct list_head    *next_position;
1153         struct isci_request *request;
1154         struct isci_request *next_request;
1155         struct sas_task     *task;
1156
1157         INIT_LIST_HEAD(&completed_request_list);
1158         INIT_LIST_HEAD(&errored_request_list);
1159
1160         spin_lock_irq(&isci_host->scic_lock);
1161
1162         scic_sds_controller_completion_handler(&isci_host->sci);
1163
1164         /* Take the lists of completed I/Os from the host. */
1165
1166         list_splice_init(&isci_host->requests_to_complete,
1167                          &completed_request_list);
1168
1169         /* Take the list of errored I/Os from the host. */
1170         list_splice_init(&isci_host->requests_to_errorback,
1171                          &errored_request_list);
1172
1173         spin_unlock_irq(&isci_host->scic_lock);
1174
1175         /* Process any completions in the lists. */
1176         list_for_each_safe(current_position, next_position,
1177                            &completed_request_list) {
1178
1179                 request = list_entry(current_position, struct isci_request,
1180                                      completed_node);
1181                 task = isci_request_access_task(request);
1182
1183                 /* Normal notification (task_done) */
1184                 dev_dbg(&isci_host->pdev->dev,
1185                         "%s: Normal - request/task = %p/%p\n",
1186                         __func__,
1187                         request,
1188                         task);
1189
1190                 /* Return the task to libsas */
1191                 if (task != NULL) {
1192
1193                         task->lldd_task = NULL;
1194                         if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
1195
1196                                 /* If the task is already in the abort path,
1197                                 * the task_done callback cannot be called.
1198                                 */
1199                                 task->task_done(task);
1200                         }
1201                 }
1202                 /* Free the request object. */
1203                 isci_request_free(isci_host, request);
1204         }
1205         list_for_each_entry_safe(request, next_request, &errored_request_list,
1206                                  completed_node) {
1207
1208                 task = isci_request_access_task(request);
1209
1210                 /* Use sas_task_abort */
1211                 dev_warn(&isci_host->pdev->dev,
1212                          "%s: Error - request/task = %p/%p\n",
1213                          __func__,
1214                          request,
1215                          task);
1216
1217                 if (task != NULL) {
1218
1219                         /* Put the task into the abort path if it's not there
1220                          * already.
1221                          */
1222                         if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED))
1223                                 sas_task_abort(task);
1224
1225                 } else {
1226                         /* This is a case where the request has completed with a
1227                          * status such that it needed further target servicing,
1228                          * but the sas_task reference has already been removed
1229                          * from the request.  Since it was errored, it was not
1230                          * being aborted, so there is nothing to do except free
1231                          * it.
1232                          */
1233
1234                         spin_lock_irq(&isci_host->scic_lock);
1235                         /* Remove the request from the remote device's list
1236                         * of pending requests.
1237                         */
1238                         list_del_init(&request->dev_node);
1239                         spin_unlock_irq(&isci_host->scic_lock);
1240
1241                         /* Free the request object. */
1242                         isci_request_free(isci_host, request);
1243                 }
1244         }
1245
1246 }
1247
1248 /**
1249  * scic_controller_stop() - This method will stop an individual controller
1250  *    object.This method will invoke the associated user callback upon
1251  *    completion.  The completion callback is called when the following
1252  *    conditions are met: -# the method return status is SCI_SUCCESS. -# the
1253  *    controller has been quiesced. This method will ensure that all IO
1254  *    requests are quiesced, phys are stopped, and all additional operation by
1255  *    the hardware is halted.
1256  * @controller: the handle to the controller object to stop.
1257  * @timeout: This parameter specifies the number of milliseconds in which the
1258  *    stop operation should complete.
1259  *
1260  * The controller must be in the STARTED or STOPPED state. Indicate if the
1261  * controller stop method succeeded or failed in some way. SCI_SUCCESS if the
1262  * stop operation successfully began. SCI_WARNING_ALREADY_IN_STATE if the
1263  * controller is already in the STOPPED state. SCI_FAILURE_INVALID_STATE if the
1264  * controller is not either in the STARTED or STOPPED states.
1265  */
1266 static enum sci_status scic_controller_stop(struct scic_sds_controller *scic,
1267                                             u32 timeout)
1268 {
1269         if (scic->state_machine.current_state_id !=
1270             SCI_BASE_CONTROLLER_STATE_READY) {
1271                 dev_warn(scic_to_dev(scic),
1272                          "SCIC Controller stop operation requested in "
1273                          "invalid state\n");
1274                 return SCI_FAILURE_INVALID_STATE;
1275         }
1276
1277         isci_timer_start(scic->timeout_timer, timeout);
1278         sci_base_state_machine_change_state(&scic->state_machine,
1279                                             SCI_BASE_CONTROLLER_STATE_STOPPING);
1280         return SCI_SUCCESS;
1281 }
1282
1283 /**
1284  * scic_controller_reset() - This method will reset the supplied core
1285  *    controller regardless of the state of said controller.  This operation is
1286  *    considered destructive.  In other words, all current operations are wiped
1287  *    out.  No IO completions for outstanding devices occur.  Outstanding IO
1288  *    requests are not aborted or completed at the actual remote device.
1289  * @controller: the handle to the controller object to reset.
1290  *
1291  * Indicate if the controller reset method succeeded or failed in some way.
1292  * SCI_SUCCESS if the reset operation successfully started. SCI_FATAL_ERROR if
1293  * the controller reset operation is unable to complete.
1294  */
1295 static enum sci_status scic_controller_reset(struct scic_sds_controller *scic)
1296 {
1297         switch (scic->state_machine.current_state_id) {
1298         case SCI_BASE_CONTROLLER_STATE_RESET:
1299         case SCI_BASE_CONTROLLER_STATE_READY:
1300         case SCI_BASE_CONTROLLER_STATE_STOPPED:
1301         case SCI_BASE_CONTROLLER_STATE_FAILED:
1302                 /*
1303                  * The reset operation is not a graceful cleanup, just
1304                  * perform the state transition.
1305                  */
1306                 sci_base_state_machine_change_state(&scic->state_machine,
1307                                 SCI_BASE_CONTROLLER_STATE_RESETTING);
1308                 return SCI_SUCCESS;
1309         default:
1310                 dev_warn(scic_to_dev(scic),
1311                          "SCIC Controller reset operation requested in "
1312                          "invalid state\n");
1313                 return SCI_FAILURE_INVALID_STATE;
1314         }
1315 }
1316
1317 void isci_host_deinit(struct isci_host *ihost)
1318 {
1319         int i;
1320
1321         isci_host_change_state(ihost, isci_stopping);
1322         for (i = 0; i < SCI_MAX_PORTS; i++) {
1323                 struct isci_port *iport = &ihost->ports[i];
1324                 struct isci_remote_device *idev, *d;
1325
1326                 list_for_each_entry_safe(idev, d, &iport->remote_dev_list, node) {
1327                         isci_remote_device_change_state(idev, isci_stopping);
1328                         isci_remote_device_stop(ihost, idev);
1329                 }
1330         }
1331
1332         set_bit(IHOST_STOP_PENDING, &ihost->flags);
1333
1334         spin_lock_irq(&ihost->scic_lock);
1335         scic_controller_stop(&ihost->sci, SCIC_CONTROLLER_STOP_TIMEOUT);
1336         spin_unlock_irq(&ihost->scic_lock);
1337
1338         wait_for_stop(ihost);
1339         scic_controller_reset(&ihost->sci);
1340         isci_timer_list_destroy(ihost);
1341 }
1342
1343 static void __iomem *scu_base(struct isci_host *isci_host)
1344 {
1345         struct pci_dev *pdev = isci_host->pdev;
1346         int id = isci_host->id;
1347
1348         return pcim_iomap_table(pdev)[SCI_SCU_BAR * 2] + SCI_SCU_BAR_SIZE * id;
1349 }
1350
1351 static void __iomem *smu_base(struct isci_host *isci_host)
1352 {
1353         struct pci_dev *pdev = isci_host->pdev;
1354         int id = isci_host->id;
1355
1356         return pcim_iomap_table(pdev)[SCI_SMU_BAR * 2] + SCI_SMU_BAR_SIZE * id;
1357 }
1358
1359 static void isci_user_parameters_get(
1360                 struct isci_host *isci_host,
1361                 union scic_user_parameters *scic_user_params)
1362 {
1363         struct scic_sds_user_parameters *u = &scic_user_params->sds1;
1364         int i;
1365
1366         for (i = 0; i < SCI_MAX_PHYS; i++) {
1367                 struct sci_phy_user_params *u_phy = &u->phys[i];
1368
1369                 u_phy->max_speed_generation = phy_gen;
1370
1371                 /* we are not exporting these for now */
1372                 u_phy->align_insertion_frequency = 0x7f;
1373                 u_phy->in_connection_align_insertion_frequency = 0xff;
1374                 u_phy->notify_enable_spin_up_insertion_frequency = 0x33;
1375         }
1376
1377         u->stp_inactivity_timeout = stp_inactive_to;
1378         u->ssp_inactivity_timeout = ssp_inactive_to;
1379         u->stp_max_occupancy_timeout = stp_max_occ_to;
1380         u->ssp_max_occupancy_timeout = ssp_max_occ_to;
1381         u->no_outbound_task_timeout = no_outbound_task_to;
1382         u->max_number_concurrent_device_spin_up = max_concurr_spinup;
1383 }
1384
1385 static void scic_sds_controller_initial_state_enter(void *object)
1386 {
1387         struct scic_sds_controller *scic = object;
1388
1389         sci_base_state_machine_change_state(&scic->state_machine,
1390                         SCI_BASE_CONTROLLER_STATE_RESET);
1391 }
1392
1393 static inline void scic_sds_controller_starting_state_exit(void *object)
1394 {
1395         struct scic_sds_controller *scic = object;
1396
1397         isci_timer_stop(scic->timeout_timer);
1398 }
1399
1400 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS 853
1401 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS 1280
1402 #define INTERRUPT_COALESCE_TIMEOUT_MAX_US                    2700000
1403 #define INTERRUPT_COALESCE_NUMBER_MAX                        256
1404 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN                7
1405 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX                28
1406
1407 /**
1408  * scic_controller_set_interrupt_coalescence() - This method allows the user to
1409  *    configure the interrupt coalescence.
1410  * @controller: This parameter represents the handle to the controller object
1411  *    for which its interrupt coalesce register is overridden.
1412  * @coalesce_number: Used to control the number of entries in the Completion
1413  *    Queue before an interrupt is generated. If the number of entries exceed
1414  *    this number, an interrupt will be generated. The valid range of the input
1415  *    is [0, 256]. A setting of 0 results in coalescing being disabled.
1416  * @coalesce_timeout: Timeout value in microseconds. The valid range of the
1417  *    input is [0, 2700000] . A setting of 0 is allowed and results in no
1418  *    interrupt coalescing timeout.
1419  *
1420  * Indicate if the user successfully set the interrupt coalesce parameters.
1421  * SCI_SUCCESS The user successfully updated the interrutp coalescence.
1422  * SCI_FAILURE_INVALID_PARAMETER_VALUE The user input value is out of range.
1423  */
1424 static enum sci_status scic_controller_set_interrupt_coalescence(
1425         struct scic_sds_controller *scic_controller,
1426         u32 coalesce_number,
1427         u32 coalesce_timeout)
1428 {
1429         u8 timeout_encode = 0;
1430         u32 min = 0;
1431         u32 max = 0;
1432
1433         /* Check if the input parameters fall in the range. */
1434         if (coalesce_number > INTERRUPT_COALESCE_NUMBER_MAX)
1435                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1436
1437         /*
1438          *  Defined encoding for interrupt coalescing timeout:
1439          *              Value   Min      Max     Units
1440          *              -----   ---      ---     -----
1441          *              0       -        -       Disabled
1442          *              1       13.3     20.0    ns
1443          *              2       26.7     40.0
1444          *              3       53.3     80.0
1445          *              4       106.7    160.0
1446          *              5       213.3    320.0
1447          *              6       426.7    640.0
1448          *              7       853.3    1280.0
1449          *              8       1.7      2.6     us
1450          *              9       3.4      5.1
1451          *              10      6.8      10.2
1452          *              11      13.7     20.5
1453          *              12      27.3     41.0
1454          *              13      54.6     81.9
1455          *              14      109.2    163.8
1456          *              15      218.5    327.7
1457          *              16      436.9    655.4
1458          *              17      873.8    1310.7
1459          *              18      1.7      2.6     ms
1460          *              19      3.5      5.2
1461          *              20      7.0      10.5
1462          *              21      14.0     21.0
1463          *              22      28.0     41.9
1464          *              23      55.9     83.9
1465          *              24      111.8    167.8
1466          *              25      223.7    335.5
1467          *              26      447.4    671.1
1468          *              27      894.8    1342.2
1469          *              28      1.8      2.7     s
1470          *              Others Undefined */
1471
1472         /*
1473          * Use the table above to decide the encode of interrupt coalescing timeout
1474          * value for register writing. */
1475         if (coalesce_timeout == 0)
1476                 timeout_encode = 0;
1477         else{
1478                 /* make the timeout value in unit of (10 ns). */
1479                 coalesce_timeout = coalesce_timeout * 100;
1480                 min = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS / 10;
1481                 max = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS / 10;
1482
1483                 /* get the encode of timeout for register writing. */
1484                 for (timeout_encode = INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN;
1485                       timeout_encode <= INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX;
1486                       timeout_encode++) {
1487                         if (min <= coalesce_timeout &&  max > coalesce_timeout)
1488                                 break;
1489                         else if (coalesce_timeout >= max && coalesce_timeout < min * 2
1490                                  && coalesce_timeout <= INTERRUPT_COALESCE_TIMEOUT_MAX_US * 100) {
1491                                 if ((coalesce_timeout - max) < (2 * min - coalesce_timeout))
1492                                         break;
1493                                 else{
1494                                         timeout_encode++;
1495                                         break;
1496                                 }
1497                         } else {
1498                                 max = max * 2;
1499                                 min = min * 2;
1500                         }
1501                 }
1502
1503                 if (timeout_encode == INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX + 1)
1504                         /* the value is out of range. */
1505                         return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1506         }
1507
1508         writel(SMU_ICC_GEN_VAL(NUMBER, coalesce_number) |
1509                SMU_ICC_GEN_VAL(TIMER, timeout_encode),
1510                &scic_controller->smu_registers->interrupt_coalesce_control);
1511
1512
1513         scic_controller->interrupt_coalesce_number = (u16)coalesce_number;
1514         scic_controller->interrupt_coalesce_timeout = coalesce_timeout / 100;
1515
1516         return SCI_SUCCESS;
1517 }
1518
1519
1520 static void scic_sds_controller_ready_state_enter(void *object)
1521 {
1522         struct scic_sds_controller *scic = object;
1523
1524         /* set the default interrupt coalescence number and timeout value. */
1525         scic_controller_set_interrupt_coalescence(scic, 0x10, 250);
1526 }
1527
1528 static void scic_sds_controller_ready_state_exit(void *object)
1529 {
1530         struct scic_sds_controller *scic = object;
1531
1532         /* disable interrupt coalescence. */
1533         scic_controller_set_interrupt_coalescence(scic, 0, 0);
1534 }
1535
1536 static enum sci_status scic_sds_controller_stop_phys(struct scic_sds_controller *scic)
1537 {
1538         u32 index;
1539         enum sci_status status;
1540         enum sci_status phy_status;
1541         struct isci_host *ihost = scic_to_ihost(scic);
1542
1543         status = SCI_SUCCESS;
1544
1545         for (index = 0; index < SCI_MAX_PHYS; index++) {
1546                 phy_status = scic_sds_phy_stop(&ihost->phys[index].sci);
1547
1548                 if (phy_status != SCI_SUCCESS &&
1549                     phy_status != SCI_FAILURE_INVALID_STATE) {
1550                         status = SCI_FAILURE;
1551
1552                         dev_warn(scic_to_dev(scic),
1553                                  "%s: Controller stop operation failed to stop "
1554                                  "phy %d because of status %d.\n",
1555                                  __func__,
1556                                  ihost->phys[index].sci.phy_index, phy_status);
1557                 }
1558         }
1559
1560         return status;
1561 }
1562
1563 static enum sci_status scic_sds_controller_stop_ports(struct scic_sds_controller *scic)
1564 {
1565         u32 index;
1566         enum sci_status port_status;
1567         enum sci_status status = SCI_SUCCESS;
1568         struct isci_host *ihost = scic_to_ihost(scic);
1569
1570         for (index = 0; index < scic->logical_port_entries; index++) {
1571                 struct scic_sds_port *sci_port = &ihost->ports[index].sci;
1572                 scic_sds_port_handler_t stop;
1573
1574                 stop = sci_port->state_handlers->stop_handler;
1575                 port_status = stop(sci_port);
1576
1577                 if ((port_status != SCI_SUCCESS) &&
1578                     (port_status != SCI_FAILURE_INVALID_STATE)) {
1579                         status = SCI_FAILURE;
1580
1581                         dev_warn(scic_to_dev(scic),
1582                                  "%s: Controller stop operation failed to "
1583                                  "stop port %d because of status %d.\n",
1584                                  __func__,
1585                                  sci_port->logical_port_index,
1586                                  port_status);
1587                 }
1588         }
1589
1590         return status;
1591 }
1592
1593 static enum sci_status scic_sds_controller_stop_devices(struct scic_sds_controller *scic)
1594 {
1595         u32 index;
1596         enum sci_status status;
1597         enum sci_status device_status;
1598
1599         status = SCI_SUCCESS;
1600
1601         for (index = 0; index < scic->remote_node_entries; index++) {
1602                 if (scic->device_table[index] != NULL) {
1603                         /* / @todo What timeout value do we want to provide to this request? */
1604                         device_status = scic_remote_device_stop(scic->device_table[index], 0);
1605
1606                         if ((device_status != SCI_SUCCESS) &&
1607                             (device_status != SCI_FAILURE_INVALID_STATE)) {
1608                                 dev_warn(scic_to_dev(scic),
1609                                          "%s: Controller stop operation failed "
1610                                          "to stop device 0x%p because of "
1611                                          "status %d.\n",
1612                                          __func__,
1613                                          scic->device_table[index], device_status);
1614                         }
1615                 }
1616         }
1617
1618         return status;
1619 }
1620
1621 static void scic_sds_controller_stopping_state_enter(void *object)
1622 {
1623         struct scic_sds_controller *scic = object;
1624
1625         /* Stop all of the components for this controller */
1626         scic_sds_controller_stop_phys(scic);
1627         scic_sds_controller_stop_ports(scic);
1628         scic_sds_controller_stop_devices(scic);
1629 }
1630
1631 static void scic_sds_controller_stopping_state_exit(void *object)
1632 {
1633         struct scic_sds_controller *scic = object;
1634
1635         isci_timer_stop(scic->timeout_timer);
1636 }
1637
1638
1639 /**
1640  * scic_sds_controller_reset_hardware() -
1641  *
1642  * This method will reset the controller hardware.
1643  */
1644 static void scic_sds_controller_reset_hardware(struct scic_sds_controller *scic)
1645 {
1646         /* Disable interrupts so we dont take any spurious interrupts */
1647         scic_controller_disable_interrupts(scic);
1648
1649         /* Reset the SCU */
1650         writel(0xFFFFFFFF, &scic->smu_registers->soft_reset_control);
1651
1652         /* Delay for 1ms to before clearing the CQP and UFQPR. */
1653         udelay(1000);
1654
1655         /* The write to the CQGR clears the CQP */
1656         writel(0x00000000, &scic->smu_registers->completion_queue_get);
1657
1658         /* The write to the UFQGP clears the UFQPR */
1659         writel(0, &scic->scu_registers->sdma.unsolicited_frame_get_pointer);
1660 }
1661
1662 static void scic_sds_controller_resetting_state_enter(void *object)
1663 {
1664         struct scic_sds_controller *scic = object;
1665
1666         scic_sds_controller_reset_hardware(scic);
1667         sci_base_state_machine_change_state(&scic->state_machine,
1668                                             SCI_BASE_CONTROLLER_STATE_RESET);
1669 }
1670
1671 static const struct sci_base_state scic_sds_controller_state_table[] = {
1672         [SCI_BASE_CONTROLLER_STATE_INITIAL] = {
1673                 .enter_state = scic_sds_controller_initial_state_enter,
1674         },
1675         [SCI_BASE_CONTROLLER_STATE_RESET] = {},
1676         [SCI_BASE_CONTROLLER_STATE_INITIALIZING] = {},
1677         [SCI_BASE_CONTROLLER_STATE_INITIALIZED] = {},
1678         [SCI_BASE_CONTROLLER_STATE_STARTING] = {
1679                 .exit_state  = scic_sds_controller_starting_state_exit,
1680         },
1681         [SCI_BASE_CONTROLLER_STATE_READY] = {
1682                 .enter_state = scic_sds_controller_ready_state_enter,
1683                 .exit_state  = scic_sds_controller_ready_state_exit,
1684         },
1685         [SCI_BASE_CONTROLLER_STATE_RESETTING] = {
1686                 .enter_state = scic_sds_controller_resetting_state_enter,
1687         },
1688         [SCI_BASE_CONTROLLER_STATE_STOPPING] = {
1689                 .enter_state = scic_sds_controller_stopping_state_enter,
1690                 .exit_state = scic_sds_controller_stopping_state_exit,
1691         },
1692         [SCI_BASE_CONTROLLER_STATE_STOPPED] = {},
1693         [SCI_BASE_CONTROLLER_STATE_FAILED] = {}
1694 };
1695
1696 static void scic_sds_controller_set_default_config_parameters(struct scic_sds_controller *scic)
1697 {
1698         /* these defaults are overridden by the platform / firmware */
1699         struct isci_host *ihost = scic_to_ihost(scic);
1700         u16 index;
1701
1702         /* Default to APC mode. */
1703         scic->oem_parameters.sds1.controller.mode_type = SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE;
1704
1705         /* Default to APC mode. */
1706         scic->oem_parameters.sds1.controller.max_concurrent_dev_spin_up = 1;
1707
1708         /* Default to no SSC operation. */
1709         scic->oem_parameters.sds1.controller.do_enable_ssc = false;
1710
1711         /* Initialize all of the port parameter information to narrow ports. */
1712         for (index = 0; index < SCI_MAX_PORTS; index++) {
1713                 scic->oem_parameters.sds1.ports[index].phy_mask = 0;
1714         }
1715
1716         /* Initialize all of the phy parameter information. */
1717         for (index = 0; index < SCI_MAX_PHYS; index++) {
1718                 /* Default to 6G (i.e. Gen 3) for now. */
1719                 scic->user_parameters.sds1.phys[index].max_speed_generation = 3;
1720
1721                 /* the frequencies cannot be 0 */
1722                 scic->user_parameters.sds1.phys[index].align_insertion_frequency = 0x7f;
1723                 scic->user_parameters.sds1.phys[index].in_connection_align_insertion_frequency = 0xff;
1724                 scic->user_parameters.sds1.phys[index].notify_enable_spin_up_insertion_frequency = 0x33;
1725
1726                 /*
1727                  * Previous Vitesse based expanders had a arbitration issue that
1728                  * is worked around by having the upper 32-bits of SAS address
1729                  * with a value greater then the Vitesse company identifier.
1730                  * Hence, usage of 0x5FCFFFFF. */
1731                 scic->oem_parameters.sds1.phys[index].sas_address.low = 0x1 + ihost->id;
1732                 scic->oem_parameters.sds1.phys[index].sas_address.high = 0x5FCFFFFF;
1733         }
1734
1735         scic->user_parameters.sds1.stp_inactivity_timeout = 5;
1736         scic->user_parameters.sds1.ssp_inactivity_timeout = 5;
1737         scic->user_parameters.sds1.stp_max_occupancy_timeout = 5;
1738         scic->user_parameters.sds1.ssp_max_occupancy_timeout = 20;
1739         scic->user_parameters.sds1.no_outbound_task_timeout = 20;
1740 }
1741
1742
1743
1744 /**
1745  * scic_controller_construct() - This method will attempt to construct a
1746  *    controller object utilizing the supplied parameter information.
1747  * @c: This parameter specifies the controller to be constructed.
1748  * @scu_base: mapped base address of the scu registers
1749  * @smu_base: mapped base address of the smu registers
1750  *
1751  * Indicate if the controller was successfully constructed or if it failed in
1752  * some way. SCI_SUCCESS This value is returned if the controller was
1753  * successfully constructed. SCI_WARNING_TIMER_CONFLICT This value is returned
1754  * if the interrupt coalescence timer may cause SAS compliance issues for SMP
1755  * Target mode response processing. SCI_FAILURE_UNSUPPORTED_CONTROLLER_TYPE
1756  * This value is returned if the controller does not support the supplied type.
1757  * SCI_FAILURE_UNSUPPORTED_INIT_DATA_VERSION This value is returned if the
1758  * controller does not support the supplied initialization data version.
1759  */
1760 static enum sci_status scic_controller_construct(struct scic_sds_controller *scic,
1761                                           void __iomem *scu_base,
1762                                           void __iomem *smu_base)
1763 {
1764         struct isci_host *ihost = scic_to_ihost(scic);
1765         u8 i;
1766
1767         sci_base_state_machine_construct(&scic->state_machine,
1768                 scic, scic_sds_controller_state_table,
1769                 SCI_BASE_CONTROLLER_STATE_INITIAL);
1770
1771         sci_base_state_machine_start(&scic->state_machine);
1772
1773         scic->scu_registers = scu_base;
1774         scic->smu_registers = smu_base;
1775
1776         scic_sds_port_configuration_agent_construct(&scic->port_agent);
1777
1778         /* Construct the ports for this controller */
1779         for (i = 0; i < SCI_MAX_PORTS; i++)
1780                 scic_sds_port_construct(&ihost->ports[i].sci, i, scic);
1781         scic_sds_port_construct(&ihost->ports[i].sci, SCIC_SDS_DUMMY_PORT, scic);
1782
1783         /* Construct the phys for this controller */
1784         for (i = 0; i < SCI_MAX_PHYS; i++) {
1785                 /* Add all the PHYs to the dummy port */
1786                 scic_sds_phy_construct(&ihost->phys[i].sci,
1787                                        &ihost->ports[SCI_MAX_PORTS].sci, i);
1788         }
1789
1790         scic->invalid_phy_mask = 0;
1791
1792         /* Set the default maximum values */
1793         scic->completion_event_entries      = SCU_EVENT_COUNT;
1794         scic->completion_queue_entries      = SCU_COMPLETION_QUEUE_COUNT;
1795         scic->remote_node_entries           = SCI_MAX_REMOTE_DEVICES;
1796         scic->logical_port_entries          = SCI_MAX_PORTS;
1797         scic->task_context_entries          = SCU_IO_REQUEST_COUNT;
1798         scic->uf_control.buffers.count      = SCU_UNSOLICITED_FRAME_COUNT;
1799         scic->uf_control.address_table.count = SCU_UNSOLICITED_FRAME_COUNT;
1800
1801         /* Initialize the User and OEM parameters to default values. */
1802         scic_sds_controller_set_default_config_parameters(scic);
1803
1804         return scic_controller_reset(scic);
1805 }
1806
1807 int scic_oem_parameters_validate(struct scic_sds_oem_params *oem)
1808 {
1809         int i;
1810
1811         for (i = 0; i < SCI_MAX_PORTS; i++)
1812                 if (oem->ports[i].phy_mask > SCIC_SDS_PARM_PHY_MASK_MAX)
1813                         return -EINVAL;
1814
1815         for (i = 0; i < SCI_MAX_PHYS; i++)
1816                 if (oem->phys[i].sas_address.high == 0 &&
1817                     oem->phys[i].sas_address.low == 0)
1818                         return -EINVAL;
1819
1820         if (oem->controller.mode_type == SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE) {
1821                 for (i = 0; i < SCI_MAX_PHYS; i++)
1822                         if (oem->ports[i].phy_mask != 0)
1823                                 return -EINVAL;
1824         } else if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
1825                 u8 phy_mask = 0;
1826
1827                 for (i = 0; i < SCI_MAX_PHYS; i++)
1828                         phy_mask |= oem->ports[i].phy_mask;
1829
1830                 if (phy_mask == 0)
1831                         return -EINVAL;
1832         } else
1833                 return -EINVAL;
1834
1835         if (oem->controller.max_concurrent_dev_spin_up > MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT)
1836                 return -EINVAL;
1837
1838         return 0;
1839 }
1840
1841 static enum sci_status scic_oem_parameters_set(struct scic_sds_controller *scic,
1842                                         union scic_oem_parameters *scic_parms)
1843 {
1844         u32 state = scic->state_machine.current_state_id;
1845
1846         if (state == SCI_BASE_CONTROLLER_STATE_RESET ||
1847             state == SCI_BASE_CONTROLLER_STATE_INITIALIZING ||
1848             state == SCI_BASE_CONTROLLER_STATE_INITIALIZED) {
1849
1850                 if (scic_oem_parameters_validate(&scic_parms->sds1))
1851                         return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1852                 scic->oem_parameters.sds1 = scic_parms->sds1;
1853
1854                 return SCI_SUCCESS;
1855         }
1856
1857         return SCI_FAILURE_INVALID_STATE;
1858 }
1859
1860 void scic_oem_parameters_get(
1861         struct scic_sds_controller *scic,
1862         union scic_oem_parameters *scic_parms)
1863 {
1864         memcpy(scic_parms, (&scic->oem_parameters), sizeof(*scic_parms));
1865 }
1866
1867 static void scic_sds_controller_timeout_handler(void *_scic)
1868 {
1869         struct scic_sds_controller *scic = _scic;
1870         struct isci_host *ihost = scic_to_ihost(scic);
1871         struct sci_base_state_machine *sm = &scic->state_machine;
1872
1873         if (sm->current_state_id == SCI_BASE_CONTROLLER_STATE_STARTING)
1874                 scic_sds_controller_transition_to_ready(scic, SCI_FAILURE_TIMEOUT);
1875         else if (sm->current_state_id == SCI_BASE_CONTROLLER_STATE_STOPPING) {
1876                 sci_base_state_machine_change_state(sm, SCI_BASE_CONTROLLER_STATE_FAILED);
1877                 isci_host_stop_complete(ihost, SCI_FAILURE_TIMEOUT);
1878         } else  /* / @todo Now what do we want to do in this case? */
1879                 dev_err(scic_to_dev(scic),
1880                         "%s: Controller timer fired when controller was not "
1881                         "in a state being timed.\n",
1882                         __func__);
1883 }
1884
1885 static enum sci_status scic_sds_controller_initialize_phy_startup(struct scic_sds_controller *scic)
1886 {
1887         struct isci_host *ihost = scic_to_ihost(scic);
1888
1889         scic->phy_startup_timer = isci_timer_create(ihost,
1890                                                     scic,
1891                                                     scic_sds_controller_phy_startup_timeout_handler);
1892
1893         if (scic->phy_startup_timer == NULL)
1894                 return SCI_FAILURE_INSUFFICIENT_RESOURCES;
1895         else {
1896                 scic->next_phy_to_start = 0;
1897                 scic->phy_startup_timer_pending = false;
1898         }
1899
1900         return SCI_SUCCESS;
1901 }
1902
1903 static void scic_sds_controller_power_control_timer_start(struct scic_sds_controller *scic)
1904 {
1905         isci_timer_start(scic->power_control.timer,
1906                          SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
1907
1908         scic->power_control.timer_started = true;
1909 }
1910
1911 static void scic_sds_controller_power_control_timer_stop(struct scic_sds_controller *scic)
1912 {
1913         if (scic->power_control.timer_started) {
1914                 isci_timer_stop(scic->power_control.timer);
1915                 scic->power_control.timer_started = false;
1916         }
1917 }
1918
1919 static void scic_sds_controller_power_control_timer_restart(struct scic_sds_controller *scic)
1920 {
1921         scic_sds_controller_power_control_timer_stop(scic);
1922         scic_sds_controller_power_control_timer_start(scic);
1923 }
1924
1925 static void scic_sds_controller_power_control_timer_handler(
1926         void *controller)
1927 {
1928         struct scic_sds_controller *scic;
1929
1930         scic = (struct scic_sds_controller *)controller;
1931
1932         scic->power_control.phys_granted_power = 0;
1933
1934         if (scic->power_control.phys_waiting == 0) {
1935                 scic->power_control.timer_started = false;
1936         } else {
1937                 struct scic_sds_phy *sci_phy = NULL;
1938                 u8 i;
1939
1940                 for (i = 0;
1941                      (i < SCI_MAX_PHYS)
1942                      && (scic->power_control.phys_waiting != 0);
1943                      i++) {
1944                         if (scic->power_control.requesters[i] != NULL) {
1945                                 if (scic->power_control.phys_granted_power <
1946                                     scic->oem_parameters.sds1.controller.max_concurrent_dev_spin_up) {
1947                                         sci_phy = scic->power_control.requesters[i];
1948                                         scic->power_control.requesters[i] = NULL;
1949                                         scic->power_control.phys_waiting--;
1950                                         scic->power_control.phys_granted_power++;
1951                                         scic_sds_phy_consume_power_handler(sci_phy);
1952                                 } else {
1953                                         break;
1954                                 }
1955                         }
1956                 }
1957
1958                 /*
1959                  * It doesn't matter if the power list is empty, we need to start the
1960                  * timer in case another phy becomes ready.
1961                  */
1962                 scic_sds_controller_power_control_timer_start(scic);
1963         }
1964 }
1965
1966 /**
1967  * This method inserts the phy in the stagger spinup control queue.
1968  * @scic:
1969  *
1970  *
1971  */
1972 void scic_sds_controller_power_control_queue_insert(
1973         struct scic_sds_controller *scic,
1974         struct scic_sds_phy *sci_phy)
1975 {
1976         BUG_ON(sci_phy == NULL);
1977
1978         if (scic->power_control.phys_granted_power <
1979             scic->oem_parameters.sds1.controller.max_concurrent_dev_spin_up) {
1980                 scic->power_control.phys_granted_power++;
1981                 scic_sds_phy_consume_power_handler(sci_phy);
1982
1983                 /*
1984                  * stop and start the power_control timer. When the timer fires, the
1985                  * no_of_phys_granted_power will be set to 0
1986                  */
1987                 scic_sds_controller_power_control_timer_restart(scic);
1988         } else {
1989                 /* Add the phy in the waiting list */
1990                 scic->power_control.requesters[sci_phy->phy_index] = sci_phy;
1991                 scic->power_control.phys_waiting++;
1992         }
1993 }
1994
1995 /**
1996  * This method removes the phy from the stagger spinup control queue.
1997  * @scic:
1998  *
1999  *
2000  */
2001 void scic_sds_controller_power_control_queue_remove(
2002         struct scic_sds_controller *scic,
2003         struct scic_sds_phy *sci_phy)
2004 {
2005         BUG_ON(sci_phy == NULL);
2006
2007         if (scic->power_control.requesters[sci_phy->phy_index] != NULL) {
2008                 scic->power_control.phys_waiting--;
2009         }
2010
2011         scic->power_control.requesters[sci_phy->phy_index] = NULL;
2012 }
2013
2014 #define AFE_REGISTER_WRITE_DELAY 10
2015
2016 /* Initialize the AFE for this phy index. We need to read the AFE setup from
2017  * the OEM parameters
2018  */
2019 static void scic_sds_controller_afe_initialization(struct scic_sds_controller *scic)
2020 {
2021         const struct scic_sds_oem_params *oem = &scic->oem_parameters.sds1;
2022         u32 afe_status;
2023         u32 phy_id;
2024
2025         /* Clear DFX Status registers */
2026         writel(0x0081000f, &scic->scu_registers->afe.afe_dfx_master_control0);
2027         udelay(AFE_REGISTER_WRITE_DELAY);
2028
2029         if (is_b0()) {
2030                 /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement
2031                  * Timer, PM Stagger Timer */
2032                 writel(0x0007BFFF, &scic->scu_registers->afe.afe_pmsn_master_control2);
2033                 udelay(AFE_REGISTER_WRITE_DELAY);
2034         }
2035
2036         /* Configure bias currents to normal */
2037         if (is_a0())
2038                 writel(0x00005500, &scic->scu_registers->afe.afe_bias_control);
2039         else if (is_a2())
2040                 writel(0x00005A00, &scic->scu_registers->afe.afe_bias_control);
2041         else if (is_b0())
2042                 writel(0x00005F00, &scic->scu_registers->afe.afe_bias_control);
2043
2044         udelay(AFE_REGISTER_WRITE_DELAY);
2045
2046         /* Enable PLL */
2047         if (is_b0())
2048                 writel(0x80040A08, &scic->scu_registers->afe.afe_pll_control0);
2049         else
2050                 writel(0x80040908, &scic->scu_registers->afe.afe_pll_control0);
2051
2052         udelay(AFE_REGISTER_WRITE_DELAY);
2053
2054         /* Wait for the PLL to lock */
2055         do {
2056                 afe_status = readl(&scic->scu_registers->afe.afe_common_block_status);
2057                 udelay(AFE_REGISTER_WRITE_DELAY);
2058         } while ((afe_status & 0x00001000) == 0);
2059
2060         if (is_a0() || is_a2()) {
2061                 /* Shorten SAS SNW lock time (RxLock timer value from 76 us to 50 us) */
2062                 writel(0x7bcc96ad, &scic->scu_registers->afe.afe_pmsn_master_control0);
2063                 udelay(AFE_REGISTER_WRITE_DELAY);
2064         }
2065
2066         for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) {
2067                 const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id];
2068
2069                 if (is_b0()) {
2070                          /* Configure transmitter SSC parameters */
2071                         writel(0x00030000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_ssc_control);
2072                         udelay(AFE_REGISTER_WRITE_DELAY);
2073                 } else {
2074                         /*
2075                          * All defaults, except the Receive Word Alignament/Comma Detect
2076                          * Enable....(0xe800) */
2077                         writel(0x00004512, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0);
2078                         udelay(AFE_REGISTER_WRITE_DELAY);
2079
2080                         writel(0x0050100F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control1);
2081                         udelay(AFE_REGISTER_WRITE_DELAY);
2082                 }
2083
2084                 /*
2085                  * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
2086                  * & increase TX int & ext bias 20%....(0xe85c) */
2087                 if (is_a0())
2088                         writel(0x000003D4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2089                 else if (is_a2())
2090                         writel(0x000003F0, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2091                 else {
2092                          /* Power down TX and RX (PWRDNTX and PWRDNRX) */
2093                         writel(0x000003d7, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2094                         udelay(AFE_REGISTER_WRITE_DELAY);
2095
2096                         /*
2097                          * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
2098                          * & increase TX int & ext bias 20%....(0xe85c) */
2099                         writel(0x000003d4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2100                 }
2101                 udelay(AFE_REGISTER_WRITE_DELAY);
2102
2103                 if (is_a0() || is_a2()) {
2104                         /* Enable TX equalization (0xe824) */
2105                         writel(0x00040000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control);
2106                         udelay(AFE_REGISTER_WRITE_DELAY);
2107                 }
2108
2109                 /*
2110                  * RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0, TPD=0x0(TX Power On),
2111                  * RDD=0x0(RX Detect Enabled) ....(0xe800) */
2112                 writel(0x00004100, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0);
2113                 udelay(AFE_REGISTER_WRITE_DELAY);
2114
2115                 /* Leave DFE/FFE on */
2116                 if (is_a0())
2117                         writel(0x3F09983F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2118                 else if (is_a2())
2119                         writel(0x3F11103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2120                 else {
2121                         writel(0x3F11103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2122                         udelay(AFE_REGISTER_WRITE_DELAY);
2123                         /* Enable TX equalization (0xe824) */
2124                         writel(0x00040000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control);
2125                 }
2126                 udelay(AFE_REGISTER_WRITE_DELAY);
2127
2128                 writel(oem_phy->afe_tx_amp_control0,
2129                         &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control0);
2130                 udelay(AFE_REGISTER_WRITE_DELAY);
2131
2132                 writel(oem_phy->afe_tx_amp_control1,
2133                         &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control1);
2134                 udelay(AFE_REGISTER_WRITE_DELAY);
2135
2136                 writel(oem_phy->afe_tx_amp_control2,
2137                         &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control2);
2138                 udelay(AFE_REGISTER_WRITE_DELAY);
2139
2140                 writel(oem_phy->afe_tx_amp_control3,
2141                         &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control3);
2142                 udelay(AFE_REGISTER_WRITE_DELAY);
2143         }
2144
2145         /* Transfer control to the PEs */
2146         writel(0x00010f00, &scic->scu_registers->afe.afe_dfx_master_control0);
2147         udelay(AFE_REGISTER_WRITE_DELAY);
2148 }
2149
2150 static enum sci_status scic_controller_set_mode(struct scic_sds_controller *scic,
2151                                                 enum sci_controller_mode operating_mode)
2152 {
2153         enum sci_status status          = SCI_SUCCESS;
2154
2155         if ((scic->state_machine.current_state_id ==
2156                                 SCI_BASE_CONTROLLER_STATE_INITIALIZING) ||
2157             (scic->state_machine.current_state_id ==
2158                                 SCI_BASE_CONTROLLER_STATE_INITIALIZED)) {
2159                 switch (operating_mode) {
2160                 case SCI_MODE_SPEED:
2161                         scic->remote_node_entries      = SCI_MAX_REMOTE_DEVICES;
2162                         scic->task_context_entries     = SCU_IO_REQUEST_COUNT;
2163                         scic->uf_control.buffers.count =
2164                                 SCU_UNSOLICITED_FRAME_COUNT;
2165                         scic->completion_event_entries = SCU_EVENT_COUNT;
2166                         scic->completion_queue_entries =
2167                                 SCU_COMPLETION_QUEUE_COUNT;
2168                         break;
2169
2170                 case SCI_MODE_SIZE:
2171                         scic->remote_node_entries      = SCI_MIN_REMOTE_DEVICES;
2172                         scic->task_context_entries     = SCI_MIN_IO_REQUESTS;
2173                         scic->uf_control.buffers.count =
2174                                 SCU_MIN_UNSOLICITED_FRAMES;
2175                         scic->completion_event_entries = SCU_MIN_EVENTS;
2176                         scic->completion_queue_entries =
2177                                 SCU_MIN_COMPLETION_QUEUE_ENTRIES;
2178                         break;
2179
2180                 default:
2181                         status = SCI_FAILURE_INVALID_PARAMETER_VALUE;
2182                         break;
2183                 }
2184         } else
2185                 status = SCI_FAILURE_INVALID_STATE;
2186
2187         return status;
2188 }
2189
2190 static void scic_sds_controller_initialize_power_control(struct scic_sds_controller *scic)
2191 {
2192         struct isci_host *ihost = scic_to_ihost(scic);
2193         scic->power_control.timer = isci_timer_create(ihost,
2194                                                       scic,
2195                                         scic_sds_controller_power_control_timer_handler);
2196
2197         memset(scic->power_control.requesters, 0,
2198                sizeof(scic->power_control.requesters));
2199
2200         scic->power_control.phys_waiting = 0;
2201         scic->power_control.phys_granted_power = 0;
2202 }
2203
2204 static enum sci_status scic_controller_initialize(struct scic_sds_controller *scic)
2205 {
2206         struct sci_base_state_machine *sm = &scic->state_machine;
2207         enum sci_status result = SCI_SUCCESS;
2208         struct isci_host *ihost = scic_to_ihost(scic);
2209         u32 index, state;
2210
2211         if (scic->state_machine.current_state_id !=
2212             SCI_BASE_CONTROLLER_STATE_RESET) {
2213                 dev_warn(scic_to_dev(scic),
2214                          "SCIC Controller initialize operation requested "
2215                          "in invalid state\n");
2216                 return SCI_FAILURE_INVALID_STATE;
2217         }
2218
2219         sci_base_state_machine_change_state(sm, SCI_BASE_CONTROLLER_STATE_INITIALIZING);
2220
2221         scic->timeout_timer = isci_timer_create(ihost, scic,
2222                                                 scic_sds_controller_timeout_handler);
2223
2224         scic_sds_controller_initialize_phy_startup(scic);
2225
2226         scic_sds_controller_initialize_power_control(scic);
2227
2228         /*
2229          * There is nothing to do here for B0 since we do not have to
2230          * program the AFE registers.
2231          * / @todo The AFE settings are supposed to be correct for the B0 but
2232          * /       presently they seem to be wrong. */
2233         scic_sds_controller_afe_initialization(scic);
2234
2235         if (result == SCI_SUCCESS) {
2236                 u32 status;
2237                 u32 terminate_loop;
2238
2239                 /* Take the hardware out of reset */
2240                 writel(0, &scic->smu_registers->soft_reset_control);
2241
2242                 /*
2243                  * / @todo Provide meaningfull error code for hardware failure
2244                  * result = SCI_FAILURE_CONTROLLER_HARDWARE; */
2245                 result = SCI_FAILURE;
2246                 terminate_loop = 100;
2247
2248                 while (terminate_loop-- && (result != SCI_SUCCESS)) {
2249                         /* Loop until the hardware reports success */
2250                         udelay(SCU_CONTEXT_RAM_INIT_STALL_TIME);
2251                         status = readl(&scic->smu_registers->control_status);
2252
2253                         if ((status & SCU_RAM_INIT_COMPLETED) ==
2254                                         SCU_RAM_INIT_COMPLETED)
2255                                 result = SCI_SUCCESS;
2256                 }
2257         }
2258
2259         if (result == SCI_SUCCESS) {
2260                 u32 max_supported_ports;
2261                 u32 max_supported_devices;
2262                 u32 max_supported_io_requests;
2263                 u32 device_context_capacity;
2264
2265                 /*
2266                  * Determine what are the actaul device capacities that the
2267                  * hardware will support */
2268                 device_context_capacity =
2269                         readl(&scic->smu_registers->device_context_capacity);
2270
2271
2272                 max_supported_ports = smu_dcc_get_max_ports(device_context_capacity);
2273                 max_supported_devices = smu_dcc_get_max_remote_node_context(device_context_capacity);
2274                 max_supported_io_requests = smu_dcc_get_max_task_context(device_context_capacity);
2275
2276                 /*
2277                  * Make all PEs that are unassigned match up with the
2278                  * logical ports
2279                  */
2280                 for (index = 0; index < max_supported_ports; index++) {
2281                         struct scu_port_task_scheduler_group_registers __iomem
2282                                 *ptsg = &scic->scu_registers->peg0.ptsg;
2283
2284                         writel(index, &ptsg->protocol_engine[index]);
2285                 }
2286
2287                 /* Record the smaller of the two capacity values */
2288                 scic->logical_port_entries =
2289                         min(max_supported_ports, scic->logical_port_entries);
2290
2291                 scic->task_context_entries =
2292                         min(max_supported_io_requests,
2293                             scic->task_context_entries);
2294
2295                 scic->remote_node_entries =
2296                         min(max_supported_devices, scic->remote_node_entries);
2297
2298                 /*
2299                  * Now that we have the correct hardware reported minimum values
2300                  * build the MDL for the controller.  Default to a performance
2301                  * configuration.
2302                  */
2303                 scic_controller_set_mode(scic, SCI_MODE_SPEED);
2304         }
2305
2306         /* Initialize hardware PCI Relaxed ordering in DMA engines */
2307         if (result == SCI_SUCCESS) {
2308                 u32 dma_configuration;
2309
2310                 /* Configure the payload DMA */
2311                 dma_configuration =
2312                         readl(&scic->scu_registers->sdma.pdma_configuration);
2313                 dma_configuration |=
2314                         SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
2315                 writel(dma_configuration,
2316                         &scic->scu_registers->sdma.pdma_configuration);
2317
2318                 /* Configure the control DMA */
2319                 dma_configuration =
2320                         readl(&scic->scu_registers->sdma.cdma_configuration);
2321                 dma_configuration |=
2322                         SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
2323                 writel(dma_configuration,
2324                         &scic->scu_registers->sdma.cdma_configuration);
2325         }
2326
2327         /*
2328          * Initialize the PHYs before the PORTs because the PHY registers
2329          * are accessed during the port initialization.
2330          */
2331         if (result == SCI_SUCCESS) {
2332                 /* Initialize the phys */
2333                 for (index = 0;
2334                      (result == SCI_SUCCESS) && (index < SCI_MAX_PHYS);
2335                      index++) {
2336                         result = scic_sds_phy_initialize(
2337                                 &ihost->phys[index].sci,
2338                                 &scic->scu_registers->peg0.pe[index].tl,
2339                                 &scic->scu_registers->peg0.pe[index].ll);
2340                 }
2341         }
2342
2343         if (result == SCI_SUCCESS) {
2344                 /* Initialize the logical ports */
2345                 for (index = 0;
2346                      (index < scic->logical_port_entries) &&
2347                      (result == SCI_SUCCESS);
2348                      index++) {
2349                         result = scic_sds_port_initialize(
2350                                 &ihost->ports[index].sci,
2351                                 &scic->scu_registers->peg0.ptsg.port[index],
2352                                 &scic->scu_registers->peg0.ptsg.protocol_engine,
2353                                 &scic->scu_registers->peg0.viit[index]);
2354                 }
2355         }
2356
2357         if (result == SCI_SUCCESS)
2358                 result = scic_sds_port_configuration_agent_initialize(
2359                                 scic,
2360                                 &scic->port_agent);
2361
2362         /* Advance the controller state machine */
2363         if (result == SCI_SUCCESS)
2364                 state = SCI_BASE_CONTROLLER_STATE_INITIALIZED;
2365         else
2366                 state = SCI_BASE_CONTROLLER_STATE_FAILED;
2367         sci_base_state_machine_change_state(sm, state);
2368
2369         return result;
2370 }
2371
2372 static enum sci_status scic_user_parameters_set(
2373         struct scic_sds_controller *scic,
2374         union scic_user_parameters *scic_parms)
2375 {
2376         u32 state = scic->state_machine.current_state_id;
2377
2378         if (state == SCI_BASE_CONTROLLER_STATE_RESET ||
2379             state == SCI_BASE_CONTROLLER_STATE_INITIALIZING ||
2380             state == SCI_BASE_CONTROLLER_STATE_INITIALIZED) {
2381                 u16 index;
2382
2383                 /*
2384                  * Validate the user parameters.  If they are not legal, then
2385                  * return a failure.
2386                  */
2387                 for (index = 0; index < SCI_MAX_PHYS; index++) {
2388                         struct sci_phy_user_params *user_phy;
2389
2390                         user_phy = &scic_parms->sds1.phys[index];
2391
2392                         if (!((user_phy->max_speed_generation <=
2393                                                 SCIC_SDS_PARM_MAX_SPEED) &&
2394                               (user_phy->max_speed_generation >
2395                                                 SCIC_SDS_PARM_NO_SPEED)))
2396                                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2397
2398                         if (user_phy->in_connection_align_insertion_frequency <
2399                                         3)
2400                                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2401
2402                         if ((user_phy->in_connection_align_insertion_frequency <
2403                                                 3) ||
2404                             (user_phy->align_insertion_frequency == 0) ||
2405                             (user_phy->
2406                                 notify_enable_spin_up_insertion_frequency ==
2407                                                 0))
2408                                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2409                 }
2410
2411                 if ((scic_parms->sds1.stp_inactivity_timeout == 0) ||
2412                     (scic_parms->sds1.ssp_inactivity_timeout == 0) ||
2413                     (scic_parms->sds1.stp_max_occupancy_timeout == 0) ||
2414                     (scic_parms->sds1.ssp_max_occupancy_timeout == 0) ||
2415                     (scic_parms->sds1.no_outbound_task_timeout == 0))
2416                         return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2417
2418                 memcpy(&scic->user_parameters, scic_parms, sizeof(*scic_parms));
2419
2420                 return SCI_SUCCESS;
2421         }
2422
2423         return SCI_FAILURE_INVALID_STATE;
2424 }
2425
2426 static int scic_controller_mem_init(struct scic_sds_controller *scic)
2427 {
2428         struct device *dev = scic_to_dev(scic);
2429         dma_addr_t dma_handle;
2430         enum sci_status result;
2431
2432         scic->completion_queue = dmam_alloc_coherent(dev,
2433                         scic->completion_queue_entries * sizeof(u32),
2434                         &dma_handle, GFP_KERNEL);
2435         if (!scic->completion_queue)
2436                 return -ENOMEM;
2437
2438         writel(lower_32_bits(dma_handle),
2439                 &scic->smu_registers->completion_queue_lower);
2440         writel(upper_32_bits(dma_handle),
2441                 &scic->smu_registers->completion_queue_upper);
2442
2443         scic->remote_node_context_table = dmam_alloc_coherent(dev,
2444                         scic->remote_node_entries *
2445                                 sizeof(union scu_remote_node_context),
2446                         &dma_handle, GFP_KERNEL);
2447         if (!scic->remote_node_context_table)
2448                 return -ENOMEM;
2449
2450         writel(lower_32_bits(dma_handle),
2451                 &scic->smu_registers->remote_node_context_lower);
2452         writel(upper_32_bits(dma_handle),
2453                 &scic->smu_registers->remote_node_context_upper);
2454
2455         scic->task_context_table = dmam_alloc_coherent(dev,
2456                         scic->task_context_entries *
2457                                 sizeof(struct scu_task_context),
2458                         &dma_handle, GFP_KERNEL);
2459         if (!scic->task_context_table)
2460                 return -ENOMEM;
2461
2462         writel(lower_32_bits(dma_handle),
2463                 &scic->smu_registers->host_task_table_lower);
2464         writel(upper_32_bits(dma_handle),
2465                 &scic->smu_registers->host_task_table_upper);
2466
2467         result = scic_sds_unsolicited_frame_control_construct(scic);
2468         if (result)
2469                 return result;
2470
2471         /*
2472          * Inform the silicon as to the location of the UF headers and
2473          * address table.
2474          */
2475         writel(lower_32_bits(scic->uf_control.headers.physical_address),
2476                 &scic->scu_registers->sdma.uf_header_base_address_lower);
2477         writel(upper_32_bits(scic->uf_control.headers.physical_address),
2478                 &scic->scu_registers->sdma.uf_header_base_address_upper);
2479
2480         writel(lower_32_bits(scic->uf_control.address_table.physical_address),
2481                 &scic->scu_registers->sdma.uf_address_table_lower);
2482         writel(upper_32_bits(scic->uf_control.address_table.physical_address),
2483                 &scic->scu_registers->sdma.uf_address_table_upper);
2484
2485         return 0;
2486 }
2487
2488 int isci_host_init(struct isci_host *isci_host)
2489 {
2490         int err = 0, i;
2491         enum sci_status status;
2492         union scic_oem_parameters oem;
2493         union scic_user_parameters scic_user_params;
2494         struct isci_pci_info *pci_info = to_pci_info(isci_host->pdev);
2495
2496         isci_timer_list_construct(isci_host);
2497
2498         spin_lock_init(&isci_host->state_lock);
2499         spin_lock_init(&isci_host->scic_lock);
2500         spin_lock_init(&isci_host->queue_lock);
2501         init_waitqueue_head(&isci_host->eventq);
2502
2503         isci_host_change_state(isci_host, isci_starting);
2504         isci_host->can_queue = ISCI_CAN_QUEUE_VAL;
2505
2506         status = scic_controller_construct(&isci_host->sci, scu_base(isci_host),
2507                                            smu_base(isci_host));
2508
2509         if (status != SCI_SUCCESS) {
2510                 dev_err(&isci_host->pdev->dev,
2511                         "%s: scic_controller_construct failed - status = %x\n",
2512                         __func__,
2513                         status);
2514                 return -ENODEV;
2515         }
2516
2517         isci_host->sas_ha.dev = &isci_host->pdev->dev;
2518         isci_host->sas_ha.lldd_ha = isci_host;
2519
2520         /*
2521          * grab initial values stored in the controller object for OEM and USER
2522          * parameters
2523          */
2524         isci_user_parameters_get(isci_host, &scic_user_params);
2525         status = scic_user_parameters_set(&isci_host->sci,
2526                                           &scic_user_params);
2527         if (status != SCI_SUCCESS) {
2528                 dev_warn(&isci_host->pdev->dev,
2529                          "%s: scic_user_parameters_set failed\n",
2530                          __func__);
2531                 return -ENODEV;
2532         }
2533
2534         scic_oem_parameters_get(&isci_host->sci, &oem);
2535
2536         /* grab any OEM parameters specified in orom */
2537         if (pci_info->orom) {
2538                 status = isci_parse_oem_parameters(&oem,
2539                                                    pci_info->orom,
2540                                                    isci_host->id);
2541                 if (status != SCI_SUCCESS) {
2542                         dev_warn(&isci_host->pdev->dev,
2543                                  "parsing firmware oem parameters failed\n");
2544                         return -EINVAL;
2545                 }
2546         }
2547
2548         status = scic_oem_parameters_set(&isci_host->sci, &oem);
2549         if (status != SCI_SUCCESS) {
2550                 dev_warn(&isci_host->pdev->dev,
2551                                 "%s: scic_oem_parameters_set failed\n",
2552                                 __func__);
2553                 return -ENODEV;
2554         }
2555
2556         tasklet_init(&isci_host->completion_tasklet,
2557                      isci_host_completion_routine, (unsigned long)isci_host);
2558
2559         INIT_LIST_HEAD(&isci_host->requests_to_complete);
2560         INIT_LIST_HEAD(&isci_host->requests_to_errorback);
2561
2562         spin_lock_irq(&isci_host->scic_lock);
2563         status = scic_controller_initialize(&isci_host->sci);
2564         spin_unlock_irq(&isci_host->scic_lock);
2565         if (status != SCI_SUCCESS) {
2566                 dev_warn(&isci_host->pdev->dev,
2567                          "%s: scic_controller_initialize failed -"
2568                          " status = 0x%x\n",
2569                          __func__, status);
2570                 return -ENODEV;
2571         }
2572
2573         err = scic_controller_mem_init(&isci_host->sci);
2574         if (err)
2575                 return err;
2576
2577         isci_host->dma_pool = dmam_pool_create(DRV_NAME, &isci_host->pdev->dev,
2578                                                sizeof(struct isci_request),
2579                                                SLAB_HWCACHE_ALIGN, 0);
2580
2581         if (!isci_host->dma_pool)
2582                 return -ENOMEM;
2583
2584         for (i = 0; i < SCI_MAX_PORTS; i++)
2585                 isci_port_init(&isci_host->ports[i], isci_host, i);
2586
2587         for (i = 0; i < SCI_MAX_PHYS; i++)
2588                 isci_phy_init(&isci_host->phys[i], isci_host, i);
2589
2590         for (i = 0; i < SCI_MAX_REMOTE_DEVICES; i++) {
2591                 struct isci_remote_device *idev = &isci_host->devices[i];
2592
2593                 INIT_LIST_HEAD(&idev->reqs_in_process);
2594                 INIT_LIST_HEAD(&idev->node);
2595                 spin_lock_init(&idev->state_lock);
2596         }
2597
2598         return 0;
2599 }
2600
2601 void scic_sds_controller_link_up(struct scic_sds_controller *scic,
2602                 struct scic_sds_port *port, struct scic_sds_phy *phy)
2603 {
2604         switch (scic->state_machine.current_state_id) {
2605         case SCI_BASE_CONTROLLER_STATE_STARTING:
2606                 scic_sds_controller_phy_timer_stop(scic);
2607                 scic->port_agent.link_up_handler(scic, &scic->port_agent,
2608                                                  port, phy);
2609                 scic_sds_controller_start_next_phy(scic);
2610                 break;
2611         case SCI_BASE_CONTROLLER_STATE_READY:
2612                 scic->port_agent.link_up_handler(scic, &scic->port_agent,
2613                                                  port, phy);
2614                 break;
2615         default:
2616                 dev_dbg(scic_to_dev(scic),
2617                         "%s: SCIC Controller linkup event from phy %d in "
2618                         "unexpected state %d\n", __func__, phy->phy_index,
2619                         scic->state_machine.current_state_id);
2620         }
2621 }
2622
2623 void scic_sds_controller_link_down(struct scic_sds_controller *scic,
2624                 struct scic_sds_port *port, struct scic_sds_phy *phy)
2625 {
2626         switch (scic->state_machine.current_state_id) {
2627         case SCI_BASE_CONTROLLER_STATE_STARTING:
2628         case SCI_BASE_CONTROLLER_STATE_READY:
2629                 scic->port_agent.link_down_handler(scic, &scic->port_agent,
2630                                                    port, phy);
2631                 break;
2632         default:
2633                 dev_dbg(scic_to_dev(scic),
2634                         "%s: SCIC Controller linkdown event from phy %d in "
2635                         "unexpected state %d\n",
2636                         __func__,
2637                         phy->phy_index,
2638                         scic->state_machine.current_state_id);
2639         }
2640 }
2641
2642 /**
2643  * This is a helper method to determine if any remote devices on this
2644  * controller are still in the stopping state.
2645  *
2646  */
2647 static bool scic_sds_controller_has_remote_devices_stopping(
2648         struct scic_sds_controller *controller)
2649 {
2650         u32 index;
2651
2652         for (index = 0; index < controller->remote_node_entries; index++) {
2653                 if ((controller->device_table[index] != NULL) &&
2654                    (controller->device_table[index]->state_machine.current_state_id
2655                     == SCI_BASE_REMOTE_DEVICE_STATE_STOPPING))
2656                         return true;
2657         }
2658
2659         return false;
2660 }
2661
2662 /**
2663  * This method is called by the remote device to inform the controller
2664  * object that the remote device has stopped.
2665  */
2666 void scic_sds_controller_remote_device_stopped(struct scic_sds_controller *scic,
2667                                                struct scic_sds_remote_device *sci_dev)
2668 {
2669         if (scic->state_machine.current_state_id !=
2670             SCI_BASE_CONTROLLER_STATE_STOPPING) {
2671                 dev_dbg(scic_to_dev(scic),
2672                         "SCIC Controller 0x%p remote device stopped event "
2673                         "from device 0x%p in unexpected state %d\n",
2674                         scic, sci_dev,
2675                         scic->state_machine.current_state_id);
2676                 return;
2677         }
2678
2679         if (!scic_sds_controller_has_remote_devices_stopping(scic)) {
2680                 sci_base_state_machine_change_state(&scic->state_machine,
2681                                 SCI_BASE_CONTROLLER_STATE_STOPPED);
2682         }
2683 }
2684
2685 /**
2686  * This method will write to the SCU PCP register the request value. The method
2687  *    is used to suspend/resume ports, devices, and phys.
2688  * @scic:
2689  *
2690  *
2691  */
2692 void scic_sds_controller_post_request(
2693         struct scic_sds_controller *scic,
2694         u32 request)
2695 {
2696         dev_dbg(scic_to_dev(scic),
2697                 "%s: SCIC Controller 0x%p post request 0x%08x\n",
2698                 __func__,
2699                 scic,
2700                 request);
2701
2702         writel(request, &scic->smu_registers->post_context_port);
2703 }
2704
2705 /**
2706  * This method will copy the soft copy of the task context into the physical
2707  *    memory accessible by the controller.
2708  * @scic: This parameter specifies the controller for which to copy
2709  *    the task context.
2710  * @sci_req: This parameter specifies the request for which the task
2711  *    context is being copied.
2712  *
2713  * After this call is made the SCIC_SDS_IO_REQUEST object will always point to
2714  * the physical memory version of the task context. Thus, all subsequent
2715  * updates to the task context are performed in the TC table (i.e. DMAable
2716  * memory). none
2717  */
2718 void scic_sds_controller_copy_task_context(
2719         struct scic_sds_controller *scic,
2720         struct scic_sds_request *sci_req)
2721 {
2722         struct scu_task_context *task_context_buffer;
2723
2724         task_context_buffer = scic_sds_controller_get_task_context_buffer(
2725                 scic, sci_req->io_tag);
2726
2727         memcpy(task_context_buffer,
2728                sci_req->task_context_buffer,
2729                offsetof(struct scu_task_context, sgl_snapshot_ac));
2730
2731         /*
2732          * Now that the soft copy of the TC has been copied into the TC
2733          * table accessible by the silicon.  Thus, any further changes to
2734          * the TC (e.g. TC termination) occur in the appropriate location. */
2735         sci_req->task_context_buffer = task_context_buffer;
2736 }
2737
2738 /**
2739  * This method returns the task context buffer for the given io tag.
2740  * @scic:
2741  * @io_tag:
2742  *
2743  * struct scu_task_context*
2744  */
2745 struct scu_task_context *scic_sds_controller_get_task_context_buffer(
2746         struct scic_sds_controller *scic,
2747         u16 io_tag
2748         ) {
2749         u16 task_index = scic_sds_io_tag_get_index(io_tag);
2750
2751         if (task_index < scic->task_context_entries) {
2752                 return &scic->task_context_table[task_index];
2753         }
2754
2755         return NULL;
2756 }
2757
2758 struct scic_sds_request *scic_request_by_tag(struct scic_sds_controller *scic,
2759                                              u16 io_tag)
2760 {
2761         u16 task_index;
2762         u16 task_sequence;
2763
2764         task_index = scic_sds_io_tag_get_index(io_tag);
2765
2766         if (task_index  < scic->task_context_entries) {
2767                 if (scic->io_request_table[task_index] != NULL) {
2768                         task_sequence = scic_sds_io_tag_get_sequence(io_tag);
2769
2770                         if (task_sequence == scic->io_request_sequence[task_index]) {
2771                                 return scic->io_request_table[task_index];
2772                         }
2773                 }
2774         }
2775
2776         return NULL;
2777 }
2778
2779 /**
2780  * This method allocates remote node index and the reserves the remote node
2781  *    context space for use. This method can fail if there are no more remote
2782  *    node index available.
2783  * @scic: This is the controller object which contains the set of
2784  *    free remote node ids
2785  * @sci_dev: This is the device object which is requesting the a remote node
2786  *    id
2787  * @node_id: This is the remote node id that is assinged to the device if one
2788  *    is available
2789  *
2790  * enum sci_status SCI_FAILURE_OUT_OF_RESOURCES if there are no available remote
2791  * node index available.
2792  */
2793 enum sci_status scic_sds_controller_allocate_remote_node_context(
2794         struct scic_sds_controller *scic,
2795         struct scic_sds_remote_device *sci_dev,
2796         u16 *node_id)
2797 {
2798         u16 node_index;
2799         u32 remote_node_count = scic_sds_remote_device_node_count(sci_dev);
2800
2801         node_index = scic_sds_remote_node_table_allocate_remote_node(
2802                 &scic->available_remote_nodes, remote_node_count
2803                 );
2804
2805         if (node_index != SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
2806                 scic->device_table[node_index] = sci_dev;
2807
2808                 *node_id = node_index;
2809
2810                 return SCI_SUCCESS;
2811         }
2812
2813         return SCI_FAILURE_INSUFFICIENT_RESOURCES;
2814 }
2815
2816 /**
2817  * This method frees the remote node index back to the available pool.  Once
2818  *    this is done the remote node context buffer is no longer valid and can
2819  *    not be used.
2820  * @scic:
2821  * @sci_dev:
2822  * @node_id:
2823  *
2824  */
2825 void scic_sds_controller_free_remote_node_context(
2826         struct scic_sds_controller *scic,
2827         struct scic_sds_remote_device *sci_dev,
2828         u16 node_id)
2829 {
2830         u32 remote_node_count = scic_sds_remote_device_node_count(sci_dev);
2831
2832         if (scic->device_table[node_id] == sci_dev) {
2833                 scic->device_table[node_id] = NULL;
2834
2835                 scic_sds_remote_node_table_release_remote_node_index(
2836                         &scic->available_remote_nodes, remote_node_count, node_id
2837                         );
2838         }
2839 }
2840
2841 /**
2842  * This method returns the union scu_remote_node_context for the specified remote
2843  *    node id.
2844  * @scic:
2845  * @node_id:
2846  *
2847  * union scu_remote_node_context*
2848  */
2849 union scu_remote_node_context *scic_sds_controller_get_remote_node_context_buffer(
2850         struct scic_sds_controller *scic,
2851         u16 node_id
2852         ) {
2853         if (
2854                 (node_id < scic->remote_node_entries)
2855                 && (scic->device_table[node_id] != NULL)
2856                 ) {
2857                 return &scic->remote_node_context_table[node_id];
2858         }
2859
2860         return NULL;
2861 }
2862
2863 /**
2864  *
2865  * @resposne_buffer: This is the buffer into which the D2H register FIS will be
2866  *    constructed.
2867  * @frame_header: This is the frame header returned by the hardware.
2868  * @frame_buffer: This is the frame buffer returned by the hardware.
2869  *
2870  * This method will combind the frame header and frame buffer to create a SATA
2871  * D2H register FIS none
2872  */
2873 void scic_sds_controller_copy_sata_response(
2874         void *response_buffer,
2875         void *frame_header,
2876         void *frame_buffer)
2877 {
2878         memcpy(response_buffer, frame_header, sizeof(u32));
2879
2880         memcpy(response_buffer + sizeof(u32),
2881                frame_buffer,
2882                sizeof(struct dev_to_host_fis) - sizeof(u32));
2883 }
2884
2885 /**
2886  * This method releases the frame once this is done the frame is available for
2887  *    re-use by the hardware.  The data contained in the frame header and frame
2888  *    buffer is no longer valid. The UF queue get pointer is only updated if UF
2889  *    control indicates this is appropriate.
2890  * @scic:
2891  * @frame_index:
2892  *
2893  */
2894 void scic_sds_controller_release_frame(
2895         struct scic_sds_controller *scic,
2896         u32 frame_index)
2897 {
2898         if (scic_sds_unsolicited_frame_control_release_frame(
2899                     &scic->uf_control, frame_index) == true)
2900                 writel(scic->uf_control.get,
2901                         &scic->scu_registers->sdma.unsolicited_frame_get_pointer);
2902 }
2903
2904 /**
2905  * scic_controller_start_io() - This method is called by the SCI user to
2906  *    send/start an IO request. If the method invocation is successful, then
2907  *    the IO request has been queued to the hardware for processing.
2908  * @controller: the handle to the controller object for which to start an IO
2909  *    request.
2910  * @remote_device: the handle to the remote device object for which to start an
2911  *    IO request.
2912  * @io_request: the handle to the io request object to start.
2913  * @io_tag: This parameter specifies a previously allocated IO tag that the
2914  *    user desires to be utilized for this request. This parameter is optional.
2915  *     The user is allowed to supply SCI_CONTROLLER_INVALID_IO_TAG as the value
2916  *    for this parameter.
2917  *
2918  * - IO tags are a protected resource.  It is incumbent upon the SCI Core user
2919  * to ensure that each of the methods that may allocate or free available IO
2920  * tags are handled in a mutually exclusive manner.  This method is one of said
2921  * methods requiring proper critical code section protection (e.g. semaphore,
2922  * spin-lock, etc.). - For SATA, the user is required to manage NCQ tags.  As a
2923  * result, it is expected the user will have set the NCQ tag field in the host
2924  * to device register FIS prior to calling this method.  There is also a
2925  * requirement for the user to call scic_stp_io_set_ncq_tag() prior to invoking
2926  * the scic_controller_start_io() method. scic_controller_allocate_tag() for
2927  * more information on allocating a tag. Indicate if the controller
2928  * successfully started the IO request. SCI_SUCCESS if the IO request was
2929  * successfully started. Determine the failure situations and return values.
2930  */
2931 enum sci_status scic_controller_start_io(
2932         struct scic_sds_controller *scic,
2933         struct scic_sds_remote_device *rdev,
2934         struct scic_sds_request *req,
2935         u16 io_tag)
2936 {
2937         enum sci_status status;
2938
2939         if (scic->state_machine.current_state_id !=
2940             SCI_BASE_CONTROLLER_STATE_READY) {
2941                 dev_warn(scic_to_dev(scic), "invalid state to start I/O");
2942                 return SCI_FAILURE_INVALID_STATE;
2943         }
2944
2945         status = scic_sds_remote_device_start_io(scic, rdev, req);
2946         if (status != SCI_SUCCESS)
2947                 return status;
2948
2949         scic->io_request_table[scic_sds_io_tag_get_index(req->io_tag)] = req;
2950         scic_sds_controller_post_request(scic, scic_sds_request_get_post_context(req));
2951         return SCI_SUCCESS;
2952 }
2953
2954 /**
2955  * scic_controller_terminate_request() - This method is called by the SCI Core
2956  *    user to terminate an ongoing (i.e. started) core IO request.  This does
2957  *    not abort the IO request at the target, but rather removes the IO request
2958  *    from the host controller.
2959  * @controller: the handle to the controller object for which to terminate a
2960  *    request.
2961  * @remote_device: the handle to the remote device object for which to
2962  *    terminate a request.
2963  * @request: the handle to the io or task management request object to
2964  *    terminate.
2965  *
2966  * Indicate if the controller successfully began the terminate process for the
2967  * IO request. SCI_SUCCESS if the terminate process was successfully started
2968  * for the request. Determine the failure situations and return values.
2969  */
2970 enum sci_status scic_controller_terminate_request(
2971         struct scic_sds_controller *scic,
2972         struct scic_sds_remote_device *rdev,
2973         struct scic_sds_request *req)
2974 {
2975         enum sci_status status;
2976
2977         if (scic->state_machine.current_state_id !=
2978             SCI_BASE_CONTROLLER_STATE_READY) {
2979                 dev_warn(scic_to_dev(scic),
2980                          "invalid state to terminate request\n");
2981                 return SCI_FAILURE_INVALID_STATE;
2982         }
2983
2984         status = scic_sds_io_request_terminate(req);
2985         if (status != SCI_SUCCESS)
2986                 return status;
2987
2988         /*
2989          * Utilize the original post context command and or in the POST_TC_ABORT
2990          * request sub-type.
2991          */
2992         scic_sds_controller_post_request(scic,
2993                 scic_sds_request_get_post_context(req) |
2994                 SCU_CONTEXT_COMMAND_REQUEST_POST_TC_ABORT);
2995         return SCI_SUCCESS;
2996 }
2997
2998 /**
2999  * scic_controller_complete_io() - This method will perform core specific
3000  *    completion operations for an IO request.  After this method is invoked,
3001  *    the user should consider the IO request as invalid until it is properly
3002  *    reused (i.e. re-constructed).
3003  * @controller: The handle to the controller object for which to complete the
3004  *    IO request.
3005  * @remote_device: The handle to the remote device object for which to complete
3006  *    the IO request.
3007  * @io_request: the handle to the io request object to complete.
3008  *
3009  * - IO tags are a protected resource.  It is incumbent upon the SCI Core user
3010  * to ensure that each of the methods that may allocate or free available IO
3011  * tags are handled in a mutually exclusive manner.  This method is one of said
3012  * methods requiring proper critical code section protection (e.g. semaphore,
3013  * spin-lock, etc.). - If the IO tag for a request was allocated, by the SCI
3014  * Core user, using the scic_controller_allocate_io_tag() method, then it is
3015  * the responsibility of the caller to invoke the scic_controller_free_io_tag()
3016  * method to free the tag (i.e. this method will not free the IO tag). Indicate
3017  * if the controller successfully completed the IO request. SCI_SUCCESS if the
3018  * completion process was successful.
3019  */
3020 enum sci_status scic_controller_complete_io(
3021         struct scic_sds_controller *scic,
3022         struct scic_sds_remote_device *rdev,
3023         struct scic_sds_request *request)
3024 {
3025         enum sci_status status;
3026         u16 index;
3027
3028         switch (scic->state_machine.current_state_id) {
3029         case SCI_BASE_CONTROLLER_STATE_STOPPING:
3030                 /* XXX: Implement this function */
3031                 return SCI_FAILURE;
3032         case SCI_BASE_CONTROLLER_STATE_READY:
3033                 status = scic_sds_remote_device_complete_io(scic, rdev, request);
3034                 if (status != SCI_SUCCESS)
3035                         return status;
3036
3037                 index = scic_sds_io_tag_get_index(request->io_tag);
3038                 scic->io_request_table[index] = NULL;
3039                 return SCI_SUCCESS;
3040         default:
3041                 dev_warn(scic_to_dev(scic), "invalid state to complete I/O");
3042                 return SCI_FAILURE_INVALID_STATE;
3043         }
3044
3045 }
3046
3047 enum sci_status scic_controller_continue_io(struct scic_sds_request *sci_req)
3048 {
3049         struct scic_sds_controller *scic = sci_req->owning_controller;
3050
3051         if (scic->state_machine.current_state_id !=
3052             SCI_BASE_CONTROLLER_STATE_READY) {
3053                 dev_warn(scic_to_dev(scic), "invalid state to continue I/O");
3054                 return SCI_FAILURE_INVALID_STATE;
3055         }
3056
3057         scic->io_request_table[scic_sds_io_tag_get_index(sci_req->io_tag)] = sci_req;
3058         scic_sds_controller_post_request(scic, scic_sds_request_get_post_context(sci_req));
3059         return SCI_SUCCESS;
3060 }
3061
3062 /**
3063  * scic_controller_start_task() - This method is called by the SCIC user to
3064  *    send/start a framework task management request.
3065  * @controller: the handle to the controller object for which to start the task
3066  *    management request.
3067  * @remote_device: the handle to the remote device object for which to start
3068  *    the task management request.
3069  * @task_request: the handle to the task request object to start.
3070  * @io_tag: This parameter specifies a previously allocated IO tag that the
3071  *    user desires to be utilized for this request.  Note this not the io_tag
3072  *    of the request being managed.  It is to be utilized for the task request
3073  *    itself. This parameter is optional.  The user is allowed to supply
3074  *    SCI_CONTROLLER_INVALID_IO_TAG as the value for this parameter.
3075  *
3076  * - IO tags are a protected resource.  It is incumbent upon the SCI Core user
3077  * to ensure that each of the methods that may allocate or free available IO
3078  * tags are handled in a mutually exclusive manner.  This method is one of said
3079  * methods requiring proper critical code section protection (e.g. semaphore,
3080  * spin-lock, etc.). - The user must synchronize this task with completion
3081  * queue processing.  If they are not synchronized then it is possible for the
3082  * io requests that are being managed by the task request can complete before
3083  * starting the task request. scic_controller_allocate_tag() for more
3084  * information on allocating a tag. Indicate if the controller successfully
3085  * started the IO request. SCI_TASK_SUCCESS if the task request was
3086  * successfully started. SCI_TASK_FAILURE_REQUIRES_SCSI_ABORT This value is
3087  * returned if there is/are task(s) outstanding that require termination or
3088  * completion before this request can succeed.
3089  */
3090 enum sci_task_status scic_controller_start_task(
3091         struct scic_sds_controller *scic,
3092         struct scic_sds_remote_device *rdev,
3093         struct scic_sds_request *req,
3094         u16 task_tag)
3095 {
3096         enum sci_status status;
3097
3098         if (scic->state_machine.current_state_id !=
3099             SCI_BASE_CONTROLLER_STATE_READY) {
3100                 dev_warn(scic_to_dev(scic),
3101                          "%s: SCIC Controller starting task from invalid "
3102                          "state\n",
3103                          __func__);
3104                 return SCI_TASK_FAILURE_INVALID_STATE;
3105         }
3106
3107         status = scic_sds_remote_device_start_task(scic, rdev, req);
3108         switch (status) {
3109         case SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS:
3110                 scic->io_request_table[scic_sds_io_tag_get_index(req->io_tag)] = req;
3111
3112                 /*
3113                  * We will let framework know this task request started successfully,
3114                  * although core is still woring on starting the request (to post tc when
3115                  * RNC is resumed.)
3116                  */
3117                 return SCI_SUCCESS;
3118         case SCI_SUCCESS:
3119                 scic->io_request_table[scic_sds_io_tag_get_index(req->io_tag)] = req;
3120
3121                 scic_sds_controller_post_request(scic,
3122                         scic_sds_request_get_post_context(req));
3123                 break;
3124         default:
3125                 break;
3126         }
3127
3128         return status;
3129 }
3130
3131 /**
3132  * scic_controller_allocate_io_tag() - This method will allocate a tag from the
3133  *    pool of free IO tags. Direct allocation of IO tags by the SCI Core user
3134  *    is optional. The scic_controller_start_io() method will allocate an IO
3135  *    tag if this method is not utilized and the tag is not supplied to the IO
3136  *    construct routine.  Direct allocation of IO tags may provide additional
3137  *    performance improvements in environments capable of supporting this usage
3138  *    model.  Additionally, direct allocation of IO tags also provides
3139  *    additional flexibility to the SCI Core user.  Specifically, the user may
3140  *    retain IO tags across the lives of multiple IO requests.
3141  * @controller: the handle to the controller object for which to allocate the
3142  *    tag.
3143  *
3144  * IO tags are a protected resource.  It is incumbent upon the SCI Core user to
3145  * ensure that each of the methods that may allocate or free available IO tags
3146  * are handled in a mutually exclusive manner.  This method is one of said
3147  * methods requiring proper critical code section protection (e.g. semaphore,
3148  * spin-lock, etc.). An unsigned integer representing an available IO tag.
3149  * SCI_CONTROLLER_INVALID_IO_TAG This value is returned if there are no
3150  * currently available tags to be allocated. All return other values indicate a
3151  * legitimate tag.
3152  */
3153 u16 scic_controller_allocate_io_tag(
3154         struct scic_sds_controller *scic)
3155 {
3156         u16 task_context;
3157         u16 sequence_count;
3158
3159         if (!sci_pool_empty(scic->tci_pool)) {
3160                 sci_pool_get(scic->tci_pool, task_context);
3161
3162                 sequence_count = scic->io_request_sequence[task_context];
3163
3164                 return scic_sds_io_tag_construct(sequence_count, task_context);
3165         }
3166
3167         return SCI_CONTROLLER_INVALID_IO_TAG;
3168 }
3169
3170 /**
3171  * scic_controller_free_io_tag() - This method will free an IO tag to the pool
3172  *    of free IO tags. This method provides the SCI Core user more flexibility
3173  *    with regards to IO tags.  The user may desire to keep an IO tag after an
3174  *    IO request has completed, because they plan on re-using the tag for a
3175  *    subsequent IO request.  This method is only legal if the tag was
3176  *    allocated via scic_controller_allocate_io_tag().
3177  * @controller: This parameter specifies the handle to the controller object
3178  *    for which to free/return the tag.
3179  * @io_tag: This parameter represents the tag to be freed to the pool of
3180  *    available tags.
3181  *
3182  * - IO tags are a protected resource.  It is incumbent upon the SCI Core user
3183  * to ensure that each of the methods that may allocate or free available IO
3184  * tags are handled in a mutually exclusive manner.  This method is one of said
3185  * methods requiring proper critical code section protection (e.g. semaphore,
3186  * spin-lock, etc.). - If the IO tag for a request was allocated, by the SCI
3187  * Core user, using the scic_controller_allocate_io_tag() method, then it is
3188  * the responsibility of the caller to invoke this method to free the tag. This
3189  * method returns an indication of whether the tag was successfully put back
3190  * (freed) to the pool of available tags. SCI_SUCCESS This return value
3191  * indicates the tag was successfully placed into the pool of available IO
3192  * tags. SCI_FAILURE_INVALID_IO_TAG This value is returned if the supplied tag
3193  * is not a valid IO tag value.
3194  */
3195 enum sci_status scic_controller_free_io_tag(
3196         struct scic_sds_controller *scic,
3197         u16 io_tag)
3198 {
3199         u16 sequence;
3200         u16 index;
3201
3202         BUG_ON(io_tag == SCI_CONTROLLER_INVALID_IO_TAG);
3203
3204         sequence = scic_sds_io_tag_get_sequence(io_tag);
3205         index    = scic_sds_io_tag_get_index(io_tag);
3206
3207         if (!sci_pool_full(scic->tci_pool)) {
3208                 if (sequence == scic->io_request_sequence[index]) {
3209                         scic_sds_io_sequence_increment(
3210                                 scic->io_request_sequence[index]);
3211
3212                         sci_pool_put(scic->tci_pool, index);
3213
3214                         return SCI_SUCCESS;
3215                 }
3216         }
3217
3218         return SCI_FAILURE_INVALID_IO_TAG;
3219 }
3220
3221