drivers/scsi/qla2xxx/qla_os.c

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2014 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 #include "qla_def.h"
   8
   9 #include <linux/moduleparam.h>
  10 #include <linux/vmalloc.h>
  11 #include <linux/delay.h>
  12 #include <linux/kthread.h>
  13 #include <linux/mutex.h>
  14 #include <linux/kobject.h>
  15 #include <linux/slab.h>
  16 #include <scsi/scsi_tcq.h>
  17 #include <scsi/scsicam.h>
  18 #include <scsi/scsi_transport.h>
  19 #include <scsi/scsi_transport_fc.h>
  20
  21 #include "qla_target.h"
  22
  23 /*
  24  * Driver version
  25  */
  26 char qla2x00_version_str[40];
  27
  28 static int apidev_major;
  29
  30 /*
  31  * SRB allocation cache
  32  */
  33 static struct kmem_cache *srb_cachep;
  34
  35 /*
  36  * CT6 CTX allocation cache
  37  */
  38 static struct kmem_cache *ctx_cachep;
  39 /*
  40  * error level for logging
  41  */
  42 int ql_errlev = ql_log_all;
  43
  44 static int ql2xenableclass2;
  45 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
  46 MODULE_PARM_DESC(ql2xenableclass2,
  47                 "Specify if Class 2 operations are supported from the very "
  48                 "beginning. Default is 0 - class 2 not supported.");
  49
  50
  51 int ql2xlogintimeout = 20;
  52 module_param(ql2xlogintimeout, int, S_IRUGO);
  53 MODULE_PARM_DESC(ql2xlogintimeout,
  54                 "Login timeout value in seconds.");
  55
  56 int qlport_down_retry;
  57 module_param(qlport_down_retry, int, S_IRUGO);
  58 MODULE_PARM_DESC(qlport_down_retry,
  59                 "Maximum number of command retries to a port that returns "
  60                 "a PORT-DOWN status.");
  61
  62 int ql2xplogiabsentdevice;
  63 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
  64 MODULE_PARM_DESC(ql2xplogiabsentdevice,
  65                 "Option to enable PLOGI to devices that are not present after "
  66                 "a Fabric scan.  This is needed for several broken switches. "
  67                 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
  68
  69 int ql2xloginretrycount = 0;
  70 module_param(ql2xloginretrycount, int, S_IRUGO);
  71 MODULE_PARM_DESC(ql2xloginretrycount,
  72                 "Specify an alternate value for the NVRAM login retry count.");
  73
  74 int ql2xallocfwdump = 1;
  75 module_param(ql2xallocfwdump, int, S_IRUGO);
  76 MODULE_PARM_DESC(ql2xallocfwdump,
  77                 "Option to enable allocation of memory for a firmware dump "
  78                 "during HBA initialization.  Memory allocation requirements "
  79                 "vary by ISP type.  Default is 1 - allocate memory.");
  80
  81 int ql2xextended_error_logging;
  82 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
  83 MODULE_PARM_DESC(ql2xextended_error_logging,
  84                 "Option to enable extended error logging,\n"
  85                 "\t\tDefault is 0 - no logging.  0x40000000 - Module Init & Probe.\n"
  86                 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
  87                 "\t\t0x08000000 - IO tracing.    0x04000000 - DPC Thread.\n"
  88                 "\t\t0x02000000 - Async events.  0x01000000 - Timer routines.\n"
  89                 "\t\t0x00800000 - User space.    0x00400000 - Task Management.\n"
  90                 "\t\t0x00200000 - AER/EEH.       0x00100000 - Multi Q.\n"
  91                 "\t\t0x00080000 - P3P Specific.  0x00040000 - Virtual Port.\n"
  92                 "\t\t0x00020000 - Buffer Dump.   0x00010000 - Misc.\n"
  93                 "\t\t0x00008000 - Verbose.       0x00004000 - Target.\n"
  94                 "\t\t0x00002000 - Target Mgmt.   0x00001000 - Target TMF.\n"
  95                 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
  96                 "\t\t0x1e400000 - Preferred value for capturing essential "
  97                 "debug information (equivalent to old "
  98                 "ql2xextended_error_logging=1).\n"
  99                 "\t\tDo LOGICAL OR of the value to enable more than one level");
 100
 101 int ql2xshiftctondsd = 6;
 102 module_param(ql2xshiftctondsd, int, S_IRUGO);
 103 MODULE_PARM_DESC(ql2xshiftctondsd,
 104                 "Set to control shifting of command type processing "
 105                 "based on total number of SG elements.");
 106
 107 int ql2xfdmienable=1;
 108 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
 109 MODULE_PARM_DESC(ql2xfdmienable,
 110                 "Enables FDMI registrations. "
 111                 "0 - no FDMI. Default is 1 - perform FDMI.");
 112
 113 #define MAX_Q_DEPTH     32
 114 static int ql2xmaxqdepth = MAX_Q_DEPTH;
 115 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
 116 MODULE_PARM_DESC(ql2xmaxqdepth,
 117                 "Maximum queue depth to set for each LUN. "
 118                 "Default is 32.");
 119
 120 int ql2xenabledif = 2;
 121 module_param(ql2xenabledif, int, S_IRUGO);
 122 MODULE_PARM_DESC(ql2xenabledif,
 123                 " Enable T10-CRC-DIF:\n"
 124                 " Default is 2.\n"
 125                 "  0 -- No DIF Support\n"
 126                 "  1 -- Enable DIF for all types\n"
 127                 "  2 -- Enable DIF for all types, except Type 0.\n");
 128
 129 int ql2xenablehba_err_chk = 2;
 130 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
 131 MODULE_PARM_DESC(ql2xenablehba_err_chk,
 132                 " Enable T10-CRC-DIF Error isolation by HBA:\n"
 133                 " Default is 2.\n"
 134                 "  0 -- Error isolation disabled\n"
 135                 "  1 -- Error isolation enabled only for DIX Type 0\n"
 136                 "  2 -- Error isolation enabled for all Types\n");
 137
 138 int ql2xiidmaenable=1;
 139 module_param(ql2xiidmaenable, int, S_IRUGO);
 140 MODULE_PARM_DESC(ql2xiidmaenable,
 141                 "Enables iIDMA settings "
 142                 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
 143
 144 int ql2xmaxqueues = 1;
 145 module_param(ql2xmaxqueues, int, S_IRUGO);
 146 MODULE_PARM_DESC(ql2xmaxqueues,
 147                 "Enables MQ settings "
 148                 "Default is 1 for single queue. Set it to number "
 149                 "of queues in MQ mode.");
 150
 151 int ql2xmultique_tag;
 152 module_param(ql2xmultique_tag, int, S_IRUGO);
 153 MODULE_PARM_DESC(ql2xmultique_tag,
 154                 "Enables CPU affinity settings for the driver "
 155                 "Default is 0 for no affinity of request and response IO. "
 156                 "Set it to 1 to turn on the cpu affinity.");
 157
 158 int ql2xfwloadbin;
 159 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
 160 MODULE_PARM_DESC(ql2xfwloadbin,
 161                 "Option to specify location from which to load ISP firmware:.\n"
 162                 " 2 -- load firmware via the request_firmware() (hotplug).\n"
 163                 "      interface.\n"
 164                 " 1 -- load firmware from flash.\n"
 165                 " 0 -- use default semantics.\n");
 166
 167 int ql2xetsenable;
 168 module_param(ql2xetsenable, int, S_IRUGO);
 169 MODULE_PARM_DESC(ql2xetsenable,
 170                 "Enables firmware ETS burst."
 171                 "Default is 0 - skip ETS enablement.");
 172
 173 int ql2xdbwr = 1;
 174 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
 175 MODULE_PARM_DESC(ql2xdbwr,
 176                 "Option to specify scheme for request queue posting.\n"
 177                 " 0 -- Regular doorbell.\n"
 178                 " 1 -- CAMRAM doorbell (faster).\n");
 179
 180 int ql2xtargetreset = 1;
 181 module_param(ql2xtargetreset, int, S_IRUGO);
 182 MODULE_PARM_DESC(ql2xtargetreset,
 183                  "Enable target reset."
 184                  "Default is 1 - use hw defaults.");
 185
 186 int ql2xgffidenable;
 187 module_param(ql2xgffidenable, int, S_IRUGO);
 188 MODULE_PARM_DESC(ql2xgffidenable,
 189                 "Enables GFF_ID checks of port type. "
 190                 "Default is 0 - Do not use GFF_ID information.");
 191
 192 int ql2xasynctmfenable;
 193 module_param(ql2xasynctmfenable, int, S_IRUGO);
 194 MODULE_PARM_DESC(ql2xasynctmfenable,
 195                 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
 196                 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
 197
 198 int ql2xdontresethba;
 199 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
 200 MODULE_PARM_DESC(ql2xdontresethba,
 201                 "Option to specify reset behaviour.\n"
 202                 " 0 (Default) -- Reset on failure.\n"
 203                 " 1 -- Do not reset on failure.\n");
 204
 205 uint64_t ql2xmaxlun = MAX_LUNS;
 206 module_param(ql2xmaxlun, ullong, S_IRUGO);
 207 MODULE_PARM_DESC(ql2xmaxlun,
 208                 "Defines the maximum LU number to register with the SCSI "
 209                 "midlayer. Default is 65535.");
 210
 211 int ql2xmdcapmask = 0x1F;
 212 module_param(ql2xmdcapmask, int, S_IRUGO);
 213 MODULE_PARM_DESC(ql2xmdcapmask,
 214                 "Set the Minidump driver capture mask level. "
 215                 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
 216
 217 int ql2xmdenable = 1;
 218 module_param(ql2xmdenable, int, S_IRUGO);
 219 MODULE_PARM_DESC(ql2xmdenable,
 220                 "Enable/disable MiniDump. "
 221                 "0 - MiniDump disabled. "
 222                 "1 (Default) - MiniDump enabled.");
 223
 224 /*
 225  * SCSI host template entry points
 226  */
 227 static int qla2xxx_slave_configure(struct scsi_device * device);
 228 static int qla2xxx_slave_alloc(struct scsi_device *);
 229 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
 230 static void qla2xxx_scan_start(struct Scsi_Host *);
 231 static void qla2xxx_slave_destroy(struct scsi_device *);
 232 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
 233 static int qla2xxx_eh_abort(struct scsi_cmnd *);
 234 static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
 235 static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
 236 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
 237 static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
 238
 239 static void qla2x00_clear_drv_active(struct qla_hw_data *);
 240 static void qla2x00_free_device(scsi_qla_host_t *);
 241 static void qla83xx_disable_laser(scsi_qla_host_t *vha);
 242
 243 struct scsi_host_template qla2xxx_driver_template = {
 244         .module                 = THIS_MODULE,
 245         .name                   = QLA2XXX_DRIVER_NAME,
 246         .queuecommand           = qla2xxx_queuecommand,
 247
 248         .eh_abort_handler       = qla2xxx_eh_abort,
 249         .eh_device_reset_handler = qla2xxx_eh_device_reset,
 250         .eh_target_reset_handler = qla2xxx_eh_target_reset,
 251         .eh_bus_reset_handler   = qla2xxx_eh_bus_reset,
 252         .eh_host_reset_handler  = qla2xxx_eh_host_reset,
 253
 254         .slave_configure        = qla2xxx_slave_configure,
 255
 256         .slave_alloc            = qla2xxx_slave_alloc,
 257         .slave_destroy          = qla2xxx_slave_destroy,
 258         .scan_finished          = qla2xxx_scan_finished,
 259         .scan_start             = qla2xxx_scan_start,
 260         .change_queue_depth     = scsi_change_queue_depth,
 261         .this_id                = -1,
 262         .cmd_per_lun            = 3,
 263         .use_clustering         = ENABLE_CLUSTERING,
 264         .sg_tablesize           = SG_ALL,
 265
 266         .max_sectors            = 0xFFFF,
 267         .shost_attrs            = qla2x00_host_attrs,
 268
 269         .supported_mode         = MODE_INITIATOR,
 270         .use_blk_tags           = 1,
 271         .track_queue_depth      = 1,
 272 };
 273
 274 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
 275 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
 276
 277 /* TODO Convert to inlines
 278  *
 279  * Timer routines
 280  */
 281
 282 __inline__ void
 283 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
 284 {
 285         init_timer(&vha->timer);
 286         vha->timer.expires = jiffies + interval * HZ;
 287         vha->timer.data = (unsigned long)vha;
 288         vha->timer.function = (void (*)(unsigned long))func;
 289         add_timer(&vha->timer);
 290         vha->timer_active = 1;
 291 }
 292
 293 static inline void
 294 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
 295 {
 296         /* Currently used for 82XX only. */
 297         if (vha->device_flags & DFLG_DEV_FAILED) {
 298                 ql_dbg(ql_dbg_timer, vha, 0x600d,
 299                     "Device in a failed state, returning.\n");
 300                 return;
 301         }
 302
 303         mod_timer(&vha->timer, jiffies + interval * HZ);
 304 }
 305
 306 static __inline__ void
 307 qla2x00_stop_timer(scsi_qla_host_t *vha)
 308 {
 309         del_timer_sync(&vha->timer);
 310         vha->timer_active = 0;
 311 }
 312
 313 static int qla2x00_do_dpc(void *data);
 314
 315 static void qla2x00_rst_aen(scsi_qla_host_t *);
 316
 317 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
 318         struct req_que **, struct rsp_que **);
 319 static void qla2x00_free_fw_dump(struct qla_hw_data *);
 320 static void qla2x00_mem_free(struct qla_hw_data *);
 321
 322 /* -------------------------------------------------------------------------- */
 323 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
 324                                 struct rsp_que *rsp)
 325 {
 326         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 327         ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
 328                                 GFP_KERNEL);
 329         if (!ha->req_q_map) {
 330                 ql_log(ql_log_fatal, vha, 0x003b,
 331                     "Unable to allocate memory for request queue ptrs.\n");
 332                 goto fail_req_map;
 333         }
 334
 335         ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
 336                                 GFP_KERNEL);
 337         if (!ha->rsp_q_map) {
 338                 ql_log(ql_log_fatal, vha, 0x003c,
 339                     "Unable to allocate memory for response queue ptrs.\n");
 340                 goto fail_rsp_map;
 341         }
 342         /*
 343          * Make sure we record at least the request and response queue zero in
 344          * case we need to free them if part of the probe fails.
 345          */
 346         ha->rsp_q_map[0] = rsp;
 347         ha->req_q_map[0] = req;
 348         set_bit(0, ha->rsp_qid_map);
 349         set_bit(0, ha->req_qid_map);
 350         return 1;
 351
 352 fail_rsp_map:
 353         kfree(ha->req_q_map);
 354         ha->req_q_map = NULL;
 355 fail_req_map:
 356         return -ENOMEM;
 357 }
 358
 359 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
 360 {
 361         if (IS_QLAFX00(ha)) {
 362                 if (req && req->ring_fx00)
 363                         dma_free_coherent(&ha->pdev->dev,
 364                             (req->length_fx00 + 1) * sizeof(request_t),
 365                             req->ring_fx00, req->dma_fx00);
 366         } else if (req && req->ring)
 367                 dma_free_coherent(&ha->pdev->dev,
 368                 (req->length + 1) * sizeof(request_t),
 369                 req->ring, req->dma);
 370
 371         if (req)
 372                 kfree(req->outstanding_cmds);
 373
 374         kfree(req);
 375         req = NULL;
 376 }
 377
 378 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
 379 {
 380         if (IS_QLAFX00(ha)) {
 381                 if (rsp && rsp->ring)
 382                         dma_free_coherent(&ha->pdev->dev,
 383                             (rsp->length_fx00 + 1) * sizeof(request_t),
 384                             rsp->ring_fx00, rsp->dma_fx00);
 385         } else if (rsp && rsp->ring) {
 386                 dma_free_coherent(&ha->pdev->dev,
 387                 (rsp->length + 1) * sizeof(response_t),
 388                 rsp->ring, rsp->dma);
 389         }
 390         kfree(rsp);
 391         rsp = NULL;
 392 }
 393
 394 static void qla2x00_free_queues(struct qla_hw_data *ha)
 395 {
 396         struct req_que *req;
 397         struct rsp_que *rsp;
 398         int cnt;
 399
 400         for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
 401                 req = ha->req_q_map[cnt];
 402                 qla2x00_free_req_que(ha, req);
 403         }
 404         kfree(ha->req_q_map);
 405         ha->req_q_map = NULL;
 406
 407         for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
 408                 rsp = ha->rsp_q_map[cnt];
 409                 qla2x00_free_rsp_que(ha, rsp);
 410         }
 411         kfree(ha->rsp_q_map);
 412         ha->rsp_q_map = NULL;
 413 }
 414
 415 static int qla25xx_setup_mode(struct scsi_qla_host *vha)
 416 {
 417         uint16_t options = 0;
 418         int ques, req, ret;
 419         struct qla_hw_data *ha = vha->hw;
 420
 421         if (!(ha->fw_attributes & BIT_6)) {
 422                 ql_log(ql_log_warn, vha, 0x00d8,
 423                     "Firmware is not multi-queue capable.\n");
 424                 goto fail;
 425         }
 426         if (ql2xmultique_tag) {
 427                 /* create a request queue for IO */
 428                 options |= BIT_7;
 429                 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
 430                         QLA_DEFAULT_QUE_QOS);
 431                 if (!req) {
 432                         ql_log(ql_log_warn, vha, 0x00e0,
 433                             "Failed to create request queue.\n");
 434                         goto fail;
 435                 }
 436                 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
 437                 vha->req = ha->req_q_map[req];
 438                 options |= BIT_1;
 439                 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
 440                         ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
 441                         if (!ret) {
 442                                 ql_log(ql_log_warn, vha, 0x00e8,
 443                                     "Failed to create response queue.\n");
 444                                 goto fail2;
 445                         }
 446                 }
 447                 ha->flags.cpu_affinity_enabled = 1;
 448                 ql_dbg(ql_dbg_multiq, vha, 0xc007,
 449                     "CPU affinity mode enabled, "
 450                     "no. of response queues:%d no. of request queues:%d.\n",
 451                     ha->max_rsp_queues, ha->max_req_queues);
 452                 ql_dbg(ql_dbg_init, vha, 0x00e9,
 453                     "CPU affinity mode enabled, "
 454                     "no. of response queues:%d no. of request queues:%d.\n",
 455                     ha->max_rsp_queues, ha->max_req_queues);
 456         }
 457         return 0;
 458 fail2:
 459         qla25xx_delete_queues(vha);
 460         destroy_workqueue(ha->wq);
 461         ha->wq = NULL;
 462         vha->req = ha->req_q_map[0];
 463 fail:
 464         ha->mqenable = 0;
 465         kfree(ha->req_q_map);
 466         kfree(ha->rsp_q_map);
 467         ha->max_req_queues = ha->max_rsp_queues = 1;
 468         return 1;
 469 }
 470
 471 static char *
 472 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
 473 {
 474         struct qla_hw_data *ha = vha->hw;
 475         static char *pci_bus_modes[] = {
 476                 "33", "66", "100", "133",
 477         };
 478         uint16_t pci_bus;
 479
 480         strcpy(str, "PCI");
 481         pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
 482         if (pci_bus) {
 483                 strcat(str, "-X (");
 484                 strcat(str, pci_bus_modes[pci_bus]);
 485         } else {
 486                 pci_bus = (ha->pci_attr & BIT_8) >> 8;
 487                 strcat(str, " (");
 488                 strcat(str, pci_bus_modes[pci_bus]);
 489         }
 490         strcat(str, " MHz)");
 491
 492         return (str);
 493 }
 494
 495 static char *
 496 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
 497 {
 498         static char *pci_bus_modes[] = { "33", "66", "100", "133", };
 499         struct qla_hw_data *ha = vha->hw;
 500         uint32_t pci_bus;
 501
 502         if (pci_is_pcie(ha->pdev)) {
 503                 char lwstr[6];
 504                 uint32_t lstat, lspeed, lwidth;
 505
 506                 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
 507                 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
 508                 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
 509
 510                 strcpy(str, "PCIe (");
 511                 switch (lspeed) {
 512                 case 1:
 513                         strcat(str, "2.5GT/s ");
 514                         break;
 515                 case 2:
 516                         strcat(str, "5.0GT/s ");
 517                         break;
 518                 case 3:
 519                         strcat(str, "8.0GT/s ");
 520                         break;
 521                 default:
 522                         strcat(str, "<unknown> ");
 523                         break;
 524                 }
 525                 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
 526                 strcat(str, lwstr);
 527
 528                 return str;
 529         }
 530
 531         strcpy(str, "PCI");
 532         pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
 533         if (pci_bus == 0 || pci_bus == 8) {
 534                 strcat(str, " (");
 535                 strcat(str, pci_bus_modes[pci_bus >> 3]);
 536         } else {
 537                 strcat(str, "-X ");
 538                 if (pci_bus & BIT_2)
 539                         strcat(str, "Mode 2");
 540                 else
 541                         strcat(str, "Mode 1");
 542                 strcat(str, " (");
 543                 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
 544         }
 545         strcat(str, " MHz)");
 546
 547         return str;
 548 }
 549
 550 static char *
 551 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
 552 {
 553         char un_str[10];
 554         struct qla_hw_data *ha = vha->hw;
 555
 556         snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
 557             ha->fw_minor_version, ha->fw_subminor_version);
 558
 559         if (ha->fw_attributes & BIT_9) {
 560                 strcat(str, "FLX");
 561                 return (str);
 562         }
 563
 564         switch (ha->fw_attributes & 0xFF) {
 565         case 0x7:
 566                 strcat(str, "EF");
 567                 break;
 568         case 0x17:
 569                 strcat(str, "TP");
 570                 break;
 571         case 0x37:
 572                 strcat(str, "IP");
 573                 break;
 574         case 0x77:
 575                 strcat(str, "VI");
 576                 break;
 577         default:
 578                 sprintf(un_str, "(%x)", ha->fw_attributes);
 579                 strcat(str, un_str);
 580                 break;
 581         }
 582         if (ha->fw_attributes & 0x100)
 583                 strcat(str, "X");
 584
 585         return (str);
 586 }
 587
 588 static char *
 589 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
 590 {
 591         struct qla_hw_data *ha = vha->hw;
 592
 593         snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
 594             ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
 595         return str;
 596 }
 597
 598 void
 599 qla2x00_sp_free_dma(void *vha, void *ptr)
 600 {
 601         srb_t *sp = (srb_t *)ptr;
 602         struct scsi_cmnd *cmd = GET_CMD_SP(sp);
 603         struct qla_hw_data *ha = sp->fcport->vha->hw;
 604         void *ctx = GET_CMD_CTX_SP(sp);
 605
 606         if (sp->flags & SRB_DMA_VALID) {
 607                 scsi_dma_unmap(cmd);
 608                 sp->flags &= ~SRB_DMA_VALID;
 609         }
 610
 611         if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
 612                 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
 613                     scsi_prot_sg_count(cmd), cmd->sc_data_direction);
 614                 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
 615         }
 616
 617         if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
 618                 /* List assured to be having elements */
 619                 qla2x00_clean_dsd_pool(ha, sp, NULL);
 620                 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
 621         }
 622
 623         if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
 624                 dma_pool_free(ha->dl_dma_pool, ctx,
 625                     ((struct crc_context *)ctx)->crc_ctx_dma);
 626                 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
 627         }
 628
 629         if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
 630                 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
 631
 632                 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
 633                         ctx1->fcp_cmnd_dma);
 634                 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
 635                 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
 636                 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
 637                 mempool_free(ctx1, ha->ctx_mempool);
 638                 ctx1 = NULL;
 639         }
 640
 641         CMD_SP(cmd) = NULL;
 642         qla2x00_rel_sp(sp->fcport->vha, sp);
 643 }
 644
 645 static void
 646 qla2x00_sp_compl(void *data, void *ptr, int res)
 647 {
 648         struct qla_hw_data *ha = (struct qla_hw_data *)data;
 649         srb_t *sp = (srb_t *)ptr;
 650         struct scsi_cmnd *cmd = GET_CMD_SP(sp);
 651
 652         cmd->result = res;
 653
 654         if (atomic_read(&sp->ref_count) == 0) {
 655                 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
 656                     "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
 657                     sp, GET_CMD_SP(sp));
 658                 if (ql2xextended_error_logging & ql_dbg_io)
 659                         WARN_ON(atomic_read(&sp->ref_count) == 0);
 660                 return;
 661         }
 662         if (!atomic_dec_and_test(&sp->ref_count))
 663                 return;
 664
 665         qla2x00_sp_free_dma(ha, sp);
 666         cmd->scsi_done(cmd);
 667 }
 668
 669 /* If we are SP1 here, we need to still take and release the host_lock as SP1
 670  * does not have the changes necessary to avoid taking host->host_lock.
 671  */
 672 static int
 673 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
 674 {
 675         scsi_qla_host_t *vha = shost_priv(host);
 676         fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
 677         struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
 678         struct qla_hw_data *ha = vha->hw;
 679         struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
 680         srb_t *sp;
 681         int rval;
 682
 683         if (ha->flags.eeh_busy) {
 684                 if (ha->flags.pci_channel_io_perm_failure) {
 685                         ql_dbg(ql_dbg_aer, vha, 0x9010,
 686                             "PCI Channel IO permanent failure, exiting "
 687                             "cmd=%p.\n", cmd);
 688                         cmd->result = DID_NO_CONNECT << 16;
 689                 } else {
 690                         ql_dbg(ql_dbg_aer, vha, 0x9011,
 691                             "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
 692                         cmd->result = DID_REQUEUE << 16;
 693                 }
 694                 goto qc24_fail_command;
 695         }
 696
 697         rval = fc_remote_port_chkready(rport);
 698         if (rval) {
 699                 cmd->result = rval;
 700                 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
 701                     "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
 702                     cmd, rval);
 703                 goto qc24_fail_command;
 704         }
 705
 706         if (!vha->flags.difdix_supported &&
 707                 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
 708                         ql_dbg(ql_dbg_io, vha, 0x3004,
 709                             "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
 710                             cmd);
 711                         cmd->result = DID_NO_CONNECT << 16;
 712                         goto qc24_fail_command;
 713         }
 714
 715         if (!fcport) {
 716                 cmd->result = DID_NO_CONNECT << 16;
 717                 goto qc24_fail_command;
 718         }
 719
 720         if (atomic_read(&fcport->state) != FCS_ONLINE) {
 721                 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
 722                         atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
 723                         ql_dbg(ql_dbg_io, vha, 0x3005,
 724                             "Returning DNC, fcport_state=%d loop_state=%d.\n",
 725                             atomic_read(&fcport->state),
 726                             atomic_read(&base_vha->loop_state));
 727                         cmd->result = DID_NO_CONNECT << 16;
 728                         goto qc24_fail_command;
 729                 }
 730                 goto qc24_target_busy;
 731         }
 732
 733         /*
 734          * Return target busy if we've received a non-zero retry_delay_timer
 735          * in a FCP_RSP.
 736          */
 737         if (fcport->retry_delay_timestamp == 0) {
 738                 /* retry delay not set */
 739         } else if (time_after(jiffies, fcport->retry_delay_timestamp))
 740                 fcport->retry_delay_timestamp = 0;
 741         else
 742                 goto qc24_target_busy;
 743
 744         sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
 745         if (!sp)
 746                 goto qc24_host_busy;
 747
 748         sp->u.scmd.cmd = cmd;
 749         sp->type = SRB_SCSI_CMD;
 750         atomic_set(&sp->ref_count, 1);
 751         CMD_SP(cmd) = (void *)sp;
 752         sp->free = qla2x00_sp_free_dma;
 753         sp->done = qla2x00_sp_compl;
 754
 755         rval = ha->isp_ops->start_scsi(sp);
 756         if (rval != QLA_SUCCESS) {
 757                 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
 758                     "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
 759                 goto qc24_host_busy_free_sp;
 760         }
 761
 762         return 0;
 763
 764 qc24_host_busy_free_sp:
 765         qla2x00_sp_free_dma(ha, sp);
 766
 767 qc24_host_busy:
 768         return SCSI_MLQUEUE_HOST_BUSY;
 769
 770 qc24_target_busy:
 771         return SCSI_MLQUEUE_TARGET_BUSY;
 772
 773 qc24_fail_command:
 774         cmd->scsi_done(cmd);
 775
 776         return 0;
 777 }
 778
 779 /*
 780  * qla2x00_eh_wait_on_command
 781  *    Waits for the command to be returned by the Firmware for some
 782  *    max time.
 783  *
 784  * Input:
 785  *    cmd = Scsi Command to wait on.
 786  *
 787  * Return:
 788  *    Not Found : 0
 789  *    Found : 1
 790  */
 791 static int
 792 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
 793 {
 794 #define ABORT_POLLING_PERIOD    1000
 795 #define ABORT_WAIT_ITER         ((2 * 1000) / (ABORT_POLLING_PERIOD))
 796         unsigned long wait_iter = ABORT_WAIT_ITER;
 797         scsi_qla_host_t *vha = shost_priv(cmd->device->host);
 798         struct qla_hw_data *ha = vha->hw;
 799         int ret = QLA_SUCCESS;
 800
 801         if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
 802                 ql_dbg(ql_dbg_taskm, vha, 0x8005,
 803                     "Return:eh_wait.\n");
 804                 return ret;
 805         }
 806
 807         while (CMD_SP(cmd) && wait_iter--) {
 808                 msleep(ABORT_POLLING_PERIOD);
 809         }
 810         if (CMD_SP(cmd))
 811                 ret = QLA_FUNCTION_FAILED;
 812
 813         return ret;
 814 }
 815
 816 /*
 817  * qla2x00_wait_for_hba_online
 818  *    Wait till the HBA is online after going through
 819  *    <= MAX_RETRIES_OF_ISP_ABORT  or
 820  *    finally HBA is disabled ie marked offline
 821  *
 822  * Input:
 823  *     ha - pointer to host adapter structure
 824  *
 825  * Note:
 826  *    Does context switching-Release SPIN_LOCK
 827  *    (if any) before calling this routine.
 828  *
 829  * Return:
 830  *    Success (Adapter is online) : 0
 831  *    Failed  (Adapter is offline/disabled) : 1
 832  */
 833 int
 834 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
 835 {
 836         int             return_status;
 837         unsigned long   wait_online;
 838         struct qla_hw_data *ha = vha->hw;
 839         scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
 840
 841         wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
 842         while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
 843             test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
 844             test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
 845             ha->dpc_active) && time_before(jiffies, wait_online)) {
 846
 847                 msleep(1000);
 848         }
 849         if (base_vha->flags.online)
 850                 return_status = QLA_SUCCESS;
 851         else
 852                 return_status = QLA_FUNCTION_FAILED;
 853
 854         return (return_status);
 855 }
 856
 857 /*
 858  * qla2x00_wait_for_hba_ready
 859  * Wait till the HBA is ready before doing driver unload
 860  *
 861  * Input:
 862  *     ha - pointer to host adapter structure
 863  *
 864  * Note:
 865  *    Does context switching-Release SPIN_LOCK
 866  *    (if any) before calling this routine.
 867  *
 868  */
 869 static void
 870 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
 871 {
 872         struct qla_hw_data *ha = vha->hw;
 873
 874         while (((qla2x00_reset_active(vha)) || ha->dpc_active ||
 875             ha->flags.mbox_busy) ||
 876                 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
 877                 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags))
 878                 msleep(1000);
 879 }
 880
 881 int
 882 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
 883 {
 884         int             return_status;
 885         unsigned long   wait_reset;
 886         struct qla_hw_data *ha = vha->hw;
 887         scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
 888
 889         wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
 890         while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
 891             test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
 892             test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
 893             ha->dpc_active) && time_before(jiffies, wait_reset)) {
 894
 895                 msleep(1000);
 896
 897                 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
 898                     ha->flags.chip_reset_done)
 899                         break;
 900         }
 901         if (ha->flags.chip_reset_done)
 902                 return_status = QLA_SUCCESS;
 903         else
 904                 return_status = QLA_FUNCTION_FAILED;
 905
 906         return return_status;
 907 }
 908
 909 static void
 910 sp_get(struct srb *sp)
 911 {
 912         atomic_inc(&sp->ref_count);
 913 }
 914
 915 /**************************************************************************
 916 * qla2xxx_eh_abort
 917 *
 918 * Description:
 919 *    The abort function will abort the specified command.
 920 *
 921 * Input:
 922 *    cmd = Linux SCSI command packet to be aborted.
 923 *
 924 * Returns:
 925 *    Either SUCCESS or FAILED.
 926 *
 927 * Note:
 928 *    Only return FAILED if command not returned by firmware.
 929 **************************************************************************/
 930 static int
 931 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
 932 {
 933         scsi_qla_host_t *vha = shost_priv(cmd->device->host);
 934         srb_t *sp;
 935         int ret;
 936         unsigned int id;
 937         uint64_t lun;
 938         unsigned long flags;
 939         int rval, wait = 0;
 940         struct qla_hw_data *ha = vha->hw;
 941
 942         if (!CMD_SP(cmd))
 943                 return SUCCESS;
 944
 945         ret = fc_block_scsi_eh(cmd);
 946         if (ret != 0)
 947                 return ret;
 948         ret = SUCCESS;
 949
 950         id = cmd->device->id;
 951         lun = cmd->device->lun;
 952
 953         spin_lock_irqsave(&ha->hardware_lock, flags);
 954         sp = (srb_t *) CMD_SP(cmd);
 955         if (!sp) {
 956                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
 957                 return SUCCESS;
 958         }
 959
 960         ql_dbg(ql_dbg_taskm, vha, 0x8002,
 961             "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
 962             vha->host_no, id, lun, sp, cmd, sp->handle);
 963
 964         /* Get a reference to the sp and drop the lock.*/
 965         sp_get(sp);
 966
 967         spin_unlock_irqrestore(&ha->hardware_lock, flags);
 968         rval = ha->isp_ops->abort_command(sp);
 969         if (rval) {
 970                 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
 971                         ret = SUCCESS;
 972                 else
 973                         ret = FAILED;
 974
 975                 ql_dbg(ql_dbg_taskm, vha, 0x8003,
 976                     "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
 977         } else {
 978                 ql_dbg(ql_dbg_taskm, vha, 0x8004,
 979                     "Abort command mbx success cmd=%p.\n", cmd);
 980                 wait = 1;
 981         }
 982
 983         spin_lock_irqsave(&ha->hardware_lock, flags);
 984         sp->done(ha, sp, 0);
 985         spin_unlock_irqrestore(&ha->hardware_lock, flags);
 986
 987         /* Did the command return during mailbox execution? */
 988         if (ret == FAILED && !CMD_SP(cmd))
 989                 ret = SUCCESS;
 990
 991         /* Wait for the command to be returned. */
 992         if (wait) {
 993                 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
 994                         ql_log(ql_log_warn, vha, 0x8006,
 995                             "Abort handler timed out cmd=%p.\n", cmd);
 996                         ret = FAILED;
 997                 }
 998         }
 999
1000         ql_log(ql_log_info, vha, 0x801c,
1001             "Abort command issued nexus=%ld:%d:%llu --  %d %x.\n",
1002             vha->host_no, id, lun, wait, ret);
1003
1004         return ret;
1005 }
1006
1007 int
1008 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1009         uint64_t l, enum nexus_wait_type type)
1010 {
1011         int cnt, match, status;
1012         unsigned long flags;
1013         struct qla_hw_data *ha = vha->hw;
1014         struct req_que *req;
1015         srb_t *sp;
1016         struct scsi_cmnd *cmd;
1017
1018         status = QLA_SUCCESS;
1019
1020         spin_lock_irqsave(&ha->hardware_lock, flags);
1021         req = vha->req;
1022         for (cnt = 1; status == QLA_SUCCESS &&
1023                 cnt < req->num_outstanding_cmds; cnt++) {
1024                 sp = req->outstanding_cmds[cnt];
1025                 if (!sp)
1026                         continue;
1027                 if (sp->type != SRB_SCSI_CMD)
1028                         continue;
1029                 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1030                         continue;
1031                 match = 0;
1032                 cmd = GET_CMD_SP(sp);
1033                 switch (type) {
1034                 case WAIT_HOST:
1035                         match = 1;
1036                         break;
1037                 case WAIT_TARGET:
1038                         match = cmd->device->id == t;
1039                         break;
1040                 case WAIT_LUN:
1041                         match = (cmd->device->id == t &&
1042                                 cmd->device->lun == l);
1043                         break;
1044                 }
1045                 if (!match)
1046                         continue;
1047
1048                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1049                 status = qla2x00_eh_wait_on_command(cmd);
1050                 spin_lock_irqsave(&ha->hardware_lock, flags);
1051         }
1052         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1053
1054         return status;
1055 }
1056
1057 static char *reset_errors[] = {
1058         "HBA not online",
1059         "HBA not ready",
1060         "Task management failed",
1061         "Waiting for command completions",
1062 };
1063
1064 static int
1065 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
1066     struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1067 {
1068         scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1069         fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1070         int err;
1071
1072         if (!fcport) {
1073                 return FAILED;
1074         }
1075
1076         err = fc_block_scsi_eh(cmd);
1077         if (err != 0)
1078                 return err;
1079
1080         ql_log(ql_log_info, vha, 0x8009,
1081             "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
1082             cmd->device->id, cmd->device->lun, cmd);
1083
1084         err = 0;
1085         if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1086                 ql_log(ql_log_warn, vha, 0x800a,
1087                     "Wait for hba online failed for cmd=%p.\n", cmd);
1088                 goto eh_reset_failed;
1089         }
1090         err = 2;
1091         if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
1092                 != QLA_SUCCESS) {
1093                 ql_log(ql_log_warn, vha, 0x800c,
1094                     "do_reset failed for cmd=%p.\n", cmd);
1095                 goto eh_reset_failed;
1096         }
1097         err = 3;
1098         if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
1099             cmd->device->lun, type) != QLA_SUCCESS) {
1100                 ql_log(ql_log_warn, vha, 0x800d,
1101                     "wait for pending cmds failed for cmd=%p.\n", cmd);
1102                 goto eh_reset_failed;
1103         }
1104
1105         ql_log(ql_log_info, vha, 0x800e,
1106             "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
1107             vha->host_no, cmd->device->id, cmd->device->lun, cmd);
1108
1109         return SUCCESS;
1110
1111 eh_reset_failed:
1112         ql_log(ql_log_info, vha, 0x800f,
1113             "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
1114             reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1115             cmd);
1116         return FAILED;
1117 }
1118
1119 static int
1120 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1121 {
1122         scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1123         struct qla_hw_data *ha = vha->hw;
1124
1125         return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1126             ha->isp_ops->lun_reset);
1127 }
1128
1129 static int
1130 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1131 {
1132         scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1133         struct qla_hw_data *ha = vha->hw;
1134
1135         return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1136             ha->isp_ops->target_reset);
1137 }
1138
1139 /**************************************************************************
1140 * qla2xxx_eh_bus_reset
1141 *
1142 * Description:
1143 *    The bus reset function will reset the bus and abort any executing
1144 *    commands.
1145 *
1146 * Input:
1147 *    cmd = Linux SCSI command packet of the command that cause the
1148 *          bus reset.
1149 *
1150 * Returns:
1151 *    SUCCESS/FAILURE (defined as macro in scsi.h).
1152 *
1153 **************************************************************************/
1154 static int
1155 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1156 {
1157         scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1158         fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1159         int ret = FAILED;
1160         unsigned int id;
1161         uint64_t lun;
1162
1163         id = cmd->device->id;
1164         lun = cmd->device->lun;
1165
1166         if (!fcport) {
1167                 return ret;
1168         }
1169
1170         ret = fc_block_scsi_eh(cmd);
1171         if (ret != 0)
1172                 return ret;
1173         ret = FAILED;
1174
1175         ql_log(ql_log_info, vha, 0x8012,
1176             "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1177
1178         if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1179                 ql_log(ql_log_fatal, vha, 0x8013,
1180                     "Wait for hba online failed board disabled.\n");
1181                 goto eh_bus_reset_done;
1182         }
1183
1184         if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1185                 ret = SUCCESS;
1186
1187         if (ret == FAILED)
1188                 goto eh_bus_reset_done;
1189
1190         /* Flush outstanding commands. */
1191         if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1192             QLA_SUCCESS) {
1193                 ql_log(ql_log_warn, vha, 0x8014,
1194                     "Wait for pending commands failed.\n");
1195                 ret = FAILED;
1196         }
1197
1198 eh_bus_reset_done:
1199         ql_log(ql_log_warn, vha, 0x802b,
1200             "BUS RESET %s nexus=%ld:%d:%llu.\n",
1201             (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1202
1203         return ret;
1204 }
1205
1206 /**************************************************************************
1207 * qla2xxx_eh_host_reset
1208 *
1209 * Description:
1210 *    The reset function will reset the Adapter.
1211 *
1212 * Input:
1213 *      cmd = Linux SCSI command packet of the command that cause the
1214 *            adapter reset.
1215 *
1216 * Returns:
1217 *      Either SUCCESS or FAILED.
1218 *
1219 * Note:
1220 **************************************************************************/
1221 static int
1222 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1223 {
1224         scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1225         struct qla_hw_data *ha = vha->hw;
1226         int ret = FAILED;
1227         unsigned int id;
1228         uint64_t lun;
1229         scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1230
1231         id = cmd->device->id;
1232         lun = cmd->device->lun;
1233
1234         ql_log(ql_log_info, vha, 0x8018,
1235             "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1236
1237         /*
1238          * No point in issuing another reset if one is active.  Also do not
1239          * attempt a reset if we are updating flash.
1240          */
1241         if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1242                 goto eh_host_reset_lock;
1243
1244         if (vha != base_vha) {
1245                 if (qla2x00_vp_abort_isp(vha))
1246                         goto eh_host_reset_lock;
1247         } else {
1248                 if (IS_P3P_TYPE(vha->hw)) {
1249                         if (!qla82xx_fcoe_ctx_reset(vha)) {
1250                                 /* Ctx reset success */
1251                                 ret = SUCCESS;
1252                                 goto eh_host_reset_lock;
1253                         }
1254                         /* fall thru if ctx reset failed */
1255                 }
1256                 if (ha->wq)
1257                         flush_workqueue(ha->wq);
1258
1259                 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1260                 if (ha->isp_ops->abort_isp(base_vha)) {
1261                         clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1262                         /* failed. schedule dpc to try */
1263                         set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1264
1265                         if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1266                                 ql_log(ql_log_warn, vha, 0x802a,
1267                                     "wait for hba online failed.\n");
1268                                 goto eh_host_reset_lock;
1269                         }
1270                 }
1271                 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1272         }
1273
1274         /* Waiting for command to be returned to OS.*/
1275         if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1276                 QLA_SUCCESS)
1277                 ret = SUCCESS;
1278
1279 eh_host_reset_lock:
1280         ql_log(ql_log_info, vha, 0x8017,
1281             "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1282             (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1283
1284         return ret;
1285 }
1286
1287 /*
1288 * qla2x00_loop_reset
1289 *      Issue loop reset.
1290 *
1291 * Input:
1292 *      ha = adapter block pointer.
1293 *
1294 * Returns:
1295 *      0 = success
1296 */
1297 int
1298 qla2x00_loop_reset(scsi_qla_host_t *vha)
1299 {
1300         int ret;
1301         struct fc_port *fcport;
1302         struct qla_hw_data *ha = vha->hw;
1303
1304         if (IS_QLAFX00(ha)) {
1305                 return qlafx00_loop_reset(vha);
1306         }
1307
1308         if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
1309                 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1310                         if (fcport->port_type != FCT_TARGET)
1311                                 continue;
1312
1313                         ret = ha->isp_ops->target_reset(fcport, 0, 0);
1314                         if (ret != QLA_SUCCESS) {
1315                                 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1316                                     "Bus Reset failed: Reset=%d "
1317                                     "d_id=%x.\n", ret, fcport->d_id.b24);
1318                         }
1319                 }
1320         }
1321
1322
1323         if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1324                 atomic_set(&vha->loop_state, LOOP_DOWN);
1325                 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1326                 qla2x00_mark_all_devices_lost(vha, 0);
1327                 ret = qla2x00_full_login_lip(vha);
1328                 if (ret != QLA_SUCCESS) {
1329                         ql_dbg(ql_dbg_taskm, vha, 0x802d,
1330                             "full_login_lip=%d.\n", ret);
1331                 }
1332         }
1333
1334         if (ha->flags.enable_lip_reset) {
1335                 ret = qla2x00_lip_reset(vha);
1336                 if (ret != QLA_SUCCESS)
1337                         ql_dbg(ql_dbg_taskm, vha, 0x802e,
1338                             "lip_reset failed (%d).\n", ret);
1339         }
1340
1341         /* Issue marker command only when we are going to start the I/O */
1342         vha->marker_needed = 1;
1343
1344         return QLA_SUCCESS;
1345 }
1346
1347 void
1348 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1349 {
1350         int que, cnt;
1351         unsigned long flags;
1352         srb_t *sp;
1353         struct qla_hw_data *ha = vha->hw;
1354         struct req_que *req;
1355
1356         qlt_host_reset_handler(ha);
1357
1358         spin_lock_irqsave(&ha->hardware_lock, flags);
1359         for (que = 0; que < ha->max_req_queues; que++) {
1360                 req = ha->req_q_map[que];
1361                 if (!req)
1362                         continue;
1363                 if (!req->outstanding_cmds)
1364                         continue;
1365                 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1366                         sp = req->outstanding_cmds[cnt];
1367                         if (sp) {
1368                                 req->outstanding_cmds[cnt] = NULL;
1369                                 sp->done(vha, sp, res);
1370                         }
1371                 }
1372         }
1373         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1374 }
1375
1376 static int
1377 qla2xxx_slave_alloc(struct scsi_device *sdev)
1378 {
1379         struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1380
1381         if (!rport || fc_remote_port_chkready(rport))
1382                 return -ENXIO;
1383
1384         sdev->hostdata = *(fc_port_t **)rport->dd_data;
1385
1386         return 0;
1387 }
1388
1389 static int
1390 qla2xxx_slave_configure(struct scsi_device *sdev)
1391 {
1392         scsi_qla_host_t *vha = shost_priv(sdev->host);
1393         struct req_que *req = vha->req;
1394
1395         if (IS_T10_PI_CAPABLE(vha->hw))
1396                 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1397
1398         scsi_change_queue_depth(sdev, req->max_q_depth);
1399         return 0;
1400 }
1401
1402 static void
1403 qla2xxx_slave_destroy(struct scsi_device *sdev)
1404 {
1405         sdev->hostdata = NULL;
1406 }
1407
1408 /**
1409  * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1410  * @ha: HA context
1411  *
1412  * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1413  * supported addressing method.
1414  */
1415 static void
1416 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1417 {
1418         /* Assume a 32bit DMA mask. */
1419         ha->flags.enable_64bit_addressing = 0;
1420
1421         if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1422                 /* Any upper-dword bits set? */
1423                 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1424                     !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
1425                         /* Ok, a 64bit DMA mask is applicable. */
1426                         ha->flags.enable_64bit_addressing = 1;
1427                         ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1428                         ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1429                         return;
1430                 }
1431         }
1432
1433         dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1434         pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1435 }
1436
1437 static void
1438 qla2x00_enable_intrs(struct qla_hw_data *ha)
1439 {
1440         unsigned long flags = 0;
1441         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1442
1443         spin_lock_irqsave(&ha->hardware_lock, flags);
1444         ha->interrupts_on = 1;
1445         /* enable risc and host interrupts */
1446         WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1447         RD_REG_WORD(&reg->ictrl);
1448         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1449
1450 }
1451
1452 static void
1453 qla2x00_disable_intrs(struct qla_hw_data *ha)
1454 {
1455         unsigned long flags = 0;
1456         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1457
1458         spin_lock_irqsave(&ha->hardware_lock, flags);
1459         ha->interrupts_on = 0;
1460         /* disable risc and host interrupts */
1461         WRT_REG_WORD(&reg->ictrl, 0);
1462         RD_REG_WORD(&reg->ictrl);
1463         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1464 }
1465
1466 static void
1467 qla24xx_enable_intrs(struct qla_hw_data *ha)
1468 {
1469         unsigned long flags = 0;
1470         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1471
1472         spin_lock_irqsave(&ha->hardware_lock, flags);
1473         ha->interrupts_on = 1;
1474         WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1475         RD_REG_DWORD(&reg->ictrl);
1476         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1477 }
1478
1479 static void
1480 qla24xx_disable_intrs(struct qla_hw_data *ha)
1481 {
1482         unsigned long flags = 0;
1483         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1484
1485         if (IS_NOPOLLING_TYPE(ha))
1486                 return;
1487         spin_lock_irqsave(&ha->hardware_lock, flags);
1488         ha->interrupts_on = 0;
1489         WRT_REG_DWORD(&reg->ictrl, 0);
1490         RD_REG_DWORD(&reg->ictrl);
1491         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1492 }
1493
1494 static int
1495 qla2x00_iospace_config(struct qla_hw_data *ha)
1496 {
1497         resource_size_t pio;
1498         uint16_t msix;
1499         int cpus;
1500
1501         if (pci_request_selected_regions(ha->pdev, ha->bars,
1502             QLA2XXX_DRIVER_NAME)) {
1503                 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1504                     "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1505                     pci_name(ha->pdev));
1506                 goto iospace_error_exit;
1507         }
1508         if (!(ha->bars & 1))
1509                 goto skip_pio;
1510
1511         /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1512         pio = pci_resource_start(ha->pdev, 0);
1513         if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1514                 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1515                         ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1516                             "Invalid pci I/O region size (%s).\n",
1517                             pci_name(ha->pdev));
1518                         pio = 0;
1519                 }
1520         } else {
1521                 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1522                     "Region #0 no a PIO resource (%s).\n",
1523                     pci_name(ha->pdev));
1524                 pio = 0;
1525         }
1526         ha->pio_address = pio;
1527         ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1528             "PIO address=%llu.\n",
1529             (unsigned long long)ha->pio_address);
1530
1531 skip_pio:
1532         /* Use MMIO operations for all accesses. */
1533         if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1534                 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1535                     "Region #1 not an MMIO resource (%s), aborting.\n",
1536                     pci_name(ha->pdev));
1537                 goto iospace_error_exit;
1538         }
1539         if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1540                 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1541                     "Invalid PCI mem region size (%s), aborting.\n",
1542                     pci_name(ha->pdev));
1543                 goto iospace_error_exit;
1544         }
1545
1546         ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1547         if (!ha->iobase) {
1548                 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1549                     "Cannot remap MMIO (%s), aborting.\n",
1550                     pci_name(ha->pdev));
1551                 goto iospace_error_exit;
1552         }
1553
1554         /* Determine queue resources */
1555         ha->max_req_queues = ha->max_rsp_queues = 1;
1556         if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1557                 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1558                 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1559                 goto mqiobase_exit;
1560
1561         ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1562                         pci_resource_len(ha->pdev, 3));
1563         if (ha->mqiobase) {
1564                 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1565                     "MQIO Base=%p.\n", ha->mqiobase);
1566                 /* Read MSIX vector size of the board */
1567                 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1568                 ha->msix_count = msix;
1569                 /* Max queues are bounded by available msix vectors */
1570                 /* queue 0 uses two msix vectors */
1571                 if (ql2xmultique_tag) {
1572                         cpus = num_online_cpus();
1573                         ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1574                                 (cpus + 1) : (ha->msix_count - 1);
1575                         ha->max_req_queues = 2;
1576                 } else if (ql2xmaxqueues > 1) {
1577                         ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1578                             QLA_MQ_SIZE : ql2xmaxqueues;
1579                         ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1580                             "QoS mode set, max no of request queues:%d.\n",
1581                             ha->max_req_queues);
1582                         ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1583                             "QoS mode set, max no of request queues:%d.\n",
1584                             ha->max_req_queues);
1585                 }
1586                 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1587                     "MSI-X vector count: %d.\n", msix);
1588         } else
1589                 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1590                     "BAR 3 not enabled.\n");
1591
1592 mqiobase_exit:
1593         ha->msix_count = ha->max_rsp_queues + 1;
1594         ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1595             "MSIX Count:%d.\n", ha->msix_count);
1596         return (0);
1597
1598 iospace_error_exit:
1599         return (-ENOMEM);
1600 }
1601
1602
1603 static int
1604 qla83xx_iospace_config(struct qla_hw_data *ha)
1605 {
1606         uint16_t msix;
1607         int cpus;
1608
1609         if (pci_request_selected_regions(ha->pdev, ha->bars,
1610             QLA2XXX_DRIVER_NAME)) {
1611                 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1612                     "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1613                     pci_name(ha->pdev));
1614
1615                 goto iospace_error_exit;
1616         }
1617
1618         /* Use MMIO operations for all accesses. */
1619         if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1620                 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1621                     "Invalid pci I/O region size (%s).\n",
1622                     pci_name(ha->pdev));
1623                 goto iospace_error_exit;
1624         }
1625         if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1626                 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1627                     "Invalid PCI mem region size (%s), aborting\n",
1628                         pci_name(ha->pdev));
1629                 goto iospace_error_exit;
1630         }
1631
1632         ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1633         if (!ha->iobase) {
1634                 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1635                     "Cannot remap MMIO (%s), aborting.\n",
1636                     pci_name(ha->pdev));
1637                 goto iospace_error_exit;
1638         }
1639
1640         /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1641         /* 83XX 26XX always use MQ type access for queues
1642          * - mbar 2, a.k.a region 4 */
1643         ha->max_req_queues = ha->max_rsp_queues = 1;
1644         ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1645                         pci_resource_len(ha->pdev, 4));
1646
1647         if (!ha->mqiobase) {
1648                 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1649                     "BAR2/region4 not enabled\n");
1650                 goto mqiobase_exit;
1651         }
1652
1653         ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1654                         pci_resource_len(ha->pdev, 2));
1655         if (ha->msixbase) {
1656                 /* Read MSIX vector size of the board */
1657                 pci_read_config_word(ha->pdev,
1658                     QLA_83XX_PCI_MSIX_CONTROL, &msix);
1659                 ha->msix_count = msix;
1660                 /* Max queues are bounded by available msix vectors */
1661                 /* queue 0 uses two msix vectors */
1662                 if (ql2xmultique_tag) {
1663                         cpus = num_online_cpus();
1664                         ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1665                                 (cpus + 1) : (ha->msix_count - 1);
1666                         ha->max_req_queues = 2;
1667                 } else if (ql2xmaxqueues > 1) {
1668                         ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1669                                                 QLA_MQ_SIZE : ql2xmaxqueues;
1670                         ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1671                             "QoS mode set, max no of request queues:%d.\n",
1672                             ha->max_req_queues);
1673                         ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1674                             "QoS mode set, max no of request queues:%d.\n",
1675                             ha->max_req_queues);
1676                 }
1677                 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1678                     "MSI-X vector count: %d.\n", msix);
1679         } else
1680                 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1681                     "BAR 1 not enabled.\n");
1682
1683 mqiobase_exit:
1684         ha->msix_count = ha->max_rsp_queues + 1;
1685
1686         qlt_83xx_iospace_config(ha);
1687
1688         ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1689             "MSIX Count:%d.\n", ha->msix_count);
1690         return 0;
1691
1692 iospace_error_exit:
1693         return -ENOMEM;
1694 }
1695
1696 static struct isp_operations qla2100_isp_ops = {
1697         .pci_config             = qla2100_pci_config,
1698         .reset_chip             = qla2x00_reset_chip,
1699         .chip_diag              = qla2x00_chip_diag,
1700         .config_rings           = qla2x00_config_rings,
1701         .reset_adapter          = qla2x00_reset_adapter,
1702         .nvram_config           = qla2x00_nvram_config,
1703         .update_fw_options      = qla2x00_update_fw_options,
1704         .load_risc              = qla2x00_load_risc,
1705         .pci_info_str           = qla2x00_pci_info_str,
1706         .fw_version_str         = qla2x00_fw_version_str,
1707         .intr_handler           = qla2100_intr_handler,
1708         .enable_intrs           = qla2x00_enable_intrs,
1709         .disable_intrs          = qla2x00_disable_intrs,
1710         .abort_command          = qla2x00_abort_command,
1711         .target_reset           = qla2x00_abort_target,
1712         .lun_reset              = qla2x00_lun_reset,
1713         .fabric_login           = qla2x00_login_fabric,
1714         .fabric_logout          = qla2x00_fabric_logout,
1715         .calc_req_entries       = qla2x00_calc_iocbs_32,
1716         .build_iocbs            = qla2x00_build_scsi_iocbs_32,
1717         .prep_ms_iocb           = qla2x00_prep_ms_iocb,
1718         .prep_ms_fdmi_iocb      = qla2x00_prep_ms_fdmi_iocb,
1719         .read_nvram             = qla2x00_read_nvram_data,
1720         .write_nvram            = qla2x00_write_nvram_data,
1721         .fw_dump                = qla2100_fw_dump,
1722         .beacon_on              = NULL,
1723         .beacon_off             = NULL,
1724         .beacon_blink           = NULL,
1725         .read_optrom            = qla2x00_read_optrom_data,
1726         .write_optrom           = qla2x00_write_optrom_data,
1727         .get_flash_version      = qla2x00_get_flash_version,
1728         .start_scsi             = qla2x00_start_scsi,
1729         .abort_isp              = qla2x00_abort_isp,
1730         .iospace_config         = qla2x00_iospace_config,
1731         .initialize_adapter     = qla2x00_initialize_adapter,
1732 };
1733
1734 static struct isp_operations qla2300_isp_ops = {
1735         .pci_config             = qla2300_pci_config,
1736         .reset_chip             = qla2x00_reset_chip,
1737         .chip_diag              = qla2x00_chip_diag,
1738         .config_rings           = qla2x00_config_rings,
1739         .reset_adapter          = qla2x00_reset_adapter,
1740         .nvram_config           = qla2x00_nvram_config,
1741         .update_fw_options      = qla2x00_update_fw_options,
1742         .load_risc              = qla2x00_load_risc,
1743         .pci_info_str           = qla2x00_pci_info_str,
1744         .fw_version_str         = qla2x00_fw_version_str,
1745         .intr_handler           = qla2300_intr_handler,
1746         .enable_intrs           = qla2x00_enable_intrs,
1747         .disable_intrs          = qla2x00_disable_intrs,
1748         .abort_command          = qla2x00_abort_command,
1749         .target_reset           = qla2x00_abort_target,
1750         .lun_reset              = qla2x00_lun_reset,
1751         .fabric_login           = qla2x00_login_fabric,
1752         .fabric_logout          = qla2x00_fabric_logout,
1753         .calc_req_entries       = qla2x00_calc_iocbs_32,
1754         .build_iocbs            = qla2x00_build_scsi_iocbs_32,
1755         .prep_ms_iocb           = qla2x00_prep_ms_iocb,
1756         .prep_ms_fdmi_iocb      = qla2x00_prep_ms_fdmi_iocb,
1757         .read_nvram             = qla2x00_read_nvram_data,
1758         .write_nvram            = qla2x00_write_nvram_data,
1759         .fw_dump                = qla2300_fw_dump,
1760         .beacon_on              = qla2x00_beacon_on,
1761         .beacon_off             = qla2x00_beacon_off,
1762         .beacon_blink           = qla2x00_beacon_blink,
1763         .read_optrom            = qla2x00_read_optrom_data,
1764         .write_optrom           = qla2x00_write_optrom_data,
1765         .get_flash_version      = qla2x00_get_flash_version,
1766         .start_scsi             = qla2x00_start_scsi,
1767         .abort_isp              = qla2x00_abort_isp,
1768         .iospace_config         = qla2x00_iospace_config,
1769         .initialize_adapter     = qla2x00_initialize_adapter,
1770 };
1771
1772 static struct isp_operations qla24xx_isp_ops = {
1773         .pci_config             = qla24xx_pci_config,
1774         .reset_chip             = qla24xx_reset_chip,
1775         .chip_diag              = qla24xx_chip_diag,
1776         .config_rings           = qla24xx_config_rings,
1777         .reset_adapter          = qla24xx_reset_adapter,
1778         .nvram_config           = qla24xx_nvram_config,
1779         .update_fw_options      = qla24xx_update_fw_options,
1780         .load_risc              = qla24xx_load_risc,
1781         .pci_info_str           = qla24xx_pci_info_str,
1782         .fw_version_str         = qla24xx_fw_version_str,
1783         .intr_handler           = qla24xx_intr_handler,
1784         .enable_intrs           = qla24xx_enable_intrs,
1785         .disable_intrs          = qla24xx_disable_intrs,
1786         .abort_command          = qla24xx_abort_command,
1787         .target_reset           = qla24xx_abort_target,
1788         .lun_reset              = qla24xx_lun_reset,
1789         .fabric_login           = qla24xx_login_fabric,
1790         .fabric_logout          = qla24xx_fabric_logout,
1791         .calc_req_entries       = NULL,
1792         .build_iocbs            = NULL,
1793         .prep_ms_iocb           = qla24xx_prep_ms_iocb,
1794         .prep_ms_fdmi_iocb      = qla24xx_prep_ms_fdmi_iocb,
1795         .read_nvram             = qla24xx_read_nvram_data,
1796         .write_nvram            = qla24xx_write_nvram_data,
1797         .fw_dump                = qla24xx_fw_dump,
1798         .beacon_on              = qla24xx_beacon_on,
1799         .beacon_off             = qla24xx_beacon_off,
1800         .beacon_blink           = qla24xx_beacon_blink,
1801         .read_optrom            = qla24xx_read_optrom_data,
1802         .write_optrom           = qla24xx_write_optrom_data,
1803         .get_flash_version      = qla24xx_get_flash_version,
1804         .start_scsi             = qla24xx_start_scsi,
1805         .abort_isp              = qla2x00_abort_isp,
1806         .iospace_config         = qla2x00_iospace_config,
1807         .initialize_adapter     = qla2x00_initialize_adapter,
1808 };
1809
1810 static struct isp_operations qla25xx_isp_ops = {
1811         .pci_config             = qla25xx_pci_config,
1812         .reset_chip             = qla24xx_reset_chip,
1813         .chip_diag              = qla24xx_chip_diag,
1814         .config_rings           = qla24xx_config_rings,
1815         .reset_adapter          = qla24xx_reset_adapter,
1816         .nvram_config           = qla24xx_nvram_config,
1817         .update_fw_options      = qla24xx_update_fw_options,
1818         .load_risc              = qla24xx_load_risc,
1819         .pci_info_str           = qla24xx_pci_info_str,
1820         .fw_version_str         = qla24xx_fw_version_str,
1821         .intr_handler           = qla24xx_intr_handler,
1822         .enable_intrs           = qla24xx_enable_intrs,
1823         .disable_intrs          = qla24xx_disable_intrs,
1824         .abort_command          = qla24xx_abort_command,
1825         .target_reset           = qla24xx_abort_target,
1826         .lun_reset              = qla24xx_lun_reset,
1827         .fabric_login           = qla24xx_login_fabric,
1828         .fabric_logout          = qla24xx_fabric_logout,
1829         .calc_req_entries       = NULL,
1830         .build_iocbs            = NULL,
1831         .prep_ms_iocb           = qla24xx_prep_ms_iocb,
1832         .prep_ms_fdmi_iocb      = qla24xx_prep_ms_fdmi_iocb,
1833         .read_nvram             = qla25xx_read_nvram_data,
1834         .write_nvram            = qla25xx_write_nvram_data,
1835         .fw_dump                = qla25xx_fw_dump,
1836         .beacon_on              = qla24xx_beacon_on,
1837         .beacon_off             = qla24xx_beacon_off,
1838         .beacon_blink           = qla24xx_beacon_blink,
1839         .read_optrom            = qla25xx_read_optrom_data,
1840         .write_optrom           = qla24xx_write_optrom_data,
1841         .get_flash_version      = qla24xx_get_flash_version,
1842         .start_scsi             = qla24xx_dif_start_scsi,
1843         .abort_isp              = qla2x00_abort_isp,
1844         .iospace_config         = qla2x00_iospace_config,
1845         .initialize_adapter     = qla2x00_initialize_adapter,
1846 };
1847
1848 static struct isp_operations qla81xx_isp_ops = {
1849         .pci_config             = qla25xx_pci_config,
1850         .reset_chip             = qla24xx_reset_chip,
1851         .chip_diag              = qla24xx_chip_diag,
1852         .config_rings           = qla24xx_config_rings,
1853         .reset_adapter          = qla24xx_reset_adapter,
1854         .nvram_config           = qla81xx_nvram_config,
1855         .update_fw_options      = qla81xx_update_fw_options,
1856         .load_risc              = qla81xx_load_risc,
1857         .pci_info_str           = qla24xx_pci_info_str,
1858         .fw_version_str         = qla24xx_fw_version_str,
1859         .intr_handler           = qla24xx_intr_handler,
1860         .enable_intrs           = qla24xx_enable_intrs,
1861         .disable_intrs          = qla24xx_disable_intrs,
1862         .abort_command          = qla24xx_abort_command,
1863         .target_reset           = qla24xx_abort_target,
1864         .lun_reset              = qla24xx_lun_reset,
1865         .fabric_login           = qla24xx_login_fabric,
1866         .fabric_logout          = qla24xx_fabric_logout,
1867         .calc_req_entries       = NULL,
1868         .build_iocbs            = NULL,
1869         .prep_ms_iocb           = qla24xx_prep_ms_iocb,
1870         .prep_ms_fdmi_iocb      = qla24xx_prep_ms_fdmi_iocb,
1871         .read_nvram             = NULL,
1872         .write_nvram            = NULL,
1873         .fw_dump                = qla81xx_fw_dump,
1874         .beacon_on              = qla24xx_beacon_on,
1875         .beacon_off             = qla24xx_beacon_off,
1876         .beacon_blink           = qla83xx_beacon_blink,
1877         .read_optrom            = qla25xx_read_optrom_data,
1878         .write_optrom           = qla24xx_write_optrom_data,
1879         .get_flash_version      = qla24xx_get_flash_version,
1880         .start_scsi             = qla24xx_dif_start_scsi,
1881         .abort_isp              = qla2x00_abort_isp,
1882         .iospace_config         = qla2x00_iospace_config,
1883         .initialize_adapter     = qla2x00_initialize_adapter,
1884 };
1885
1886 static struct isp_operations qla82xx_isp_ops = {
1887         .pci_config             = qla82xx_pci_config,
1888         .reset_chip             = qla82xx_reset_chip,
1889         .chip_diag              = qla24xx_chip_diag,
1890         .config_rings           = qla82xx_config_rings,
1891         .reset_adapter          = qla24xx_reset_adapter,
1892         .nvram_config           = qla81xx_nvram_config,
1893         .update_fw_options      = qla24xx_update_fw_options,
1894         .load_risc              = qla82xx_load_risc,
1895         .pci_info_str           = qla24xx_pci_info_str,
1896         .fw_version_str         = qla24xx_fw_version_str,
1897         .intr_handler           = qla82xx_intr_handler,
1898         .enable_intrs           = qla82xx_enable_intrs,
1899         .disable_intrs          = qla82xx_disable_intrs,
1900         .abort_command          = qla24xx_abort_command,
1901         .target_reset           = qla24xx_abort_target,
1902         .lun_reset              = qla24xx_lun_reset,
1903         .fabric_login           = qla24xx_login_fabric,
1904         .fabric_logout          = qla24xx_fabric_logout,
1905         .calc_req_entries       = NULL,
1906         .build_iocbs            = NULL,
1907         .prep_ms_iocb           = qla24xx_prep_ms_iocb,
1908         .prep_ms_fdmi_iocb      = qla24xx_prep_ms_fdmi_iocb,
1909         .read_nvram             = qla24xx_read_nvram_data,
1910         .write_nvram            = qla24xx_write_nvram_data,
1911         .fw_dump                = qla82xx_fw_dump,
1912         .beacon_on              = qla82xx_beacon_on,
1913         .beacon_off             = qla82xx_beacon_off,
1914         .beacon_blink           = NULL,
1915         .read_optrom            = qla82xx_read_optrom_data,
1916         .write_optrom           = qla82xx_write_optrom_data,
1917         .get_flash_version      = qla82xx_get_flash_version,
1918         .start_scsi             = qla82xx_start_scsi,
1919         .abort_isp              = qla82xx_abort_isp,
1920         .iospace_config         = qla82xx_iospace_config,
1921         .initialize_adapter     = qla2x00_initialize_adapter,
1922 };
1923
1924 static struct isp_operations qla8044_isp_ops = {
1925         .pci_config             = qla82xx_pci_config,
1926         .reset_chip             = qla82xx_reset_chip,
1927         .chip_diag              = qla24xx_chip_diag,
1928         .config_rings           = qla82xx_config_rings,
1929         .reset_adapter          = qla24xx_reset_adapter,
1930         .nvram_config           = qla81xx_nvram_config,
1931         .update_fw_options      = qla24xx_update_fw_options,
1932         .load_risc              = qla82xx_load_risc,
1933         .pci_info_str           = qla24xx_pci_info_str,
1934         .fw_version_str         = qla24xx_fw_version_str,
1935         .intr_handler           = qla8044_intr_handler,
1936         .enable_intrs           = qla82xx_enable_intrs,
1937         .disable_intrs          = qla82xx_disable_intrs,
1938         .abort_command          = qla24xx_abort_command,
1939         .target_reset           = qla24xx_abort_target,
1940         .lun_reset              = qla24xx_lun_reset,
1941         .fabric_login           = qla24xx_login_fabric,
1942         .fabric_logout          = qla24xx_fabric_logout,
1943         .calc_req_entries       = NULL,
1944         .build_iocbs            = NULL,
1945         .prep_ms_iocb           = qla24xx_prep_ms_iocb,
1946         .prep_ms_fdmi_iocb      = qla24xx_prep_ms_fdmi_iocb,
1947         .read_nvram             = NULL,
1948         .write_nvram            = NULL,
1949         .fw_dump                = qla8044_fw_dump,
1950         .beacon_on              = qla82xx_beacon_on,
1951         .beacon_off             = qla82xx_beacon_off,
1952         .beacon_blink           = NULL,
1953         .read_optrom            = qla8044_read_optrom_data,
1954         .write_optrom           = qla8044_write_optrom_data,
1955         .get_flash_version      = qla82xx_get_flash_version,
1956         .start_scsi             = qla82xx_start_scsi,
1957         .abort_isp              = qla8044_abort_isp,
1958         .iospace_config         = qla82xx_iospace_config,
1959         .initialize_adapter     = qla2x00_initialize_adapter,
1960 };
1961
1962 static struct isp_operations qla83xx_isp_ops = {
1963         .pci_config             = qla25xx_pci_config,
1964         .reset_chip             = qla24xx_reset_chip,
1965         .chip_diag              = qla24xx_chip_diag,
1966         .config_rings           = qla24xx_config_rings,
1967         .reset_adapter          = qla24xx_reset_adapter,
1968         .nvram_config           = qla81xx_nvram_config,
1969         .update_fw_options      = qla81xx_update_fw_options,
1970         .load_risc              = qla81xx_load_risc,
1971         .pci_info_str           = qla24xx_pci_info_str,
1972         .fw_version_str         = qla24xx_fw_version_str,
1973         .intr_handler           = qla24xx_intr_handler,
1974         .enable_intrs           = qla24xx_enable_intrs,
1975         .disable_intrs          = qla24xx_disable_intrs,
1976         .abort_command          = qla24xx_abort_command,
1977         .target_reset           = qla24xx_abort_target,
1978         .lun_reset              = qla24xx_lun_reset,
1979         .fabric_login           = qla24xx_login_fabric,
1980         .fabric_logout          = qla24xx_fabric_logout,
1981         .calc_req_entries       = NULL,
1982         .build_iocbs            = NULL,
1983         .prep_ms_iocb           = qla24xx_prep_ms_iocb,
1984         .prep_ms_fdmi_iocb      = qla24xx_prep_ms_fdmi_iocb,
1985         .read_nvram             = NULL,
1986         .write_nvram            = NULL,
1987         .fw_dump                = qla83xx_fw_dump,
1988         .beacon_on              = qla24xx_beacon_on,
1989         .beacon_off             = qla24xx_beacon_off,
1990         .beacon_blink           = qla83xx_beacon_blink,
1991         .read_optrom            = qla25xx_read_optrom_data,
1992         .write_optrom           = qla24xx_write_optrom_data,
1993         .get_flash_version      = qla24xx_get_flash_version,
1994         .start_scsi             = qla24xx_dif_start_scsi,
1995         .abort_isp              = qla2x00_abort_isp,
1996         .iospace_config         = qla83xx_iospace_config,
1997         .initialize_adapter     = qla2x00_initialize_adapter,
1998 };
1999
2000 static struct isp_operations qlafx00_isp_ops = {
2001         .pci_config             = qlafx00_pci_config,
2002         .reset_chip             = qlafx00_soft_reset,
2003         .chip_diag              = qlafx00_chip_diag,
2004         .config_rings           = qlafx00_config_rings,
2005         .reset_adapter          = qlafx00_soft_reset,
2006         .nvram_config           = NULL,
2007         .update_fw_options      = NULL,
2008         .load_risc              = NULL,
2009         .pci_info_str           = qlafx00_pci_info_str,
2010         .fw_version_str         = qlafx00_fw_version_str,
2011         .intr_handler           = qlafx00_intr_handler,
2012         .enable_intrs           = qlafx00_enable_intrs,
2013         .disable_intrs          = qlafx00_disable_intrs,
2014         .abort_command          = qla24xx_async_abort_command,
2015         .target_reset           = qlafx00_abort_target,
2016         .lun_reset              = qlafx00_lun_reset,
2017         .fabric_login           = NULL,
2018         .fabric_logout          = NULL,
2019         .calc_req_entries       = NULL,
2020         .build_iocbs            = NULL,
2021         .prep_ms_iocb           = qla24xx_prep_ms_iocb,
2022         .prep_ms_fdmi_iocb      = qla24xx_prep_ms_fdmi_iocb,
2023         .read_nvram             = qla24xx_read_nvram_data,
2024         .write_nvram            = qla24xx_write_nvram_data,
2025         .fw_dump                = NULL,
2026         .beacon_on              = qla24xx_beacon_on,
2027         .beacon_off             = qla24xx_beacon_off,
2028         .beacon_blink           = NULL,
2029         .read_optrom            = qla24xx_read_optrom_data,
2030         .write_optrom           = qla24xx_write_optrom_data,
2031         .get_flash_version      = qla24xx_get_flash_version,
2032         .start_scsi             = qlafx00_start_scsi,
2033         .abort_isp              = qlafx00_abort_isp,
2034         .iospace_config         = qlafx00_iospace_config,
2035         .initialize_adapter     = qlafx00_initialize_adapter,
2036 };
2037
2038 static struct isp_operations qla27xx_isp_ops = {
2039         .pci_config             = qla25xx_pci_config,
2040         .reset_chip             = qla24xx_reset_chip,
2041         .chip_diag              = qla24xx_chip_diag,
2042         .config_rings           = qla24xx_config_rings,
2043         .reset_adapter          = qla24xx_reset_adapter,
2044         .nvram_config           = qla81xx_nvram_config,
2045         .update_fw_options      = qla81xx_update_fw_options,
2046         .load_risc              = qla81xx_load_risc,
2047         .pci_info_str           = qla24xx_pci_info_str,
2048         .fw_version_str         = qla24xx_fw_version_str,
2049         .intr_handler           = qla24xx_intr_handler,
2050         .enable_intrs           = qla24xx_enable_intrs,
2051         .disable_intrs          = qla24xx_disable_intrs,
2052         .abort_command          = qla24xx_abort_command,
2053         .target_reset           = qla24xx_abort_target,
2054         .lun_reset              = qla24xx_lun_reset,
2055         .fabric_login           = qla24xx_login_fabric,
2056         .fabric_logout          = qla24xx_fabric_logout,
2057         .calc_req_entries       = NULL,
2058         .build_iocbs            = NULL,
2059         .prep_ms_iocb           = qla24xx_prep_ms_iocb,
2060         .prep_ms_fdmi_iocb      = qla24xx_prep_ms_fdmi_iocb,
2061         .read_nvram             = NULL,
2062         .write_nvram            = NULL,
2063         .fw_dump                = qla27xx_fwdump,
2064         .beacon_on              = qla24xx_beacon_on,
2065         .beacon_off             = qla24xx_beacon_off,
2066         .beacon_blink           = qla83xx_beacon_blink,
2067         .read_optrom            = qla25xx_read_optrom_data,
2068         .write_optrom           = qla24xx_write_optrom_data,
2069         .get_flash_version      = qla24xx_get_flash_version,
2070         .start_scsi             = qla24xx_dif_start_scsi,
2071         .abort_isp              = qla2x00_abort_isp,
2072         .iospace_config         = qla83xx_iospace_config,
2073         .initialize_adapter     = qla2x00_initialize_adapter,
2074 };
2075
2076 static inline void
2077 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2078 {
2079         ha->device_type = DT_EXTENDED_IDS;
2080         switch (ha->pdev->device) {
2081         case PCI_DEVICE_ID_QLOGIC_ISP2100:
2082                 ha->device_type |= DT_ISP2100;
2083                 ha->device_type &= ~DT_EXTENDED_IDS;
2084                 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2085                 break;
2086         case PCI_DEVICE_ID_QLOGIC_ISP2200:
2087                 ha->device_type |= DT_ISP2200;
2088                 ha->device_type &= ~DT_EXTENDED_IDS;
2089                 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2090                 break;
2091         case PCI_DEVICE_ID_QLOGIC_ISP2300:
2092                 ha->device_type |= DT_ISP2300;
2093                 ha->device_type |= DT_ZIO_SUPPORTED;
2094                 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2095                 break;
2096         case PCI_DEVICE_ID_QLOGIC_ISP2312:
2097                 ha->device_type |= DT_ISP2312;
2098                 ha->device_type |= DT_ZIO_SUPPORTED;
2099                 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2100                 break;
2101         case PCI_DEVICE_ID_QLOGIC_ISP2322:
2102                 ha->device_type |= DT_ISP2322;
2103                 ha->device_type |= DT_ZIO_SUPPORTED;
2104                 if (ha->pdev->subsystem_vendor == 0x1028 &&
2105                     ha->pdev->subsystem_device == 0x0170)
2106                         ha->device_type |= DT_OEM_001;
2107                 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2108                 break;
2109         case PCI_DEVICE_ID_QLOGIC_ISP6312:
2110                 ha->device_type |= DT_ISP6312;
2111                 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2112                 break;
2113         case PCI_DEVICE_ID_QLOGIC_ISP6322:
2114                 ha->device_type |= DT_ISP6322;
2115                 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2116                 break;
2117         case PCI_DEVICE_ID_QLOGIC_ISP2422:
2118                 ha->device_type |= DT_ISP2422;
2119                 ha->device_type |= DT_ZIO_SUPPORTED;
2120                 ha->device_type |= DT_FWI2;
2121                 ha->device_type |= DT_IIDMA;
2122                 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2123                 break;
2124         case PCI_DEVICE_ID_QLOGIC_ISP2432:
2125                 ha->device_type |= DT_ISP2432;
2126                 ha->device_type |= DT_ZIO_SUPPORTED;
2127                 ha->device_type |= DT_FWI2;
2128                 ha->device_type |= DT_IIDMA;
2129                 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2130                 break;
2131         case PCI_DEVICE_ID_QLOGIC_ISP8432:
2132                 ha->device_type |= DT_ISP8432;
2133                 ha->device_type |= DT_ZIO_SUPPORTED;
2134                 ha->device_type |= DT_FWI2;
2135                 ha->device_type |= DT_IIDMA;
2136                 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2137                 break;
2138         case PCI_DEVICE_ID_QLOGIC_ISP5422:
2139                 ha->device_type |= DT_ISP5422;
2140                 ha->device_type |= DT_FWI2;
2141                 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2142                 break;
2143         case PCI_DEVICE_ID_QLOGIC_ISP5432:
2144                 ha->device_type |= DT_ISP5432;
2145                 ha->device_type |= DT_FWI2;
2146                 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2147                 break;
2148         case PCI_DEVICE_ID_QLOGIC_ISP2532:
2149                 ha->device_type |= DT_ISP2532;
2150                 ha->device_type |= DT_ZIO_SUPPORTED;
2151                 ha->device_type |= DT_FWI2;
2152                 ha->device_type |= DT_IIDMA;
2153                 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2154                 break;
2155         case PCI_DEVICE_ID_QLOGIC_ISP8001:
2156                 ha->device_type |= DT_ISP8001;
2157                 ha->device_type |= DT_ZIO_SUPPORTED;
2158                 ha->device_type |= DT_FWI2;
2159                 ha->device_type |= DT_IIDMA;
2160                 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2161                 break;
2162         case PCI_DEVICE_ID_QLOGIC_ISP8021:
2163                 ha->device_type |= DT_ISP8021;
2164                 ha->device_type |= DT_ZIO_SUPPORTED;
2165                 ha->device_type |= DT_FWI2;
2166                 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2167                 /* Initialize 82XX ISP flags */
2168                 qla82xx_init_flags(ha);
2169                 break;
2170          case PCI_DEVICE_ID_QLOGIC_ISP8044:
2171                 ha->device_type |= DT_ISP8044;
2172                 ha->device_type |= DT_ZIO_SUPPORTED;
2173                 ha->device_type |= DT_FWI2;
2174                 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2175                 /* Initialize 82XX ISP flags */
2176                 qla82xx_init_flags(ha);
2177                 break;
2178         case PCI_DEVICE_ID_QLOGIC_ISP2031:
2179                 ha->device_type |= DT_ISP2031;
2180                 ha->device_type |= DT_ZIO_SUPPORTED;
2181                 ha->device_type |= DT_FWI2;
2182                 ha->device_type |= DT_IIDMA;
2183                 ha->device_type |= DT_T10_PI;
2184                 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2185                 break;
2186         case PCI_DEVICE_ID_QLOGIC_ISP8031:
2187                 ha->device_type |= DT_ISP8031;
2188                 ha->device_type |= DT_ZIO_SUPPORTED;
2189                 ha->device_type |= DT_FWI2;
2190                 ha->device_type |= DT_IIDMA;
2191                 ha->device_type |= DT_T10_PI;
2192                 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2193                 break;
2194         case PCI_DEVICE_ID_QLOGIC_ISPF001:
2195                 ha->device_type |= DT_ISPFX00;
2196                 break;
2197         case PCI_DEVICE_ID_QLOGIC_ISP2071:
2198                 ha->device_type |= DT_ISP2071;
2199                 ha->device_type |= DT_ZIO_SUPPORTED;
2200                 ha->device_type |= DT_FWI2;
2201                 ha->device_type |= DT_IIDMA;
2202                 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2203                 break;
2204         case PCI_DEVICE_ID_QLOGIC_ISP2271:
2205                 ha->device_type |= DT_ISP2271;
2206                 ha->device_type |= DT_ZIO_SUPPORTED;
2207                 ha->device_type |= DT_FWI2;
2208                 ha->device_type |= DT_IIDMA;
2209                 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2210                 break;
2211         }
2212
2213         if (IS_QLA82XX(ha))
2214                 ha->port_no = ha->portnum & 1;
2215         else {
2216                 /* Get adapter physical port no from interrupt pin register. */
2217                 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2218                 if (IS_QLA27XX(ha))
2219                         ha->port_no--;
2220                 else
2221                         ha->port_no = !(ha->port_no & 1);
2222         }
2223
2224         ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2225             "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2226             ha->device_type, ha->port_no, ha->fw_srisc_address);
2227 }
2228
2229 static void
2230 qla2xxx_scan_start(struct Scsi_Host *shost)
2231 {
2232         scsi_qla_host_t *vha = shost_priv(shost);
2233
2234         if (vha->hw->flags.running_gold_fw)
2235                 return;
2236
2237         set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2238         set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2239         set_bit(RSCN_UPDATE, &vha->dpc_flags);
2240         set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2241 }
2242
2243 static int
2244 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2245 {
2246         scsi_qla_host_t *vha = shost_priv(shost);
2247
2248         if (!vha->host)
2249                 return 1;
2250         if (time > vha->hw->loop_reset_delay * HZ)
2251                 return 1;
2252
2253         return atomic_read(&vha->loop_state) == LOOP_READY;
2254 }
2255
2256 /*
2257  * PCI driver interface
2258  */
2259 static int
2260 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2261 {
2262         int     ret = -ENODEV;
2263         struct Scsi_Host *host;
2264         scsi_qla_host_t *base_vha = NULL;
2265         struct qla_hw_data *ha;
2266         char pci_info[30];
2267         char fw_str[30], wq_name[30];
2268         struct scsi_host_template *sht;
2269         int bars, mem_only = 0;
2270         uint16_t req_length = 0, rsp_length = 0;
2271         struct req_que *req = NULL;
2272         struct rsp_que *rsp = NULL;
2273         bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2274         sht = &qla2xxx_driver_template;
2275         if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2276             pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2277             pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2278             pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2279             pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2280             pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2281             pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2282             pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2283             pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2284             pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2285             pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2286             pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2287             pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2288             pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271) {
2289                 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2290                 mem_only = 1;
2291                 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2292                     "Mem only adapter.\n");
2293         }
2294         ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2295             "Bars=%d.\n", bars);
2296
2297         if (mem_only) {
2298                 if (pci_enable_device_mem(pdev))
2299                         goto probe_out;
2300         } else {
2301                 if (pci_enable_device(pdev))
2302                         goto probe_out;
2303         }
2304
2305         /* This may fail but that's ok */
2306         pci_enable_pcie_error_reporting(pdev);
2307
2308         ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2309         if (!ha) {
2310                 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2311                     "Unable to allocate memory for ha.\n");
2312                 goto probe_out;
2313         }
2314         ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2315             "Memory allocated for ha=%p.\n", ha);
2316         ha->pdev = pdev;
2317         ha->tgt.enable_class_2 = ql2xenableclass2;
2318         INIT_LIST_HEAD(&ha->tgt.q_full_list);
2319         spin_lock_init(&ha->tgt.q_full_lock);
2320
2321         /* Clear our data area */
2322         ha->bars = bars;
2323         ha->mem_only = mem_only;
2324         spin_lock_init(&ha->hardware_lock);
2325         spin_lock_init(&ha->vport_slock);
2326         mutex_init(&ha->selflogin_lock);
2327         mutex_init(&ha->optrom_mutex);
2328
2329         /* Set ISP-type information. */
2330         qla2x00_set_isp_flags(ha);
2331
2332         /* Set EEH reset type to fundamental if required by hba */
2333         if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2334             IS_QLA83XX(ha) || IS_QLA27XX(ha))
2335                 pdev->needs_freset = 1;
2336
2337         ha->prev_topology = 0;
2338         ha->init_cb_size = sizeof(init_cb_t);
2339         ha->link_data_rate = PORT_SPEED_UNKNOWN;
2340         ha->optrom_size = OPTROM_SIZE_2300;
2341
2342         /* Assign ISP specific operations. */
2343         if (IS_QLA2100(ha)) {
2344                 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2345                 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2346                 req_length = REQUEST_ENTRY_CNT_2100;
2347                 rsp_length = RESPONSE_ENTRY_CNT_2100;
2348                 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2349                 ha->gid_list_info_size = 4;
2350                 ha->flash_conf_off = ~0;
2351                 ha->flash_data_off = ~0;
2352                 ha->nvram_conf_off = ~0;
2353                 ha->nvram_data_off = ~0;
2354                 ha->isp_ops = &qla2100_isp_ops;
2355         } else if (IS_QLA2200(ha)) {
2356                 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2357                 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
2358                 req_length = REQUEST_ENTRY_CNT_2200;
2359                 rsp_length = RESPONSE_ENTRY_CNT_2100;
2360                 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2361                 ha->gid_list_info_size = 4;
2362                 ha->flash_conf_off = ~0;
2363                 ha->flash_data_off = ~0;
2364                 ha->nvram_conf_off = ~0;
2365                 ha->nvram_data_off = ~0;
2366                 ha->isp_ops = &qla2100_isp_ops;
2367         } else if (IS_QLA23XX(ha)) {
2368                 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2369                 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2370                 req_length = REQUEST_ENTRY_CNT_2200;
2371                 rsp_length = RESPONSE_ENTRY_CNT_2300;
2372                 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2373                 ha->gid_list_info_size = 6;
2374                 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2375                         ha->optrom_size = OPTROM_SIZE_2322;
2376                 ha->flash_conf_off = ~0;
2377                 ha->flash_data_off = ~0;
2378                 ha->nvram_conf_off = ~0;
2379                 ha->nvram_data_off = ~0;
2380                 ha->isp_ops = &qla2300_isp_ops;
2381         } else if (IS_QLA24XX_TYPE(ha)) {
2382                 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2383                 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2384                 req_length = REQUEST_ENTRY_CNT_24XX;
2385                 rsp_length = RESPONSE_ENTRY_CNT_2300;
2386                 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2387                 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2388                 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2389                 ha->gid_list_info_size = 8;
2390                 ha->optrom_size = OPTROM_SIZE_24XX;
2391                 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
2392                 ha->isp_ops = &qla24xx_isp_ops;
2393                 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2394                 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2395                 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2396                 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2397         } else if (IS_QLA25XX(ha)) {
2398                 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2399                 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2400                 req_length = REQUEST_ENTRY_CNT_24XX;
2401                 rsp_length = RESPONSE_ENTRY_CNT_2300;
2402                 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2403                 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2404                 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2405                 ha->gid_list_info_size = 8;
2406                 ha->optrom_size = OPTROM_SIZE_25XX;
2407                 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2408                 ha->isp_ops = &qla25xx_isp_ops;
2409                 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2410                 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2411                 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2412                 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2413         } else if (IS_QLA81XX(ha)) {
2414                 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2415                 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2416                 req_length = REQUEST_ENTRY_CNT_24XX;
2417                 rsp_length = RESPONSE_ENTRY_CNT_2300;
2418                 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2419                 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2420                 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2421                 ha->gid_list_info_size = 8;
2422                 ha->optrom_size = OPTROM_SIZE_81XX;
2423                 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2424                 ha->isp_ops = &qla81xx_isp_ops;
2425                 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2426                 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2427                 ha->nvram_conf_off = ~0;
2428                 ha->nvram_data_off = ~0;
2429         } else if (IS_QLA82XX(ha)) {
2430                 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2431                 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2432                 req_length = REQUEST_ENTRY_CNT_82XX;
2433                 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2434                 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2435                 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2436                 ha->gid_list_info_size = 8;
2437                 ha->optrom_size = OPTROM_SIZE_82XX;
2438                 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2439                 ha->isp_ops = &qla82xx_isp_ops;
2440                 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2441                 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2442                 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2443                 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2444         } else if (IS_QLA8044(ha)) {
2445                 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2446                 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2447                 req_length = REQUEST_ENTRY_CNT_82XX;
2448                 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2449                 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2450                 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2451                 ha->gid_list_info_size = 8;
2452                 ha->optrom_size = OPTROM_SIZE_83XX;
2453                 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2454                 ha->isp_ops = &qla8044_isp_ops;
2455                 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2456                 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2457                 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2458                 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2459         } else if (IS_QLA83XX(ha)) {
2460                 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2461                 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2462                 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2463                 req_length = REQUEST_ENTRY_CNT_83XX;
2464                 rsp_length = RESPONSE_ENTRY_CNT_2300;
2465                 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2466                 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2467                 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2468                 ha->gid_list_info_size = 8;
2469                 ha->optrom_size = OPTROM_SIZE_83XX;
2470                 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2471                 ha->isp_ops = &qla83xx_isp_ops;
2472                 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2473                 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2474                 ha->nvram_conf_off = ~0;
2475                 ha->nvram_data_off = ~0;
2476         }  else if (IS_QLAFX00(ha)) {
2477                 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2478                 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2479                 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2480                 req_length = REQUEST_ENTRY_CNT_FX00;
2481                 rsp_length = RESPONSE_ENTRY_CNT_FX00;
2482                 ha->isp_ops = &qlafx00_isp_ops;
2483                 ha->port_down_retry_count = 30; /* default value */
2484                 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2485                 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
2486                 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
2487                 ha->mr.fw_hbt_en = 1;
2488                 ha->mr.host_info_resend = false;
2489                 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
2490         } else if (IS_QLA27XX(ha)) {
2491                 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2492                 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2493                 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2494                 req_length = REQUEST_ENTRY_CNT_24XX;
2495                 rsp_length = RESPONSE_ENTRY_CNT_2300;
2496                 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2497                 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2498                 ha->gid_list_info_size = 8;
2499                 ha->optrom_size = OPTROM_SIZE_83XX;
2500                 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2501                 ha->isp_ops = &qla27xx_isp_ops;
2502                 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2503                 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2504                 ha->nvram_conf_off = ~0;
2505                 ha->nvram_data_off = ~0;
2506         }
2507
2508         ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2509             "mbx_count=%d, req_length=%d, "
2510             "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
2511             "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2512             "max_fibre_devices=%d.\n",
2513             ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2514             ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
2515             ha->nvram_npiv_size, ha->max_fibre_devices);
2516         ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2517             "isp_ops=%p, flash_conf_off=%d, "
2518             "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2519             ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2520             ha->nvram_conf_off, ha->nvram_data_off);
2521
2522         /* Configure PCI I/O space */
2523         ret = ha->isp_ops->iospace_config(ha);
2524         if (ret)
2525                 goto iospace_config_failed;
2526
2527         ql_log_pci(ql_log_info, pdev, 0x001d,
2528             "Found an ISP%04X irq %d iobase 0x%p.\n",
2529             pdev->device, pdev->irq, ha->iobase);
2530         mutex_init(&ha->vport_lock);
2531         init_completion(&ha->mbx_cmd_comp);
2532         complete(&ha->mbx_cmd_comp);
2533         init_completion(&ha->mbx_intr_comp);
2534         init_completion(&ha->dcbx_comp);
2535         init_completion(&ha->lb_portup_comp);
2536
2537         set_bit(0, (unsigned long *) ha->vp_idx_map);
2538
2539         qla2x00_config_dma_addressing(ha);
2540         ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2541             "64 Bit addressing is %s.\n",
2542             ha->flags.enable_64bit_addressing ? "enable" :
2543             "disable");
2544         ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
2545         if (ret) {
2546                 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2547                     "Failed to allocate memory for adapter, aborting.\n");
2548
2549                 goto probe_hw_failed;
2550         }
2551
2552         req->max_q_depth = MAX_Q_DEPTH;
2553         if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
2554                 req->max_q_depth = ql2xmaxqdepth;
2555
2556
2557         base_vha = qla2x00_create_host(sht, ha);
2558         if (!base_vha) {
2559                 ret = -ENOMEM;
2560                 qla2x00_mem_free(ha);
2561                 qla2x00_free_req_que(ha, req);
2562                 qla2x00_free_rsp_que(ha, rsp);
2563                 goto probe_hw_failed;
2564         }
2565
2566         pci_set_drvdata(pdev, base_vha);
2567         set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
2568
2569         host = base_vha->host;
2570         base_vha->req = req;
2571         if (IS_QLA2XXX_MIDTYPE(ha))
2572                 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
2573         else
2574                 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2575                                                 base_vha->vp_idx;
2576
2577         /* Setup fcport template structure. */
2578         ha->mr.fcport.vha = base_vha;
2579         ha->mr.fcport.port_type = FCT_UNKNOWN;
2580         ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2581         qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2582         ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2583         ha->mr.fcport.scan_state = 1;
2584
2585         /* Set the SG table size based on ISP type */
2586         if (!IS_FWI2_CAPABLE(ha)) {
2587                 if (IS_QLA2100(ha))
2588                         host->sg_tablesize = 32;
2589         } else {
2590                 if (!IS_QLA82XX(ha))
2591                         host->sg_tablesize = QLA_SG_ALL;
2592         }
2593         host->max_id = ha->max_fibre_devices;
2594         host->cmd_per_lun = 3;
2595         host->unique_id = host->host_no;
2596         if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
2597                 host->max_cmd_len = 32;
2598         else
2599                 host->max_cmd_len = MAX_CMDSZ;
2600         host->max_channel = MAX_BUSES - 1;
2601         /* Older HBAs support only 16-bit LUNs */
2602         if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2603             ql2xmaxlun > 0xffff)
2604                 host->max_lun = 0xffff;
2605         else
2606                 host->max_lun = ql2xmaxlun;
2607         host->transportt = qla2xxx_transport_template;
2608         sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
2609
2610         ql_dbg(ql_dbg_init, base_vha, 0x0033,
2611             "max_id=%d this_id=%d "
2612             "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
2613             "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
2614             host->this_id, host->cmd_per_lun, host->unique_id,
2615             host->max_cmd_len, host->max_channel, host->max_lun,
2616             host->transportt, sht->vendor_id);
2617
2618 que_init:
2619         /* Alloc arrays of request and response ring ptrs */
2620         if (!qla2x00_alloc_queues(ha, req, rsp)) {
2621                 ql_log(ql_log_fatal, base_vha, 0x003d,
2622                     "Failed to allocate memory for queue pointers..."
2623                     "aborting.\n");
2624                 goto probe_init_failed;
2625         }
2626
2627         qlt_probe_one_stage1(base_vha, ha);
2628
2629         /* Set up the irqs */
2630         ret = qla2x00_request_irqs(ha, rsp);
2631         if (ret)
2632                 goto probe_init_failed;
2633
2634         pci_save_state(pdev);
2635
2636         /* Assign back pointers */
2637         rsp->req = req;
2638         req->rsp = rsp;
2639
2640         if (IS_QLAFX00(ha)) {
2641                 ha->rsp_q_map[0] = rsp;
2642                 ha->req_q_map[0] = req;
2643                 set_bit(0, ha->req_qid_map);
2644                 set_bit(0, ha->rsp_qid_map);
2645         }
2646
2647         /* FWI2-capable only. */
2648         req->req_q_in = &ha->iobase->isp24.req_q_in;
2649         req->req_q_out = &ha->iobase->isp24.req_q_out;
2650         rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2651         rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
2652         if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
2653                 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2654                 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2655                 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2656                 rsp->rsp_q_out =  &ha->mqiobase->isp25mq.rsp_q_out;
2657         }
2658
2659         if (IS_QLAFX00(ha)) {
2660                 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2661                 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2662                 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2663                 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2664         }
2665
2666         if (IS_P3P_TYPE(ha)) {
2667                 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2668                 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2669                 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2670         }
2671
2672         ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2673             "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2674             ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2675         ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2676             "req->req_q_in=%p req->req_q_out=%p "
2677             "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2678             req->req_q_in, req->req_q_out,
2679             rsp->rsp_q_in, rsp->rsp_q_out);
2680         ql_dbg(ql_dbg_init, base_vha, 0x003e,
2681             "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2682             ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2683         ql_dbg(ql_dbg_init, base_vha, 0x003f,
2684             "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2685             req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
2686
2687         if (ha->isp_ops->initialize_adapter(base_vha)) {
2688                 ql_log(ql_log_fatal, base_vha, 0x00d6,
2689                     "Failed to initialize adapter - Adapter flags %x.\n",
2690                     base_vha->device_flags);
2691
2692                 if (IS_QLA82XX(ha)) {
2693                         qla82xx_idc_lock(ha);
2694                         qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2695                                 QLA8XXX_DEV_FAILED);
2696                         qla82xx_idc_unlock(ha);
2697                         ql_log(ql_log_fatal, base_vha, 0x00d7,
2698                             "HW State: FAILED.\n");
2699                 } else if (IS_QLA8044(ha)) {
2700                         qla8044_idc_lock(ha);
2701                         qla8044_wr_direct(base_vha,
2702                                 QLA8044_CRB_DEV_STATE_INDEX,
2703                                 QLA8XXX_DEV_FAILED);
2704                         qla8044_idc_unlock(ha);
2705                         ql_log(ql_log_fatal, base_vha, 0x0150,
2706                             "HW State: FAILED.\n");
2707                 }
2708
2709                 ret = -ENODEV;
2710                 goto probe_failed;
2711         }
2712
2713         if (IS_QLAFX00(ha))
2714                 host->can_queue = QLAFX00_MAX_CANQUEUE;
2715         else
2716                 host->can_queue = req->num_outstanding_cmds - 10;
2717
2718         ql_dbg(ql_dbg_init, base_vha, 0x0032,
2719             "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2720             host->can_queue, base_vha->req,
2721             base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2722
2723         if (ha->mqenable) {
2724                 if (qla25xx_setup_mode(base_vha)) {
2725                         ql_log(ql_log_warn, base_vha, 0x00ec,
2726                             "Failed to create queues, falling back to single queue mode.\n");
2727                         goto que_init;
2728                 }
2729         }
2730
2731         if (ha->flags.running_gold_fw)
2732                 goto skip_dpc;
2733
2734         /*
2735          * Startup the kernel thread for this host adapter
2736          */
2737         ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
2738             "%s_dpc", base_vha->host_str);
2739         if (IS_ERR(ha->dpc_thread)) {
2740                 ql_log(ql_log_fatal, base_vha, 0x00ed,
2741                     "Failed to start DPC thread.\n");
2742                 ret = PTR_ERR(ha->dpc_thread);
2743                 goto probe_failed;
2744         }
2745         ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2746             "DPC thread started successfully.\n");
2747
2748         /*
2749          * If we're not coming up in initiator mode, we might sit for
2750          * a while without waking up the dpc thread, which leads to a
2751          * stuck process warning.  So just kick the dpc once here and
2752          * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2753          */
2754         qla2xxx_wake_dpc(base_vha);
2755
2756         INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2757
2758         if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2759                 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2760                 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2761                 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2762
2763                 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2764                 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2765                 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2766                 INIT_WORK(&ha->idc_state_handler,
2767                     qla83xx_idc_state_handler_work);
2768                 INIT_WORK(&ha->nic_core_unrecoverable,
2769                     qla83xx_nic_core_unrecoverable_work);
2770         }
2771
2772 skip_dpc:
2773         list_add_tail(&base_vha->list, &ha->vp_list);
2774         base_vha->host->irq = ha->pdev->irq;
2775
2776         /* Initialized the timer */
2777         qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
2778         ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2779             "Started qla2x00_timer with "
2780             "interval=%d.\n", WATCH_INTERVAL);
2781         ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2782             "Detected hba at address=%p.\n",
2783             ha);
2784
2785         if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
2786                 if (ha->fw_attributes & BIT_4) {
2787                         int prot = 0, guard;
2788                         base_vha->flags.difdix_supported = 1;
2789                         ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2790                             "Registering for DIF/DIX type 1 and 3 protection.\n");
2791                         if (ql2xenabledif == 1)
2792                                 prot = SHOST_DIX_TYPE0_PROTECTION;
2793                         scsi_host_set_prot(host,
2794                             prot | SHOST_DIF_TYPE1_PROTECTION
2795                             | SHOST_DIF_TYPE2_PROTECTION
2796                             | SHOST_DIF_TYPE3_PROTECTION
2797                             | SHOST_DIX_TYPE1_PROTECTION
2798                             | SHOST_DIX_TYPE2_PROTECTION
2799                             | SHOST_DIX_TYPE3_PROTECTION);
2800
2801                         guard = SHOST_DIX_GUARD_CRC;
2802
2803                         if (IS_PI_IPGUARD_CAPABLE(ha) &&
2804                             (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2805                                 guard |= SHOST_DIX_GUARD_IP;
2806
2807                         scsi_host_set_guard(host, guard);
2808                 } else
2809                         base_vha->flags.difdix_supported = 0;
2810         }
2811
2812         ha->isp_ops->enable_intrs(ha);
2813
2814         if (IS_QLAFX00(ha)) {
2815                 ret = qlafx00_fx_disc(base_vha,
2816                         &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2817                 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2818                     QLA_SG_ALL : 128;
2819         }
2820
2821         ret = scsi_add_host(host, &pdev->dev);
2822         if (ret)
2823                 goto probe_failed;
2824
2825         base_vha->flags.init_done = 1;
2826         base_vha->flags.online = 1;
2827         ha->prev_minidump_failed = 0;
2828
2829         ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2830             "Init done and hba is online.\n");
2831
2832         if (qla_ini_mode_enabled(base_vha))
2833                 scsi_scan_host(host);
2834         else
2835                 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2836                         "skipping scsi_scan_host() for non-initiator port\n");
2837
2838         qla2x00_alloc_sysfs_attr(base_vha);
2839
2840         if (IS_QLAFX00(ha)) {
2841                 ret = qlafx00_fx_disc(base_vha,
2842                         &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2843
2844                 /* Register system information */
2845                 ret =  qlafx00_fx_disc(base_vha,
2846                         &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2847         }
2848
2849         qla2x00_init_host_attr(base_vha);
2850
2851         qla2x00_dfs_setup(base_vha);
2852
2853         ql_log(ql_log_info, base_vha, 0x00fb,
2854             "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
2855         ql_log(ql_log_info, base_vha, 0x00fc,
2856             "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2857             pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2858             pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2859             base_vha->host_no,
2860             ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
2861
2862         qlt_add_target(ha, base_vha);
2863
2864         clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
2865         return 0;
2866
2867 probe_init_failed:
2868         qla2x00_free_req_que(ha, req);
2869         ha->req_q_map[0] = NULL;
2870         clear_bit(0, ha->req_qid_map);
2871         qla2x00_free_rsp_que(ha, rsp);
2872         ha->rsp_q_map[0] = NULL;
2873         clear_bit(0, ha->rsp_qid_map);
2874         ha->max_req_queues = ha->max_rsp_queues = 0;
2875
2876 probe_failed:
2877         if (base_vha->timer_active)
2878                 qla2x00_stop_timer(base_vha);
2879         base_vha->flags.online = 0;
2880         if (ha->dpc_thread) {
2881                 struct task_struct *t = ha->dpc_thread;
2882
2883                 ha->dpc_thread = NULL;
2884                 kthread_stop(t);
2885         }
2886
2887         qla2x00_free_device(base_vha);
2888
2889         scsi_host_put(base_vha->host);
2890
2891 probe_hw_failed:
2892         qla2x00_clear_drv_active(ha);
2893
2894 iospace_config_failed:
2895         if (IS_P3P_TYPE(ha)) {
2896                 if (!ha->nx_pcibase)
2897                         iounmap((device_reg_t *)ha->nx_pcibase);
2898                 if (!ql2xdbwr)
2899                         iounmap((device_reg_t *)ha->nxdb_wr_ptr);
2900         } else {
2901                 if (ha->iobase)
2902                         iounmap(ha->iobase);
2903                 if (ha->cregbase)
2904                         iounmap(ha->cregbase);
2905         }
2906         pci_release_selected_regions(ha->pdev, ha->bars);
2907         kfree(ha);
2908         ha = NULL;
2909
2910 probe_out:
2911         pci_disable_device(pdev);
2912         return ret;
2913 }
2914
2915 static void
2916 qla2x00_shutdown(struct pci_dev *pdev)
2917 {
2918         scsi_qla_host_t *vha;
2919         struct qla_hw_data  *ha;
2920
2921         if (!atomic_read(&pdev->enable_cnt))
2922                 return;
2923
2924         vha = pci_get_drvdata(pdev);
2925         ha = vha->hw;
2926
2927         /* Notify ISPFX00 firmware */
2928         if (IS_QLAFX00(ha))
2929                 qlafx00_driver_shutdown(vha, 20);
2930
2931         /* Turn-off FCE trace */
2932         if (ha->flags.fce_enabled) {
2933                 qla2x00_disable_fce_trace(vha, NULL, NULL);
2934                 ha->flags.fce_enabled = 0;
2935         }
2936
2937         /* Turn-off EFT trace */
2938         if (ha->eft)
2939                 qla2x00_disable_eft_trace(vha);
2940
2941         /* Stop currently executing firmware. */
2942         qla2x00_try_to_stop_firmware(vha);
2943
2944         /* Turn adapter off line */
2945         vha->flags.online = 0;
2946
2947         /* turn-off interrupts on the card */
2948         if (ha->interrupts_on) {
2949                 vha->flags.init_done = 0;
2950                 ha->isp_ops->disable_intrs(ha);
2951         }
2952
2953         qla2x00_free_irqs(vha);
2954
2955         qla2x00_free_fw_dump(ha);
2956
2957         pci_disable_pcie_error_reporting(pdev);
2958         pci_disable_device(pdev);
2959 }
2960
2961 /* Deletes all the virtual ports for a given ha */
2962 static void
2963 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
2964 {
2965         scsi_qla_host_t *vha;
2966         unsigned long flags;
2967
2968         mutex_lock(&ha->vport_lock);
2969         while (ha->cur_vport_count) {
2970                 spin_lock_irqsave(&ha->vport_slock, flags);
2971
2972                 BUG_ON(base_vha->list.next == &ha->vp_list);
2973                 /* This assumes first entry in ha->vp_list is always base vha */
2974                 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
2975                 scsi_host_get(vha->host);
2976
2977                 spin_unlock_irqrestore(&ha->vport_slock, flags);
2978                 mutex_unlock(&ha->vport_lock);
2979
2980                 fc_vport_terminate(vha->fc_vport);
2981                 scsi_host_put(vha->host);
2982
2983                 mutex_lock(&ha->vport_lock);
2984         }
2985         mutex_unlock(&ha->vport_lock);
2986 }
2987
2988 /* Stops all deferred work threads */
2989 static void
2990 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
2991 {
2992         /* Flush the work queue and remove it */
2993         if (ha->wq) {
2994                 flush_workqueue(ha->wq);
2995                 destroy_workqueue(ha->wq);
2996                 ha->wq = NULL;
2997         }
2998
2999         /* Cancel all work and destroy DPC workqueues */
3000         if (ha->dpc_lp_wq) {
3001                 cancel_work_sync(&ha->idc_aen);
3002                 destroy_workqueue(ha->dpc_lp_wq);
3003                 ha->dpc_lp_wq = NULL;
3004         }
3005
3006         if (ha->dpc_hp_wq) {
3007                 cancel_work_sync(&ha->nic_core_reset);
3008                 cancel_work_sync(&ha->idc_state_handler);
3009                 cancel_work_sync(&ha->nic_core_unrecoverable);
3010                 destroy_workqueue(ha->dpc_hp_wq);
3011                 ha->dpc_hp_wq = NULL;
3012         }
3013
3014         /* Kill the kernel thread for this host */
3015         if (ha->dpc_thread) {
3016                 struct task_struct *t = ha->dpc_thread;
3017
3018                 /*
3019                  * qla2xxx_wake_dpc checks for ->dpc_thread
3020                  * so we need to zero it out.
3021                  */
3022                 ha->dpc_thread = NULL;
3023                 kthread_stop(t);
3024         }
3025 }
3026
3027 static void
3028 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3029 {
3030         if (IS_QLA82XX(ha)) {
3031
3032                 iounmap((device_reg_t *)ha->nx_pcibase);
3033                 if (!ql2xdbwr)
3034                         iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3035         } else {
3036                 if (ha->iobase)
3037                         iounmap(ha->iobase);
3038
3039                 if (ha->cregbase)
3040                         iounmap(ha->cregbase);
3041
3042                 if (ha->mqiobase)
3043                         iounmap(ha->mqiobase);
3044
3045                 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
3046                         iounmap(ha->msixbase);
3047         }
3048 }
3049
3050 static void
3051 qla2x00_clear_drv_active(struct qla_hw_data *ha)
3052 {
3053         if (IS_QLA8044(ha)) {
3054                 qla8044_idc_lock(ha);
3055                 qla8044_clear_drv_active(ha);
3056                 qla8044_idc_unlock(ha);
3057         } else if (IS_QLA82XX(ha)) {
3058                 qla82xx_idc_lock(ha);
3059                 qla82xx_clear_drv_active(ha);
3060                 qla82xx_idc_unlock(ha);
3061         }
3062 }
3063
3064 static void
3065 qla2x00_remove_one(struct pci_dev *pdev)
3066 {
3067         scsi_qla_host_t *base_vha;
3068         struct qla_hw_data  *ha;
3069
3070         base_vha = pci_get_drvdata(pdev);
3071         ha = base_vha->hw;
3072
3073         /* Indicate device removal to prevent future board_disable and wait
3074          * until any pending board_disable has completed. */
3075         set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3076         cancel_work_sync(&ha->board_disable);
3077
3078         /*
3079          * If the PCI device is disabled then there was a PCI-disconnect and
3080          * qla2x00_disable_board_on_pci_error has taken care of most of the
3081          * resources.
3082          */
3083         if (!atomic_read(&pdev->enable_cnt)) {
3084                 scsi_host_put(base_vha->host);
3085                 kfree(ha);
3086                 pci_set_drvdata(pdev, NULL);
3087                 return;
3088         }
3089
3090         qla2x00_wait_for_hba_ready(base_vha);
3091
3092         set_bit(UNLOADING, &base_vha->dpc_flags);
3093
3094         if (IS_QLAFX00(ha))
3095                 qlafx00_driver_shutdown(base_vha, 20);
3096
3097         qla2x00_delete_all_vps(ha, base_vha);
3098
3099         if (IS_QLA8031(ha)) {
3100                 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3101                     "Clearing fcoe driver presence.\n");
3102                 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3103                         ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3104                             "Error while clearing DRV-Presence.\n");
3105         }
3106
3107         qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3108
3109         qla2x00_dfs_remove(base_vha);
3110
3111         qla84xx_put_chip(base_vha);
3112
3113         /* Laser should be disabled only for ISP2031 */
3114         if (IS_QLA2031(ha))
3115                 qla83xx_disable_laser(base_vha);
3116
3117         /* Disable timer */
3118         if (base_vha->timer_active)
3119                 qla2x00_stop_timer(base_vha);
3120
3121         base_vha->flags.online = 0;
3122
3123         qla2x00_destroy_deferred_work(ha);
3124
3125         qlt_remove_target(ha, base_vha);
3126
3127         qla2x00_free_sysfs_attr(base_vha, true);
3128
3129         fc_remove_host(base_vha->host);
3130
3131         scsi_remove_host(base_vha->host);
3132
3133         qla2x00_free_device(base_vha);
3134
3135         qla2x00_clear_drv_active(ha);
3136
3137         scsi_host_put(base_vha->host);
3138
3139         qla2x00_unmap_iobases(ha);
3140
3141         pci_release_selected_regions(ha->pdev, ha->bars);
3142         kfree(ha);
3143         ha = NULL;
3144
3145         pci_disable_pcie_error_reporting(pdev);
3146
3147         pci_disable_device(pdev);
3148 }
3149
3150 static void
3151 qla2x00_free_device(scsi_qla_host_t *vha)
3152 {
3153         struct qla_hw_data *ha = vha->hw;
3154
3155         qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3156
3157         /* Disable timer */
3158         if (vha->timer_active)
3159                 qla2x00_stop_timer(vha);
3160
3161         qla25xx_delete_queues(vha);
3162
3163         if (ha->flags.fce_enabled)
3164                 qla2x00_disable_fce_trace(vha, NULL, NULL);
3165
3166         if (ha->eft)
3167                 qla2x00_disable_eft_trace(vha);
3168
3169         /* Stop currently executing firmware. */
3170         qla2x00_try_to_stop_firmware(vha);
3171
3172         vha->flags.online = 0;
3173
3174         /* turn-off interrupts on the card */
3175         if (ha->interrupts_on) {
3176                 vha->flags.init_done = 0;
3177                 ha->isp_ops->disable_intrs(ha);
3178         }
3179
3180         qla2x00_free_irqs(vha);
3181
3182         qla2x00_free_fcports(vha);
3183
3184         qla2x00_mem_free(ha);
3185
3186         qla82xx_md_free(vha);
3187
3188         qla2x00_free_queues(ha);
3189 }
3190
3191 void qla2x00_free_fcports(struct scsi_qla_host *vha)
3192 {
3193         fc_port_t *fcport, *tfcport;
3194
3195         list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3196                 list_del(&fcport->list);
3197                 qla2x00_clear_loop_id(fcport);
3198                 kfree(fcport);
3199                 fcport = NULL;
3200         }
3201 }
3202
3203 static inline void
3204 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
3205     int defer)
3206 {
3207         struct fc_rport *rport;
3208         scsi_qla_host_t *base_vha;
3209         unsigned long flags;
3210
3211         if (!fcport->rport)
3212                 return;
3213
3214         rport = fcport->rport;
3215         if (defer) {
3216                 base_vha = pci_get_drvdata(vha->hw->pdev);
3217                 spin_lock_irqsave(vha->host->host_lock, flags);
3218                 fcport->drport = rport;
3219                 spin_unlock_irqrestore(vha->host->host_lock, flags);
3220                 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3221                 qla2xxx_wake_dpc(base_vha);
3222         } else {
3223                 fc_remote_port_delete(rport);
3224                 qlt_fc_port_deleted(vha, fcport);
3225         }
3226 }
3227
3228 /*
3229  * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3230  *
3231  * Input: ha = adapter block pointer.  fcport = port structure pointer.
3232  *
3233  * Return: None.
3234  *
3235  * Context:
3236  */
3237 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
3238     int do_login, int defer)
3239 {
3240         if (IS_QLAFX00(vha->hw)) {
3241                 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3242                 qla2x00_schedule_rport_del(vha, fcport, defer);
3243                 return;
3244         }
3245
3246         if (atomic_read(&fcport->state) == FCS_ONLINE &&
3247             vha->vp_idx == fcport->vha->vp_idx) {
3248                 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3249                 qla2x00_schedule_rport_del(vha, fcport, defer);
3250         }
3251         /*
3252          * We may need to retry the login, so don't change the state of the
3253          * port but do the retries.
3254          */
3255         if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
3256                 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3257
3258         if (!do_login)
3259                 return;
3260
3261         set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3262
3263         if (fcport->login_retry == 0) {
3264                 fcport->login_retry = vha->hw->login_retry_count;
3265
3266                 ql_dbg(ql_dbg_disc, vha, 0x2067,
3267                     "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3268                     fcport->port_name, fcport->loop_id, fcport->login_retry);
3269         }
3270 }
3271
3272 /*
3273  * qla2x00_mark_all_devices_lost
3274  *      Updates fcport state when device goes offline.
3275  *
3276  * Input:
3277  *      ha = adapter block pointer.
3278  *      fcport = port structure pointer.
3279  *
3280  * Return:
3281  *      None.
3282  *
3283  * Context:
3284  */
3285 void
3286 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
3287 {
3288         fc_port_t *fcport;
3289
3290         list_for_each_entry(fcport, &vha->vp_fcports, list) {
3291                 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
3292                         continue;
3293
3294                 /*
3295                  * No point in marking the device as lost, if the device is
3296                  * already DEAD.
3297                  */
3298                 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3299                         continue;
3300                 if (atomic_read(&fcport->state) == FCS_ONLINE) {
3301                         qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3302                         if (defer)
3303                                 qla2x00_schedule_rport_del(vha, fcport, defer);
3304                         else if (vha->vp_idx == fcport->vha->vp_idx)
3305                                 qla2x00_schedule_rport_del(vha, fcport, defer);
3306                 }
3307         }
3308 }
3309
3310 /*
3311 * qla2x00_mem_alloc
3312 *      Allocates adapter memory.
3313 *
3314 * Returns:
3315 *      0  = success.
3316 *      !0  = failure.
3317 */
3318 static int
3319 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3320         struct req_que **req, struct rsp_que **rsp)
3321 {
3322         char    name[16];
3323
3324         ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
3325                 &ha->init_cb_dma, GFP_KERNEL);
3326         if (!ha->init_cb)
3327                 goto fail;
3328
3329         if (qlt_mem_alloc(ha) < 0)
3330                 goto fail_free_init_cb;
3331
3332         ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3333                 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
3334         if (!ha->gid_list)
3335                 goto fail_free_tgt_mem;
3336
3337         ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3338         if (!ha->srb_mempool)
3339                 goto fail_free_gid_list;
3340
3341         if (IS_P3P_TYPE(ha)) {
3342                 /* Allocate cache for CT6 Ctx. */
3343                 if (!ctx_cachep) {
3344                         ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3345                                 sizeof(struct ct6_dsd), 0,
3346                                 SLAB_HWCACHE_ALIGN, NULL);
3347                         if (!ctx_cachep)
3348                                 goto fail_free_gid_list;
3349                 }
3350                 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3351                         ctx_cachep);
3352                 if (!ha->ctx_mempool)
3353                         goto fail_free_srb_mempool;
3354                 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3355                     "ctx_cachep=%p ctx_mempool=%p.\n",
3356                     ctx_cachep, ha->ctx_mempool);
3357         }
3358
3359         /* Get memory for cached NVRAM */
3360         ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3361         if (!ha->nvram)
3362                 goto fail_free_ctx_mempool;
3363
3364         snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3365                 ha->pdev->device);
3366         ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3367                 DMA_POOL_SIZE, 8, 0);
3368         if (!ha->s_dma_pool)
3369                 goto fail_free_nvram;
3370
3371         ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3372             "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3373             ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3374
3375         if (IS_P3P_TYPE(ha) || ql2xenabledif) {
3376                 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3377                         DSD_LIST_DMA_POOL_SIZE, 8, 0);
3378                 if (!ha->dl_dma_pool) {
3379                         ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3380                             "Failed to allocate memory for dl_dma_pool.\n");
3381                         goto fail_s_dma_pool;
3382                 }
3383
3384                 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3385                         FCP_CMND_DMA_POOL_SIZE, 8, 0);
3386                 if (!ha->fcp_cmnd_dma_pool) {
3387                         ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3388                             "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
3389                         goto fail_dl_dma_pool;
3390                 }
3391                 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3392                     "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3393                     ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
3394         }
3395
3396         /* Allocate memory for SNS commands */
3397         if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3398         /* Get consistent memory allocated for SNS commands */
3399                 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
3400                 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
3401                 if (!ha->sns_cmd)
3402                         goto fail_dma_pool;
3403                 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
3404                     "sns_cmd: %p.\n", ha->sns_cmd);
3405         } else {
3406         /* Get consistent memory allocated for MS IOCB */
3407                 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3408                         &ha->ms_iocb_dma);
3409                 if (!ha->ms_iocb)
3410                         goto fail_dma_pool;
3411         /* Get consistent memory allocated for CT SNS commands */
3412                 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
3413                         sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
3414                 if (!ha->ct_sns)
3415                         goto fail_free_ms_iocb;
3416                 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3417                     "ms_iocb=%p ct_sns=%p.\n",
3418                     ha->ms_iocb, ha->ct_sns);
3419         }
3420
3421         /* Allocate memory for request ring */
3422         *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3423         if (!*req) {
3424                 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3425                     "Failed to allocate memory for req.\n");
3426                 goto fail_req;
3427         }
3428         (*req)->length = req_len;
3429         (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3430                 ((*req)->length + 1) * sizeof(request_t),
3431                 &(*req)->dma, GFP_KERNEL);
3432         if (!(*req)->ring) {
3433                 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3434                     "Failed to allocate memory for req_ring.\n");
3435                 goto fail_req_ring;
3436         }
3437         /* Allocate memory for response ring */
3438         *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3439         if (!*rsp) {
3440                 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3441                     "Failed to allocate memory for rsp.\n");
3442                 goto fail_rsp;
3443         }
3444         (*rsp)->hw = ha;
3445         (*rsp)->length = rsp_len;
3446         (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3447                 ((*rsp)->length + 1) * sizeof(response_t),
3448                 &(*rsp)->dma, GFP_KERNEL);
3449         if (!(*rsp)->ring) {
3450                 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3451                     "Failed to allocate memory for rsp_ring.\n");
3452                 goto fail_rsp_ring;
3453         }
3454         (*req)->rsp = *rsp;
3455         (*rsp)->req = *req;
3456         ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3457             "req=%p req->length=%d req->ring=%p rsp=%p "
3458             "rsp->length=%d rsp->ring=%p.\n",
3459             *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3460             (*rsp)->ring);
3461         /* Allocate memory for NVRAM data for vports */
3462         if (ha->nvram_npiv_size) {
3463                 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
3464                     ha->nvram_npiv_size, GFP_KERNEL);
3465                 if (!ha->npiv_info) {
3466                         ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3467                             "Failed to allocate memory for npiv_info.\n");
3468                         goto fail_npiv_info;
3469                 }
3470         } else
3471                 ha->npiv_info = NULL;
3472
3473         /* Get consistent memory allocated for EX-INIT-CB. */
3474         if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
3475                 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3476                     &ha->ex_init_cb_dma);
3477                 if (!ha->ex_init_cb)
3478                         goto fail_ex_init_cb;
3479                 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3480                     "ex_init_cb=%p.\n", ha->ex_init_cb);
3481         }
3482
3483         INIT_LIST_HEAD(&ha->gbl_dsd_list);
3484
3485         /* Get consistent memory allocated for Async Port-Database. */
3486         if (!IS_FWI2_CAPABLE(ha)) {
3487                 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3488                         &ha->async_pd_dma);
3489                 if (!ha->async_pd)
3490                         goto fail_async_pd;
3491                 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3492                     "async_pd=%p.\n", ha->async_pd);
3493         }
3494
3495         INIT_LIST_HEAD(&ha->vp_list);
3496
3497         /* Allocate memory for our loop_id bitmap */
3498         ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3499             GFP_KERNEL);
3500         if (!ha->loop_id_map)
3501                 goto fail_async_pd;
3502         else {
3503                 qla2x00_set_reserved_loop_ids(ha);
3504                 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
3505                     "loop_id_map=%p.\n", ha->loop_id_map);
3506         }
3507
3508         return 0;
3509
3510 fail_async_pd:
3511         dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
3512 fail_ex_init_cb:
3513         kfree(ha->npiv_info);
3514 fail_npiv_info:
3515         dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3516                 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3517         (*rsp)->ring = NULL;
3518         (*rsp)->dma = 0;
3519 fail_rsp_ring:
3520         kfree(*rsp);
3521 fail_rsp:
3522         dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3523                 sizeof(request_t), (*req)->ring, (*req)->dma);
3524         (*req)->ring = NULL;
3525         (*req)->dma = 0;
3526 fail_req_ring:
3527         kfree(*req);
3528 fail_req:
3529         dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3530                 ha->ct_sns, ha->ct_sns_dma);
3531         ha->ct_sns = NULL;
3532         ha->ct_sns_dma = 0;
3533 fail_free_ms_iocb:
3534         dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3535         ha->ms_iocb = NULL;
3536         ha->ms_iocb_dma = 0;
3537 fail_dma_pool:
3538         if (IS_QLA82XX(ha) || ql2xenabledif) {
3539                 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3540                 ha->fcp_cmnd_dma_pool = NULL;
3541         }
3542 fail_dl_dma_pool:
3543         if (IS_QLA82XX(ha) || ql2xenabledif) {
3544                 dma_pool_destroy(ha->dl_dma_pool);
3545                 ha->dl_dma_pool = NULL;
3546         }
3547 fail_s_dma_pool:
3548         dma_pool_destroy(ha->s_dma_pool);
3549         ha->s_dma_pool = NULL;
3550 fail_free_nvram:
3551         kfree(ha->nvram);
3552         ha->nvram = NULL;
3553 fail_free_ctx_mempool:
3554         mempool_destroy(ha->ctx_mempool);
3555         ha->ctx_mempool = NULL;
3556 fail_free_srb_mempool:
3557         mempool_destroy(ha->srb_mempool);
3558         ha->srb_mempool = NULL;
3559 fail_free_gid_list:
3560         dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3561         ha->gid_list,
3562         ha->gid_list_dma);
3563         ha->gid_list = NULL;
3564         ha->gid_list_dma = 0;
3565 fail_free_tgt_mem:
3566         qlt_mem_free(ha);
3567 fail_free_init_cb:
3568         dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3569         ha->init_cb_dma);
3570         ha->init_cb = NULL;
3571         ha->init_cb_dma = 0;
3572 fail:
3573         ql_log(ql_log_fatal, NULL, 0x0030,
3574             "Memory allocation failure.\n");
3575         return -ENOMEM;
3576 }
3577
3578 /*
3579 * qla2x00_free_fw_dump
3580 *       Frees fw dump stuff.
3581 *
3582 * Input:
3583 *       ha = adapter block pointer
3584 */
3585 static void
3586 qla2x00_free_fw_dump(struct qla_hw_data *ha)
3587 {
3588         if (ha->fce)
3589                 dma_free_coherent(&ha->pdev->dev,
3590                     FCE_SIZE, ha->fce, ha->fce_dma);
3591
3592         if (ha->eft)
3593                 dma_free_coherent(&ha->pdev->dev,
3594                     EFT_SIZE, ha->eft, ha->eft_dma);
3595
3596         if (ha->fw_dump)
3597                 vfree(ha->fw_dump);
3598         if (ha->fw_dump_template)
3599                 vfree(ha->fw_dump_template);
3600
3601         ha->fce = NULL;
3602         ha->fce_dma = 0;
3603         ha->eft = NULL;
3604         ha->eft_dma = 0;
3605         ha->fw_dumped = 0;
3606         ha->fw_dump_cap_flags = 0;
3607         ha->fw_dump_reading = 0;
3608         ha->fw_dump = NULL;
3609         ha->fw_dump_len = 0;
3610         ha->fw_dump_template = NULL;
3611         ha->fw_dump_template_len = 0;
3612 }
3613
3614 /*
3615 * qla2x00_mem_free
3616 *      Frees all adapter allocated memory.
3617 *
3618 * Input:
3619 *      ha = adapter block pointer.
3620 */
3621 static void
3622 qla2x00_mem_free(struct qla_hw_data *ha)
3623 {
3624         qla2x00_free_fw_dump(ha);
3625
3626         if (ha->mctp_dump)
3627                 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3628                     ha->mctp_dump_dma);
3629
3630         if (ha->srb_mempool)
3631                 mempool_destroy(ha->srb_mempool);
3632
3633         if (ha->dcbx_tlv)
3634                 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3635                     ha->dcbx_tlv, ha->dcbx_tlv_dma);
3636
3637         if (ha->xgmac_data)
3638                 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3639                     ha->xgmac_data, ha->xgmac_data_dma);
3640
3641         if (ha->sns_cmd)
3642                 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3643                 ha->sns_cmd, ha->sns_cmd_dma);
3644
3645         if (ha->ct_sns)
3646                 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3647                 ha->ct_sns, ha->ct_sns_dma);
3648
3649         if (ha->sfp_data)
3650                 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3651
3652         if (ha->ms_iocb)
3653                 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3654
3655         if (ha->ex_init_cb)
3656                 dma_pool_free(ha->s_dma_pool,
3657                         ha->ex_init_cb, ha->ex_init_cb_dma);
3658
3659         if (ha->async_pd)
3660                 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3661
3662         if (ha->s_dma_pool)
3663                 dma_pool_destroy(ha->s_dma_pool);
3664
3665         if (ha->gid_list)
3666                 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3667                 ha->gid_list, ha->gid_list_dma);
3668
3669         if (IS_QLA82XX(ha)) {
3670                 if (!list_empty(&ha->gbl_dsd_list)) {
3671                         struct dsd_dma *dsd_ptr, *tdsd_ptr;
3672
3673                         /* clean up allocated prev pool */
3674                         list_for_each_entry_safe(dsd_ptr,
3675                                 tdsd_ptr, &ha->gbl_dsd_list, list) {
3676                                 dma_pool_free(ha->dl_dma_pool,
3677                                 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3678                                 list_del(&dsd_ptr->list);
3679                                 kfree(dsd_ptr);
3680                         }
3681                 }
3682         }
3683
3684         if (ha->dl_dma_pool)
3685                 dma_pool_destroy(ha->dl_dma_pool);
3686
3687         if (ha->fcp_cmnd_dma_pool)
3688                 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3689
3690         if (ha->ctx_mempool)
3691                 mempool_destroy(ha->ctx_mempool);
3692
3693         qlt_mem_free(ha);
3694
3695         if (ha->init_cb)
3696                 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
3697                         ha->init_cb, ha->init_cb_dma);
3698         vfree(ha->optrom_buffer);
3699         kfree(ha->nvram);
3700         kfree(ha->npiv_info);
3701         kfree(ha->swl);
3702         kfree(ha->loop_id_map);
3703
3704         ha->srb_mempool = NULL;
3705         ha->ctx_mempool = NULL;
3706         ha->sns_cmd = NULL;
3707         ha->sns_cmd_dma = 0;
3708         ha->ct_sns = NULL;
3709         ha->ct_sns_dma = 0;
3710         ha->ms_iocb = NULL;
3711         ha->ms_iocb_dma = 0;
3712         ha->init_cb = NULL;
3713         ha->init_cb_dma = 0;
3714         ha->ex_init_cb = NULL;
3715         ha->ex_init_cb_dma = 0;
3716         ha->async_pd = NULL;
3717         ha->async_pd_dma = 0;
3718
3719         ha->s_dma_pool = NULL;
3720         ha->dl_dma_pool = NULL;
3721         ha->fcp_cmnd_dma_pool = NULL;
3722
3723         ha->gid_list = NULL;
3724         ha->gid_list_dma = 0;
3725
3726         ha->tgt.atio_ring = NULL;
3727         ha->tgt.atio_dma = 0;
3728         ha->tgt.tgt_vp_map = NULL;
3729 }
3730
3731 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3732                                                 struct qla_hw_data *ha)
3733 {
3734         struct Scsi_Host *host;
3735         struct scsi_qla_host *vha = NULL;
3736
3737         host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3738         if (host == NULL) {
3739                 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3740                     "Failed to allocate host from the scsi layer, aborting.\n");
3741                 goto fail;
3742         }
3743
3744         /* Clear our data area */
3745         vha = shost_priv(host);
3746         memset(vha, 0, sizeof(scsi_qla_host_t));
3747
3748         vha->host = host;
3749         vha->host_no = host->host_no;
3750         vha->hw = ha;
3751
3752         INIT_LIST_HEAD(&vha->vp_fcports);
3753         INIT_LIST_HEAD(&vha->work_list);
3754         INIT_LIST_HEAD(&vha->list);
3755
3756         spin_lock_init(&vha->work_lock);
3757
3758         sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
3759         ql_dbg(ql_dbg_init, vha, 0x0041,
3760             "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3761             vha->host, vha->hw, vha,
3762             dev_name(&(ha->pdev->dev)));
3763
3764         return vha;
3765
3766 fail:
3767         return vha;
3768 }
3769
3770 static struct qla_work_evt *
3771 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
3772 {
3773         struct qla_work_evt *e;
3774         uint8_t bail;
3775
3776         QLA_VHA_MARK_BUSY(vha, bail);
3777         if (bail)
3778                 return NULL;
3779
3780         e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
3781         if (!e) {
3782                 QLA_VHA_MARK_NOT_BUSY(vha);
3783                 return NULL;
3784         }
3785
3786         INIT_LIST_HEAD(&e->list);
3787         e->type = type;
3788         e->flags = QLA_EVT_FLAG_FREE;
3789         return e;
3790 }
3791
3792 static int
3793 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
3794 {
3795         unsigned long flags;
3796
3797         spin_lock_irqsave(&vha->work_lock, flags);
3798         list_add_tail(&e->list, &vha->work_list);
3799         spin_unlock_irqrestore(&vha->work_lock, flags);
3800         qla2xxx_wake_dpc(vha);
3801
3802         return QLA_SUCCESS;
3803 }
3804
3805 int
3806 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
3807     u32 data)
3808 {
3809         struct qla_work_evt *e;
3810
3811         e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
3812         if (!e)
3813                 return QLA_FUNCTION_FAILED;
3814
3815         e->u.aen.code = code;
3816         e->u.aen.data = data;
3817         return qla2x00_post_work(vha, e);
3818 }
3819
3820 int
3821 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3822 {
3823         struct qla_work_evt *e;
3824
3825         e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
3826         if (!e)
3827                 return QLA_FUNCTION_FAILED;
3828
3829         memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
3830         return qla2x00_post_work(vha, e);
3831 }
3832
3833 #define qla2x00_post_async_work(name, type)     \
3834 int qla2x00_post_async_##name##_work(           \
3835     struct scsi_qla_host *vha,                  \
3836     fc_port_t *fcport, uint16_t *data)          \
3837 {                                               \
3838         struct qla_work_evt *e;                 \
3839                                                 \
3840         e = qla2x00_alloc_work(vha, type);      \
3841         if (!e)                                 \
3842                 return QLA_FUNCTION_FAILED;     \
3843                                                 \
3844         e->u.logio.fcport = fcport;             \
3845         if (data) {                             \
3846                 e->u.logio.data[0] = data[0];   \
3847                 e->u.logio.data[1] = data[1];   \
3848         }                                       \
3849         return qla2x00_post_work(vha, e);       \
3850 }
3851
3852 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3853 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3854 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3855 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
3856 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3857 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
3858
3859 int
3860 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3861 {
3862         struct qla_work_evt *e;
3863
3864         e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3865         if (!e)
3866                 return QLA_FUNCTION_FAILED;
3867
3868         e->u.uevent.code = code;
3869         return qla2x00_post_work(vha, e);
3870 }
3871
3872 static void
3873 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3874 {
3875         char event_string[40];
3876         char *envp[] = { event_string, NULL };
3877
3878         switch (code) {
3879         case QLA_UEVENT_CODE_FW_DUMP:
3880                 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3881                     vha->host_no);
3882                 break;
3883         default:
3884                 /* do nothing */
3885                 break;
3886         }
3887         kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3888 }
3889
3890 int
3891 qlafx00_post_aenfx_work(struct scsi_qla_host *vha,  uint32_t evtcode,
3892                         uint32_t *data, int cnt)
3893 {
3894         struct qla_work_evt *e;
3895
3896         e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3897         if (!e)
3898                 return QLA_FUNCTION_FAILED;
3899
3900         e->u.aenfx.evtcode = evtcode;
3901         e->u.aenfx.count = cnt;
3902         memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3903         return qla2x00_post_work(vha, e);
3904 }
3905
3906 void
3907 qla2x00_do_work(struct scsi_qla_host *vha)
3908 {
3909         struct qla_work_evt *e, *tmp;
3910         unsigned long flags;
3911         LIST_HEAD(work);
3912
3913         spin_lock_irqsave(&vha->work_lock, flags);
3914         list_splice_init(&vha->work_list, &work);
3915         spin_unlock_irqrestore(&vha->work_lock, flags);
3916
3917         list_for_each_entry_safe(e, tmp, &work, list) {
3918                 list_del_init(&e->list);
3919
3920                 switch (e->type) {
3921                 case QLA_EVT_AEN:
3922                         fc_host_post_event(vha->host, fc_get_event_number(),
3923                             e->u.aen.code, e->u.aen.data);
3924                         break;
3925                 case QLA_EVT_IDC_ACK:
3926                         qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3927                         break;
3928                 case QLA_EVT_ASYNC_LOGIN:
3929                         qla2x00_async_login(vha, e->u.logio.fcport,
3930                             e->u.logio.data);
3931                         break;
3932                 case QLA_EVT_ASYNC_LOGIN_DONE:
3933                         qla2x00_async_login_done(vha, e->u.logio.fcport,
3934                             e->u.logio.data);
3935                         break;
3936                 case QLA_EVT_ASYNC_LOGOUT:
3937                         qla2x00_async_logout(vha, e->u.logio.fcport);
3938                         break;
3939                 case QLA_EVT_ASYNC_LOGOUT_DONE:
3940                         qla2x00_async_logout_done(vha, e->u.logio.fcport,
3941                             e->u.logio.data);
3942                         break;
3943                 case QLA_EVT_ASYNC_ADISC:
3944                         qla2x00_async_adisc(vha, e->u.logio.fcport,
3945                             e->u.logio.data);
3946                         break;
3947                 case QLA_EVT_ASYNC_ADISC_DONE:
3948                         qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3949                             e->u.logio.data);
3950                         break;
3951                 case QLA_EVT_UEVENT:
3952                         qla2x00_uevent_emit(vha, e->u.uevent.code);
3953                         break;
3954                 case QLA_EVT_AENFX:
3955                         qlafx00_process_aen(vha, e);
3956                         break;
3957                 }
3958                 if (e->flags & QLA_EVT_FLAG_FREE)
3959                         kfree(e);
3960
3961                 /* For each work completed decrement vha ref count */
3962                 QLA_VHA_MARK_NOT_BUSY(vha);
3963         }
3964 }
3965
3966 /* Relogins all the fcports of a vport
3967  * Context: dpc thread
3968  */
3969 void qla2x00_relogin(struct scsi_qla_host *vha)
3970 {
3971         fc_port_t       *fcport;
3972         int status;
3973         uint16_t        next_loopid = 0;
3974         struct qla_hw_data *ha = vha->hw;
3975         uint16_t data[2];
3976
3977         list_for_each_entry(fcport, &vha->vp_fcports, list) {
3978         /*
3979          * If the port is not ONLINE then try to login
3980          * to it if we haven't run out of retries.
3981          */
3982                 if (atomic_read(&fcport->state) != FCS_ONLINE &&
3983                     fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
3984                         fcport->login_retry--;
3985                         if (fcport->flags & FCF_FABRIC_DEVICE) {
3986                                 if (fcport->flags & FCF_FCP2_DEVICE)
3987                                         ha->isp_ops->fabric_logout(vha,
3988                                                         fcport->loop_id,
3989                                                         fcport->d_id.b.domain,
3990                                                         fcport->d_id.b.area,
3991                                                         fcport->d_id.b.al_pa);
3992
3993                                 if (fcport->loop_id == FC_NO_LOOP_ID) {
3994                                         fcport->loop_id = next_loopid =
3995                                             ha->min_external_loopid;
3996                                         status = qla2x00_find_new_loop_id(
3997                                             vha, fcport);
3998                                         if (status != QLA_SUCCESS) {
3999                                                 /* Ran out of IDs to use */
4000                                                 break;
4001                                         }
4002                                 }
4003
4004                                 if (IS_ALOGIO_CAPABLE(ha)) {
4005                                         fcport->flags |= FCF_ASYNC_SENT;
4006                                         data[0] = 0;
4007                                         data[1] = QLA_LOGIO_LOGIN_RETRIED;
4008                                         status = qla2x00_post_async_login_work(
4009                                             vha, fcport, data);
4010                                         if (status == QLA_SUCCESS)
4011                                                 continue;
4012                                         /* Attempt a retry. */
4013                                         status = 1;
4014                                 } else {
4015                                         status = qla2x00_fabric_login(vha,
4016                                             fcport, &next_loopid);
4017                                         if (status ==  QLA_SUCCESS) {
4018                                                 int status2;
4019                                                 uint8_t opts;
4020
4021                                                 opts = 0;
4022                                                 if (fcport->flags &
4023                                                     FCF_FCP2_DEVICE)
4024                                                         opts |= BIT_1;
4025                                                 status2 =
4026                                                     qla2x00_get_port_database(
4027                                                         vha, fcport, opts);
4028                                                 if (status2 != QLA_SUCCESS)
4029                                                         status = 1;
4030                                         }
4031                                 }
4032                         } else
4033                                 status = qla2x00_local_device_login(vha,
4034                                                                 fcport);
4035
4036                         if (status == QLA_SUCCESS) {
4037                                 fcport->old_loop_id = fcport->loop_id;
4038
4039                                 ql_dbg(ql_dbg_disc, vha, 0x2003,
4040                                     "Port login OK: logged in ID 0x%x.\n",
4041                                     fcport->loop_id);
4042
4043                                 qla2x00_update_fcport(vha, fcport);
4044
4045                         } else if (status == 1) {
4046                                 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4047                                 /* retry the login again */
4048                                 ql_dbg(ql_dbg_disc, vha, 0x2007,
4049                                     "Retrying %d login again loop_id 0x%x.\n",
4050                                     fcport->login_retry, fcport->loop_id);
4051                         } else {
4052                                 fcport->login_retry = 0;
4053                         }
4054
4055                         if (fcport->login_retry == 0 && status != QLA_SUCCESS)
4056                                 qla2x00_clear_loop_id(fcport);
4057                 }
4058                 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4059                         break;
4060         }
4061 }
4062
4063 /* Schedule work on any of the dpc-workqueues */
4064 void
4065 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4066 {
4067         struct qla_hw_data *ha = base_vha->hw;
4068
4069         switch (work_code) {
4070         case MBA_IDC_AEN: /* 0x8200 */
4071                 if (ha->dpc_lp_wq)
4072                         queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4073                 break;
4074
4075         case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4076                 if (!ha->flags.nic_core_reset_hdlr_active) {
4077                         if (ha->dpc_hp_wq)
4078                                 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4079                 } else
4080                         ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4081                             "NIC Core reset is already active. Skip "
4082                             "scheduling it again.\n");
4083                 break;
4084         case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4085                 if (ha->dpc_hp_wq)
4086                         queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4087                 break;
4088         case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4089                 if (ha->dpc_hp_wq)
4090                         queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4091                 break;
4092         default:
4093                 ql_log(ql_log_warn, base_vha, 0xb05f,
4094                     "Unknown work-code=0x%x.\n", work_code);
4095         }
4096
4097         return;
4098 }
4099
4100 /* Work: Perform NIC Core Unrecoverable state handling */
4101 void
4102 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4103 {
4104         struct qla_hw_data *ha =
4105                 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
4106         scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4107         uint32_t dev_state = 0;
4108
4109         qla83xx_idc_lock(base_vha, 0);
4110         qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4111         qla83xx_reset_ownership(base_vha);
4112         if (ha->flags.nic_core_reset_owner) {
4113                 ha->flags.nic_core_reset_owner = 0;
4114                 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4115                     QLA8XXX_DEV_FAILED);
4116                 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4117                 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4118         }
4119         qla83xx_idc_unlock(base_vha, 0);
4120 }
4121
4122 /* Work: Execute IDC state handler */
4123 void
4124 qla83xx_idc_state_handler_work(struct work_struct *work)
4125 {
4126         struct qla_hw_data *ha =
4127                 container_of(work, struct qla_hw_data, idc_state_handler);
4128         scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4129         uint32_t dev_state = 0;
4130
4131         qla83xx_idc_lock(base_vha, 0);
4132         qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4133         if (dev_state == QLA8XXX_DEV_FAILED ||
4134                         dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4135                 qla83xx_idc_state_handler(base_vha);
4136         qla83xx_idc_unlock(base_vha, 0);
4137 }
4138
4139 static int
4140 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4141 {
4142         int rval = QLA_SUCCESS;
4143         unsigned long heart_beat_wait = jiffies + (1 * HZ);
4144         uint32_t heart_beat_counter1, heart_beat_counter2;
4145
4146         do {
4147                 if (time_after(jiffies, heart_beat_wait)) {
4148                         ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4149                             "Nic Core f/w is not alive.\n");
4150                         rval = QLA_FUNCTION_FAILED;
4151                         break;
4152                 }
4153
4154                 qla83xx_idc_lock(base_vha, 0);
4155                 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4156                     &heart_beat_counter1);
4157                 qla83xx_idc_unlock(base_vha, 0);
4158                 msleep(100);
4159                 qla83xx_idc_lock(base_vha, 0);
4160                 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4161                     &heart_beat_counter2);
4162                 qla83xx_idc_unlock(base_vha, 0);
4163         } while (heart_beat_counter1 == heart_beat_counter2);
4164
4165         return rval;
4166 }
4167
4168 /* Work: Perform NIC Core Reset handling */
4169 void
4170 qla83xx_nic_core_reset_work(struct work_struct *work)
4171 {
4172         struct qla_hw_data *ha =
4173                 container_of(work, struct qla_hw_data, nic_core_reset);
4174         scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4175         uint32_t dev_state = 0;
4176
4177         if (IS_QLA2031(ha)) {
4178                 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4179                         ql_log(ql_log_warn, base_vha, 0xb081,
4180                             "Failed to dump mctp\n");
4181                 return;
4182         }
4183
4184         if (!ha->flags.nic_core_reset_hdlr_active) {
4185                 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4186                         qla83xx_idc_lock(base_vha, 0);
4187                         qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4188                             &dev_state);
4189                         qla83xx_idc_unlock(base_vha, 0);
4190                         if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4191                                 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4192                                     "Nic Core f/w is alive.\n");
4193                                 return;
4194                         }
4195                 }
4196
4197                 ha->flags.nic_core_reset_hdlr_active = 1;
4198                 if (qla83xx_nic_core_reset(base_vha)) {
4199                         /* NIC Core reset failed. */
4200                         ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4201                             "NIC Core reset failed.\n");
4202                 }
4203                 ha->flags.nic_core_reset_hdlr_active = 0;
4204         }
4205 }
4206
4207 /* Work: Handle 8200 IDC aens */
4208 void
4209 qla83xx_service_idc_aen(struct work_struct *work)
4210 {
4211         struct qla_hw_data *ha =
4212                 container_of(work, struct qla_hw_data, idc_aen);
4213         scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4214         uint32_t dev_state, idc_control;
4215
4216         qla83xx_idc_lock(base_vha, 0);
4217         qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4218         qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4219         qla83xx_idc_unlock(base_vha, 0);
4220         if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4221                 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4222                         ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4223                             "Application requested NIC Core Reset.\n");
4224                         qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4225                 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4226                     QLA_SUCCESS) {
4227                         ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4228                             "Other protocol driver requested NIC Core Reset.\n");
4229                         qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4230                 }
4231         } else if (dev_state == QLA8XXX_DEV_FAILED ||
4232                         dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4233                 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4234         }
4235 }
4236
4237 static void
4238 qla83xx_wait_logic(void)
4239 {
4240         int i;
4241
4242         /* Yield CPU */
4243         if (!in_interrupt()) {
4244                 /*
4245                  * Wait about 200ms before retrying again.
4246                  * This controls the number of retries for single
4247                  * lock operation.
4248                  */
4249                 msleep(100);
4250                 schedule();
4251         } else {
4252                 for (i = 0; i < 20; i++)
4253                         cpu_relax(); /* This a nop instr on i386 */
4254         }
4255 }
4256
4257 static int
4258 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4259 {
4260         int rval;
4261         uint32_t data;
4262         uint32_t idc_lck_rcvry_stage_mask = 0x3;
4263         uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4264         struct qla_hw_data *ha = base_vha->hw;
4265         ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4266             "Trying force recovery of the IDC lock.\n");
4267
4268         rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4269         if (rval)
4270                 return rval;
4271
4272         if ((data & idc_lck_rcvry_stage_mask) > 0) {
4273                 return QLA_SUCCESS;
4274         } else {
4275                 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4276                 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4277                     data);
4278                 if (rval)
4279                         return rval;
4280
4281                 msleep(200);
4282
4283                 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4284                     &data);
4285                 if (rval)
4286                         return rval;
4287
4288                 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4289                         data &= (IDC_LOCK_RECOVERY_STAGE2 |
4290                                         ~(idc_lck_rcvry_stage_mask));
4291                         rval = qla83xx_wr_reg(base_vha,
4292                             QLA83XX_IDC_LOCK_RECOVERY, data);
4293                         if (rval)
4294                                 return rval;
4295
4296                         /* Forcefully perform IDC UnLock */
4297                         rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4298                             &data);
4299                         if (rval)
4300                                 return rval;
4301                         /* Clear lock-id by setting 0xff */
4302                         rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4303                             0xff);
4304                         if (rval)
4305                                 return rval;
4306                         /* Clear lock-recovery by setting 0x0 */
4307                         rval = qla83xx_wr_reg(base_vha,
4308                             QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4309                         if (rval)
4310                                 return rval;
4311                 } else
4312                         return QLA_SUCCESS;
4313         }
4314
4315         return rval;
4316 }
4317
4318 static int
4319 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4320 {
4321         int rval = QLA_SUCCESS;
4322         uint32_t o_drv_lockid, n_drv_lockid;
4323         unsigned long lock_recovery_timeout;
4324
4325         lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4326 retry_lockid:
4327         rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4328         if (rval)
4329                 goto exit;
4330
4331         /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4332         if (time_after_eq(jiffies, lock_recovery_timeout)) {
4333                 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4334                         return QLA_SUCCESS;
4335                 else
4336                         return QLA_FUNCTION_FAILED;
4337         }
4338
4339         rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4340         if (rval)
4341                 goto exit;
4342
4343         if (o_drv_lockid == n_drv_lockid) {
4344                 qla83xx_wait_logic();
4345                 goto retry_lockid;
4346         } else
4347                 return QLA_SUCCESS;
4348
4349 exit:
4350         return rval;
4351 }
4352
4353 void
4354 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4355 {
4356         uint16_t options = (requester_id << 15) | BIT_6;
4357         uint32_t data;
4358         uint32_t lock_owner;
4359         struct qla_hw_data *ha = base_vha->hw;
4360
4361         /* IDC-lock implementation using driver-lock/lock-id remote registers */
4362 retry_lock:
4363         if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4364             == QLA_SUCCESS) {
4365                 if (data) {
4366                         /* Setting lock-id to our function-number */
4367                         qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4368                             ha->portnum);
4369                 } else {
4370                         qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4371                             &lock_owner);
4372                         ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
4373                             "Failed to acquire IDC lock, acquired by %d, "
4374                             "retrying...\n", lock_owner);
4375
4376                         /* Retry/Perform IDC-Lock recovery */
4377                         if (qla83xx_idc_lock_recovery(base_vha)
4378                             == QLA_SUCCESS) {
4379                                 qla83xx_wait_logic();
4380                                 goto retry_lock;
4381                         } else
4382                                 ql_log(ql_log_warn, base_vha, 0xb075,
4383                                     "IDC Lock recovery FAILED.\n");
4384                 }
4385
4386         }
4387
4388         return;
4389
4390         /* XXX: IDC-lock implementation using access-control mbx */
4391 retry_lock2:
4392         if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4393                 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4394                     "Failed to acquire IDC lock. retrying...\n");
4395                 /* Retry/Perform IDC-Lock recovery */
4396                 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4397                         qla83xx_wait_logic();
4398                         goto retry_lock2;
4399                 } else
4400                         ql_log(ql_log_warn, base_vha, 0xb076,
4401                             "IDC Lock recovery FAILED.\n");
4402         }
4403
4404         return;
4405 }
4406
4407 void
4408 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4409 {
4410 #if 0
4411         uint16_t options = (requester_id << 15) | BIT_7;
4412 #endif
4413         uint16_t retry;
4414         uint32_t data;
4415         struct qla_hw_data *ha = base_vha->hw;
4416
4417         /* IDC-unlock implementation using driver-unlock/lock-id
4418          * remote registers
4419          */
4420         retry = 0;
4421 retry_unlock:
4422         if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4423             == QLA_SUCCESS) {
4424                 if (data == ha->portnum) {
4425                         qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4426                         /* Clearing lock-id by setting 0xff */
4427                         qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4428                 } else if (retry < 10) {
4429                         /* SV: XXX: IDC unlock retrying needed here? */
4430
4431                         /* Retry for IDC-unlock */
4432                         qla83xx_wait_logic();
4433                         retry++;
4434                         ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4435                             "Failed to release IDC lock, retyring=%d\n", retry);
4436                         goto retry_unlock;
4437                 }
4438         } else if (retry < 10) {
4439                 /* Retry for IDC-unlock */
4440                 qla83xx_wait_logic();
4441                 retry++;
4442                 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4443                     "Failed to read drv-lockid, retyring=%d\n", retry);
4444                 goto retry_unlock;
4445         }
4446
4447         return;
4448
4449 #if 0
4450         /* XXX: IDC-unlock implementation using access-control mbx */
4451         retry = 0;
4452 retry_unlock2:
4453         if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4454                 if (retry < 10) {
4455                         /* Retry for IDC-unlock */
4456                         qla83xx_wait_logic();
4457                         retry++;
4458                         ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4459                             "Failed to release IDC lock, retyring=%d\n", retry);
4460                         goto retry_unlock2;
4461                 }
4462         }
4463
4464         return;
4465 #endif
4466 }
4467
4468 int
4469 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4470 {
4471         int rval = QLA_SUCCESS;
4472         struct qla_hw_data *ha = vha->hw;
4473         uint32_t drv_presence;
4474
4475         rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4476         if (rval == QLA_SUCCESS) {
4477                 drv_presence |= (1 << ha->portnum);
4478                 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4479                     drv_presence);
4480         }
4481
4482         return rval;
4483 }
4484
4485 int
4486 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4487 {
4488         int rval = QLA_SUCCESS;
4489
4490         qla83xx_idc_lock(vha, 0);
4491         rval = __qla83xx_set_drv_presence(vha);
4492         qla83xx_idc_unlock(vha, 0);
4493
4494         return rval;
4495 }
4496
4497 int
4498 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4499 {
4500         int rval = QLA_SUCCESS;
4501         struct qla_hw_data *ha = vha->hw;
4502         uint32_t drv_presence;
4503
4504         rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4505         if (rval == QLA_SUCCESS) {
4506                 drv_presence &= ~(1 << ha->portnum);
4507                 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4508                     drv_presence);
4509         }
4510
4511         return rval;
4512 }
4513
4514 int
4515 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4516 {
4517         int rval = QLA_SUCCESS;
4518
4519         qla83xx_idc_lock(vha, 0);
4520         rval = __qla83xx_clear_drv_presence(vha);
4521         qla83xx_idc_unlock(vha, 0);
4522
4523         return rval;
4524 }
4525
4526 static void
4527 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4528 {
4529         struct qla_hw_data *ha = vha->hw;
4530         uint32_t drv_ack, drv_presence;
4531         unsigned long ack_timeout;
4532
4533         /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4534         ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4535         while (1) {
4536                 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4537                 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4538                 if ((drv_ack & drv_presence) == drv_presence)
4539                         break;
4540
4541                 if (time_after_eq(jiffies, ack_timeout)) {
4542                         ql_log(ql_log_warn, vha, 0xb067,
4543                             "RESET ACK TIMEOUT! drv_presence=0x%x "
4544                             "drv_ack=0x%x\n", drv_presence, drv_ack);
4545                         /*
4546                          * The function(s) which did not ack in time are forced
4547                          * to withdraw any further participation in the IDC
4548                          * reset.
4549                          */
4550                         if (drv_ack != drv_presence)
4551                                 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4552                                     drv_ack);
4553                         break;
4554                 }
4555
4556                 qla83xx_idc_unlock(vha, 0);
4557                 msleep(1000);
4558                 qla83xx_idc_lock(vha, 0);
4559         }
4560
4561         qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4562         ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4563 }
4564
4565 static int
4566 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4567 {
4568         int rval = QLA_SUCCESS;
4569         uint32_t idc_control;
4570
4571         qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4572         ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4573
4574         /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4575         __qla83xx_get_idc_control(vha, &idc_control);
4576         idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4577         __qla83xx_set_idc_control(vha, 0);
4578
4579         qla83xx_idc_unlock(vha, 0);
4580         rval = qla83xx_restart_nic_firmware(vha);
4581         qla83xx_idc_lock(vha, 0);
4582
4583         if (rval != QLA_SUCCESS) {
4584                 ql_log(ql_log_fatal, vha, 0xb06a,
4585                     "Failed to restart NIC f/w.\n");
4586                 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4587                 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4588         } else {
4589                 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4590                     "Success in restarting nic f/w.\n");
4591                 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4592                 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4593         }
4594
4595         return rval;
4596 }
4597
4598 /* Assumes idc_lock always held on entry */
4599 int
4600 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4601 {
4602         struct qla_hw_data *ha = base_vha->hw;
4603         int rval = QLA_SUCCESS;
4604         unsigned long dev_init_timeout;
4605         uint32_t dev_state;
4606
4607         /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4608         dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4609
4610         while (1) {
4611
4612                 if (time_after_eq(jiffies, dev_init_timeout)) {
4613                         ql_log(ql_log_warn, base_vha, 0xb06e,
4614                             "Initialization TIMEOUT!\n");
4615                         /* Init timeout. Disable further NIC Core
4616                          * communication.
4617                          */
4618                         qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4619                                 QLA8XXX_DEV_FAILED);
4620                         ql_log(ql_log_info, base_vha, 0xb06f,
4621                             "HW State: FAILED.\n");
4622                 }
4623
4624                 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4625                 switch (dev_state) {
4626                 case QLA8XXX_DEV_READY:
4627                         if (ha->flags.nic_core_reset_owner)
4628                                 qla83xx_idc_audit(base_vha,
4629                                     IDC_AUDIT_COMPLETION);
4630                         ha->flags.nic_core_reset_owner = 0;
4631                         ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4632                             "Reset_owner reset by 0x%x.\n",
4633                             ha->portnum);
4634                         goto exit;
4635                 case QLA8XXX_DEV_COLD:
4636                         if (ha->flags.nic_core_reset_owner)
4637                                 rval = qla83xx_device_bootstrap(base_vha);
4638                         else {
4639                         /* Wait for AEN to change device-state */
4640                                 qla83xx_idc_unlock(base_vha, 0);
4641                                 msleep(1000);
4642                                 qla83xx_idc_lock(base_vha, 0);
4643                         }
4644                         break;
4645                 case QLA8XXX_DEV_INITIALIZING:
4646                         /* Wait for AEN to change device-state */
4647                         qla83xx_idc_unlock(base_vha, 0);
4648                         msleep(1000);
4649                         qla83xx_idc_lock(base_vha, 0);
4650                         break;
4651                 case QLA8XXX_DEV_NEED_RESET:
4652                         if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4653                                 qla83xx_need_reset_handler(base_vha);
4654                         else {
4655                                 /* Wait for AEN to change device-state */
4656                                 qla83xx_idc_unlock(base_vha, 0);
4657                                 msleep(1000);
4658                                 qla83xx_idc_lock(base_vha, 0);
4659                         }
4660                         /* reset timeout value after need reset handler */
4661                         dev_init_timeout = jiffies +
4662                             (ha->fcoe_dev_init_timeout * HZ);
4663                         break;
4664                 case QLA8XXX_DEV_NEED_QUIESCENT:
4665                         /* XXX: DEBUG for now */
4666                         qla83xx_idc_unlock(base_vha, 0);
4667                         msleep(1000);
4668                         qla83xx_idc_lock(base_vha, 0);
4669                         break;
4670                 case QLA8XXX_DEV_QUIESCENT:
4671                         /* XXX: DEBUG for now */
4672                         if (ha->flags.quiesce_owner)
4673                                 goto exit;
4674
4675                         qla83xx_idc_unlock(base_vha, 0);
4676                         msleep(1000);
4677                         qla83xx_idc_lock(base_vha, 0);
4678                         dev_init_timeout = jiffies +
4679                             (ha->fcoe_dev_init_timeout * HZ);
4680                         break;
4681                 case QLA8XXX_DEV_FAILED:
4682                         if (ha->flags.nic_core_reset_owner)
4683                                 qla83xx_idc_audit(base_vha,
4684                                     IDC_AUDIT_COMPLETION);
4685                         ha->flags.nic_core_reset_owner = 0;
4686                         __qla83xx_clear_drv_presence(base_vha);
4687                         qla83xx_idc_unlock(base_vha, 0);
4688                         qla8xxx_dev_failed_handler(base_vha);
4689                         rval = QLA_FUNCTION_FAILED;
4690                         qla83xx_idc_lock(base_vha, 0);
4691                         goto exit;
4692                 case QLA8XXX_BAD_VALUE:
4693                         qla83xx_idc_unlock(base_vha, 0);
4694                         msleep(1000);
4695                         qla83xx_idc_lock(base_vha, 0);
4696                         break;
4697                 default:
4698                         ql_log(ql_log_warn, base_vha, 0xb071,
4699                             "Unknown Device State: %x.\n", dev_state);
4700                         qla83xx_idc_unlock(base_vha, 0);
4701                         qla8xxx_dev_failed_handler(base_vha);
4702                         rval = QLA_FUNCTION_FAILED;
4703                         qla83xx_idc_lock(base_vha, 0);
4704                         goto exit;
4705                 }
4706         }
4707
4708 exit:
4709         return rval;
4710 }
4711
4712 void
4713 qla2x00_disable_board_on_pci_error(struct work_struct *work)
4714 {
4715         struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
4716             board_disable);
4717         struct pci_dev *pdev = ha->pdev;
4718         scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4719
4720         ql_log(ql_log_warn, base_vha, 0x015b,
4721             "Disabling adapter.\n");
4722
4723         set_bit(UNLOADING, &base_vha->dpc_flags);
4724
4725         qla2x00_delete_all_vps(ha, base_vha);
4726
4727         qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4728
4729         qla2x00_dfs_remove(base_vha);
4730
4731         qla84xx_put_chip(base_vha);
4732
4733         if (base_vha->timer_active)
4734                 qla2x00_stop_timer(base_vha);
4735
4736         base_vha->flags.online = 0;
4737
4738         qla2x00_destroy_deferred_work(ha);
4739
4740         /*
4741          * Do not try to stop beacon blink as it will issue a mailbox
4742          * command.
4743          */
4744         qla2x00_free_sysfs_attr(base_vha, false);
4745
4746         fc_remove_host(base_vha->host);
4747
4748         scsi_remove_host(base_vha->host);
4749
4750         base_vha->flags.init_done = 0;
4751         qla25xx_delete_queues(base_vha);
4752         qla2x00_free_irqs(base_vha);
4753         qla2x00_free_fcports(base_vha);
4754         qla2x00_mem_free(ha);
4755         qla82xx_md_free(base_vha);
4756         qla2x00_free_queues(ha);
4757
4758         qla2x00_unmap_iobases(ha);
4759
4760         pci_release_selected_regions(ha->pdev, ha->bars);
4761         pci_disable_pcie_error_reporting(pdev);
4762         pci_disable_device(pdev);
4763
4764         /*
4765          * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
4766          */
4767 }
4768
4769 /**************************************************************************
4770 * qla2x00_do_dpc
4771 *   This kernel thread is a task that is schedule by the interrupt handler
4772 *   to perform the background processing for interrupts.
4773 *
4774 * Notes:
4775 * This task always run in the context of a kernel thread.  It
4776 * is kick-off by the driver's detect code and starts up
4777 * up one per adapter. It immediately goes to sleep and waits for
4778 * some fibre event.  When either the interrupt handler or
4779 * the timer routine detects a event it will one of the task
4780 * bits then wake us up.
4781 **************************************************************************/
4782 static int
4783 qla2x00_do_dpc(void *data)
4784 {
4785         scsi_qla_host_t *base_vha;
4786         struct qla_hw_data *ha;
4787
4788         ha = (struct qla_hw_data *)data;
4789         base_vha = pci_get_drvdata(ha->pdev);
4790
4791         set_user_nice(current, MIN_NICE);
4792
4793         set_current_state(TASK_INTERRUPTIBLE);
4794         while (!kthread_should_stop()) {
4795                 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4796                     "DPC handler sleeping.\n");
4797
4798                 schedule();
4799
4800                 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4801                         goto end_loop;
4802
4803                 if (ha->flags.eeh_busy) {
4804                         ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4805                             "eeh_busy=%d.\n", ha->flags.eeh_busy);
4806                         goto end_loop;
4807                 }
4808
4809                 ha->dpc_active = 1;
4810
4811                 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4812                     "DPC handler waking up, dpc_flags=0x%lx.\n",
4813                     base_vha->dpc_flags);
4814
4815                 qla2x00_do_work(base_vha);
4816
4817                 if (IS_P3P_TYPE(ha)) {
4818                         if (IS_QLA8044(ha)) {
4819                                 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4820                                         &base_vha->dpc_flags)) {
4821                                         qla8044_idc_lock(ha);
4822                                         qla8044_wr_direct(base_vha,
4823                                                 QLA8044_CRB_DEV_STATE_INDEX,
4824                                                 QLA8XXX_DEV_FAILED);
4825                                         qla8044_idc_unlock(ha);
4826                                         ql_log(ql_log_info, base_vha, 0x4004,
4827                                                 "HW State: FAILED.\n");
4828                                         qla8044_device_state_handler(base_vha);
4829                                         continue;
4830                                 }
4831
4832                         } else {
4833                                 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4834                                         &base_vha->dpc_flags)) {
4835                                         qla82xx_idc_lock(ha);
4836                                         qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4837                                                 QLA8XXX_DEV_FAILED);
4838                                         qla82xx_idc_unlock(ha);
4839                                         ql_log(ql_log_info, base_vha, 0x0151,
4840                                                 "HW State: FAILED.\n");
4841                                         qla82xx_device_state_handler(base_vha);
4842                                         continue;
4843                                 }
4844                         }
4845
4846                         if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4847                                 &base_vha->dpc_flags)) {
4848
4849                                 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4850                                     "FCoE context reset scheduled.\n");
4851                                 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4852                                         &base_vha->dpc_flags))) {
4853                                         if (qla82xx_fcoe_ctx_reset(base_vha)) {
4854                                                 /* FCoE-ctx reset failed.
4855                                                  * Escalate to chip-reset
4856                                                  */
4857                                                 set_bit(ISP_ABORT_NEEDED,
4858                                                         &base_vha->dpc_flags);
4859                                         }
4860                                         clear_bit(ABORT_ISP_ACTIVE,
4861                                                 &base_vha->dpc_flags);
4862                                 }
4863
4864                                 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4865                                     "FCoE context reset end.\n");
4866                         }
4867                 } else if (IS_QLAFX00(ha)) {
4868                         if (test_and_clear_bit(ISP_UNRECOVERABLE,
4869                                 &base_vha->dpc_flags)) {
4870                                 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4871                                     "Firmware Reset Recovery\n");
4872                                 if (qlafx00_reset_initialize(base_vha)) {
4873                                         /* Failed. Abort isp later. */
4874                                         if (!test_bit(UNLOADING,
4875                                             &base_vha->dpc_flags)) {
4876                                                 set_bit(ISP_UNRECOVERABLE,
4877                                                     &base_vha->dpc_flags);
4878                                                 ql_dbg(ql_dbg_dpc, base_vha,
4879                                                     0x4021,
4880                                                     "Reset Recovery Failed\n");
4881                                         }
4882                                 }
4883                         }
4884
4885                         if (test_and_clear_bit(FX00_TARGET_SCAN,
4886                                 &base_vha->dpc_flags)) {
4887                                 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4888                                     "ISPFx00 Target Scan scheduled\n");
4889                                 if (qlafx00_rescan_isp(base_vha)) {
4890                                         if (!test_bit(UNLOADING,
4891                                             &base_vha->dpc_flags))
4892                                                 set_bit(ISP_UNRECOVERABLE,
4893                                                     &base_vha->dpc_flags);
4894                                         ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4895                                             "ISPFx00 Target Scan Failed\n");
4896                                 }
4897                                 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4898                                     "ISPFx00 Target Scan End\n");
4899                         }
4900                         if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
4901                                 &base_vha->dpc_flags)) {
4902                                 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
4903                                     "ISPFx00 Host Info resend scheduled\n");
4904                                 qlafx00_fx_disc(base_vha,
4905                                     &base_vha->hw->mr.fcport,
4906                                     FXDISC_REG_HOST_INFO);
4907                         }
4908                 }
4909
4910                 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4911                                                 &base_vha->dpc_flags)) {
4912
4913                         ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4914                             "ISP abort scheduled.\n");
4915                         if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4916                             &base_vha->dpc_flags))) {
4917
4918                                 if (ha->isp_ops->abort_isp(base_vha)) {
4919                                         /* failed. retry later */
4920                                         set_bit(ISP_ABORT_NEEDED,
4921                                             &base_vha->dpc_flags);
4922                                 }
4923                                 clear_bit(ABORT_ISP_ACTIVE,
4924                                                 &base_vha->dpc_flags);
4925                         }
4926
4927                         ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4928                             "ISP abort end.\n");
4929                 }
4930
4931                 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4932                     &base_vha->dpc_flags)) {
4933                         qla2x00_update_fcports(base_vha);
4934                 }
4935
4936                 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4937                         int ret;
4938                         ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4939                         if (ret != QLA_SUCCESS)
4940                                 ql_log(ql_log_warn, base_vha, 0x121,
4941                                     "Failed to enable receiving of RSCN "
4942                                     "requests: 0x%x.\n", ret);
4943                         clear_bit(SCR_PENDING, &base_vha->dpc_flags);
4944                 }
4945
4946                 if (IS_QLAFX00(ha))
4947                         goto loop_resync_check;
4948
4949                 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
4950                         ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
4951                             "Quiescence mode scheduled.\n");
4952                         if (IS_P3P_TYPE(ha)) {
4953                                 if (IS_QLA82XX(ha))
4954                                         qla82xx_device_state_handler(base_vha);
4955                                 if (IS_QLA8044(ha))
4956                                         qla8044_device_state_handler(base_vha);
4957                                 clear_bit(ISP_QUIESCE_NEEDED,
4958                                     &base_vha->dpc_flags);
4959                                 if (!ha->flags.quiesce_owner) {
4960                                         qla2x00_perform_loop_resync(base_vha);
4961                                         if (IS_QLA82XX(ha)) {
4962                                                 qla82xx_idc_lock(ha);
4963                                                 qla82xx_clear_qsnt_ready(
4964                                                     base_vha);
4965                                                 qla82xx_idc_unlock(ha);
4966                                         } else if (IS_QLA8044(ha)) {
4967                                                 qla8044_idc_lock(ha);
4968                                                 qla8044_clear_qsnt_ready(
4969                                                     base_vha);
4970                                                 qla8044_idc_unlock(ha);
4971                                         }
4972                                 }
4973                         } else {
4974                                 clear_bit(ISP_QUIESCE_NEEDED,
4975                                     &base_vha->dpc_flags);
4976                                 qla2x00_quiesce_io(base_vha);
4977                         }
4978                         ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
4979                             "Quiescence mode end.\n");
4980                 }
4981
4982                 if (test_and_clear_bit(RESET_MARKER_NEEDED,
4983                                 &base_vha->dpc_flags) &&
4984                     (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
4985
4986                         ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
4987                             "Reset marker scheduled.\n");
4988                         qla2x00_rst_aen(base_vha);
4989                         clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
4990                         ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
4991                             "Reset marker end.\n");
4992                 }
4993
4994                 /* Retry each device up to login retry count */
4995                 if ((test_and_clear_bit(RELOGIN_NEEDED,
4996                                                 &base_vha->dpc_flags)) &&
4997                     !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
4998                     atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
4999
5000                         ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5001                             "Relogin scheduled.\n");
5002                         qla2x00_relogin(base_vha);
5003                         ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5004                             "Relogin end.\n");
5005                 }
5006 loop_resync_check:
5007                 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
5008                     &base_vha->dpc_flags)) {
5009
5010                         ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5011                             "Loop resync scheduled.\n");
5012
5013                         if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
5014                             &base_vha->dpc_flags))) {
5015
5016                                 qla2x00_loop_resync(base_vha);
5017
5018                                 clear_bit(LOOP_RESYNC_ACTIVE,
5019                                                 &base_vha->dpc_flags);
5020                         }
5021
5022                         ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5023                             "Loop resync end.\n");
5024                 }
5025
5026                 if (IS_QLAFX00(ha))
5027                         goto intr_on_check;
5028
5029                 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5030                     atomic_read(&base_vha->loop_state) == LOOP_READY) {
5031                         clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5032                         qla2xxx_flash_npiv_conf(base_vha);
5033                 }
5034
5035 intr_on_check:
5036                 if (!ha->interrupts_on)
5037                         ha->isp_ops->enable_intrs(ha);
5038
5039                 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
5040                                         &base_vha->dpc_flags)) {
5041                         if (ha->beacon_blink_led == 1)
5042                                 ha->isp_ops->beacon_blink(base_vha);
5043                 }
5044
5045                 if (!IS_QLAFX00(ha))
5046                         qla2x00_do_dpc_all_vps(base_vha);
5047
5048                 ha->dpc_active = 0;
5049 end_loop:
5050                 set_current_state(TASK_INTERRUPTIBLE);
5051         } /* End of while(1) */
5052         __set_current_state(TASK_RUNNING);
5053
5054         ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5055             "DPC handler exiting.\n");
5056
5057         /*
5058          * Make sure that nobody tries to wake us up again.
5059          */
5060         ha->dpc_active = 0;
5061
5062         /* Cleanup any residual CTX SRBs. */
5063         qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5064
5065         return 0;
5066 }
5067
5068 void
5069 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
5070 {
5071         struct qla_hw_data *ha = vha->hw;
5072         struct task_struct *t = ha->dpc_thread;
5073
5074         if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
5075                 wake_up_process(t);
5076 }
5077
5078 /*
5079 *  qla2x00_rst_aen
5080 *      Processes asynchronous reset.
5081 *
5082 * Input:
5083 *      ha  = adapter block pointer.
5084 */
5085 static void
5086 qla2x00_rst_aen(scsi_qla_host_t *vha)
5087 {
5088         if (vha->flags.online && !vha->flags.reset_active &&
5089             !atomic_read(&vha->loop_down_timer) &&
5090             !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
5091                 do {
5092                         clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5093
5094                         /*
5095                          * Issue marker command only when we are going to start
5096                          * the I/O.
5097                          */
5098                         vha->marker_needed = 1;
5099                 } while (!atomic_read(&vha->loop_down_timer) &&
5100                     (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
5101         }
5102 }
5103
5104 /**************************************************************************
5105 *   qla2x00_timer
5106 *
5107 * Description:
5108 *   One second timer
5109 *
5110 * Context: Interrupt
5111 ***************************************************************************/
5112 void
5113 qla2x00_timer(scsi_qla_host_t *vha)
5114 {
5115         unsigned long   cpu_flags = 0;
5116         int             start_dpc = 0;
5117         int             index;
5118         srb_t           *sp;
5119         uint16_t        w;
5120         struct qla_hw_data *ha = vha->hw;
5121         struct req_que *req;
5122
5123         if (ha->flags.eeh_busy) {
5124                 ql_dbg(ql_dbg_timer, vha, 0x6000,
5125                     "EEH = %d, restarting timer.\n",
5126                     ha->flags.eeh_busy);
5127                 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5128                 return;
5129         }
5130
5131         /*
5132          * Hardware read to raise pending EEH errors during mailbox waits. If
5133          * the read returns -1 then disable the board.
5134          */
5135         if (!pci_channel_offline(ha->pdev)) {
5136                 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
5137                 qla2x00_check_reg16_for_disconnect(vha, w);
5138         }
5139
5140         /* Make sure qla82xx_watchdog is run only for physical port */
5141         if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
5142                 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5143                         start_dpc++;
5144                 if (IS_QLA82XX(ha))
5145                         qla82xx_watchdog(vha);
5146                 else if (IS_QLA8044(ha))
5147                         qla8044_watchdog(vha);
5148         }
5149
5150         if (!vha->vp_idx && IS_QLAFX00(ha))
5151                 qlafx00_timer_routine(vha);
5152
5153         /* Loop down handler. */
5154         if (atomic_read(&vha->loop_down_timer) > 0 &&
5155             !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5156             !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
5157                 && vha->flags.online) {
5158
5159                 if (atomic_read(&vha->loop_down_timer) ==
5160                     vha->loop_down_abort_time) {
5161
5162                         ql_log(ql_log_info, vha, 0x6008,
5163                             "Loop down - aborting the queues before time expires.\n");
5164
5165                         if (!IS_QLA2100(ha) && vha->link_down_timeout)
5166                                 atomic_set(&vha->loop_state, LOOP_DEAD);
5167
5168                         /*
5169                          * Schedule an ISP abort to return any FCP2-device
5170                          * commands.
5171                          */
5172                         /* NPIV - scan physical port only */
5173                         if (!vha->vp_idx) {
5174                                 spin_lock_irqsave(&ha->hardware_lock,
5175                                     cpu_flags);
5176                                 req = ha->req_q_map[0];
5177                                 for (index = 1;
5178                                     index < req->num_outstanding_cmds;
5179                                     index++) {
5180                                         fc_port_t *sfcp;
5181
5182                                         sp = req->outstanding_cmds[index];
5183                                         if (!sp)
5184                                                 continue;
5185                                         if (sp->type != SRB_SCSI_CMD)
5186                                                 continue;
5187                                         sfcp = sp->fcport;
5188                                         if (!(sfcp->flags & FCF_FCP2_DEVICE))
5189                                                 continue;
5190
5191                                         if (IS_QLA82XX(ha))
5192                                                 set_bit(FCOE_CTX_RESET_NEEDED,
5193                                                         &vha->dpc_flags);
5194                                         else
5195                                                 set_bit(ISP_ABORT_NEEDED,
5196                                                         &vha->dpc_flags);
5197                                         break;
5198                                 }
5199                                 spin_unlock_irqrestore(&ha->hardware_lock,
5200                                                                 cpu_flags);
5201                         }
5202                         start_dpc++;
5203                 }
5204
5205                 /* if the loop has been down for 4 minutes, reinit adapter */
5206                 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
5207                         if (!(vha->device_flags & DFLG_NO_CABLE)) {
5208                                 ql_log(ql_log_warn, vha, 0x6009,
5209                                     "Loop down - aborting ISP.\n");
5210
5211                                 if (IS_QLA82XX(ha))
5212                                         set_bit(FCOE_CTX_RESET_NEEDED,
5213                                                 &vha->dpc_flags);
5214                                 else
5215                                         set_bit(ISP_ABORT_NEEDED,
5216                                                 &vha->dpc_flags);
5217                         }
5218                 }
5219                 ql_dbg(ql_dbg_timer, vha, 0x600a,
5220                     "Loop down - seconds remaining %d.\n",
5221                     atomic_read(&vha->loop_down_timer));
5222         }
5223         /* Check if beacon LED needs to be blinked for physical host only */
5224         if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
5225                 /* There is no beacon_blink function for ISP82xx */
5226                 if (!IS_P3P_TYPE(ha)) {
5227                         set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5228                         start_dpc++;
5229                 }
5230         }
5231
5232         /* Process any deferred work. */
5233         if (!list_empty(&vha->work_list))
5234                 start_dpc++;
5235
5236         /* Schedule the DPC routine if needed */
5237         if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5238             test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5239             test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
5240             start_dpc ||
5241             test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5242             test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
5243             test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5244             test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
5245             test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
5246             test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
5247                 ql_dbg(ql_dbg_timer, vha, 0x600b,
5248                     "isp_abort_needed=%d loop_resync_needed=%d "
5249                     "fcport_update_needed=%d start_dpc=%d "
5250                     "reset_marker_needed=%d",
5251                     test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5252                     test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5253                     test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5254                     start_dpc,
5255                     test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5256                 ql_dbg(ql_dbg_timer, vha, 0x600c,
5257                     "beacon_blink_needed=%d isp_unrecoverable=%d "
5258                     "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
5259                     "relogin_needed=%d.\n",
5260                     test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5261                     test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5262                     test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5263                     test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
5264                     test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
5265                 qla2xxx_wake_dpc(vha);
5266         }
5267
5268         qla2x00_restart_timer(vha, WATCH_INTERVAL);
5269 }
5270
5271 /* Firmware interface routines. */
5272
5273 #define FW_BLOBS        11
5274 #define FW_ISP21XX      0
5275 #define FW_ISP22XX      1
5276 #define FW_ISP2300      2
5277 #define FW_ISP2322      3
5278 #define FW_ISP24XX      4
5279 #define FW_ISP25XX      5
5280 #define FW_ISP81XX      6
5281 #define FW_ISP82XX      7
5282 #define FW_ISP2031      8
5283 #define FW_ISP8031      9
5284 #define FW_ISP27XX      10
5285
5286 #define FW_FILE_ISP21XX "ql2100_fw.bin"
5287 #define FW_FILE_ISP22XX "ql2200_fw.bin"
5288 #define FW_FILE_ISP2300 "ql2300_fw.bin"
5289 #define FW_FILE_ISP2322 "ql2322_fw.bin"
5290 #define FW_FILE_ISP24XX "ql2400_fw.bin"
5291 #define FW_FILE_ISP25XX "ql2500_fw.bin"
5292 #define FW_FILE_ISP81XX "ql8100_fw.bin"
5293 #define FW_FILE_ISP82XX "ql8200_fw.bin"
5294 #define FW_FILE_ISP2031 "ql2600_fw.bin"
5295 #define FW_FILE_ISP8031 "ql8300_fw.bin"
5296 #define FW_FILE_ISP27XX "ql2700_fw.bin"
5297
5298
5299 static DEFINE_MUTEX(qla_fw_lock);
5300
5301 static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
5302         { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5303         { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5304         { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5305         { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5306         { .name = FW_FILE_ISP24XX, },
5307         { .name = FW_FILE_ISP25XX, },
5308         { .name = FW_FILE_ISP81XX, },
5309         { .name = FW_FILE_ISP82XX, },
5310         { .name = FW_FILE_ISP2031, },
5311         { .name = FW_FILE_ISP8031, },
5312         { .name = FW_FILE_ISP27XX, },
5313 };
5314
5315 struct fw_blob *
5316 qla2x00_request_firmware(scsi_qla_host_t *vha)
5317 {
5318         struct qla_hw_data *ha = vha->hw;
5319         struct fw_blob *blob;
5320
5321         if (IS_QLA2100(ha)) {
5322                 blob = &qla_fw_blobs[FW_ISP21XX];
5323         } else if (IS_QLA2200(ha)) {
5324                 blob = &qla_fw_blobs[FW_ISP22XX];
5325         } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5326                 blob = &qla_fw_blobs[FW_ISP2300];
5327         } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5328                 blob = &qla_fw_blobs[FW_ISP2322];
5329         } else if (IS_QLA24XX_TYPE(ha)) {
5330                 blob = &qla_fw_blobs[FW_ISP24XX];
5331         } else if (IS_QLA25XX(ha)) {
5332                 blob = &qla_fw_blobs[FW_ISP25XX];
5333         } else if (IS_QLA81XX(ha)) {
5334                 blob = &qla_fw_blobs[FW_ISP81XX];
5335         } else if (IS_QLA82XX(ha)) {
5336                 blob = &qla_fw_blobs[FW_ISP82XX];
5337         } else if (IS_QLA2031(ha)) {
5338                 blob = &qla_fw_blobs[FW_ISP2031];
5339         } else if (IS_QLA8031(ha)) {
5340                 blob = &qla_fw_blobs[FW_ISP8031];
5341         } else if (IS_QLA27XX(ha)) {
5342                 blob = &qla_fw_blobs[FW_ISP27XX];
5343         } else {
5344                 return NULL;
5345         }
5346
5347         mutex_lock(&qla_fw_lock);
5348         if (blob->fw)
5349                 goto out;
5350
5351         if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
5352                 ql_log(ql_log_warn, vha, 0x0063,
5353                     "Failed to load firmware image (%s).\n", blob->name);
5354                 blob->fw = NULL;
5355                 blob = NULL;
5356                 goto out;
5357         }
5358
5359 out:
5360         mutex_unlock(&qla_fw_lock);
5361         return blob;
5362 }
5363
5364 static void
5365 qla2x00_release_firmware(void)
5366 {
5367         int idx;
5368
5369         mutex_lock(&qla_fw_lock);
5370         for (idx = 0; idx < FW_BLOBS; idx++)
5371                 release_firmware(qla_fw_blobs[idx].fw);
5372         mutex_unlock(&qla_fw_lock);
5373 }
5374
5375 static pci_ers_result_t
5376 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5377 {
5378         scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5379         struct qla_hw_data *ha = vha->hw;
5380
5381         ql_dbg(ql_dbg_aer, vha, 0x9000,
5382             "PCI error detected, state %x.\n", state);
5383
5384         switch (state) {
5385         case pci_channel_io_normal:
5386                 ha->flags.eeh_busy = 0;
5387                 return PCI_ERS_RESULT_CAN_RECOVER;
5388         case pci_channel_io_frozen:
5389                 ha->flags.eeh_busy = 1;
5390                 /* For ISP82XX complete any pending mailbox cmd */
5391                 if (IS_QLA82XX(ha)) {
5392                         ha->flags.isp82xx_fw_hung = 1;
5393                         ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5394                         qla82xx_clear_pending_mbx(vha);
5395                 }
5396                 qla2x00_free_irqs(vha);
5397                 pci_disable_device(pdev);
5398                 /* Return back all IOs */
5399                 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
5400                 return PCI_ERS_RESULT_NEED_RESET;
5401         case pci_channel_io_perm_failure:
5402                 ha->flags.pci_channel_io_perm_failure = 1;
5403                 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
5404                 return PCI_ERS_RESULT_DISCONNECT;
5405         }
5406         return PCI_ERS_RESULT_NEED_RESET;
5407 }
5408
5409 static pci_ers_result_t
5410 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5411 {
5412         int risc_paused = 0;
5413         uint32_t stat;
5414         unsigned long flags;
5415         scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5416         struct qla_hw_data *ha = base_vha->hw;
5417         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5418         struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5419
5420         if (IS_QLA82XX(ha))
5421                 return PCI_ERS_RESULT_RECOVERED;
5422
5423         spin_lock_irqsave(&ha->hardware_lock, flags);
5424         if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5425                 stat = RD_REG_DWORD(&reg->hccr);
5426                 if (stat & HCCR_RISC_PAUSE)
5427                         risc_paused = 1;
5428         } else if (IS_QLA23XX(ha)) {
5429                 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5430                 if (stat & HSR_RISC_PAUSED)
5431                         risc_paused = 1;
5432         } else if (IS_FWI2_CAPABLE(ha)) {
5433                 stat = RD_REG_DWORD(&reg24->host_status);
5434                 if (stat & HSRX_RISC_PAUSED)
5435                         risc_paused = 1;
5436         }
5437         spin_unlock_irqrestore(&ha->hardware_lock, flags);
5438
5439         if (risc_paused) {
5440                 ql_log(ql_log_info, base_vha, 0x9003,
5441                     "RISC paused -- mmio_enabled, Dumping firmware.\n");
5442                 ha->isp_ops->fw_dump(base_vha, 0);
5443
5444                 return PCI_ERS_RESULT_NEED_RESET;
5445         } else
5446                 return PCI_ERS_RESULT_RECOVERED;
5447 }
5448
5449 static uint32_t
5450 qla82xx_error_recovery(scsi_qla_host_t *base_vha)
5451 {
5452         uint32_t rval = QLA_FUNCTION_FAILED;
5453         uint32_t drv_active = 0;
5454         struct qla_hw_data *ha = base_vha->hw;
5455         int fn;
5456         struct pci_dev *other_pdev = NULL;
5457
5458         ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5459             "Entered %s.\n", __func__);
5460
5461         set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5462
5463         if (base_vha->flags.online) {
5464                 /* Abort all outstanding commands,
5465                  * so as to be requeued later */
5466                 qla2x00_abort_isp_cleanup(base_vha);
5467         }
5468
5469
5470         fn = PCI_FUNC(ha->pdev->devfn);
5471         while (fn > 0) {
5472                 fn--;
5473                 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5474                     "Finding pci device at function = 0x%x.\n", fn);
5475                 other_pdev =
5476                     pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5477                     ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5478                     fn));
5479
5480                 if (!other_pdev)
5481                         continue;
5482                 if (atomic_read(&other_pdev->enable_cnt)) {
5483                         ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5484                             "Found PCI func available and enable at 0x%x.\n",
5485                             fn);
5486                         pci_dev_put(other_pdev);
5487                         break;
5488                 }
5489                 pci_dev_put(other_pdev);
5490         }
5491
5492         if (!fn) {
5493                 /* Reset owner */
5494                 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5495                     "This devfn is reset owner = 0x%x.\n",
5496                     ha->pdev->devfn);
5497                 qla82xx_idc_lock(ha);
5498
5499                 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5500                     QLA8XXX_DEV_INITIALIZING);
5501
5502                 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5503                     QLA82XX_IDC_VERSION);
5504
5505                 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
5506                 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5507                     "drv_active = 0x%x.\n", drv_active);
5508
5509                 qla82xx_idc_unlock(ha);
5510                 /* Reset if device is not already reset
5511                  * drv_active would be 0 if a reset has already been done
5512                  */
5513                 if (drv_active)
5514                         rval = qla82xx_start_firmware(base_vha);
5515                 else
5516                         rval = QLA_SUCCESS;
5517                 qla82xx_idc_lock(ha);
5518
5519                 if (rval != QLA_SUCCESS) {
5520                         ql_log(ql_log_info, base_vha, 0x900b,
5521                             "HW State: FAILED.\n");
5522                         qla82xx_clear_drv_active(ha);
5523                         qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5524                             QLA8XXX_DEV_FAILED);
5525                 } else {
5526                         ql_log(ql_log_info, base_vha, 0x900c,
5527                             "HW State: READY.\n");
5528                         qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5529                             QLA8XXX_DEV_READY);
5530                         qla82xx_idc_unlock(ha);
5531                         ha->flags.isp82xx_fw_hung = 0;
5532                         rval = qla82xx_restart_isp(base_vha);
5533                         qla82xx_idc_lock(ha);
5534                         /* Clear driver state register */
5535                         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5536                         qla82xx_set_drv_active(base_vha);
5537                 }
5538                 qla82xx_idc_unlock(ha);
5539         } else {
5540                 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5541                     "This devfn is not reset owner = 0x%x.\n",
5542                     ha->pdev->devfn);
5543                 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
5544                     QLA8XXX_DEV_READY)) {
5545                         ha->flags.isp82xx_fw_hung = 0;
5546                         rval = qla82xx_restart_isp(base_vha);
5547                         qla82xx_idc_lock(ha);
5548                         qla82xx_set_drv_active(base_vha);
5549                         qla82xx_idc_unlock(ha);
5550                 }
5551         }
5552         clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5553
5554         return rval;
5555 }
5556
5557 static pci_ers_result_t
5558 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5559 {
5560         pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
5561         scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5562         struct qla_hw_data *ha = base_vha->hw;
5563         struct rsp_que *rsp;
5564         int rc, retries = 10;
5565
5566         ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5567             "Slot Reset.\n");
5568
5569         /* Workaround: qla2xxx driver which access hardware earlier
5570          * needs error state to be pci_channel_io_online.
5571          * Otherwise mailbox command timesout.
5572          */
5573         pdev->error_state = pci_channel_io_normal;
5574
5575         pci_restore_state(pdev);
5576
5577         /* pci_restore_state() clears the saved_state flag of the device
5578          * save restored state which resets saved_state flag
5579          */
5580         pci_save_state(pdev);
5581
5582         if (ha->mem_only)
5583                 rc = pci_enable_device_mem(pdev);
5584         else
5585                 rc = pci_enable_device(pdev);
5586
5587         if (rc) {
5588                 ql_log(ql_log_warn, base_vha, 0x9005,
5589                     "Can't re-enable PCI device after reset.\n");
5590                 goto exit_slot_reset;
5591         }
5592
5593         rsp = ha->rsp_q_map[0];
5594         if (qla2x00_request_irqs(ha, rsp))
5595                 goto exit_slot_reset;
5596
5597         if (ha->isp_ops->pci_config(base_vha))
5598                 goto exit_slot_reset;
5599
5600         if (IS_QLA82XX(ha)) {
5601                 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5602                         ret = PCI_ERS_RESULT_RECOVERED;
5603                         goto exit_slot_reset;
5604                 } else
5605                         goto exit_slot_reset;
5606         }
5607
5608         while (ha->flags.mbox_busy && retries--)
5609                 msleep(1000);
5610
5611         set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5612         if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
5613                 ret =  PCI_ERS_RESULT_RECOVERED;
5614         clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5615
5616
5617 exit_slot_reset:
5618         ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5619             "slot_reset return %x.\n", ret);
5620
5621         return ret;
5622 }
5623
5624 static void
5625 qla2xxx_pci_resume(struct pci_dev *pdev)
5626 {
5627         scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5628         struct qla_hw_data *ha = base_vha->hw;
5629         int ret;
5630
5631         ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5632             "pci_resume.\n");
5633
5634         ret = qla2x00_wait_for_hba_online(base_vha);
5635         if (ret != QLA_SUCCESS) {
5636                 ql_log(ql_log_fatal, base_vha, 0x9002,
5637                     "The device failed to resume I/O from slot/link_reset.\n");
5638         }
5639
5640         pci_cleanup_aer_uncorrect_error_status(pdev);
5641
5642         ha->flags.eeh_busy = 0;
5643 }
5644
5645 static void
5646 qla83xx_disable_laser(scsi_qla_host_t *vha)
5647 {
5648         uint32_t reg, data, fn;
5649         struct qla_hw_data *ha = vha->hw;
5650         struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
5651
5652         /* pci func #/port # */
5653         ql_dbg(ql_dbg_init, vha, 0x004b,
5654             "Disabling Laser for hba: %p\n", vha);
5655
5656         fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
5657                 (BIT_15|BIT_14|BIT_13|BIT_12));
5658
5659         fn = (fn >> 12);
5660
5661         if (fn & 1)
5662                 reg = PORT_1_2031;
5663         else
5664                 reg = PORT_0_2031;
5665
5666         data = LASER_OFF_2031;
5667
5668         qla83xx_wr_reg(vha, reg, data);
5669 }
5670
5671 static const struct pci_error_handlers qla2xxx_err_handler = {
5672         .error_detected = qla2xxx_pci_error_detected,
5673         .mmio_enabled = qla2xxx_pci_mmio_enabled,
5674         .slot_reset = qla2xxx_pci_slot_reset,
5675         .resume = qla2xxx_pci_resume,
5676 };
5677
5678 static struct pci_device_id qla2xxx_pci_tbl[] = {
5679         { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5680         { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5681         { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5682         { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5683         { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5684         { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5685         { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5686         { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5687         { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
5688         { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
5689         { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5690         { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
5691         { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
5692         { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
5693         { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
5694         { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
5695         { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
5696         { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
5697         { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
5698         { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
5699         { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
5700         { 0 },
5701 };
5702 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5703
5704 static struct pci_driver qla2xxx_pci_driver = {
5705         .name           = QLA2XXX_DRIVER_NAME,
5706         .driver         = {
5707                 .owner          = THIS_MODULE,
5708         },
5709         .id_table       = qla2xxx_pci_tbl,
5710         .probe          = qla2x00_probe_one,
5711         .remove         = qla2x00_remove_one,
5712         .shutdown       = qla2x00_shutdown,
5713         .err_handler    = &qla2xxx_err_handler,
5714 };
5715
5716 static const struct file_operations apidev_fops = {
5717         .owner = THIS_MODULE,
5718         .llseek = noop_llseek,
5719 };
5720
5721 /**
5722  * qla2x00_module_init - Module initialization.
5723  **/
5724 static int __init
5725 qla2x00_module_init(void)
5726 {
5727         int ret = 0;
5728
5729         /* Allocate cache for SRBs. */
5730         srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
5731             SLAB_HWCACHE_ALIGN, NULL);
5732         if (srb_cachep == NULL) {
5733                 ql_log(ql_log_fatal, NULL, 0x0001,
5734                     "Unable to allocate SRB cache...Failing load!.\n");
5735                 return -ENOMEM;
5736         }
5737
5738         /* Initialize target kmem_cache and mem_pools */
5739         ret = qlt_init();
5740         if (ret < 0) {
5741                 kmem_cache_destroy(srb_cachep);
5742                 return ret;
5743         } else if (ret > 0) {
5744                 /*
5745                  * If initiator mode is explictly disabled by qlt_init(),
5746                  * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5747                  * performing scsi_scan_target() during LOOP UP event.
5748                  */
5749                 qla2xxx_transport_functions.disable_target_scan = 1;
5750                 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5751         }
5752
5753         /* Derive version string. */
5754         strcpy(qla2x00_version_str, QLA2XXX_VERSION);
5755         if (ql2xextended_error_logging)
5756                 strcat(qla2x00_version_str, "-debug");
5757
5758         qla2xxx_transport_template =
5759             fc_attach_transport(&qla2xxx_transport_functions);
5760         if (!qla2xxx_transport_template) {
5761                 kmem_cache_destroy(srb_cachep);
5762                 ql_log(ql_log_fatal, NULL, 0x0002,
5763                     "fc_attach_transport failed...Failing load!.\n");
5764                 qlt_exit();
5765                 return -ENODEV;
5766         }
5767
5768         apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5769         if (apidev_major < 0) {
5770                 ql_log(ql_log_fatal, NULL, 0x0003,
5771                     "Unable to register char device %s.\n", QLA2XXX_APIDEV);
5772         }
5773
5774         qla2xxx_transport_vport_template =
5775             fc_attach_transport(&qla2xxx_transport_vport_functions);
5776         if (!qla2xxx_transport_vport_template) {
5777                 kmem_cache_destroy(srb_cachep);
5778                 qlt_exit();
5779                 fc_release_transport(qla2xxx_transport_template);
5780                 ql_log(ql_log_fatal, NULL, 0x0004,
5781                     "fc_attach_transport vport failed...Failing load!.\n");
5782                 return -ENODEV;
5783         }
5784         ql_log(ql_log_info, NULL, 0x0005,
5785             "QLogic Fibre Channel HBA Driver: %s.\n",
5786             qla2x00_version_str);
5787         ret = pci_register_driver(&qla2xxx_pci_driver);
5788         if (ret) {
5789                 kmem_cache_destroy(srb_cachep);
5790                 qlt_exit();
5791                 fc_release_transport(qla2xxx_transport_template);
5792                 fc_release_transport(qla2xxx_transport_vport_template);
5793                 ql_log(ql_log_fatal, NULL, 0x0006,
5794                     "pci_register_driver failed...ret=%d Failing load!.\n",
5795                     ret);
5796         }
5797         return ret;
5798 }
5799
5800 /**
5801  * qla2x00_module_exit - Module cleanup.
5802  **/
5803 static void __exit
5804 qla2x00_module_exit(void)
5805 {
5806         unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
5807         pci_unregister_driver(&qla2xxx_pci_driver);
5808         qla2x00_release_firmware();
5809         kmem_cache_destroy(srb_cachep);
5810         qlt_exit();
5811         if (ctx_cachep)
5812                 kmem_cache_destroy(ctx_cachep);
5813         fc_release_transport(qla2xxx_transport_template);
5814         fc_release_transport(qla2xxx_transport_vport_template);
5815 }
5816
5817 module_init(qla2x00_module_init);
5818 module_exit(qla2x00_module_exit);
5819
5820 MODULE_AUTHOR("QLogic Corporation");
5821 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5822 MODULE_LICENSE("GPL");
5823 MODULE_VERSION(QLA2XXX_VERSION);
5824 MODULE_FIRMWARE(FW_FILE_ISP21XX);
5825 MODULE_FIRMWARE(FW_FILE_ISP22XX);
5826 MODULE_FIRMWARE(FW_FILE_ISP2300);
5827 MODULE_FIRMWARE(FW_FILE_ISP2322);
5828 MODULE_FIRMWARE(FW_FILE_ISP24XX);
5829 MODULE_FIRMWARE(FW_FILE_ISP25XX);
5830 MODULE_FIRMWARE(FW_FILE_ISP2031);
5831 MODULE_FIRMWARE(FW_FILE_ISP8031);
5832 MODULE_FIRMWARE(FW_FILE_ISP27XX);