2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/ioport.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/spi/spi.h>
28 #include <linux/workqueue.h>
29 #include <linux/delay.h>
30 #include <linux/clk.h>
34 #include <asm/hardware.h>
35 #include <asm/delay.h>
38 #include <asm/arch/hardware.h>
39 #include <asm/arch/pxa-regs.h>
40 #include <asm/arch/regs-ssp.h>
41 #include <asm/arch/ssp.h>
42 #include <asm/arch/pxa2xx_spi.h>
44 MODULE_AUTHOR("Stephen Street");
45 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
46 MODULE_LICENSE("GPL");
50 #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
51 #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
52 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
54 /* for testing SSCR1 changes that require SSP restart, basically
55 * everything except the service and interrupt enables */
56 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_EBCEI | SSCR1_SCFR \
57 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
58 | SSCR1_RWOT | SSCR1_TRAIL | SSCR1_PINTE \
59 | SSCR1_STRF | SSCR1_EFWR |SSCR1_RFT \
60 | SSCR1_TFT | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
62 #define DEFINE_SSP_REG(reg, off) \
63 static inline u32 read_##reg(void *p) { return __raw_readl(p + (off)); } \
64 static inline void write_##reg(u32 v, void *p) { __raw_writel(v, p + (off)); }
66 DEFINE_SSP_REG(SSCR0, 0x00)
67 DEFINE_SSP_REG(SSCR1, 0x04)
68 DEFINE_SSP_REG(SSSR, 0x08)
69 DEFINE_SSP_REG(SSITR, 0x0c)
70 DEFINE_SSP_REG(SSDR, 0x10)
71 DEFINE_SSP_REG(SSTO, 0x28)
72 DEFINE_SSP_REG(SSPSP, 0x2c)
74 #define START_STATE ((void*)0)
75 #define RUNNING_STATE ((void*)1)
76 #define DONE_STATE ((void*)2)
77 #define ERROR_STATE ((void*)-1)
79 #define QUEUE_RUNNING 0
80 #define QUEUE_STOPPED 1
83 /* Driver model hookup */
84 struct platform_device *pdev;
87 struct ssp_device *ssp;
89 /* SPI framework hookup */
90 enum pxa_ssp_type ssp_type;
91 struct spi_master *master;
94 struct pxa2xx_spi_master *master_info;
101 /* SSP register addresses */
111 /* Driver message queue */
112 struct workqueue_struct *workqueue;
113 struct work_struct pump_messages;
115 struct list_head queue;
119 /* Message Transfer pump */
120 struct tasklet_struct pump_transfers;
122 /* Current message transfer state info */
123 struct spi_message* cur_msg;
124 struct spi_transfer* cur_transfer;
125 struct chip_data *cur_chip;
139 int (*write)(struct driver_data *drv_data);
140 int (*read)(struct driver_data *drv_data);
141 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
142 void (*cs_control)(u32 command);
158 int (*write)(struct driver_data *drv_data);
159 int (*read)(struct driver_data *drv_data);
160 void (*cs_control)(u32 command);
163 static void pump_messages(struct work_struct *work);
165 static int flush(struct driver_data *drv_data)
167 unsigned long limit = loops_per_jiffy << 1;
169 void *reg = drv_data->ioaddr;
172 while (read_SSSR(reg) & SSSR_RNE) {
175 } while ((read_SSSR(reg) & SSSR_BSY) && limit--);
176 write_SSSR(SSSR_ROR, reg);
181 static void null_cs_control(u32 command)
185 static int null_writer(struct driver_data *drv_data)
187 void *reg = drv_data->ioaddr;
188 u8 n_bytes = drv_data->n_bytes;
190 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
191 || (drv_data->tx == drv_data->tx_end))
195 drv_data->tx += n_bytes;
200 static int null_reader(struct driver_data *drv_data)
202 void *reg = drv_data->ioaddr;
203 u8 n_bytes = drv_data->n_bytes;
205 while ((read_SSSR(reg) & SSSR_RNE)
206 && (drv_data->rx < drv_data->rx_end)) {
208 drv_data->rx += n_bytes;
211 return drv_data->rx == drv_data->rx_end;
214 static int u8_writer(struct driver_data *drv_data)
216 void *reg = drv_data->ioaddr;
218 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
219 || (drv_data->tx == drv_data->tx_end))
222 write_SSDR(*(u8 *)(drv_data->tx), reg);
228 static int u8_reader(struct driver_data *drv_data)
230 void *reg = drv_data->ioaddr;
232 while ((read_SSSR(reg) & SSSR_RNE)
233 && (drv_data->rx < drv_data->rx_end)) {
234 *(u8 *)(drv_data->rx) = read_SSDR(reg);
238 return drv_data->rx == drv_data->rx_end;
241 static int u16_writer(struct driver_data *drv_data)
243 void *reg = drv_data->ioaddr;
245 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
246 || (drv_data->tx == drv_data->tx_end))
249 write_SSDR(*(u16 *)(drv_data->tx), reg);
255 static int u16_reader(struct driver_data *drv_data)
257 void *reg = drv_data->ioaddr;
259 while ((read_SSSR(reg) & SSSR_RNE)
260 && (drv_data->rx < drv_data->rx_end)) {
261 *(u16 *)(drv_data->rx) = read_SSDR(reg);
265 return drv_data->rx == drv_data->rx_end;
268 static int u32_writer(struct driver_data *drv_data)
270 void *reg = drv_data->ioaddr;
272 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
273 || (drv_data->tx == drv_data->tx_end))
276 write_SSDR(*(u32 *)(drv_data->tx), reg);
282 static int u32_reader(struct driver_data *drv_data)
284 void *reg = drv_data->ioaddr;
286 while ((read_SSSR(reg) & SSSR_RNE)
287 && (drv_data->rx < drv_data->rx_end)) {
288 *(u32 *)(drv_data->rx) = read_SSDR(reg);
292 return drv_data->rx == drv_data->rx_end;
295 static void *next_transfer(struct driver_data *drv_data)
297 struct spi_message *msg = drv_data->cur_msg;
298 struct spi_transfer *trans = drv_data->cur_transfer;
300 /* Move to next transfer */
301 if (trans->transfer_list.next != &msg->transfers) {
302 drv_data->cur_transfer =
303 list_entry(trans->transfer_list.next,
306 return RUNNING_STATE;
311 static int map_dma_buffers(struct driver_data *drv_data)
313 struct spi_message *msg = drv_data->cur_msg;
314 struct device *dev = &msg->spi->dev;
316 if (!drv_data->cur_chip->enable_dma)
319 if (msg->is_dma_mapped)
320 return drv_data->rx_dma && drv_data->tx_dma;
322 if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
325 /* Modify setup if rx buffer is null */
326 if (drv_data->rx == NULL) {
327 *drv_data->null_dma_buf = 0;
328 drv_data->rx = drv_data->null_dma_buf;
329 drv_data->rx_map_len = 4;
331 drv_data->rx_map_len = drv_data->len;
334 /* Modify setup if tx buffer is null */
335 if (drv_data->tx == NULL) {
336 *drv_data->null_dma_buf = 0;
337 drv_data->tx = drv_data->null_dma_buf;
338 drv_data->tx_map_len = 4;
340 drv_data->tx_map_len = drv_data->len;
342 /* Stream map the rx buffer */
343 drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
344 drv_data->rx_map_len,
346 if (dma_mapping_error(drv_data->rx_dma))
349 /* Stream map the tx buffer */
350 drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
351 drv_data->tx_map_len,
354 if (dma_mapping_error(drv_data->tx_dma)) {
355 dma_unmap_single(dev, drv_data->rx_dma,
356 drv_data->rx_map_len, DMA_FROM_DEVICE);
363 static void unmap_dma_buffers(struct driver_data *drv_data)
367 if (!drv_data->dma_mapped)
370 if (!drv_data->cur_msg->is_dma_mapped) {
371 dev = &drv_data->cur_msg->spi->dev;
372 dma_unmap_single(dev, drv_data->rx_dma,
373 drv_data->rx_map_len, DMA_FROM_DEVICE);
374 dma_unmap_single(dev, drv_data->tx_dma,
375 drv_data->tx_map_len, DMA_TO_DEVICE);
378 drv_data->dma_mapped = 0;
381 /* caller already set message->status; dma and pio irqs are blocked */
382 static void giveback(struct driver_data *drv_data)
384 struct spi_transfer* last_transfer;
386 struct spi_message *msg;
388 spin_lock_irqsave(&drv_data->lock, flags);
389 msg = drv_data->cur_msg;
390 drv_data->cur_msg = NULL;
391 drv_data->cur_transfer = NULL;
392 drv_data->cur_chip = NULL;
393 queue_work(drv_data->workqueue, &drv_data->pump_messages);
394 spin_unlock_irqrestore(&drv_data->lock, flags);
396 last_transfer = list_entry(msg->transfers.prev,
400 if (!last_transfer->cs_change)
401 drv_data->cs_control(PXA2XX_CS_DEASSERT);
405 msg->complete(msg->context);
408 static int wait_ssp_rx_stall(void *ioaddr)
410 unsigned long limit = loops_per_jiffy << 1;
412 while ((read_SSSR(ioaddr) & SSSR_BSY) && limit--)
418 static int wait_dma_channel_stop(int channel)
420 unsigned long limit = loops_per_jiffy << 1;
422 while (!(DCSR(channel) & DCSR_STOPSTATE) && limit--)
428 void dma_error_stop(struct driver_data *drv_data, const char *msg)
430 void *reg = drv_data->ioaddr;
433 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
434 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
435 write_SSSR(drv_data->clear_sr, reg);
436 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
437 if (drv_data->ssp_type != PXA25x_SSP)
440 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
442 unmap_dma_buffers(drv_data);
444 dev_err(&drv_data->pdev->dev, "%s\n", msg);
446 drv_data->cur_msg->state = ERROR_STATE;
447 tasklet_schedule(&drv_data->pump_transfers);
450 static void dma_transfer_complete(struct driver_data *drv_data)
452 void *reg = drv_data->ioaddr;
453 struct spi_message *msg = drv_data->cur_msg;
455 /* Clear and disable interrupts on SSP and DMA channels*/
456 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
457 write_SSSR(drv_data->clear_sr, reg);
458 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
459 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
461 if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
462 dev_err(&drv_data->pdev->dev,
463 "dma_handler: dma rx channel stop failed\n");
465 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
466 dev_err(&drv_data->pdev->dev,
467 "dma_transfer: ssp rx stall failed\n");
469 unmap_dma_buffers(drv_data);
471 /* update the buffer pointer for the amount completed in dma */
472 drv_data->rx += drv_data->len -
473 (DCMD(drv_data->rx_channel) & DCMD_LENGTH);
475 /* read trailing data from fifo, it does not matter how many
476 * bytes are in the fifo just read until buffer is full
477 * or fifo is empty, which ever occurs first */
478 drv_data->read(drv_data);
480 /* return count of what was actually read */
481 msg->actual_length += drv_data->len -
482 (drv_data->rx_end - drv_data->rx);
484 /* Release chip select if requested, transfer delays are
485 * handled in pump_transfers */
486 if (drv_data->cs_change)
487 drv_data->cs_control(PXA2XX_CS_DEASSERT);
489 /* Move to next transfer */
490 msg->state = next_transfer(drv_data);
492 /* Schedule transfer tasklet */
493 tasklet_schedule(&drv_data->pump_transfers);
496 static void dma_handler(int channel, void *data)
498 struct driver_data *drv_data = data;
499 u32 irq_status = DCSR(channel) & DMA_INT_MASK;
501 if (irq_status & DCSR_BUSERR) {
503 if (channel == drv_data->tx_channel)
504 dma_error_stop(drv_data,
506 "bad bus address on tx channel");
508 dma_error_stop(drv_data,
510 "bad bus address on rx channel");
514 /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
515 if ((channel == drv_data->tx_channel)
516 && (irq_status & DCSR_ENDINTR)
517 && (drv_data->ssp_type == PXA25x_SSP)) {
519 /* Wait for rx to stall */
520 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
521 dev_err(&drv_data->pdev->dev,
522 "dma_handler: ssp rx stall failed\n");
524 /* finish this transfer, start the next */
525 dma_transfer_complete(drv_data);
529 static irqreturn_t dma_transfer(struct driver_data *drv_data)
532 void *reg = drv_data->ioaddr;
534 irq_status = read_SSSR(reg) & drv_data->mask_sr;
535 if (irq_status & SSSR_ROR) {
536 dma_error_stop(drv_data, "dma_transfer: fifo overrun");
540 /* Check for false positive timeout */
541 if ((irq_status & SSSR_TINT)
542 && (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
543 write_SSSR(SSSR_TINT, reg);
547 if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {
549 /* Clear and disable timeout interrupt, do the rest in
550 * dma_transfer_complete */
551 if (drv_data->ssp_type != PXA25x_SSP)
554 /* finish this transfer, start the next */
555 dma_transfer_complete(drv_data);
560 /* Opps problem detected */
564 static void int_error_stop(struct driver_data *drv_data, const char* msg)
566 void *reg = drv_data->ioaddr;
568 /* Stop and reset SSP */
569 write_SSSR(drv_data->clear_sr, reg);
570 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
571 if (drv_data->ssp_type != PXA25x_SSP)
574 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
576 dev_err(&drv_data->pdev->dev, "%s\n", msg);
578 drv_data->cur_msg->state = ERROR_STATE;
579 tasklet_schedule(&drv_data->pump_transfers);
582 static void int_transfer_complete(struct driver_data *drv_data)
584 void *reg = drv_data->ioaddr;
587 write_SSSR(drv_data->clear_sr, reg);
588 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
589 if (drv_data->ssp_type != PXA25x_SSP)
592 /* Update total byte transfered return count actual bytes read */
593 drv_data->cur_msg->actual_length += drv_data->len -
594 (drv_data->rx_end - drv_data->rx);
596 /* Release chip select if requested, transfer delays are
597 * handled in pump_transfers */
598 if (drv_data->cs_change)
599 drv_data->cs_control(PXA2XX_CS_DEASSERT);
601 /* Move to next transfer */
602 drv_data->cur_msg->state = next_transfer(drv_data);
604 /* Schedule transfer tasklet */
605 tasklet_schedule(&drv_data->pump_transfers);
608 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
610 void *reg = drv_data->ioaddr;
612 u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
613 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
615 u32 irq_status = read_SSSR(reg) & irq_mask;
617 if (irq_status & SSSR_ROR) {
618 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
622 if (irq_status & SSSR_TINT) {
623 write_SSSR(SSSR_TINT, reg);
624 if (drv_data->read(drv_data)) {
625 int_transfer_complete(drv_data);
630 /* Drain rx fifo, Fill tx fifo and prevent overruns */
632 if (drv_data->read(drv_data)) {
633 int_transfer_complete(drv_data);
636 } while (drv_data->write(drv_data));
638 if (drv_data->read(drv_data)) {
639 int_transfer_complete(drv_data);
643 if (drv_data->tx == drv_data->tx_end) {
644 write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg);
645 /* PXA25x_SSP has no timeout, read trailing bytes */
646 if (drv_data->ssp_type == PXA25x_SSP) {
647 if (!wait_ssp_rx_stall(reg))
649 int_error_stop(drv_data, "interrupt_transfer: "
653 if (!drv_data->read(drv_data))
655 int_error_stop(drv_data,
656 "interrupt_transfer: "
657 "trailing byte read failed");
660 int_transfer_complete(drv_data);
664 /* We did something */
668 static irqreturn_t ssp_int(int irq, void *dev_id)
670 struct driver_data *drv_data = dev_id;
671 void *reg = drv_data->ioaddr;
673 if (!drv_data->cur_msg) {
675 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
676 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
677 if (drv_data->ssp_type != PXA25x_SSP)
679 write_SSSR(drv_data->clear_sr, reg);
681 dev_err(&drv_data->pdev->dev, "bad message state "
682 "in interrupt handler\n");
688 return drv_data->transfer_handler(drv_data);
691 int set_dma_burst_and_threshold(struct chip_data *chip, struct spi_device *spi,
692 u8 bits_per_word, u32 *burst_code,
695 struct pxa2xx_spi_chip *chip_info =
696 (struct pxa2xx_spi_chip *)spi->controller_data;
703 /* Set the threshold (in registers) to equal the same amount of data
704 * as represented by burst size (in bytes). The computation below
705 * is (burst_size rounded up to nearest 8 byte, word or long word)
706 * divided by (bytes/register); the tx threshold is the inverse of
707 * the rx, so that there will always be enough data in the rx fifo
708 * to satisfy a burst, and there will always be enough space in the
709 * tx fifo to accept a burst (a tx burst will overwrite the fifo if
710 * there is not enough space), there must always remain enough empty
711 * space in the rx fifo for any data loaded to the tx fifo.
712 * Whenever burst_size (in bytes) equals bits/word, the fifo threshold
713 * will be 8, or half the fifo;
714 * The threshold can only be set to 2, 4 or 8, but not 16, because
715 * to burst 16 to the tx fifo, the fifo would have to be empty;
716 * however, the minimum fifo trigger level is 1, and the tx will
717 * request service when the fifo is at this level, with only 15 spaces.
720 /* find bytes/word */
721 if (bits_per_word <= 8)
723 else if (bits_per_word <= 16)
728 /* use struct pxa2xx_spi_chip->dma_burst_size if available */
730 req_burst_size = chip_info->dma_burst_size;
732 switch (chip->dma_burst_size) {
734 /* if the default burst size is not set,
736 chip->dma_burst_size = DCMD_BURST8;
748 if (req_burst_size <= 8) {
749 *burst_code = DCMD_BURST8;
751 } else if (req_burst_size <= 16) {
752 if (bytes_per_word == 1) {
753 /* don't burst more than 1/2 the fifo */
754 *burst_code = DCMD_BURST8;
758 *burst_code = DCMD_BURST16;
762 if (bytes_per_word == 1) {
763 /* don't burst more than 1/2 the fifo */
764 *burst_code = DCMD_BURST8;
767 } else if (bytes_per_word == 2) {
768 /* don't burst more than 1/2 the fifo */
769 *burst_code = DCMD_BURST16;
773 *burst_code = DCMD_BURST32;
778 thresh_words = burst_bytes / bytes_per_word;
780 /* thresh_words will be between 2 and 8 */
781 *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)
782 | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);
787 static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate)
789 unsigned long ssp_clk = clk_get_rate(ssp->clk);
791 if (ssp->type == PXA25x_SSP)
792 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
794 return ((ssp_clk / rate - 1) & 0xfff) << 8;
797 static void pump_transfers(unsigned long data)
799 struct driver_data *drv_data = (struct driver_data *)data;
800 struct spi_message *message = NULL;
801 struct spi_transfer *transfer = NULL;
802 struct spi_transfer *previous = NULL;
803 struct chip_data *chip = NULL;
804 struct ssp_device *ssp = drv_data->ssp;
805 void *reg = drv_data->ioaddr;
811 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
812 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
814 /* Get current state information */
815 message = drv_data->cur_msg;
816 transfer = drv_data->cur_transfer;
817 chip = drv_data->cur_chip;
819 /* Handle for abort */
820 if (message->state == ERROR_STATE) {
821 message->status = -EIO;
826 /* Handle end of message */
827 if (message->state == DONE_STATE) {
833 /* Delay if requested at end of transfer*/
834 if (message->state == RUNNING_STATE) {
835 previous = list_entry(transfer->transfer_list.prev,
838 if (previous->delay_usecs)
839 udelay(previous->delay_usecs);
842 /* Check transfer length */
843 if (transfer->len > 8191)
845 dev_warn(&drv_data->pdev->dev, "pump_transfers: transfer "
846 "length greater than 8191\n");
847 message->status = -EINVAL;
852 /* Setup the transfer state based on the type of transfer */
853 if (flush(drv_data) == 0) {
854 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
855 message->status = -EIO;
859 drv_data->n_bytes = chip->n_bytes;
860 drv_data->dma_width = chip->dma_width;
861 drv_data->cs_control = chip->cs_control;
862 drv_data->tx = (void *)transfer->tx_buf;
863 drv_data->tx_end = drv_data->tx + transfer->len;
864 drv_data->rx = transfer->rx_buf;
865 drv_data->rx_end = drv_data->rx + transfer->len;
866 drv_data->rx_dma = transfer->rx_dma;
867 drv_data->tx_dma = transfer->tx_dma;
868 drv_data->len = transfer->len & DCMD_LENGTH;
869 drv_data->write = drv_data->tx ? chip->write : null_writer;
870 drv_data->read = drv_data->rx ? chip->read : null_reader;
871 drv_data->cs_change = transfer->cs_change;
873 /* Change speed and bit per word on a per transfer */
875 if (transfer->speed_hz || transfer->bits_per_word) {
877 bits = chip->bits_per_word;
878 speed = chip->speed_hz;
880 if (transfer->speed_hz)
881 speed = transfer->speed_hz;
883 if (transfer->bits_per_word)
884 bits = transfer->bits_per_word;
886 clk_div = ssp_get_clk_div(ssp, speed);
889 drv_data->n_bytes = 1;
890 drv_data->dma_width = DCMD_WIDTH1;
891 drv_data->read = drv_data->read != null_reader ?
892 u8_reader : null_reader;
893 drv_data->write = drv_data->write != null_writer ?
894 u8_writer : null_writer;
895 } else if (bits <= 16) {
896 drv_data->n_bytes = 2;
897 drv_data->dma_width = DCMD_WIDTH2;
898 drv_data->read = drv_data->read != null_reader ?
899 u16_reader : null_reader;
900 drv_data->write = drv_data->write != null_writer ?
901 u16_writer : null_writer;
902 } else if (bits <= 32) {
903 drv_data->n_bytes = 4;
904 drv_data->dma_width = DCMD_WIDTH4;
905 drv_data->read = drv_data->read != null_reader ?
906 u32_reader : null_reader;
907 drv_data->write = drv_data->write != null_writer ?
908 u32_writer : null_writer;
910 /* if bits/word is changed in dma mode, then must check the
911 * thresholds and burst also */
912 if (chip->enable_dma) {
913 if (set_dma_burst_and_threshold(chip, message->spi,
916 if (printk_ratelimit())
917 dev_warn(&message->spi->dev,
919 "DMA burst size reduced to "
920 "match bits_per_word\n");
925 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
927 | (bits > 16 ? SSCR0_EDSS : 0);
930 message->state = RUNNING_STATE;
932 /* Try to map dma buffer and do a dma transfer if successful */
933 if ((drv_data->dma_mapped = map_dma_buffers(drv_data))) {
935 /* Ensure we have the correct interrupt handler */
936 drv_data->transfer_handler = dma_transfer;
938 /* Setup rx DMA Channel */
939 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
940 DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
941 DTADR(drv_data->rx_channel) = drv_data->rx_dma;
942 if (drv_data->rx == drv_data->null_dma_buf)
943 /* No target address increment */
944 DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
945 | drv_data->dma_width
949 DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
951 | drv_data->dma_width
955 /* Setup tx DMA Channel */
956 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
957 DSADR(drv_data->tx_channel) = drv_data->tx_dma;
958 DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
959 if (drv_data->tx == drv_data->null_dma_buf)
960 /* No source address increment */
961 DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
962 | drv_data->dma_width
966 DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
968 | drv_data->dma_width
972 /* Enable dma end irqs on SSP to detect end of transfer */
973 if (drv_data->ssp_type == PXA25x_SSP)
974 DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
976 /* Fix me, need to handle cs polarity */
977 drv_data->cs_control(PXA2XX_CS_ASSERT);
979 /* Clear status and start DMA engine */
980 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
981 write_SSSR(drv_data->clear_sr, reg);
982 DCSR(drv_data->rx_channel) |= DCSR_RUN;
983 DCSR(drv_data->tx_channel) |= DCSR_RUN;
985 /* Ensure we have the correct interrupt handler */
986 drv_data->transfer_handler = interrupt_transfer;
988 /* Fix me, need to handle cs polarity */
989 drv_data->cs_control(PXA2XX_CS_ASSERT);
992 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
993 write_SSSR(drv_data->clear_sr, reg);
996 /* see if we need to reload the config registers */
997 if ((read_SSCR0(reg) != cr0)
998 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
999 (cr1 & SSCR1_CHANGE_MASK)) {
1001 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
1002 if (drv_data->ssp_type != PXA25x_SSP)
1003 write_SSTO(chip->timeout, reg);
1004 write_SSCR1(cr1, reg);
1005 write_SSCR0(cr0, reg);
1007 if (drv_data->ssp_type != PXA25x_SSP)
1008 write_SSTO(chip->timeout, reg);
1009 write_SSCR1(cr1, reg);
1013 static void pump_messages(struct work_struct *work)
1015 struct driver_data *drv_data =
1016 container_of(work, struct driver_data, pump_messages);
1017 unsigned long flags;
1019 /* Lock queue and check for queue work */
1020 spin_lock_irqsave(&drv_data->lock, flags);
1021 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
1023 spin_unlock_irqrestore(&drv_data->lock, flags);
1027 /* Make sure we are not already running a message */
1028 if (drv_data->cur_msg) {
1029 spin_unlock_irqrestore(&drv_data->lock, flags);
1033 /* Extract head of queue */
1034 drv_data->cur_msg = list_entry(drv_data->queue.next,
1035 struct spi_message, queue);
1036 list_del_init(&drv_data->cur_msg->queue);
1038 /* Initial message state*/
1039 drv_data->cur_msg->state = START_STATE;
1040 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1041 struct spi_transfer,
1044 /* prepare to setup the SSP, in pump_transfers, using the per
1045 * chip configuration */
1046 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1048 /* Mark as busy and launch transfers */
1049 tasklet_schedule(&drv_data->pump_transfers);
1052 spin_unlock_irqrestore(&drv_data->lock, flags);
1055 static int transfer(struct spi_device *spi, struct spi_message *msg)
1057 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1058 unsigned long flags;
1060 spin_lock_irqsave(&drv_data->lock, flags);
1062 if (drv_data->run == QUEUE_STOPPED) {
1063 spin_unlock_irqrestore(&drv_data->lock, flags);
1067 msg->actual_length = 0;
1068 msg->status = -EINPROGRESS;
1069 msg->state = START_STATE;
1071 list_add_tail(&msg->queue, &drv_data->queue);
1073 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1074 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1076 spin_unlock_irqrestore(&drv_data->lock, flags);
1081 /* the spi->mode bits understood by this driver: */
1082 #define MODEBITS (SPI_CPOL | SPI_CPHA)
1084 static int setup(struct spi_device *spi)
1086 struct pxa2xx_spi_chip *chip_info = NULL;
1087 struct chip_data *chip;
1088 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1089 struct ssp_device *ssp = drv_data->ssp;
1090 unsigned int clk_div;
1092 if (!spi->bits_per_word)
1093 spi->bits_per_word = 8;
1095 if (drv_data->ssp_type != PXA25x_SSP
1096 && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
1097 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1098 "b/w not 4-32 for type non-PXA25x_SSP\n",
1099 drv_data->ssp_type, spi->bits_per_word);
1102 else if (drv_data->ssp_type == PXA25x_SSP
1103 && (spi->bits_per_word < 4
1104 || spi->bits_per_word > 16)) {
1105 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1106 "b/w not 4-16 for type PXA25x_SSP\n",
1107 drv_data->ssp_type, spi->bits_per_word);
1111 if (spi->mode & ~MODEBITS) {
1112 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
1113 spi->mode & ~MODEBITS);
1117 /* Only alloc on first setup */
1118 chip = spi_get_ctldata(spi);
1120 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1123 "failed setup: can't allocate chip data\n");
1127 chip->cs_control = null_cs_control;
1128 chip->enable_dma = 0;
1129 chip->timeout = 1000;
1130 chip->threshold = SSCR1_RxTresh(1) | SSCR1_TxTresh(1);
1131 chip->dma_burst_size = drv_data->master_info->enable_dma ?
1135 /* protocol drivers may change the chip settings, so...
1136 * if chip_info exists, use it */
1137 chip_info = spi->controller_data;
1139 /* chip_info isn't always needed */
1142 if (chip_info->cs_control)
1143 chip->cs_control = chip_info->cs_control;
1145 chip->timeout = chip_info->timeout;
1147 chip->threshold = (SSCR1_RxTresh(chip_info->rx_threshold) &
1149 (SSCR1_TxTresh(chip_info->tx_threshold) &
1152 chip->enable_dma = chip_info->dma_burst_size != 0
1153 && drv_data->master_info->enable_dma;
1154 chip->dma_threshold = 0;
1156 if (chip_info->enable_loopback)
1157 chip->cr1 = SSCR1_LBM;
1160 /* set dma burst and threshold outside of chip_info path so that if
1161 * chip_info goes away after setting chip->enable_dma, the
1162 * burst and threshold can still respond to changes in bits_per_word */
1163 if (chip->enable_dma) {
1164 /* set up legal burst and threshold for dma */
1165 if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word,
1166 &chip->dma_burst_size,
1167 &chip->dma_threshold)) {
1168 dev_warn(&spi->dev, "in setup: DMA burst size reduced "
1169 "to match bits_per_word\n");
1173 clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz);
1174 chip->speed_hz = spi->max_speed_hz;
1178 | SSCR0_DataSize(spi->bits_per_word > 16 ?
1179 spi->bits_per_word - 16 : spi->bits_per_word)
1181 | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
1182 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1183 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1184 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1186 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1187 if (drv_data->ssp_type != PXA25x_SSP)
1188 dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n",
1190 clk_get_rate(ssp->clk)
1191 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1194 dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n",
1196 clk_get_rate(ssp->clk)
1197 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1200 if (spi->bits_per_word <= 8) {
1202 chip->dma_width = DCMD_WIDTH1;
1203 chip->read = u8_reader;
1204 chip->write = u8_writer;
1205 } else if (spi->bits_per_word <= 16) {
1207 chip->dma_width = DCMD_WIDTH2;
1208 chip->read = u16_reader;
1209 chip->write = u16_writer;
1210 } else if (spi->bits_per_word <= 32) {
1211 chip->cr0 |= SSCR0_EDSS;
1213 chip->dma_width = DCMD_WIDTH4;
1214 chip->read = u32_reader;
1215 chip->write = u32_writer;
1217 dev_err(&spi->dev, "invalid wordsize\n");
1220 chip->bits_per_word = spi->bits_per_word;
1222 spi_set_ctldata(spi, chip);
1227 static void cleanup(struct spi_device *spi)
1229 struct chip_data *chip = spi_get_ctldata(spi);
1234 static int __init init_queue(struct driver_data *drv_data)
1236 INIT_LIST_HEAD(&drv_data->queue);
1237 spin_lock_init(&drv_data->lock);
1239 drv_data->run = QUEUE_STOPPED;
1242 tasklet_init(&drv_data->pump_transfers,
1243 pump_transfers, (unsigned long)drv_data);
1245 INIT_WORK(&drv_data->pump_messages, pump_messages);
1246 drv_data->workqueue = create_singlethread_workqueue(
1247 drv_data->master->dev.parent->bus_id);
1248 if (drv_data->workqueue == NULL)
1254 static int start_queue(struct driver_data *drv_data)
1256 unsigned long flags;
1258 spin_lock_irqsave(&drv_data->lock, flags);
1260 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1261 spin_unlock_irqrestore(&drv_data->lock, flags);
1265 drv_data->run = QUEUE_RUNNING;
1266 drv_data->cur_msg = NULL;
1267 drv_data->cur_transfer = NULL;
1268 drv_data->cur_chip = NULL;
1269 spin_unlock_irqrestore(&drv_data->lock, flags);
1271 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1276 static int stop_queue(struct driver_data *drv_data)
1278 unsigned long flags;
1279 unsigned limit = 500;
1282 spin_lock_irqsave(&drv_data->lock, flags);
1284 /* This is a bit lame, but is optimized for the common execution path.
1285 * A wait_queue on the drv_data->busy could be used, but then the common
1286 * execution path (pump_messages) would be required to call wake_up or
1287 * friends on every SPI message. Do this instead */
1288 drv_data->run = QUEUE_STOPPED;
1289 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1290 spin_unlock_irqrestore(&drv_data->lock, flags);
1292 spin_lock_irqsave(&drv_data->lock, flags);
1295 if (!list_empty(&drv_data->queue) || drv_data->busy)
1298 spin_unlock_irqrestore(&drv_data->lock, flags);
1303 static int destroy_queue(struct driver_data *drv_data)
1307 status = stop_queue(drv_data);
1308 /* we are unloading the module or failing to load (only two calls
1309 * to this routine), and neither call can handle a return value.
1310 * However, destroy_workqueue calls flush_workqueue, and that will
1311 * block until all work is done. If the reason that stop_queue
1312 * timed out is that the work will never finish, then it does no
1313 * good to call destroy_workqueue, so return anyway. */
1317 destroy_workqueue(drv_data->workqueue);
1322 static int __init pxa2xx_spi_probe(struct platform_device *pdev)
1324 struct device *dev = &pdev->dev;
1325 struct pxa2xx_spi_master *platform_info;
1326 struct spi_master *master;
1327 struct driver_data *drv_data = 0;
1328 struct ssp_device *ssp;
1331 platform_info = dev->platform_data;
1333 ssp = ssp_request(pdev->id, pdev->name);
1335 dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id);
1339 /* Allocate master with space for drv_data and null dma buffer */
1340 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1342 dev_err(&pdev->dev, "can not alloc spi_master\n");
1346 drv_data = spi_master_get_devdata(master);
1347 drv_data->master = master;
1348 drv_data->master_info = platform_info;
1349 drv_data->pdev = pdev;
1350 drv_data->ssp = ssp;
1352 master->bus_num = pdev->id;
1353 master->num_chipselect = platform_info->num_chipselect;
1354 master->cleanup = cleanup;
1355 master->setup = setup;
1356 master->transfer = transfer;
1358 drv_data->ssp_type = ssp->type;
1359 drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
1360 sizeof(struct driver_data)), 8);
1362 drv_data->ioaddr = ssp->mmio_base;
1363 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1364 if (ssp->type == PXA25x_SSP) {
1365 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1366 drv_data->dma_cr1 = 0;
1367 drv_data->clear_sr = SSSR_ROR;
1368 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1370 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1371 drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
1372 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1373 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1376 status = request_irq(ssp->irq, ssp_int, 0, dev->bus_id, drv_data);
1378 dev_err(&pdev->dev, "can not get IRQ\n");
1379 goto out_error_master_alloc;
1382 /* Setup DMA if requested */
1383 drv_data->tx_channel = -1;
1384 drv_data->rx_channel = -1;
1385 if (platform_info->enable_dma) {
1387 /* Get two DMA channels (rx and tx) */
1388 drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
1392 if (drv_data->rx_channel < 0) {
1393 dev_err(dev, "problem (%d) requesting rx channel\n",
1394 drv_data->rx_channel);
1396 goto out_error_irq_alloc;
1398 drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
1402 if (drv_data->tx_channel < 0) {
1403 dev_err(dev, "problem (%d) requesting tx channel\n",
1404 drv_data->tx_channel);
1406 goto out_error_dma_alloc;
1409 DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel;
1410 DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel;
1413 /* Enable SOC clock */
1414 clk_enable(ssp->clk);
1416 /* Load default SSP configuration */
1417 write_SSCR0(0, drv_data->ioaddr);
1418 write_SSCR1(SSCR1_RxTresh(4) | SSCR1_TxTresh(12), drv_data->ioaddr);
1419 write_SSCR0(SSCR0_SerClkDiv(2)
1421 | SSCR0_DataSize(8),
1423 if (drv_data->ssp_type != PXA25x_SSP)
1424 write_SSTO(0, drv_data->ioaddr);
1425 write_SSPSP(0, drv_data->ioaddr);
1427 /* Initial and start queue */
1428 status = init_queue(drv_data);
1430 dev_err(&pdev->dev, "problem initializing queue\n");
1431 goto out_error_clock_enabled;
1433 status = start_queue(drv_data);
1435 dev_err(&pdev->dev, "problem starting queue\n");
1436 goto out_error_clock_enabled;
1439 /* Register with the SPI framework */
1440 platform_set_drvdata(pdev, drv_data);
1441 status = spi_register_master(master);
1443 dev_err(&pdev->dev, "problem registering spi master\n");
1444 goto out_error_queue_alloc;
1449 out_error_queue_alloc:
1450 destroy_queue(drv_data);
1452 out_error_clock_enabled:
1453 clk_disable(ssp->clk);
1455 out_error_dma_alloc:
1456 if (drv_data->tx_channel != -1)
1457 pxa_free_dma(drv_data->tx_channel);
1458 if (drv_data->rx_channel != -1)
1459 pxa_free_dma(drv_data->rx_channel);
1461 out_error_irq_alloc:
1462 free_irq(ssp->irq, drv_data);
1464 out_error_master_alloc:
1465 spi_master_put(master);
1470 static int pxa2xx_spi_remove(struct platform_device *pdev)
1472 struct driver_data *drv_data = platform_get_drvdata(pdev);
1473 struct ssp_device *ssp = drv_data->ssp;
1479 /* Remove the queue */
1480 status = destroy_queue(drv_data);
1482 /* the kernel does not check the return status of this
1483 * this routine (mod->exit, within the kernel). Therefore
1484 * nothing is gained by returning from here, the module is
1485 * going away regardless, and we should not leave any more
1486 * resources allocated than necessary. We cannot free the
1487 * message memory in drv_data->queue, but we can release the
1488 * resources below. I think the kernel should honor -EBUSY
1490 dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not "
1491 "complete, message memory not freed\n");
1493 /* Disable the SSP at the peripheral and SOC level */
1494 write_SSCR0(0, drv_data->ioaddr);
1495 clk_disable(ssp->clk);
1498 if (drv_data->master_info->enable_dma) {
1499 DRCMR(ssp->drcmr_rx) = 0;
1500 DRCMR(ssp->drcmr_tx) = 0;
1501 pxa_free_dma(drv_data->tx_channel);
1502 pxa_free_dma(drv_data->rx_channel);
1506 free_irq(ssp->irq, drv_data);
1511 /* Disconnect from the SPI framework */
1512 spi_unregister_master(drv_data->master);
1514 /* Prevent double remove */
1515 platform_set_drvdata(pdev, NULL);
1520 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1524 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1525 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1529 static int suspend_devices(struct device *dev, void *pm_message)
1531 pm_message_t *state = pm_message;
1533 if (dev->power.power_state.event != state->event) {
1534 dev_warn(dev, "pm state does not match request\n");
1541 static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1543 struct driver_data *drv_data = platform_get_drvdata(pdev);
1544 struct ssp_device *ssp = drv_data->ssp;
1547 /* Check all childern for current power state */
1548 if (device_for_each_child(&pdev->dev, &state, suspend_devices) != 0) {
1549 dev_warn(&pdev->dev, "suspend aborted\n");
1553 status = stop_queue(drv_data);
1556 write_SSCR0(0, drv_data->ioaddr);
1557 clk_disable(ssp->clk);
1562 static int pxa2xx_spi_resume(struct platform_device *pdev)
1564 struct driver_data *drv_data = platform_get_drvdata(pdev);
1565 struct ssp_device *ssp = drv_data->ssp;
1568 /* Enable the SSP clock */
1569 clk_disable(ssp->clk);
1571 /* Start the queue running */
1572 status = start_queue(drv_data);
1574 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1581 #define pxa2xx_spi_suspend NULL
1582 #define pxa2xx_spi_resume NULL
1583 #endif /* CONFIG_PM */
1585 static struct platform_driver driver = {
1587 .name = "pxa2xx-spi",
1588 .bus = &platform_bus_type,
1589 .owner = THIS_MODULE,
1591 .remove = pxa2xx_spi_remove,
1592 .shutdown = pxa2xx_spi_shutdown,
1593 .suspend = pxa2xx_spi_suspend,
1594 .resume = pxa2xx_spi_resume,
1597 static int __init pxa2xx_spi_init(void)
1599 return platform_driver_probe(&driver, pxa2xx_spi_probe);
1601 module_init(pxa2xx_spi_init);
1603 static void __exit pxa2xx_spi_exit(void)
1605 platform_driver_unregister(&driver);
1607 module_exit(pxa2xx_spi_exit);