2 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
4 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
6 * This driver has been based on the spi-gpio.c:
7 * Copyright (C) 2006,2008 David Brownell
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/delay.h>
18 #include <linux/spinlock.h>
19 #include <linux/platform_device.h>
21 #include <linux/spi/spi.h>
22 #include <linux/spi/spi_bitbang.h>
23 #include <linux/bitops.h>
24 #include <linux/gpio.h>
25 #include <linux/clk.h>
26 #include <linux/err.h>
28 #include <asm/mach-ath79/ar71xx_regs.h>
29 #include <asm/mach-ath79/ath79_spi_platform.h>
31 #define DRV_NAME "ath79-spi"
33 #define ATH79_SPI_RRW_DELAY_FACTOR 12000
34 #define MHZ (1000 * 1000)
37 struct spi_bitbang bitbang;
45 static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
47 return ioread32(sp->base + reg);
50 static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val)
52 iowrite32(val, sp->base + reg);
55 static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
57 return spi_master_get_devdata(spi->master);
60 static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs)
62 if (nsecs > sp->rrw_delay)
63 ndelay(nsecs - sp->rrw_delay);
66 static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
68 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
69 int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
72 /* set initial clock polarity */
73 if (spi->mode & SPI_CPOL)
74 sp->ioc_base |= AR71XX_SPI_IOC_CLK;
76 sp->ioc_base &= ~AR71XX_SPI_IOC_CLK;
78 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
81 if (spi->chip_select) {
82 /* SPI is normally active-low */
83 gpio_set_value(spi->cs_gpio, cs_high);
86 sp->ioc_base |= AR71XX_SPI_IOC_CS0;
88 sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
90 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
95 static void ath79_spi_enable(struct ath79_spi *sp)
97 /* enable GPIO mode */
98 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
100 /* save CTRL register */
101 sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
102 sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
104 /* TODO: setup speed? */
105 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
108 static void ath79_spi_disable(struct ath79_spi *sp)
110 /* restore CTRL register */
111 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
112 /* disable GPIO mode */
113 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
116 static int ath79_spi_setup_cs(struct spi_device *spi)
120 if (spi->chip_select && !gpio_is_valid(spi->cs_gpio))
124 if (spi->chip_select) {
127 flags = GPIOF_DIR_OUT;
128 if (spi->mode & SPI_CS_HIGH)
129 flags |= GPIOF_INIT_LOW;
131 flags |= GPIOF_INIT_HIGH;
133 status = gpio_request_one(spi->cs_gpio, flags,
134 dev_name(&spi->dev));
140 static void ath79_spi_cleanup_cs(struct spi_device *spi)
142 if (spi->chip_select) {
143 gpio_free(spi->cs_gpio);
147 static int ath79_spi_setup(struct spi_device *spi)
151 if (!spi->controller_state) {
152 status = ath79_spi_setup_cs(spi);
157 status = spi_bitbang_setup(spi);
158 if (status && !spi->controller_state)
159 ath79_spi_cleanup_cs(spi);
164 static void ath79_spi_cleanup(struct spi_device *spi)
166 ath79_spi_cleanup_cs(spi);
167 spi_bitbang_cleanup(spi);
170 static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs,
173 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
174 u32 ioc = sp->ioc_base;
176 /* clock starts at inactive polarity */
177 for (word <<= (32 - bits); likely(bits); bits--) {
180 if (word & (1 << 31))
181 out = ioc | AR71XX_SPI_IOC_DO;
183 out = ioc & ~AR71XX_SPI_IOC_DO;
185 /* setup MSB (to slave) on trailing edge */
186 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
187 ath79_spi_delay(sp, nsecs);
188 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
189 ath79_spi_delay(sp, nsecs);
191 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
196 return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
199 static int ath79_spi_probe(struct platform_device *pdev)
201 struct spi_master *master;
202 struct ath79_spi *sp;
203 struct ath79_spi_platform_data *pdata;
208 master = spi_alloc_master(&pdev->dev, sizeof(*sp));
209 if (master == NULL) {
210 dev_err(&pdev->dev, "failed to allocate spi master\n");
214 sp = spi_master_get_devdata(master);
215 master->dev.of_node = pdev->dev.of_node;
216 platform_set_drvdata(pdev, sp);
218 pdata = dev_get_platdata(&pdev->dev);
220 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
221 master->setup = ath79_spi_setup;
222 master->cleanup = ath79_spi_cleanup;
224 master->bus_num = pdata->bus_num;
225 master->num_chipselect = pdata->num_chipselect;
228 sp->bitbang.master = master;
229 sp->bitbang.chipselect = ath79_spi_chipselect;
230 sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
231 sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
232 sp->bitbang.flags = SPI_CS_HIGH;
234 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
240 sp->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
246 sp->clk = devm_clk_get(&pdev->dev, "ahb");
247 if (IS_ERR(sp->clk)) {
248 ret = PTR_ERR(sp->clk);
252 ret = clk_enable(sp->clk);
256 rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
259 goto err_clk_disable;
262 sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
263 dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
266 ath79_spi_enable(sp);
267 ret = spi_bitbang_start(&sp->bitbang);
274 ath79_spi_disable(sp);
276 clk_disable(sp->clk);
278 spi_master_put(sp->bitbang.master);
283 static int ath79_spi_remove(struct platform_device *pdev)
285 struct ath79_spi *sp = platform_get_drvdata(pdev);
287 spi_bitbang_stop(&sp->bitbang);
288 ath79_spi_disable(sp);
289 clk_disable(sp->clk);
290 spi_master_put(sp->bitbang.master);
295 static void ath79_spi_shutdown(struct platform_device *pdev)
297 ath79_spi_remove(pdev);
300 static const struct of_device_id ath79_spi_of_match[] = {
301 { .compatible = "qca,ar7100-spi", },
305 static struct platform_driver ath79_spi_driver = {
306 .probe = ath79_spi_probe,
307 .remove = ath79_spi_remove,
308 .shutdown = ath79_spi_shutdown,
311 .of_match_table = ath79_spi_of_match,
314 module_platform_driver(ath79_spi_driver);
316 MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
317 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
318 MODULE_LICENSE("GPL v2");
319 MODULE_ALIAS("platform:" DRV_NAME);