drivers/spi/spi-dw.c

   1 /*
   2  * Designware SPI core controller driver (refer pxa2xx_spi.c)
   3  *
   4  * Copyright (c) 2009, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #include <linux/dma-mapping.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/module.h>
  19 #include <linux/highmem.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/gpio.h>
  24
  25 #include "spi-dw.h"
  26
  27 #ifdef CONFIG_DEBUG_FS
  28 #include <linux/debugfs.h>
  29 #endif
  30
  31 /* Slave spi_dev related */
  32 struct chip_data {
  33         u8 cs;                  /* chip select pin */
  34         u8 tmode;               /* TR/TO/RO/EEPROM */
  35         u8 type;                /* SPI/SSP/MicroWire */
  36
  37         u8 poll_mode;           /* 1 means use poll mode */
  38
  39         u8 enable_dma;
  40         u16 clk_div;            /* baud rate divider */
  41         u32 speed_hz;           /* baud rate */
  42         void (*cs_control)(u32 command);
  43 };
  44
  45 #ifdef CONFIG_DEBUG_FS
  46 #define SPI_REGS_BUFSIZE        1024
  47 static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
  48                 size_t count, loff_t *ppos)
  49 {
  50         struct dw_spi *dws = file->private_data;
  51         char *buf;
  52         u32 len = 0;
  53         ssize_t ret;
  54
  55         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
  56         if (!buf)
  57                 return 0;
  58
  59         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  60                         "%s registers:\n", dev_name(&dws->master->dev));
  61         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  62                         "=================================\n");
  63         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  64                         "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
  65         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  66                         "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
  67         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  68                         "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
  69         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  70                         "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
  71         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  72                         "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
  73         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  74                         "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
  75         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  76                         "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
  77         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  78                         "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
  79         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  80                         "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
  81         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  82                         "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
  83         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  84                         "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
  85         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  86                         "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
  87         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  88                         "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
  89         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  90                         "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
  91         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  92                         "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
  93         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  94                         "=================================\n");
  95
  96         ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
  97         kfree(buf);
  98         return ret;
  99 }
 100
 101 static const struct file_operations dw_spi_regs_ops = {
 102         .owner          = THIS_MODULE,
 103         .open           = simple_open,
 104         .read           = dw_spi_show_regs,
 105         .llseek         = default_llseek,
 106 };
 107
 108 static int dw_spi_debugfs_init(struct dw_spi *dws)
 109 {
 110         char name[32];
 111
 112         snprintf(name, 32, "dw_spi%d", dws->master->bus_num);
 113         dws->debugfs = debugfs_create_dir(name, NULL);
 114         if (!dws->debugfs)
 115                 return -ENOMEM;
 116
 117         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 118                 dws->debugfs, (void *)dws, &dw_spi_regs_ops);
 119         return 0;
 120 }
 121
 122 static void dw_spi_debugfs_remove(struct dw_spi *dws)
 123 {
 124         debugfs_remove_recursive(dws->debugfs);
 125 }
 126
 127 #else
 128 static inline int dw_spi_debugfs_init(struct dw_spi *dws)
 129 {
 130         return 0;
 131 }
 132
 133 static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
 134 {
 135 }
 136 #endif /* CONFIG_DEBUG_FS */
 137
 138 static void dw_spi_set_cs(struct spi_device *spi, bool enable)
 139 {
 140         struct dw_spi *dws = spi_master_get_devdata(spi->master);
 141         struct chip_data *chip = spi_get_ctldata(spi);
 142
 143         /* Chip select logic is inverted from spi_set_cs() */
 144         if (chip && chip->cs_control)
 145                 chip->cs_control(!enable);
 146
 147         if (!enable)
 148                 dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
 149 }
 150
 151 /* Return the max entries we can fill into tx fifo */
 152 static inline u32 tx_max(struct dw_spi *dws)
 153 {
 154         u32 tx_left, tx_room, rxtx_gap;
 155
 156         tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
 157         tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
 158
 159         /*
 160          * Another concern is about the tx/rx mismatch, we
 161          * though to use (dws->fifo_len - rxflr - txflr) as
 162          * one maximum value for tx, but it doesn't cover the
 163          * data which is out of tx/rx fifo and inside the
 164          * shift registers. So a control from sw point of
 165          * view is taken.
 166          */
 167         rxtx_gap =  ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
 168                         / dws->n_bytes;
 169
 170         return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
 171 }
 172
 173 /* Return the max entries we should read out of rx fifo */
 174 static inline u32 rx_max(struct dw_spi *dws)
 175 {
 176         u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
 177
 178         return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
 179 }
 180
 181 static void dw_writer(struct dw_spi *dws)
 182 {
 183         u32 max = tx_max(dws);
 184         u16 txw = 0;
 185
 186         while (max--) {
 187                 /* Set the tx word if the transfer's original "tx" is not null */
 188                 if (dws->tx_end - dws->len) {
 189                         if (dws->n_bytes == 1)
 190                                 txw = *(u8 *)(dws->tx);
 191                         else
 192                                 txw = *(u16 *)(dws->tx);
 193                 }
 194                 dw_write_io_reg(dws, DW_SPI_DR, txw);
 195                 dws->tx += dws->n_bytes;
 196         }
 197 }
 198
 199 static void dw_reader(struct dw_spi *dws)
 200 {
 201         u32 max = rx_max(dws);
 202         u16 rxw;
 203
 204         while (max--) {
 205                 rxw = dw_read_io_reg(dws, DW_SPI_DR);
 206                 /* Care rx only if the transfer's original "rx" is not null */
 207                 if (dws->rx_end - dws->len) {
 208                         if (dws->n_bytes == 1)
 209                                 *(u8 *)(dws->rx) = rxw;
 210                         else
 211                                 *(u16 *)(dws->rx) = rxw;
 212                 }
 213                 dws->rx += dws->n_bytes;
 214         }
 215 }
 216
 217 static void int_error_stop(struct dw_spi *dws, const char *msg)
 218 {
 219         spi_reset_chip(dws);
 220
 221         dev_err(&dws->master->dev, "%s\n", msg);
 222         dws->master->cur_msg->status = -EIO;
 223         spi_finalize_current_transfer(dws->master);
 224 }
 225
 226 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
 227 {
 228         u16 irq_status = dw_readl(dws, DW_SPI_ISR);
 229
 230         /* Error handling */
 231         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
 232                 dw_readl(dws, DW_SPI_ICR);
 233                 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
 234                 return IRQ_HANDLED;
 235         }
 236
 237         dw_reader(dws);
 238         if (dws->rx_end == dws->rx) {
 239                 spi_mask_intr(dws, SPI_INT_TXEI);
 240                 spi_finalize_current_transfer(dws->master);
 241                 return IRQ_HANDLED;
 242         }
 243         if (irq_status & SPI_INT_TXEI) {
 244                 spi_mask_intr(dws, SPI_INT_TXEI);
 245                 dw_writer(dws);
 246                 /* Enable TX irq always, it will be disabled when RX finished */
 247                 spi_umask_intr(dws, SPI_INT_TXEI);
 248         }
 249
 250         return IRQ_HANDLED;
 251 }
 252
 253 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
 254 {
 255         struct spi_master *master = dev_id;
 256         struct dw_spi *dws = spi_master_get_devdata(master);
 257         u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;
 258
 259         if (!irq_status)
 260                 return IRQ_NONE;
 261
 262         if (!master->cur_msg) {
 263                 spi_mask_intr(dws, SPI_INT_TXEI);
 264                 return IRQ_HANDLED;
 265         }
 266
 267         return dws->transfer_handler(dws);
 268 }
 269
 270 /* Must be called inside pump_transfers() */
 271 static int poll_transfer(struct dw_spi *dws)
 272 {
 273         do {
 274                 dw_writer(dws);
 275                 dw_reader(dws);
 276                 cpu_relax();
 277         } while (dws->rx_end > dws->rx);
 278
 279         return 0;
 280 }
 281
 282 static int dw_spi_transfer_one(struct spi_master *master,
 283                 struct spi_device *spi, struct spi_transfer *transfer)
 284 {
 285         struct dw_spi *dws = spi_master_get_devdata(master);
 286         struct chip_data *chip = spi_get_ctldata(spi);
 287         u8 imask = 0;
 288         u16 txlevel = 0;
 289         u32 cr0;
 290         int ret;
 291
 292         dws->dma_mapped = 0;
 293
 294         dws->tx = (void *)transfer->tx_buf;
 295         dws->tx_end = dws->tx + transfer->len;
 296         dws->rx = transfer->rx_buf;
 297         dws->rx_end = dws->rx + transfer->len;
 298         dws->len = transfer->len;
 299
 300         spi_enable_chip(dws, 0);
 301
 302         /* Handle per transfer options for bpw and speed */
 303         if (transfer->speed_hz != dws->current_freq) {
 304                 if (transfer->speed_hz != chip->speed_hz) {
 305                         /* clk_div doesn't support odd number */
 306                         chip->clk_div = (DIV_ROUND_UP(dws->max_freq, transfer->speed_hz) + 1) & 0xfffe;
 307                         chip->speed_hz = transfer->speed_hz;
 308                 }
 309                 dws->current_freq = transfer->speed_hz;
 310                 spi_set_clk(dws, chip->clk_div);
 311         }
 312         if (transfer->bits_per_word == 8) {
 313                 dws->n_bytes = 1;
 314                 dws->dma_width = 1;
 315         } else if (transfer->bits_per_word == 16) {
 316                 dws->n_bytes = 2;
 317                 dws->dma_width = 2;
 318         } else {
 319                 return -EINVAL;
 320         }
 321         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
 322         cr0 = (transfer->bits_per_word - 1)
 323                 | (chip->type << SPI_FRF_OFFSET)
 324                 | (spi->mode << SPI_MODE_OFFSET)
 325                 | (chip->tmode << SPI_TMOD_OFFSET);
 326
 327         /*
 328          * Adjust transfer mode if necessary. Requires platform dependent
 329          * chipselect mechanism.
 330          */
 331         if (chip->cs_control) {
 332                 if (dws->rx && dws->tx)
 333                         chip->tmode = SPI_TMOD_TR;
 334                 else if (dws->rx)
 335                         chip->tmode = SPI_TMOD_RO;
 336                 else
 337                         chip->tmode = SPI_TMOD_TO;
 338
 339                 cr0 &= ~SPI_TMOD_MASK;
 340                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
 341         }
 342
 343         dw_writel(dws, DW_SPI_CTRL0, cr0);
 344
 345         /* Check if current transfer is a DMA transaction */
 346         if (master->can_dma && master->can_dma(master, spi, transfer))
 347                 dws->dma_mapped = master->cur_msg_mapped;
 348
 349         /* For poll mode just disable all interrupts */
 350         spi_mask_intr(dws, 0xff);
 351
 352         /*
 353          * Interrupt mode
 354          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
 355          */
 356         if (dws->dma_mapped) {
 357                 ret = dws->dma_ops->dma_setup(dws, transfer);
 358                 if (ret < 0) {
 359                         spi_enable_chip(dws, 1);
 360                         return ret;
 361                 }
 362         } else if (!chip->poll_mode) {
 363                 txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
 364                 dw_writel(dws, DW_SPI_TXFLTR, txlevel);
 365
 366                 /* Set the interrupt mask */
 367                 imask |= SPI_INT_TXEI | SPI_INT_TXOI |
 368                          SPI_INT_RXUI | SPI_INT_RXOI;
 369                 spi_umask_intr(dws, imask);
 370
 371                 dws->transfer_handler = interrupt_transfer;
 372         }
 373
 374         spi_enable_chip(dws, 1);
 375
 376         if (dws->dma_mapped) {
 377                 ret = dws->dma_ops->dma_transfer(dws, transfer);
 378                 if (ret < 0)
 379                         return ret;
 380         }
 381
 382         if (chip->poll_mode)
 383                 return poll_transfer(dws);
 384
 385         return 1;
 386 }
 387
 388 static void dw_spi_handle_err(struct spi_master *master,
 389                 struct spi_message *msg)
 390 {
 391         struct dw_spi *dws = spi_master_get_devdata(master);
 392
 393         if (dws->dma_mapped)
 394                 dws->dma_ops->dma_stop(dws);
 395
 396         spi_reset_chip(dws);
 397 }
 398
 399 /* This may be called twice for each spi dev */
 400 static int dw_spi_setup(struct spi_device *spi)
 401 {
 402         struct dw_spi_chip *chip_info = NULL;
 403         struct chip_data *chip;
 404         int ret;
 405
 406         /* Only alloc on first setup */
 407         chip = spi_get_ctldata(spi);
 408         if (!chip) {
 409                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 410                 if (!chip)
 411                         return -ENOMEM;
 412                 spi_set_ctldata(spi, chip);
 413         }
 414
 415         /*
 416          * Protocol drivers may change the chip settings, so...
 417          * if chip_info exists, use it
 418          */
 419         chip_info = spi->controller_data;
 420
 421         /* chip_info doesn't always exist */
 422         if (chip_info) {
 423                 if (chip_info->cs_control)
 424                         chip->cs_control = chip_info->cs_control;
 425
 426                 chip->poll_mode = chip_info->poll_mode;
 427                 chip->type = chip_info->type;
 428         }
 429
 430         chip->tmode = SPI_TMOD_TR;
 431
 432         if (gpio_is_valid(spi->cs_gpio)) {
 433                 ret = gpio_direction_output(spi->cs_gpio,
 434                                 !(spi->mode & SPI_CS_HIGH));
 435                 if (ret)
 436                         return ret;
 437         }
 438
 439         return 0;
 440 }
 441
 442 static void dw_spi_cleanup(struct spi_device *spi)
 443 {
 444         struct chip_data *chip = spi_get_ctldata(spi);
 445
 446         kfree(chip);
 447         spi_set_ctldata(spi, NULL);
 448 }
 449
 450 /* Restart the controller, disable all interrupts, clean rx fifo */
 451 static void spi_hw_init(struct device *dev, struct dw_spi *dws)
 452 {
 453         spi_reset_chip(dws);
 454
 455         /*
 456          * Try to detect the FIFO depth if not set by interface driver,
 457          * the depth could be from 2 to 256 from HW spec
 458          */
 459         if (!dws->fifo_len) {
 460                 u32 fifo;
 461
 462                 for (fifo = 1; fifo < 256; fifo++) {
 463                         dw_writel(dws, DW_SPI_TXFLTR, fifo);
 464                         if (fifo != dw_readl(dws, DW_SPI_TXFLTR))
 465                                 break;
 466                 }
 467                 dw_writel(dws, DW_SPI_TXFLTR, 0);
 468
 469                 dws->fifo_len = (fifo == 1) ? 0 : fifo;
 470                 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
 471         }
 472 }
 473
 474 int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
 475 {
 476         struct spi_master *master;
 477         int ret;
 478
 479         BUG_ON(dws == NULL);
 480
 481         master = spi_alloc_master(dev, 0);
 482         if (!master)
 483                 return -ENOMEM;
 484
 485         dws->master = master;
 486         dws->type = SSI_MOTO_SPI;
 487         dws->dma_inited = 0;
 488         dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
 489
 490         ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev),
 491                           master);
 492         if (ret < 0) {
 493                 dev_err(dev, "can not get IRQ\n");
 494                 goto err_free_master;
 495         }
 496
 497         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
 498         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
 499         master->bus_num = dws->bus_num;
 500         master->num_chipselect = dws->num_cs;
 501         master->setup = dw_spi_setup;
 502         master->cleanup = dw_spi_cleanup;
 503         master->set_cs = dw_spi_set_cs;
 504         master->transfer_one = dw_spi_transfer_one;
 505         master->handle_err = dw_spi_handle_err;
 506         master->max_speed_hz = dws->max_freq;
 507         master->dev.of_node = dev->of_node;
 508         master->flags = SPI_MASTER_GPIO_SS;
 509
 510         /* Basic HW init */
 511         spi_hw_init(dev, dws);
 512
 513         if (dws->dma_ops && dws->dma_ops->dma_init) {
 514                 ret = dws->dma_ops->dma_init(dws);
 515                 if (ret) {
 516                         dev_warn(dev, "DMA init failed\n");
 517                         dws->dma_inited = 0;
 518                 } else {
 519                         master->can_dma = dws->dma_ops->can_dma;
 520                 }
 521         }
 522
 523         spi_master_set_devdata(master, dws);
 524         ret = devm_spi_register_master(dev, master);
 525         if (ret) {
 526                 dev_err(&master->dev, "problem registering spi master\n");
 527                 goto err_dma_exit;
 528         }
 529
 530         dw_spi_debugfs_init(dws);
 531         return 0;
 532
 533 err_dma_exit:
 534         if (dws->dma_ops && dws->dma_ops->dma_exit)
 535                 dws->dma_ops->dma_exit(dws);
 536         spi_enable_chip(dws, 0);
 537         free_irq(dws->irq, master);
 538 err_free_master:
 539         spi_master_put(master);
 540         return ret;
 541 }
 542 EXPORT_SYMBOL_GPL(dw_spi_add_host);
 543
 544 void dw_spi_remove_host(struct dw_spi *dws)
 545 {
 546         dw_spi_debugfs_remove(dws);
 547
 548         if (dws->dma_ops && dws->dma_ops->dma_exit)
 549                 dws->dma_ops->dma_exit(dws);
 550
 551         spi_shutdown_chip(dws);
 552
 553         free_irq(dws->irq, dws->master);
 554 }
 555 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
 556
 557 int dw_spi_suspend_host(struct dw_spi *dws)
 558 {
 559         int ret;
 560
 561         ret = spi_master_suspend(dws->master);
 562         if (ret)
 563                 return ret;
 564
 565         spi_shutdown_chip(dws);
 566         return 0;
 567 }
 568 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
 569
 570 int dw_spi_resume_host(struct dw_spi *dws)
 571 {
 572         int ret;
 573
 574         spi_hw_init(&dws->master->dev, dws);
 575         ret = spi_master_resume(dws->master);
 576         if (ret)
 577                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
 578         return ret;
 579 }
 580 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
 581
 582 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
 583 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
 584 MODULE_LICENSE("GPL v2");