2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
21 #include <linux/clk.h>
22 #include <linux/completion.h>
23 #include <linux/delay.h>
24 #include <linux/dmaengine.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/interrupt.h>
30 #include <linux/irq.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/platform_device.h>
34 #include <linux/slab.h>
35 #include <linux/spi/spi.h>
36 #include <linux/spi/spi_bitbang.h>
37 #include <linux/types.h>
39 #include <linux/of_device.h>
40 #include <linux/of_gpio.h>
42 #include <linux/platform_data/dma-imx.h>
43 #include <linux/platform_data/spi-imx.h>
45 #define DRIVER_NAME "spi_imx"
47 #define MXC_CSPIRXDATA 0x00
48 #define MXC_CSPITXDATA 0x04
49 #define MXC_CSPICTRL 0x08
50 #define MXC_CSPIINT 0x0c
51 #define MXC_RESET 0x1c
53 /* generic defines to abstract from the different register layouts */
54 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
55 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
57 /* The maximum bytes that a sdma BD can transfer.*/
58 #define MAX_SDMA_BD_BYTES (1 << 15)
59 struct spi_imx_config {
60 unsigned int speed_hz;
66 enum spi_imx_devtype {
71 IMX35_CSPI, /* CSPI on all i.mx except above */
72 IMX51_ECSPI, /* ECSPI on i.mx51 and later */
77 struct spi_imx_devtype_data {
78 void (*intctrl)(struct spi_imx_data *, int);
79 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
80 void (*trigger)(struct spi_imx_data *);
81 int (*rx_available)(struct spi_imx_data *);
82 void (*reset)(struct spi_imx_data *);
83 enum spi_imx_devtype devtype;
87 struct spi_bitbang bitbang;
90 struct completion xfer_done;
94 unsigned long spi_clk;
95 unsigned int spi_bus_clk;
98 void (*tx)(struct spi_imx_data *);
99 void (*rx)(struct spi_imx_data *);
102 unsigned int txfifo; /* number of words pushed in tx FIFO */
105 unsigned int dma_is_inited;
106 unsigned int dma_finished;
109 struct completion dma_rx_completion;
110 struct completion dma_tx_completion;
112 const struct spi_imx_devtype_data *devtype_data;
116 static inline int is_imx27_cspi(struct spi_imx_data *d)
118 return d->devtype_data->devtype == IMX27_CSPI;
121 static inline int is_imx35_cspi(struct spi_imx_data *d)
123 return d->devtype_data->devtype == IMX35_CSPI;
126 static inline int is_imx51_ecspi(struct spi_imx_data *d)
128 return d->devtype_data->devtype == IMX51_ECSPI;
131 static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
133 return is_imx51_ecspi(d) ? 64 : 8;
136 #define MXC_SPI_BUF_RX(type) \
137 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
139 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
141 if (spi_imx->rx_buf) { \
142 *(type *)spi_imx->rx_buf = val; \
143 spi_imx->rx_buf += sizeof(type); \
147 #define MXC_SPI_BUF_TX(type) \
148 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
152 if (spi_imx->tx_buf) { \
153 val = *(type *)spi_imx->tx_buf; \
154 spi_imx->tx_buf += sizeof(type); \
157 spi_imx->count -= sizeof(type); \
159 writel(val, spi_imx->base + MXC_CSPITXDATA); \
169 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
170 * (which is currently not the case in this driver)
172 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
173 256, 384, 512, 768, 1024};
176 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
177 unsigned int fspi, unsigned int max)
181 for (i = 2; i < max; i++)
182 if (fspi * mxc_clkdivs[i] >= fin)
188 /* MX1, MX31, MX35, MX51 CSPI */
189 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
194 for (i = 0; i < 7; i++) {
195 if (fspi * div >= fin)
203 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
204 struct spi_transfer *transfer)
206 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
208 if (spi_imx->dma_is_inited && transfer->len >= spi_imx->wml &&
209 (transfer->len % spi_imx->wml) == 0)
214 #define MX51_ECSPI_CTRL 0x08
215 #define MX51_ECSPI_CTRL_ENABLE (1 << 0)
216 #define MX51_ECSPI_CTRL_XCH (1 << 2)
217 #define MX51_ECSPI_CTRL_SMC (1 << 3)
218 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
219 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
220 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
221 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
222 #define MX51_ECSPI_CTRL_BL_OFFSET 20
224 #define MX51_ECSPI_CONFIG 0x0c
225 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
226 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
227 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
228 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
229 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
231 #define MX51_ECSPI_INT 0x10
232 #define MX51_ECSPI_INT_TEEN (1 << 0)
233 #define MX51_ECSPI_INT_RREN (1 << 3)
235 #define MX51_ECSPI_DMA 0x14
236 #define MX51_ECSPI_DMA_TX_WML_OFFSET 0
237 #define MX51_ECSPI_DMA_TX_WML_MASK 0x3F
238 #define MX51_ECSPI_DMA_RX_WML_OFFSET 16
239 #define MX51_ECSPI_DMA_RX_WML_MASK (0x3F << 16)
240 #define MX51_ECSPI_DMA_RXT_WML_OFFSET 24
241 #define MX51_ECSPI_DMA_RXT_WML_MASK (0x3F << 24)
243 #define MX51_ECSPI_DMA_TEDEN_OFFSET 7
244 #define MX51_ECSPI_DMA_RXDEN_OFFSET 23
245 #define MX51_ECSPI_DMA_RXTDEN_OFFSET 31
247 #define MX51_ECSPI_STAT 0x18
248 #define MX51_ECSPI_STAT_RR (1 << 3)
250 #define MX51_ECSPI_TESTREG 0x20
251 #define MX51_ECSPI_TESTREG_LBC BIT(31)
254 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
255 unsigned int fspi, unsigned int *fres)
258 * there are two 4-bit dividers, the pre-divider divides by
259 * $pre, the post-divider by 2^$post
261 unsigned int pre, post;
262 unsigned int fin = spi_imx->spi_clk;
264 if (unlikely(fspi > fin))
267 post = fls(fin) - fls(fspi);
268 if (fin > fspi << post)
271 /* now we have: (fin <= fspi << post) with post being minimal */
273 post = max(4U, post) - 4;
274 if (unlikely(post > 0xf)) {
275 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
280 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
282 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
283 __func__, fin, fspi, post, pre);
285 /* Resulting frequency for the SCLK line. */
286 *fres = (fin / (pre + 1)) >> post;
288 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
289 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
292 static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
296 if (enable & MXC_INT_TE)
297 val |= MX51_ECSPI_INT_TEEN;
299 if (enable & MXC_INT_RR)
300 val |= MX51_ECSPI_INT_RREN;
302 writel(val, spi_imx->base + MX51_ECSPI_INT);
305 static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
307 u32 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
309 if (!spi_imx->usedma)
310 reg |= MX51_ECSPI_CTRL_XCH;
311 else if (!spi_imx->dma_finished)
312 reg |= MX51_ECSPI_CTRL_SMC;
314 reg &= ~MX51_ECSPI_CTRL_SMC;
315 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
318 static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
319 struct spi_imx_config *config)
321 u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0, dma = 0;
322 u32 tx_wml_cfg, rx_wml_cfg, rxt_wml_cfg;
323 u32 clk = config->speed_hz, delay, reg;
326 * The hardware seems to have a race condition when changing modes. The
327 * current assumption is that the selection of the channel arrives
328 * earlier in the hardware than the mode bits when they are written at
330 * So set master mode for all channels as we do not support slave mode.
332 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
334 /* set clock speed */
335 ctrl |= mx51_ecspi_clkdiv(spi_imx, config->speed_hz, &clk);
336 spi_imx->spi_bus_clk = clk;
338 /* set chip select to use */
339 ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
341 ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
343 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
345 if (config->mode & SPI_CPHA)
346 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
348 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
350 if (config->mode & SPI_CPOL) {
351 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
352 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
354 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
355 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
357 if (config->mode & SPI_CS_HIGH)
358 cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
360 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(config->cs);
362 /* CTRL register always go first to bring out controller from reset */
363 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
365 reg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
366 if (config->mode & SPI_LOOP)
367 reg |= MX51_ECSPI_TESTREG_LBC;
369 reg &= ~MX51_ECSPI_TESTREG_LBC;
370 writel(reg, spi_imx->base + MX51_ECSPI_TESTREG);
372 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
375 * Wait until the changes in the configuration register CONFIGREG
376 * propagate into the hardware. It takes exactly one tick of the
377 * SCLK clock, but we will wait two SCLK clock just to be sure. The
378 * effect of the delay it takes for the hardware to apply changes
379 * is noticable if the SCLK clock run very slow. In such a case, if
380 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
381 * be asserted before the SCLK polarity changes, which would disrupt
382 * the SPI communication as the device on the other end would consider
383 * the change of SCLK polarity as a clock tick already.
385 delay = (2 * 1000000) / clk;
386 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
388 else /* SCLK is _very_ slow */
389 usleep_range(delay, delay + 10);
392 * Configure the DMA register: setup the watermark
393 * and enable DMA request.
395 if (spi_imx->dma_is_inited) {
396 dma = readl(spi_imx->base + MX51_ECSPI_DMA);
398 rx_wml_cfg = spi_imx->wml << MX51_ECSPI_DMA_RX_WML_OFFSET;
399 tx_wml_cfg = spi_imx->wml << MX51_ECSPI_DMA_TX_WML_OFFSET;
400 rxt_wml_cfg = spi_imx->wml << MX51_ECSPI_DMA_RXT_WML_OFFSET;
401 dma = (dma & ~MX51_ECSPI_DMA_TX_WML_MASK
402 & ~MX51_ECSPI_DMA_RX_WML_MASK
403 & ~MX51_ECSPI_DMA_RXT_WML_MASK)
404 | rx_wml_cfg | tx_wml_cfg | rxt_wml_cfg
405 |(1 << MX51_ECSPI_DMA_TEDEN_OFFSET)
406 |(1 << MX51_ECSPI_DMA_RXDEN_OFFSET)
407 |(1 << MX51_ECSPI_DMA_RXTDEN_OFFSET);
409 writel(dma, spi_imx->base + MX51_ECSPI_DMA);
415 static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
417 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
420 static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
422 /* drain receive buffer */
423 while (mx51_ecspi_rx_available(spi_imx))
424 readl(spi_imx->base + MXC_CSPIRXDATA);
427 #define MX31_INTREG_TEEN (1 << 0)
428 #define MX31_INTREG_RREN (1 << 3)
430 #define MX31_CSPICTRL_ENABLE (1 << 0)
431 #define MX31_CSPICTRL_MASTER (1 << 1)
432 #define MX31_CSPICTRL_XCH (1 << 2)
433 #define MX31_CSPICTRL_POL (1 << 4)
434 #define MX31_CSPICTRL_PHA (1 << 5)
435 #define MX31_CSPICTRL_SSCTL (1 << 6)
436 #define MX31_CSPICTRL_SSPOL (1 << 7)
437 #define MX31_CSPICTRL_BC_SHIFT 8
438 #define MX35_CSPICTRL_BL_SHIFT 20
439 #define MX31_CSPICTRL_CS_SHIFT 24
440 #define MX35_CSPICTRL_CS_SHIFT 12
441 #define MX31_CSPICTRL_DR_SHIFT 16
443 #define MX31_CSPISTATUS 0x14
444 #define MX31_STATUS_RR (1 << 3)
446 /* These functions also work for the i.MX35, but be aware that
447 * the i.MX35 has a slightly different register layout for bits
448 * we do not use here.
450 static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
452 unsigned int val = 0;
454 if (enable & MXC_INT_TE)
455 val |= MX31_INTREG_TEEN;
456 if (enable & MXC_INT_RR)
457 val |= MX31_INTREG_RREN;
459 writel(val, spi_imx->base + MXC_CSPIINT);
462 static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
466 reg = readl(spi_imx->base + MXC_CSPICTRL);
467 reg |= MX31_CSPICTRL_XCH;
468 writel(reg, spi_imx->base + MXC_CSPICTRL);
471 static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
472 struct spi_imx_config *config)
474 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
475 int cs = spi_imx->chipselect[config->cs];
477 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
478 MX31_CSPICTRL_DR_SHIFT;
480 if (is_imx35_cspi(spi_imx)) {
481 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
482 reg |= MX31_CSPICTRL_SSCTL;
484 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
487 if (config->mode & SPI_CPHA)
488 reg |= MX31_CSPICTRL_PHA;
489 if (config->mode & SPI_CPOL)
490 reg |= MX31_CSPICTRL_POL;
491 if (config->mode & SPI_CS_HIGH)
492 reg |= MX31_CSPICTRL_SSPOL;
495 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
496 MX31_CSPICTRL_CS_SHIFT);
498 writel(reg, spi_imx->base + MXC_CSPICTRL);
503 static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
505 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
508 static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
510 /* drain receive buffer */
511 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
512 readl(spi_imx->base + MXC_CSPIRXDATA);
515 #define MX21_INTREG_RR (1 << 4)
516 #define MX21_INTREG_TEEN (1 << 9)
517 #define MX21_INTREG_RREN (1 << 13)
519 #define MX21_CSPICTRL_POL (1 << 5)
520 #define MX21_CSPICTRL_PHA (1 << 6)
521 #define MX21_CSPICTRL_SSPOL (1 << 8)
522 #define MX21_CSPICTRL_XCH (1 << 9)
523 #define MX21_CSPICTRL_ENABLE (1 << 10)
524 #define MX21_CSPICTRL_MASTER (1 << 11)
525 #define MX21_CSPICTRL_DR_SHIFT 14
526 #define MX21_CSPICTRL_CS_SHIFT 19
528 static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
530 unsigned int val = 0;
532 if (enable & MXC_INT_TE)
533 val |= MX21_INTREG_TEEN;
534 if (enable & MXC_INT_RR)
535 val |= MX21_INTREG_RREN;
537 writel(val, spi_imx->base + MXC_CSPIINT);
540 static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
544 reg = readl(spi_imx->base + MXC_CSPICTRL);
545 reg |= MX21_CSPICTRL_XCH;
546 writel(reg, spi_imx->base + MXC_CSPICTRL);
549 static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
550 struct spi_imx_config *config)
552 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
553 int cs = spi_imx->chipselect[config->cs];
554 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
556 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
557 MX21_CSPICTRL_DR_SHIFT;
558 reg |= config->bpw - 1;
560 if (config->mode & SPI_CPHA)
561 reg |= MX21_CSPICTRL_PHA;
562 if (config->mode & SPI_CPOL)
563 reg |= MX21_CSPICTRL_POL;
564 if (config->mode & SPI_CS_HIGH)
565 reg |= MX21_CSPICTRL_SSPOL;
567 reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
569 writel(reg, spi_imx->base + MXC_CSPICTRL);
574 static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
576 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
579 static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
581 writel(1, spi_imx->base + MXC_RESET);
584 #define MX1_INTREG_RR (1 << 3)
585 #define MX1_INTREG_TEEN (1 << 8)
586 #define MX1_INTREG_RREN (1 << 11)
588 #define MX1_CSPICTRL_POL (1 << 4)
589 #define MX1_CSPICTRL_PHA (1 << 5)
590 #define MX1_CSPICTRL_XCH (1 << 8)
591 #define MX1_CSPICTRL_ENABLE (1 << 9)
592 #define MX1_CSPICTRL_MASTER (1 << 10)
593 #define MX1_CSPICTRL_DR_SHIFT 13
595 static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
597 unsigned int val = 0;
599 if (enable & MXC_INT_TE)
600 val |= MX1_INTREG_TEEN;
601 if (enable & MXC_INT_RR)
602 val |= MX1_INTREG_RREN;
604 writel(val, spi_imx->base + MXC_CSPIINT);
607 static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
611 reg = readl(spi_imx->base + MXC_CSPICTRL);
612 reg |= MX1_CSPICTRL_XCH;
613 writel(reg, spi_imx->base + MXC_CSPICTRL);
616 static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
617 struct spi_imx_config *config)
619 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
621 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
622 MX1_CSPICTRL_DR_SHIFT;
623 reg |= config->bpw - 1;
625 if (config->mode & SPI_CPHA)
626 reg |= MX1_CSPICTRL_PHA;
627 if (config->mode & SPI_CPOL)
628 reg |= MX1_CSPICTRL_POL;
630 writel(reg, spi_imx->base + MXC_CSPICTRL);
635 static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
637 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
640 static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
642 writel(1, spi_imx->base + MXC_RESET);
645 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
646 .intctrl = mx1_intctrl,
647 .config = mx1_config,
648 .trigger = mx1_trigger,
649 .rx_available = mx1_rx_available,
651 .devtype = IMX1_CSPI,
654 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
655 .intctrl = mx21_intctrl,
656 .config = mx21_config,
657 .trigger = mx21_trigger,
658 .rx_available = mx21_rx_available,
660 .devtype = IMX21_CSPI,
663 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
664 /* i.mx27 cspi shares the functions with i.mx21 one */
665 .intctrl = mx21_intctrl,
666 .config = mx21_config,
667 .trigger = mx21_trigger,
668 .rx_available = mx21_rx_available,
670 .devtype = IMX27_CSPI,
673 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
674 .intctrl = mx31_intctrl,
675 .config = mx31_config,
676 .trigger = mx31_trigger,
677 .rx_available = mx31_rx_available,
679 .devtype = IMX31_CSPI,
682 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
683 /* i.mx35 and later cspi shares the functions with i.mx31 one */
684 .intctrl = mx31_intctrl,
685 .config = mx31_config,
686 .trigger = mx31_trigger,
687 .rx_available = mx31_rx_available,
689 .devtype = IMX35_CSPI,
692 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
693 .intctrl = mx51_ecspi_intctrl,
694 .config = mx51_ecspi_config,
695 .trigger = mx51_ecspi_trigger,
696 .rx_available = mx51_ecspi_rx_available,
697 .reset = mx51_ecspi_reset,
698 .devtype = IMX51_ECSPI,
701 static const struct platform_device_id spi_imx_devtype[] = {
704 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
706 .name = "imx21-cspi",
707 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
709 .name = "imx27-cspi",
710 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
712 .name = "imx31-cspi",
713 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
715 .name = "imx35-cspi",
716 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
718 .name = "imx51-ecspi",
719 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
725 static const struct of_device_id spi_imx_dt_ids[] = {
726 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
727 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
728 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
729 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
730 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
731 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
734 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
736 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
738 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
739 int gpio = spi_imx->chipselect[spi->chip_select];
740 int active = is_active != BITBANG_CS_INACTIVE;
741 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
743 if (!gpio_is_valid(gpio))
746 gpio_set_value(gpio, dev_is_lowactive ^ active);
749 static void spi_imx_push(struct spi_imx_data *spi_imx)
751 while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
754 spi_imx->tx(spi_imx);
758 spi_imx->devtype_data->trigger(spi_imx);
761 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
763 struct spi_imx_data *spi_imx = dev_id;
765 while (spi_imx->devtype_data->rx_available(spi_imx)) {
766 spi_imx->rx(spi_imx);
770 if (spi_imx->count) {
771 spi_imx_push(spi_imx);
775 if (spi_imx->txfifo) {
776 /* No data left to push, but still waiting for rx data,
777 * enable receive data available interrupt.
779 spi_imx->devtype_data->intctrl(
780 spi_imx, MXC_INT_RR);
784 spi_imx->devtype_data->intctrl(spi_imx, 0);
785 complete(&spi_imx->xfer_done);
790 static int spi_imx_setupxfer(struct spi_device *spi,
791 struct spi_transfer *t)
793 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
794 struct spi_imx_config config;
796 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
797 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
798 config.mode = spi->mode;
799 config.cs = spi->chip_select;
801 if (!config.speed_hz)
802 config.speed_hz = spi->max_speed_hz;
804 config.bpw = spi->bits_per_word;
806 /* Initialize the functions for transfer */
807 if (config.bpw <= 8) {
808 spi_imx->rx = spi_imx_buf_rx_u8;
809 spi_imx->tx = spi_imx_buf_tx_u8;
810 } else if (config.bpw <= 16) {
811 spi_imx->rx = spi_imx_buf_rx_u16;
812 spi_imx->tx = spi_imx_buf_tx_u16;
814 spi_imx->rx = spi_imx_buf_rx_u32;
815 spi_imx->tx = spi_imx_buf_tx_u32;
818 spi_imx->devtype_data->config(spi_imx, &config);
823 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
825 struct spi_master *master = spi_imx->bitbang.master;
827 if (master->dma_rx) {
828 dma_release_channel(master->dma_rx);
829 master->dma_rx = NULL;
832 if (master->dma_tx) {
833 dma_release_channel(master->dma_tx);
834 master->dma_tx = NULL;
837 spi_imx->dma_is_inited = 0;
840 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
841 struct spi_master *master,
842 const struct resource *res)
844 struct dma_slave_config slave_config = {};
847 /* use pio mode for i.mx6dl chip TKT238285 */
848 if (of_machine_is_compatible("fsl,imx6dl"))
851 spi_imx->wml = spi_imx_get_fifosize(spi_imx) / 2;
853 /* Prepare for TX DMA: */
854 master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
855 if (IS_ERR(master->dma_tx)) {
856 ret = PTR_ERR(master->dma_tx);
857 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
858 master->dma_tx = NULL;
862 slave_config.direction = DMA_MEM_TO_DEV;
863 slave_config.dst_addr = res->start + MXC_CSPITXDATA;
864 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
865 slave_config.dst_maxburst = spi_imx->wml;
866 ret = dmaengine_slave_config(master->dma_tx, &slave_config);
868 dev_err(dev, "error in TX dma configuration.\n");
872 /* Prepare for RX : */
873 master->dma_rx = dma_request_slave_channel_reason(dev, "rx");
874 if (IS_ERR(master->dma_rx)) {
875 ret = PTR_ERR(master->dma_rx);
876 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
877 master->dma_rx = NULL;
881 slave_config.direction = DMA_DEV_TO_MEM;
882 slave_config.src_addr = res->start + MXC_CSPIRXDATA;
883 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
884 slave_config.src_maxburst = spi_imx->wml;
885 ret = dmaengine_slave_config(master->dma_rx, &slave_config);
887 dev_err(dev, "error in RX dma configuration.\n");
891 init_completion(&spi_imx->dma_rx_completion);
892 init_completion(&spi_imx->dma_tx_completion);
893 master->can_dma = spi_imx_can_dma;
894 master->max_dma_len = MAX_SDMA_BD_BYTES;
895 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
897 spi_imx->dma_is_inited = 1;
901 spi_imx_sdma_exit(spi_imx);
905 static void spi_imx_dma_rx_callback(void *cookie)
907 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
909 complete(&spi_imx->dma_rx_completion);
912 static void spi_imx_dma_tx_callback(void *cookie)
914 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
916 complete(&spi_imx->dma_tx_completion);
919 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
921 unsigned long timeout = 0;
923 /* Time with actual data transfer and CS change delay related to HW */
924 timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
926 /* Add extra second for scheduler related activities */
929 /* Double calculated timeout */
930 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
933 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
934 struct spi_transfer *transfer)
936 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
938 unsigned long transfer_timeout;
939 unsigned long timeout;
940 struct spi_master *master = spi_imx->bitbang.master;
941 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
944 desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
945 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
946 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
950 desc_tx->callback = spi_imx_dma_tx_callback;
951 desc_tx->callback_param = (void *)spi_imx;
952 dmaengine_submit(desc_tx);
956 desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
957 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
958 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
962 desc_rx->callback = spi_imx_dma_rx_callback;
963 desc_rx->callback_param = (void *)spi_imx;
964 dmaengine_submit(desc_rx);
967 reinit_completion(&spi_imx->dma_rx_completion);
968 reinit_completion(&spi_imx->dma_tx_completion);
970 /* Trigger the cspi module. */
971 spi_imx->dma_finished = 0;
974 * Set these order to avoid potential RX overflow. The overflow may
975 * happen if we enable SPI HW before starting RX DMA due to rescheduling
976 * for another task and/or interrupt.
977 * So RX DMA enabled first to make sure data would be read out from FIFO
978 * ASAP. TX DMA enabled next to start filling TX FIFO with new data.
979 * And finaly SPI HW enabled to start actual data transfer.
981 dma_async_issue_pending(master->dma_rx);
982 dma_async_issue_pending(master->dma_tx);
983 spi_imx->devtype_data->trigger(spi_imx);
985 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
987 /* Wait SDMA to finish the data transfer.*/
988 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
991 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
992 dmaengine_terminate_all(master->dma_tx);
993 dmaengine_terminate_all(master->dma_rx);
995 timeout = wait_for_completion_timeout(
996 &spi_imx->dma_rx_completion, transfer_timeout);
998 dev_err(spi_imx->dev, "I/O Error in DMA RX\n");
999 spi_imx->devtype_data->reset(spi_imx);
1000 dmaengine_terminate_all(master->dma_rx);
1004 spi_imx->dma_finished = 1;
1005 spi_imx->devtype_data->trigger(spi_imx);
1010 ret = transfer->len;
1015 dmaengine_terminate_all(master->dma_tx);
1017 dev_warn_once(spi_imx->dev, "DMA not available, falling back to PIO\n");
1021 static int spi_imx_pio_transfer(struct spi_device *spi,
1022 struct spi_transfer *transfer)
1024 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1026 spi_imx->tx_buf = transfer->tx_buf;
1027 spi_imx->rx_buf = transfer->rx_buf;
1028 spi_imx->count = transfer->len;
1029 spi_imx->txfifo = 0;
1031 reinit_completion(&spi_imx->xfer_done);
1033 spi_imx_push(spi_imx);
1035 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1037 wait_for_completion(&spi_imx->xfer_done);
1039 return transfer->len;
1042 static int spi_imx_transfer(struct spi_device *spi,
1043 struct spi_transfer *transfer)
1046 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1048 if (spi_imx->bitbang.master->can_dma &&
1049 spi_imx_can_dma(spi_imx->bitbang.master, spi, transfer)) {
1050 spi_imx->usedma = true;
1051 ret = spi_imx_dma_transfer(spi_imx, transfer);
1055 spi_imx->usedma = false;
1057 return spi_imx_pio_transfer(spi, transfer);
1060 static int spi_imx_setup(struct spi_device *spi)
1062 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1063 int gpio = spi_imx->chipselect[spi->chip_select];
1065 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1066 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1068 if (gpio_is_valid(gpio))
1069 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
1071 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
1076 static void spi_imx_cleanup(struct spi_device *spi)
1081 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1083 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1086 ret = clk_enable(spi_imx->clk_per);
1090 ret = clk_enable(spi_imx->clk_ipg);
1092 clk_disable(spi_imx->clk_per);
1100 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1102 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1104 clk_disable(spi_imx->clk_ipg);
1105 clk_disable(spi_imx->clk_per);
1109 static int spi_imx_probe(struct platform_device *pdev)
1111 struct device_node *np = pdev->dev.of_node;
1112 const struct of_device_id *of_id =
1113 of_match_device(spi_imx_dt_ids, &pdev->dev);
1114 struct spi_imx_master *mxc_platform_info =
1115 dev_get_platdata(&pdev->dev);
1116 struct spi_master *master;
1117 struct spi_imx_data *spi_imx;
1118 struct resource *res;
1119 int i, ret, num_cs, irq;
1121 if (!np && !mxc_platform_info) {
1122 dev_err(&pdev->dev, "can't get the platform data\n");
1126 ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
1128 if (mxc_platform_info)
1129 num_cs = mxc_platform_info->num_chipselect;
1134 master = spi_alloc_master(&pdev->dev,
1135 sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
1139 platform_set_drvdata(pdev, master);
1141 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1142 master->bus_num = pdev->id;
1143 master->num_chipselect = num_cs;
1145 spi_imx = spi_master_get_devdata(master);
1146 spi_imx->bitbang.master = master;
1147 spi_imx->dev = &pdev->dev;
1149 spi_imx->devtype_data = of_id ? of_id->data :
1150 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1152 for (i = 0; i < master->num_chipselect; i++) {
1153 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
1154 if (!gpio_is_valid(cs_gpio) && mxc_platform_info)
1155 cs_gpio = mxc_platform_info->chipselect[i];
1157 spi_imx->chipselect[i] = cs_gpio;
1158 if (!gpio_is_valid(cs_gpio))
1161 ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i],
1164 dev_err(&pdev->dev, "can't get cs gpios\n");
1165 goto out_master_put;
1169 spi_imx->bitbang.chipselect = spi_imx_chipselect;
1170 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1171 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1172 spi_imx->bitbang.master->setup = spi_imx_setup;
1173 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1174 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1175 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1176 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1177 if (is_imx51_ecspi(spi_imx))
1178 spi_imx->bitbang.master->mode_bits |= SPI_LOOP;
1180 init_completion(&spi_imx->xfer_done);
1182 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1183 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1184 if (IS_ERR(spi_imx->base)) {
1185 ret = PTR_ERR(spi_imx->base);
1186 goto out_master_put;
1189 irq = platform_get_irq(pdev, 0);
1192 goto out_master_put;
1195 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1196 dev_name(&pdev->dev), spi_imx);
1198 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1199 goto out_master_put;
1202 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1203 if (IS_ERR(spi_imx->clk_ipg)) {
1204 ret = PTR_ERR(spi_imx->clk_ipg);
1205 goto out_master_put;
1208 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1209 if (IS_ERR(spi_imx->clk_per)) {
1210 ret = PTR_ERR(spi_imx->clk_per);
1211 goto out_master_put;
1214 ret = clk_prepare_enable(spi_imx->clk_per);
1216 goto out_master_put;
1218 ret = clk_prepare_enable(spi_imx->clk_ipg);
1222 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1224 * Only validated on i.mx6 now, can remove the constrain if validated on
1227 if (is_imx51_ecspi(spi_imx)) {
1228 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master, res);
1229 if (ret == -EPROBE_DEFER)
1233 dev_err(&pdev->dev, "dma setup error %d, use pio\n",
1237 spi_imx->devtype_data->reset(spi_imx);
1239 spi_imx->devtype_data->intctrl(spi_imx, 0);
1241 master->dev.of_node = pdev->dev.of_node;
1242 ret = spi_bitbang_start(&spi_imx->bitbang);
1244 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1248 dev_info(&pdev->dev, "probed\n");
1250 clk_disable(spi_imx->clk_ipg);
1251 clk_disable(spi_imx->clk_per);
1255 clk_disable_unprepare(spi_imx->clk_ipg);
1257 clk_disable_unprepare(spi_imx->clk_per);
1259 spi_master_put(master);
1264 static int spi_imx_remove(struct platform_device *pdev)
1266 struct spi_master *master = platform_get_drvdata(pdev);
1267 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1269 spi_bitbang_stop(&spi_imx->bitbang);
1271 writel(0, spi_imx->base + MXC_CSPICTRL);
1272 clk_unprepare(spi_imx->clk_ipg);
1273 clk_unprepare(spi_imx->clk_per);
1274 spi_imx_sdma_exit(spi_imx);
1275 spi_master_put(master);
1280 static struct platform_driver spi_imx_driver = {
1282 .name = DRIVER_NAME,
1283 .of_match_table = spi_imx_dt_ids,
1285 .id_table = spi_imx_devtype,
1286 .probe = spi_imx_probe,
1287 .remove = spi_imx_remove,
1289 module_platform_driver(spi_imx_driver);
1291 MODULE_DESCRIPTION("SPI Master Controller driver");
1292 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1293 MODULE_LICENSE("GPL");
1294 MODULE_ALIAS("platform:" DRIVER_NAME);