2 * Copyright (C) 2012-2017 ARM Limited or its affiliates.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 #ifndef _CC_CRYPTO_CTX_H_
19 #define _CC_CRYPTO_CTX_H_
22 #include <linux/types.h>
23 #define INT32_MAX 0x7FFFFFFFL
30 #define max(a, b) ((a) > (b) ? (a) : (b))
31 #define min(a, b) ((a) < (b) ? (a) : (b))
35 #ifndef CC_CTX_SIZE_LOG2
36 #if (CC_SUPPORT_SHA > 256)
37 #define CC_CTX_SIZE_LOG2 8
39 #define CC_CTX_SIZE_LOG2 7
42 #define CC_CTX_SIZE (1<<CC_CTX_SIZE_LOG2)
43 #define CC_DRV_CTX_SIZE_WORDS (CC_CTX_SIZE >> 2)
45 #define CC_DRV_DES_IV_SIZE 8
46 #define CC_DRV_DES_BLOCK_SIZE 8
48 #define CC_DRV_DES_ONE_KEY_SIZE 8
49 #define CC_DRV_DES_DOUBLE_KEY_SIZE 16
50 #define CC_DRV_DES_TRIPLE_KEY_SIZE 24
51 #define CC_DRV_DES_KEY_SIZE_MAX CC_DRV_DES_TRIPLE_KEY_SIZE
53 #define CC_AES_IV_SIZE 16
54 #define CC_AES_IV_SIZE_WORDS (CC_AES_IV_SIZE >> 2)
56 #define CC_AES_BLOCK_SIZE 16
57 #define CC_AES_BLOCK_SIZE_WORDS 4
59 #define CC_AES_128_BIT_KEY_SIZE 16
60 #define CC_AES_128_BIT_KEY_SIZE_WORDS (CC_AES_128_BIT_KEY_SIZE >> 2)
61 #define CC_AES_192_BIT_KEY_SIZE 24
62 #define CC_AES_192_BIT_KEY_SIZE_WORDS (CC_AES_192_BIT_KEY_SIZE >> 2)
63 #define CC_AES_256_BIT_KEY_SIZE 32
64 #define CC_AES_256_BIT_KEY_SIZE_WORDS (CC_AES_256_BIT_KEY_SIZE >> 2)
65 #define CC_AES_KEY_SIZE_MAX CC_AES_256_BIT_KEY_SIZE
66 #define CC_AES_KEY_SIZE_WORDS_MAX (CC_AES_KEY_SIZE_MAX >> 2)
68 #define CC_MD5_DIGEST_SIZE 16
69 #define CC_SHA1_DIGEST_SIZE 20
70 #define CC_SHA224_DIGEST_SIZE 28
71 #define CC_SHA256_DIGEST_SIZE 32
72 #define CC_SHA256_DIGEST_SIZE_IN_WORDS 8
73 #define CC_SHA384_DIGEST_SIZE 48
74 #define CC_SHA512_DIGEST_SIZE 64
76 #define CC_SHA1_BLOCK_SIZE 64
77 #define CC_SHA1_BLOCK_SIZE_IN_WORDS 16
78 #define CC_MD5_BLOCK_SIZE 64
79 #define CC_MD5_BLOCK_SIZE_IN_WORDS 16
80 #define CC_SHA224_BLOCK_SIZE 64
81 #define CC_SHA256_BLOCK_SIZE 64
82 #define CC_SHA256_BLOCK_SIZE_IN_WORDS 16
83 #define CC_SHA1_224_256_BLOCK_SIZE 64
84 #define CC_SHA384_BLOCK_SIZE 128
85 #define CC_SHA512_BLOCK_SIZE 128
87 #if (CC_SUPPORT_SHA > 256)
88 #define CC_DIGEST_SIZE_MAX CC_SHA512_DIGEST_SIZE
89 #define CC_HASH_BLOCK_SIZE_MAX CC_SHA512_BLOCK_SIZE /*1024b*/
90 #else /* Only up to SHA256 */
91 #define CC_DIGEST_SIZE_MAX CC_SHA256_DIGEST_SIZE
92 #define CC_HASH_BLOCK_SIZE_MAX CC_SHA256_BLOCK_SIZE /*512b*/
95 #define CC_HMAC_BLOCK_SIZE_MAX CC_HASH_BLOCK_SIZE_MAX
97 #define CC_MULTI2_SYSTEM_KEY_SIZE 32
98 #define CC_MULTI2_DATA_KEY_SIZE 8
99 #define CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE (CC_MULTI2_SYSTEM_KEY_SIZE + CC_MULTI2_DATA_KEY_SIZE)
100 #define CC_MULTI2_BLOCK_SIZE 8
101 #define CC_MULTI2_IV_SIZE 8
102 #define CC_MULTI2_MIN_NUM_ROUNDS 8
103 #define CC_MULTI2_MAX_NUM_ROUNDS 128
106 #define CC_DRV_ALG_MAX_BLOCK_SIZE CC_HASH_BLOCK_SIZE_MAX
109 enum drv_engine_type {
116 DRV_ENGINE_RESERVE32B = INT32_MAX,
119 enum drv_crypto_alg {
120 DRV_CRYPTO_ALG_NULL = -1,
121 DRV_CRYPTO_ALG_AES = 0,
122 DRV_CRYPTO_ALG_DES = 1,
123 DRV_CRYPTO_ALG_HASH = 2,
124 DRV_CRYPTO_ALG_C2 = 3,
125 DRV_CRYPTO_ALG_HMAC = 4,
126 DRV_CRYPTO_ALG_AEAD = 5,
127 DRV_CRYPTO_ALG_BYPASS = 6,
128 DRV_CRYPTO_ALG_NUM = 7,
129 DRV_CRYPTO_ALG_RESERVE32B = INT32_MAX
132 enum drv_crypto_direction {
133 DRV_CRYPTO_DIRECTION_NULL = -1,
134 DRV_CRYPTO_DIRECTION_ENCRYPT = 0,
135 DRV_CRYPTO_DIRECTION_DECRYPT = 1,
136 DRV_CRYPTO_DIRECTION_DECRYPT_ENCRYPT = 3,
137 DRV_CRYPTO_DIRECTION_RESERVE32B = INT32_MAX
140 enum drv_cipher_mode {
141 DRV_CIPHER_NULL_MODE = -1,
145 DRV_CIPHER_CBC_MAC = 3,
147 DRV_CIPHER_XCBC_MAC = 5,
151 DRV_CIPHER_CBC_CTS = 11,
152 DRV_CIPHER_GCTR = 12,
153 DRV_CIPHER_ESSIV = 13,
154 DRV_CIPHER_BITLOCKER = 14,
155 DRV_CIPHER_RESERVE32B = INT32_MAX
166 DRV_HASH_CBC_MAC = 6,
167 DRV_HASH_XCBC_MAC = 7,
169 DRV_HASH_MODE_NUM = 9,
170 DRV_HASH_RESERVE32B = INT32_MAX
173 enum drv_hash_hw_mode {
175 DRV_HASH_HW_SHA1 = 1,
176 DRV_HASH_HW_SHA256 = 2,
177 DRV_HASH_HW_SHA224 = 10,
178 DRV_HASH_HW_SHA512 = 4,
179 DRV_HASH_HW_SHA384 = 12,
180 DRV_HASH_HW_GHASH = 6,
181 DRV_HASH_HW_RESERVE32B = INT32_MAX
184 enum drv_multi2_mode {
185 DRV_MULTI2_NULL = -1,
189 DRV_MULTI2_RESERVE32B = INT32_MAX
193 /* drv_crypto_key_type[1:0] is mapped to cipher_do[1:0] */
194 /* drv_crypto_key_type[2] is mapped to cipher_config2 */
195 enum drv_crypto_key_type {
197 DRV_USER_KEY = 0, /* 0x000 */
198 DRV_ROOT_KEY = 1, /* 0x001 */
199 DRV_PROVISIONING_KEY = 2, /* 0x010 */
200 DRV_SESSION_KEY = 3, /* 0x011 */
201 DRV_APPLET_KEY = 4, /* NA */
202 DRV_PLATFORM_KEY = 5, /* 0x101 */
203 DRV_CUSTOMER_KEY = 6, /* 0x110 */
204 DRV_END_OF_KEYS = INT32_MAX,
207 enum drv_crypto_padding_type {
208 DRV_PADDING_NONE = 0,
209 DRV_PADDING_PKCS7 = 1,
210 DRV_PADDING_RESERVE32B = INT32_MAX
213 /*******************************************************************/
214 /***************** DESCRIPTOR BASED CONTEXTS ***********************/
215 /*******************************************************************/
217 /* Generic context ("super-class") */
218 struct drv_ctx_generic {
219 enum drv_crypto_alg alg;
220 } __attribute__((__may_alias__));
223 struct drv_ctx_hash {
224 enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_HASH */
225 enum drv_hash_mode mode;
226 uint8_t digest[CC_DIGEST_SIZE_MAX];
227 /* reserve to end of allocated context size */
228 uint8_t reserved[CC_CTX_SIZE - 2 * sizeof(uint32_t) -
232 /* !!!! drv_ctx_hmac should have the same structure as drv_ctx_hash except
233 k0, k0_size fields */
234 struct drv_ctx_hmac {
235 enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_HMAC */
236 enum drv_hash_mode mode;
237 uint8_t digest[CC_DIGEST_SIZE_MAX];
238 uint32_t k0[CC_HMAC_BLOCK_SIZE_MAX/sizeof(uint32_t)];
240 /* reserve to end of allocated context size */
241 uint8_t reserved[CC_CTX_SIZE - 3 * sizeof(uint32_t) -
242 CC_DIGEST_SIZE_MAX - CC_HMAC_BLOCK_SIZE_MAX];
245 struct drv_ctx_cipher {
246 enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_AES */
247 enum drv_cipher_mode mode;
248 enum drv_crypto_direction direction;
249 enum drv_crypto_key_type crypto_key_type;
250 enum drv_crypto_padding_type padding_type;
251 uint32_t key_size; /* numeric value in bytes */
252 uint32_t data_unit_size; /* required for XTS */
253 /* block_state is the AES engine block state.
254 * It is used by the host to pass IV or counter at initialization.
255 * It is used by SeP for intermediate block chaining state and for
256 * returning MAC algorithms results. */
257 uint8_t block_state[CC_AES_BLOCK_SIZE];
258 uint8_t key[CC_AES_KEY_SIZE_MAX];
259 uint8_t xex_key[CC_AES_KEY_SIZE_MAX];
260 /* reserve to end of allocated context size */
261 uint32_t reserved[CC_DRV_CTX_SIZE_WORDS - 7 -
262 CC_AES_BLOCK_SIZE/sizeof(uint32_t) - 2 *
263 (CC_AES_KEY_SIZE_MAX/sizeof(uint32_t))];
266 /* authentication and encryption with associated data class */
267 struct drv_ctx_aead {
268 enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_AES */
269 enum drv_cipher_mode mode;
270 enum drv_crypto_direction direction;
271 uint32_t key_size; /* numeric value in bytes */
272 uint32_t nonce_size; /* nonce size (octets) */
273 uint32_t header_size; /* finit additional data size (octets) */
274 uint32_t text_size; /* finit text data size (octets) */
275 uint32_t tag_size; /* mac size, element of {4, 6, 8, 10, 12, 14, 16} */
276 /* block_state1/2 is the AES engine block state */
277 uint8_t block_state[CC_AES_BLOCK_SIZE];
278 uint8_t mac_state[CC_AES_BLOCK_SIZE]; /* MAC result */
279 uint8_t nonce[CC_AES_BLOCK_SIZE]; /* nonce buffer */
280 uint8_t key[CC_AES_KEY_SIZE_MAX];
281 /* reserve to end of allocated context size */
282 uint32_t reserved[CC_DRV_CTX_SIZE_WORDS - 8 -
283 3 * (CC_AES_BLOCK_SIZE/sizeof(uint32_t)) -
284 CC_AES_KEY_SIZE_MAX/sizeof(uint32_t)];
287 /*******************************************************************/
288 /***************** MESSAGE BASED CONTEXTS **************************/
289 /*******************************************************************/
292 /* Get the address of a @member within a given @ctx address
293 @ctx: The context address
294 @type: Type of context structure
295 @member: Associated context field */
296 #define GET_CTX_FIELD_ADDR(ctx, type, member) (ctx + offsetof(type, member))
298 #endif /* _CC_CRYPTO_CTX_H_ */