drivers/staging/comedi/drivers/ni_tio.c

   1 /*
   2  * Support for NI general purpose counters
   3  *
   4  * Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 /*
  18  * Module: ni_tio
  19  * Description: National Instruments general purpose counters
  20  * Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
  21  *         Herman.Bruyninckx@mech.kuleuven.ac.be,
  22  *         Wim.Meeussen@mech.kuleuven.ac.be,
  23  *         Klaas.Gadeyne@mech.kuleuven.ac.be,
  24  *         Frank Mori Hess <fmhess@users.sourceforge.net>
  25  * Updated: Thu Nov 16 09:50:32 EST 2006
  26  * Status: works
  27  *
  28  * This module is not used directly by end-users.  Rather, it
  29  * is used by other drivers (for example ni_660x and ni_pcimio)
  30  * to provide support for NI's general purpose counters.  It was
  31  * originally based on the counter code from ni_660x.c and
  32  * ni_mio_common.c.
  33  *
  34  * References:
  35  * DAQ 660x Register-Level Programmer Manual  (NI 370505A-01)
  36  * DAQ 6601/6602 User Manual (NI 322137B-01)
  37  * 340934b.pdf  DAQ-STC reference manual
  38  *
  39  * TODO: Support use of both banks X and Y
  40  */
  41
  42 #include <linux/module.h>
  43 #include <linux/slab.h>
  44
  45 #include "ni_tio_internal.h"
  46
  47 /*
  48  * clock sources for ni e and m series boards,
  49  * get bits with GI_SRC_SEL()
  50  */
  51 #define NI_M_TIMEBASE_1_CLK             0x0     /* 20MHz */
  52 #define NI_M_PFI_CLK(x)                 (((x) < 10) ? (1 + (x)) : (0xb + (x)))
  53 #define NI_M_RTSI_CLK(x)                (((x) == 7) ? 0x1b : (0xb + (x)))
  54 #define NI_M_TIMEBASE_2_CLK             0x12    /* 100KHz */
  55 #define NI_M_NEXT_TC_CLK                0x13
  56 #define NI_M_NEXT_GATE_CLK              0x14    /* Gi_Src_SubSelect=0 */
  57 #define NI_M_PXI_STAR_TRIGGER_CLK       0x14    /* Gi_Src_SubSelect=1 */
  58 #define NI_M_PXI10_CLK                  0x1d
  59 #define NI_M_TIMEBASE_3_CLK             0x1e    /* 80MHz, Gi_Src_SubSelect=0 */
  60 #define NI_M_ANALOG_TRIGGER_OUT_CLK     0x1e    /* Gi_Src_SubSelect=1 */
  61 #define NI_M_LOGIC_LOW_CLK              0x1f
  62 #define NI_M_MAX_PFI_CHAN               15
  63 #define NI_M_MAX_RTSI_CHAN              7
  64
  65 /*
  66  * clock sources for ni_660x boards,
  67  * get bits with GI_SRC_SEL()
  68  */
  69 #define NI_660X_TIMEBASE_1_CLK          0x0     /* 20MHz */
  70 #define NI_660X_SRC_PIN_I_CLK           0x1
  71 #define NI_660X_SRC_PIN_CLK(x)          (0x2 + (x))
  72 #define NI_660X_NEXT_GATE_CLK           0xa
  73 #define NI_660X_RTSI_CLK(x)             (0xb + (x))
  74 #define NI_660X_TIMEBASE_2_CLK          0x12    /* 100KHz */
  75 #define NI_660X_NEXT_TC_CLK             0x13
  76 #define NI_660X_TIMEBASE_3_CLK          0x1e    /* 80MHz */
  77 #define NI_660X_LOGIC_LOW_CLK           0x1f
  78 #define NI_660X_MAX_SRC_PIN             7
  79 #define NI_660X_MAX_RTSI_CHAN           6
  80
  81 /* ni m series gate_select */
  82 #define NI_M_TIMESTAMP_MUX_GATE_SEL     0x0
  83 #define NI_M_PFI_GATE_SEL(x)            (((x) < 10) ? (1 + (x)) : (0xb + (x)))
  84 #define NI_M_RTSI_GATE_SEL(x)           (((x) == 7) ? 0x1b : (0xb + (x)))
  85 #define NI_M_AI_START2_GATE_SEL         0x12
  86 #define NI_M_PXI_STAR_TRIGGER_GATE_SEL  0x13
  87 #define NI_M_NEXT_OUT_GATE_SEL          0x14
  88 #define NI_M_AI_START1_GATE_SEL         0x1c
  89 #define NI_M_NEXT_SRC_GATE_SEL          0x1d
  90 #define NI_M_ANALOG_TRIG_OUT_GATE_SEL   0x1e
  91 #define NI_M_LOGIC_LOW_GATE_SEL         0x1f
  92
  93 /* ni_660x gate select */
  94 #define NI_660X_SRC_PIN_I_GATE_SEL      0x0
  95 #define NI_660X_GATE_PIN_I_GATE_SEL     0x1
  96 #define NI_660X_PIN_GATE_SEL(x)         (0x2 + (x))
  97 #define NI_660X_NEXT_SRC_GATE_SEL       0xa
  98 #define NI_660X_RTSI_GATE_SEL(x)        (0xb + (x))
  99 #define NI_660X_NEXT_OUT_GATE_SEL       0x14
 100 #define NI_660X_LOGIC_LOW_GATE_SEL      0x1f
 101 #define NI_660X_MAX_GATE_PIN            7
 102
 103 /* ni_660x second gate select */
 104 #define NI_660X_SRC_PIN_I_GATE2_SEL     0x0
 105 #define NI_660X_UD_PIN_I_GATE2_SEL      0x1
 106 #define NI_660X_UD_PIN_GATE2_SEL(x)     (0x2 + (x))
 107 #define NI_660X_NEXT_SRC_GATE2_SEL      0xa
 108 #define NI_660X_RTSI_GATE2_SEL(x)       (0xb + (x))
 109 #define NI_660X_NEXT_OUT_GATE2_SEL      0x14
 110 #define NI_660X_SELECTED_GATE2_SEL      0x1e
 111 #define NI_660X_LOGIC_LOW_GATE2_SEL     0x1f
 112 #define NI_660X_MAX_UP_DOWN_PIN         7
 113
 114 static inline unsigned int GI_PRESCALE_X2(enum ni_gpct_variant variant)
 115 {
 116         switch (variant) {
 117         case ni_gpct_variant_e_series:
 118         default:
 119                 return 0;
 120         case ni_gpct_variant_m_series:
 121                 return GI_M_PRESCALE_X2;
 122         case ni_gpct_variant_660x:
 123                 return GI_660X_PRESCALE_X2;
 124         }
 125 }
 126
 127 static inline unsigned int GI_PRESCALE_X8(enum ni_gpct_variant variant)
 128 {
 129         switch (variant) {
 130         case ni_gpct_variant_e_series:
 131         default:
 132                 return 0;
 133         case ni_gpct_variant_m_series:
 134                 return GI_M_PRESCALE_X8;
 135         case ni_gpct_variant_660x:
 136                 return GI_660X_PRESCALE_X8;
 137         }
 138 }
 139
 140 static bool ni_tio_has_gate2_registers(const struct ni_gpct_device *counter_dev)
 141 {
 142         switch (counter_dev->variant) {
 143         case ni_gpct_variant_e_series:
 144         default:
 145                 return false;
 146         case ni_gpct_variant_m_series:
 147         case ni_gpct_variant_660x:
 148                 return true;
 149         }
 150 }
 151
 152 /**
 153  * ni_tio_write() - Write a TIO register using the driver provided callback.
 154  * @counter: struct ni_gpct counter.
 155  * @value: the value to write
 156  * @reg: the register to write.
 157  */
 158 void ni_tio_write(struct ni_gpct *counter, unsigned int value,
 159                   enum ni_gpct_register reg)
 160 {
 161         if (reg < NITIO_NUM_REGS)
 162                 counter->counter_dev->write(counter, value, reg);
 163 }
 164 EXPORT_SYMBOL_GPL(ni_tio_write);
 165
 166 /**
 167  * ni_tio_read() - Read a TIO register using the driver provided callback.
 168  * @counter: struct ni_gpct counter.
 169  * @reg: the register to read.
 170  */
 171 unsigned int ni_tio_read(struct ni_gpct *counter, enum ni_gpct_register reg)
 172 {
 173         if (reg < NITIO_NUM_REGS)
 174                 return counter->counter_dev->read(counter, reg);
 175         return 0;
 176 }
 177 EXPORT_SYMBOL_GPL(ni_tio_read);
 178
 179 static void ni_tio_reset_count_and_disarm(struct ni_gpct *counter)
 180 {
 181         unsigned int cidx = counter->counter_index;
 182
 183         ni_tio_write(counter, GI_RESET(cidx), NITIO_RESET_REG(cidx));
 184 }
 185
 186 static int ni_tio_clock_period_ps(const struct ni_gpct *counter,
 187                                   unsigned int generic_clock_source,
 188                                   u64 *period_ps)
 189 {
 190         u64 clock_period_ps;
 191
 192         switch (generic_clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
 193         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 194                 clock_period_ps = 50000;
 195                 break;
 196         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 197                 clock_period_ps = 10000000;
 198                 break;
 199         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 200                 clock_period_ps = 12500;
 201                 break;
 202         case NI_GPCT_PXI10_CLOCK_SRC_BITS:
 203                 clock_period_ps = 100000;
 204                 break;
 205         default:
 206                 /*
 207                  * clock period is specified by user with prescaling
 208                  * already taken into account.
 209                  */
 210                 return counter->clock_period_ps;
 211         }
 212
 213         switch (generic_clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
 214         case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
 215                 break;
 216         case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
 217                 clock_period_ps *= 2;
 218                 break;
 219         case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
 220                 clock_period_ps *= 8;
 221                 break;
 222         default:
 223                 return -EINVAL;
 224         }
 225         *period_ps = clock_period_ps;
 226         return 0;
 227 }
 228
 229 static void ni_tio_set_bits_transient(struct ni_gpct *counter,
 230                                       enum ni_gpct_register reg,
 231                                       unsigned int mask, unsigned int value,
 232                                       unsigned int transient)
 233 {
 234         struct ni_gpct_device *counter_dev = counter->counter_dev;
 235         unsigned long flags;
 236
 237         if (reg < NITIO_NUM_REGS) {
 238                 spin_lock_irqsave(&counter_dev->regs_lock, flags);
 239                 counter_dev->regs[reg] &= ~mask;
 240                 counter_dev->regs[reg] |= (value & mask);
 241                 ni_tio_write(counter, counter_dev->regs[reg] | transient, reg);
 242                 mmiowb();
 243                 spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
 244         }
 245 }
 246
 247 /**
 248  * ni_tio_set_bits() - Safely write a counter register.
 249  * @counter: struct ni_gpct counter.
 250  * @reg: the register to write.
 251  * @mask: the bits to change.
 252  * @value: the new bits value.
 253  *
 254  * Used to write to, and update the software copy, a register whose bits may
 255  * be twiddled in interrupt context, or whose software copy may be read in
 256  * interrupt context.
 257  */
 258 void ni_tio_set_bits(struct ni_gpct *counter, enum ni_gpct_register reg,
 259                      unsigned int mask, unsigned int value)
 260 {
 261         ni_tio_set_bits_transient(counter, reg, mask, value, 0x0);
 262 }
 263 EXPORT_SYMBOL_GPL(ni_tio_set_bits);
 264
 265 /**
 266  * ni_tio_get_soft_copy() - Safely read the software copy of a counter register.
 267  * @counter: struct ni_gpct counter.
 268  * @reg: the register to read.
 269  *
 270  * Used to get the software copy of a register whose bits might be modified
 271  * in interrupt context, or whose software copy might need to be read in
 272  * interrupt context.
 273  */
 274 unsigned int ni_tio_get_soft_copy(const struct ni_gpct *counter,
 275                                   enum ni_gpct_register reg)
 276 {
 277         struct ni_gpct_device *counter_dev = counter->counter_dev;
 278         unsigned int value = 0;
 279         unsigned long flags;
 280
 281         if (reg < NITIO_NUM_REGS) {
 282                 spin_lock_irqsave(&counter_dev->regs_lock, flags);
 283                 value = counter_dev->regs[reg];
 284                 spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
 285         }
 286         return value;
 287 }
 288 EXPORT_SYMBOL_GPL(ni_tio_get_soft_copy);
 289
 290 static unsigned int ni_tio_clock_src_modifiers(const struct ni_gpct *counter)
 291 {
 292         struct ni_gpct_device *counter_dev = counter->counter_dev;
 293         unsigned int cidx = counter->counter_index;
 294         unsigned int counting_mode_bits =
 295                 ni_tio_get_soft_copy(counter, NITIO_CNT_MODE_REG(cidx));
 296         unsigned int bits = 0;
 297
 298         if (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
 299             GI_SRC_POL_INVERT)
 300                 bits |= NI_GPCT_INVERT_CLOCK_SRC_BIT;
 301         if (counting_mode_bits & GI_PRESCALE_X2(counter_dev->variant))
 302                 bits |= NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS;
 303         if (counting_mode_bits & GI_PRESCALE_X8(counter_dev->variant))
 304                 bits |= NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS;
 305         return bits;
 306 }
 307
 308 static int ni_m_series_clock_src_select(const struct ni_gpct *counter,
 309                                         unsigned int *clk_src)
 310 {
 311         struct ni_gpct_device *counter_dev = counter->counter_dev;
 312         unsigned int cidx = counter->counter_index;
 313         unsigned int second_gate_reg = NITIO_GATE2_REG(cidx);
 314         unsigned int clock_source = 0;
 315         unsigned int src;
 316         unsigned int i;
 317
 318         src = GI_BITS_TO_SRC(ni_tio_get_soft_copy(counter,
 319                                                   NITIO_INPUT_SEL_REG(cidx)));
 320
 321         switch (src) {
 322         case NI_M_TIMEBASE_1_CLK:
 323                 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
 324                 break;
 325         case NI_M_TIMEBASE_2_CLK:
 326                 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
 327                 break;
 328         case NI_M_TIMEBASE_3_CLK:
 329                 if (counter_dev->regs[second_gate_reg] & GI_SRC_SUBSEL)
 330                         clock_source =
 331                             NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS;
 332                 else
 333                         clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
 334                 break;
 335         case NI_M_LOGIC_LOW_CLK:
 336                 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
 337                 break;
 338         case NI_M_NEXT_GATE_CLK:
 339                 if (counter_dev->regs[second_gate_reg] & GI_SRC_SUBSEL)
 340                         clock_source = NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS;
 341                 else
 342                         clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
 343                 break;
 344         case NI_M_PXI10_CLK:
 345                 clock_source = NI_GPCT_PXI10_CLOCK_SRC_BITS;
 346                 break;
 347         case NI_M_NEXT_TC_CLK:
 348                 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
 349                 break;
 350         default:
 351                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
 352                         if (src == NI_M_RTSI_CLK(i)) {
 353                                 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
 354                                 break;
 355                         }
 356                 }
 357                 if (i <= NI_M_MAX_RTSI_CHAN)
 358                         break;
 359                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
 360                         if (src == NI_M_PFI_CLK(i)) {
 361                                 clock_source = NI_GPCT_PFI_CLOCK_SRC_BITS(i);
 362                                 break;
 363                         }
 364                 }
 365                 if (i <= NI_M_MAX_PFI_CHAN)
 366                         break;
 367                 return -EINVAL;
 368         }
 369         clock_source |= ni_tio_clock_src_modifiers(counter);
 370         *clk_src = clock_source;
 371         return 0;
 372 }
 373
 374 static int ni_660x_clock_src_select(const struct ni_gpct *counter,
 375                                     unsigned int *clk_src)
 376 {
 377         unsigned int clock_source = 0;
 378         unsigned int cidx = counter->counter_index;
 379         unsigned int src;
 380         unsigned int i;
 381
 382         src = GI_BITS_TO_SRC(ni_tio_get_soft_copy(counter,
 383                                                   NITIO_INPUT_SEL_REG(cidx)));
 384
 385         switch (src) {
 386         case NI_660X_TIMEBASE_1_CLK:
 387                 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
 388                 break;
 389         case NI_660X_TIMEBASE_2_CLK:
 390                 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
 391                 break;
 392         case NI_660X_TIMEBASE_3_CLK:
 393                 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
 394                 break;
 395         case NI_660X_LOGIC_LOW_CLK:
 396                 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
 397                 break;
 398         case NI_660X_SRC_PIN_I_CLK:
 399                 clock_source = NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS;
 400                 break;
 401         case NI_660X_NEXT_GATE_CLK:
 402                 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
 403                 break;
 404         case NI_660X_NEXT_TC_CLK:
 405                 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
 406                 break;
 407         default:
 408                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 409                         if (src == NI_660X_RTSI_CLK(i)) {
 410                                 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
 411                                 break;
 412                         }
 413                 }
 414                 if (i <= NI_660X_MAX_RTSI_CHAN)
 415                         break;
 416                 for (i = 0; i <= NI_660X_MAX_SRC_PIN; ++i) {
 417                         if (src == NI_660X_SRC_PIN_CLK(i)) {
 418                                 clock_source =
 419                                     NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i);
 420                                 break;
 421                         }
 422                 }
 423                 if (i <= NI_660X_MAX_SRC_PIN)
 424                         break;
 425                 return -EINVAL;
 426         }
 427         clock_source |= ni_tio_clock_src_modifiers(counter);
 428         *clk_src = clock_source;
 429         return 0;
 430 }
 431
 432 static int ni_tio_generic_clock_src_select(const struct ni_gpct *counter,
 433                                            unsigned int *clk_src)
 434 {
 435         switch (counter->counter_dev->variant) {
 436         case ni_gpct_variant_e_series:
 437         case ni_gpct_variant_m_series:
 438         default:
 439                 return ni_m_series_clock_src_select(counter, clk_src);
 440         case ni_gpct_variant_660x:
 441                 return ni_660x_clock_src_select(counter, clk_src);
 442         }
 443 }
 444
 445 static void ni_tio_set_sync_mode(struct ni_gpct *counter)
 446 {
 447         struct ni_gpct_device *counter_dev = counter->counter_dev;
 448         unsigned int cidx = counter->counter_index;
 449         static const u64 min_normal_sync_period_ps = 25000;
 450         unsigned int mask = 0;
 451         unsigned int bits = 0;
 452         unsigned int reg;
 453         unsigned int mode;
 454         unsigned int clk_src;
 455         u64 ps;
 456         bool force_alt_sync;
 457
 458         /* only m series and 660x variants have counting mode registers */
 459         switch (counter_dev->variant) {
 460         case ni_gpct_variant_e_series:
 461         default:
 462                 return;
 463         case ni_gpct_variant_m_series:
 464                 mask = GI_M_ALT_SYNC;
 465                 break;
 466         case ni_gpct_variant_660x:
 467                 mask = GI_660X_ALT_SYNC;
 468                 break;
 469         }
 470
 471         reg = NITIO_CNT_MODE_REG(cidx);
 472         mode = ni_tio_get_soft_copy(counter, reg);
 473         switch (mode & GI_CNT_MODE_MASK) {
 474         case GI_CNT_MODE_QUADX1:
 475         case GI_CNT_MODE_QUADX2:
 476         case GI_CNT_MODE_QUADX4:
 477         case GI_CNT_MODE_SYNC_SRC:
 478                 force_alt_sync = true;
 479                 break;
 480         default:
 481                 force_alt_sync = false;
 482                 break;
 483         }
 484
 485         ni_tio_generic_clock_src_select(counter, &clk_src);
 486         ni_tio_clock_period_ps(counter, clk_src, &ps);
 487
 488         /*
 489          * It's not clear what we should do if clock_period is unknown, so we
 490          * are not using the alt sync bit in that case.
 491          */
 492         if (force_alt_sync || (ps && ps < min_normal_sync_period_ps))
 493                 bits = mask;
 494
 495         ni_tio_set_bits(counter, reg, mask, bits);
 496 }
 497
 498 static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned int mode)
 499 {
 500         struct ni_gpct_device *counter_dev = counter->counter_dev;
 501         unsigned int cidx = counter->counter_index;
 502         unsigned int mode_reg_mask;
 503         unsigned int mode_reg_values;
 504         unsigned int input_select_bits = 0;
 505         /* these bits map directly on to the mode register */
 506         static const unsigned int mode_reg_direct_mask =
 507             NI_GPCT_GATE_ON_BOTH_EDGES_BIT | NI_GPCT_EDGE_GATE_MODE_MASK |
 508             NI_GPCT_STOP_MODE_MASK | NI_GPCT_OUTPUT_MODE_MASK |
 509             NI_GPCT_HARDWARE_DISARM_MASK | NI_GPCT_LOADING_ON_TC_BIT |
 510             NI_GPCT_LOADING_ON_GATE_BIT | NI_GPCT_LOAD_B_SELECT_BIT;
 511
 512         mode_reg_mask = mode_reg_direct_mask | GI_RELOAD_SRC_SWITCHING;
 513         mode_reg_values = mode & mode_reg_direct_mask;
 514         switch (mode & NI_GPCT_RELOAD_SOURCE_MASK) {
 515         case NI_GPCT_RELOAD_SOURCE_FIXED_BITS:
 516                 break;
 517         case NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS:
 518                 mode_reg_values |= GI_RELOAD_SRC_SWITCHING;
 519                 break;
 520         case NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS:
 521                 input_select_bits |= GI_GATE_SEL_LOAD_SRC;
 522                 mode_reg_mask |= GI_GATING_MODE_MASK;
 523                 mode_reg_values |= GI_LEVEL_GATING;
 524                 break;
 525         default:
 526                 break;
 527         }
 528         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
 529                         mode_reg_mask, mode_reg_values);
 530
 531         if (ni_tio_counting_mode_registers_present(counter_dev)) {
 532                 unsigned int bits = 0;
 533
 534                 bits |= GI_CNT_MODE(mode >> NI_GPCT_COUNTING_MODE_SHIFT);
 535                 bits |= GI_INDEX_PHASE((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT));
 536                 if (mode & NI_GPCT_INDEX_ENABLE_BIT)
 537                         bits |= GI_INDEX_MODE;
 538                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 539                                 GI_CNT_MODE_MASK | GI_INDEX_PHASE_MASK |
 540                                 GI_INDEX_MODE, bits);
 541                 ni_tio_set_sync_mode(counter);
 542         }
 543
 544         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_CNT_DIR_MASK,
 545                         GI_CNT_DIR(mode >> NI_GPCT_COUNTING_DIRECTION_SHIFT));
 546
 547         if (mode & NI_GPCT_OR_GATE_BIT)
 548                 input_select_bits |= GI_OR_GATE;
 549         if (mode & NI_GPCT_INVERT_OUTPUT_BIT)
 550                 input_select_bits |= GI_OUTPUT_POL_INVERT;
 551         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 552                         GI_GATE_SEL_LOAD_SRC | GI_OR_GATE |
 553                         GI_OUTPUT_POL_INVERT, input_select_bits);
 554
 555         return 0;
 556 }
 557
 558 int ni_tio_arm(struct ni_gpct *counter, bool arm, unsigned int start_trigger)
 559 {
 560         struct ni_gpct_device *counter_dev = counter->counter_dev;
 561         unsigned int cidx = counter->counter_index;
 562         unsigned int transient_bits = 0;
 563
 564         if (arm) {
 565                 unsigned int mask = 0;
 566                 unsigned int bits = 0;
 567
 568                 /* only m series and 660x have counting mode registers */
 569                 switch (counter_dev->variant) {
 570                 case ni_gpct_variant_e_series:
 571                 default:
 572                         break;
 573                 case ni_gpct_variant_m_series:
 574                         mask = GI_M_HW_ARM_SEL_MASK;
 575                         break;
 576                 case ni_gpct_variant_660x:
 577                         mask = GI_660X_HW_ARM_SEL_MASK;
 578                         break;
 579                 }
 580
 581                 switch (start_trigger) {
 582                 case NI_GPCT_ARM_IMMEDIATE:
 583                         transient_bits |= GI_ARM;
 584                         break;
 585                 case NI_GPCT_ARM_PAIRED_IMMEDIATE:
 586                         transient_bits |= GI_ARM | GI_ARM_COPY;
 587                         break;
 588                 default:
 589                         /*
 590                          * for m series and 660x, pass-through the least
 591                          * significant bits so we can figure out what select
 592                          * later
 593                          */
 594                         if (mask && (start_trigger & NI_GPCT_ARM_UNKNOWN)) {
 595                                 bits |= GI_HW_ARM_ENA |
 596                                         (GI_HW_ARM_SEL(start_trigger) & mask);
 597                         } else {
 598                                 return -EINVAL;
 599                         }
 600                         break;
 601                 }
 602
 603                 if (mask)
 604                         ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 605                                         GI_HW_ARM_ENA | mask, bits);
 606         } else {
 607                 transient_bits |= GI_DISARM;
 608         }
 609         ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
 610                                   0, 0, transient_bits);
 611         return 0;
 612 }
 613 EXPORT_SYMBOL_GPL(ni_tio_arm);
 614
 615 static int ni_660x_clk_src(unsigned int clock_source, unsigned int *bits)
 616 {
 617         unsigned int clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
 618         unsigned int ni_660x_clock;
 619         unsigned int i;
 620
 621         switch (clk_src) {
 622         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 623                 ni_660x_clock = NI_660X_TIMEBASE_1_CLK;
 624                 break;
 625         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 626                 ni_660x_clock = NI_660X_TIMEBASE_2_CLK;
 627                 break;
 628         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 629                 ni_660x_clock = NI_660X_TIMEBASE_3_CLK;
 630                 break;
 631         case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
 632                 ni_660x_clock = NI_660X_LOGIC_LOW_CLK;
 633                 break;
 634         case NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS:
 635                 ni_660x_clock = NI_660X_SRC_PIN_I_CLK;
 636                 break;
 637         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 638                 ni_660x_clock = NI_660X_NEXT_GATE_CLK;
 639                 break;
 640         case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
 641                 ni_660x_clock = NI_660X_NEXT_TC_CLK;
 642                 break;
 643         default:
 644                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 645                         if (clk_src == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
 646                                 ni_660x_clock = NI_660X_RTSI_CLK(i);
 647                                 break;
 648                         }
 649                 }
 650                 if (i <= NI_660X_MAX_RTSI_CHAN)
 651                         break;
 652                 for (i = 0; i <= NI_660X_MAX_SRC_PIN; ++i) {
 653                         if (clk_src == NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i)) {
 654                                 ni_660x_clock = NI_660X_SRC_PIN_CLK(i);
 655                                 break;
 656                         }
 657                 }
 658                 if (i <= NI_660X_MAX_SRC_PIN)
 659                         break;
 660                 return -EINVAL;
 661         }
 662         *bits = GI_SRC_SEL(ni_660x_clock);
 663         return 0;
 664 }
 665
 666 static int ni_m_clk_src(unsigned int clock_source, unsigned int *bits)
 667 {
 668         unsigned int clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
 669         unsigned int ni_m_series_clock;
 670         unsigned int i;
 671
 672         switch (clk_src) {
 673         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 674                 ni_m_series_clock = NI_M_TIMEBASE_1_CLK;
 675                 break;
 676         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 677                 ni_m_series_clock = NI_M_TIMEBASE_2_CLK;
 678                 break;
 679         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 680                 ni_m_series_clock = NI_M_TIMEBASE_3_CLK;
 681                 break;
 682         case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
 683                 ni_m_series_clock = NI_M_LOGIC_LOW_CLK;
 684                 break;
 685         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 686                 ni_m_series_clock = NI_M_NEXT_GATE_CLK;
 687                 break;
 688         case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
 689                 ni_m_series_clock = NI_M_NEXT_TC_CLK;
 690                 break;
 691         case NI_GPCT_PXI10_CLOCK_SRC_BITS:
 692                 ni_m_series_clock = NI_M_PXI10_CLK;
 693                 break;
 694         case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
 695                 ni_m_series_clock = NI_M_PXI_STAR_TRIGGER_CLK;
 696                 break;
 697         case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
 698                 ni_m_series_clock = NI_M_ANALOG_TRIGGER_OUT_CLK;
 699                 break;
 700         default:
 701                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
 702                         if (clk_src == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
 703                                 ni_m_series_clock = NI_M_RTSI_CLK(i);
 704                                 break;
 705                         }
 706                 }
 707                 if (i <= NI_M_MAX_RTSI_CHAN)
 708                         break;
 709                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
 710                         if (clk_src == NI_GPCT_PFI_CLOCK_SRC_BITS(i)) {
 711                                 ni_m_series_clock = NI_M_PFI_CLK(i);
 712                                 break;
 713                         }
 714                 }
 715                 if (i <= NI_M_MAX_PFI_CHAN)
 716                         break;
 717                 return -EINVAL;
 718         }
 719         *bits = GI_SRC_SEL(ni_m_series_clock);
 720         return 0;
 721 };
 722
 723 static void ni_tio_set_source_subselect(struct ni_gpct *counter,
 724                                         unsigned int clock_source)
 725 {
 726         struct ni_gpct_device *counter_dev = counter->counter_dev;
 727         unsigned int cidx = counter->counter_index;
 728         unsigned int second_gate_reg = NITIO_GATE2_REG(cidx);
 729
 730         if (counter_dev->variant != ni_gpct_variant_m_series)
 731                 return;
 732         switch (clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
 733                 /* Gi_Source_Subselect is zero */
 734         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 735         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 736                 counter_dev->regs[second_gate_reg] &= ~GI_SRC_SUBSEL;
 737                 break;
 738                 /* Gi_Source_Subselect is one */
 739         case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
 740         case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
 741                 counter_dev->regs[second_gate_reg] |= GI_SRC_SUBSEL;
 742                 break;
 743                 /* Gi_Source_Subselect doesn't matter */
 744         default:
 745                 return;
 746         }
 747         ni_tio_write(counter, counter_dev->regs[second_gate_reg],
 748                      second_gate_reg);
 749 }
 750
 751 static int ni_tio_set_clock_src(struct ni_gpct *counter,
 752                                 unsigned int clock_source,
 753                                 unsigned int period_ns)
 754 {
 755         struct ni_gpct_device *counter_dev = counter->counter_dev;
 756         unsigned int cidx = counter->counter_index;
 757         unsigned int bits = 0;
 758         int ret;
 759
 760         switch (counter_dev->variant) {
 761         case ni_gpct_variant_660x:
 762                 ret = ni_660x_clk_src(clock_source, &bits);
 763                 break;
 764         case ni_gpct_variant_e_series:
 765         case ni_gpct_variant_m_series:
 766         default:
 767                 ret = ni_m_clk_src(clock_source, &bits);
 768                 break;
 769         }
 770         if (ret) {
 771                 struct comedi_device *dev = counter_dev->dev;
 772
 773                 dev_err(dev->class_dev, "invalid clock source 0x%x\n",
 774                         clock_source);
 775                 return ret;
 776         }
 777
 778         if (clock_source & NI_GPCT_INVERT_CLOCK_SRC_BIT)
 779                 bits |= GI_SRC_POL_INVERT;
 780         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 781                         GI_SRC_SEL_MASK | GI_SRC_POL_INVERT, bits);
 782         ni_tio_set_source_subselect(counter, clock_source);
 783
 784         if (ni_tio_counting_mode_registers_present(counter_dev)) {
 785                 bits = 0;
 786                 switch (clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
 787                 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
 788                         break;
 789                 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
 790                         bits |= GI_PRESCALE_X2(counter_dev->variant);
 791                         break;
 792                 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
 793                         bits |= GI_PRESCALE_X8(counter_dev->variant);
 794                         break;
 795                 default:
 796                         return -EINVAL;
 797                 }
 798                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 799                                 GI_PRESCALE_X2(counter_dev->variant) |
 800                                 GI_PRESCALE_X8(counter_dev->variant), bits);
 801         }
 802         counter->clock_period_ps = period_ns * 1000;
 803         ni_tio_set_sync_mode(counter);
 804         return 0;
 805 }
 806
 807 static int ni_tio_get_clock_src(struct ni_gpct *counter,
 808                                 unsigned int *clock_source,
 809                                 unsigned int *period_ns)
 810 {
 811         u64 temp64;
 812         int ret;
 813
 814         ret = ni_tio_generic_clock_src_select(counter, clock_source);
 815         if (ret)
 816                 return ret;
 817         ret = ni_tio_clock_period_ps(counter, *clock_source, &temp64);
 818         if (ret)
 819                 return ret;
 820         do_div(temp64, 1000);   /* ps to ns */
 821         *period_ns = temp64;
 822         return 0;
 823 }
 824
 825 static int ni_660x_set_gate(struct ni_gpct *counter, unsigned int gate_source)
 826 {
 827         unsigned int chan = CR_CHAN(gate_source);
 828         unsigned int cidx = counter->counter_index;
 829         unsigned int gate_sel;
 830         unsigned int i;
 831
 832         switch (chan) {
 833         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
 834                 gate_sel = NI_660X_NEXT_SRC_GATE_SEL;
 835                 break;
 836         case NI_GPCT_NEXT_OUT_GATE_SELECT:
 837         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
 838         case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
 839         case NI_GPCT_GATE_PIN_i_GATE_SELECT:
 840                 gate_sel = chan & 0x1f;
 841                 break;
 842         default:
 843                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 844                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
 845                                 gate_sel = chan & 0x1f;
 846                                 break;
 847                         }
 848                 }
 849                 if (i <= NI_660X_MAX_RTSI_CHAN)
 850                         break;
 851                 for (i = 0; i <= NI_660X_MAX_GATE_PIN; ++i) {
 852                         if (chan == NI_GPCT_GATE_PIN_GATE_SELECT(i)) {
 853                                 gate_sel = chan & 0x1f;
 854                                 break;
 855                         }
 856                 }
 857                 if (i <= NI_660X_MAX_GATE_PIN)
 858                         break;
 859                 return -EINVAL;
 860         }
 861         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 862                         GI_GATE_SEL_MASK, GI_GATE_SEL(gate_sel));
 863         return 0;
 864 }
 865
 866 static int ni_m_set_gate(struct ni_gpct *counter, unsigned int gate_source)
 867 {
 868         unsigned int chan = CR_CHAN(gate_source);
 869         unsigned int cidx = counter->counter_index;
 870         unsigned int gate_sel;
 871         unsigned int i;
 872
 873         switch (chan) {
 874         case NI_GPCT_TIMESTAMP_MUX_GATE_SELECT:
 875         case NI_GPCT_AI_START2_GATE_SELECT:
 876         case NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT:
 877         case NI_GPCT_NEXT_OUT_GATE_SELECT:
 878         case NI_GPCT_AI_START1_GATE_SELECT:
 879         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
 880         case NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT:
 881         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
 882                 gate_sel = chan & 0x1f;
 883                 break;
 884         default:
 885                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
 886                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
 887                                 gate_sel = chan & 0x1f;
 888                                 break;
 889                         }
 890                 }
 891                 if (i <= NI_M_MAX_RTSI_CHAN)
 892                         break;
 893                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
 894                         if (chan == NI_GPCT_PFI_GATE_SELECT(i)) {
 895                                 gate_sel = chan & 0x1f;
 896                                 break;
 897                         }
 898                 }
 899                 if (i <= NI_M_MAX_PFI_CHAN)
 900                         break;
 901                 return -EINVAL;
 902         }
 903         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 904                         GI_GATE_SEL_MASK, GI_GATE_SEL(gate_sel));
 905         return 0;
 906 }
 907
 908 static int ni_660x_set_gate2(struct ni_gpct *counter, unsigned int gate_source)
 909 {
 910         struct ni_gpct_device *counter_dev = counter->counter_dev;
 911         unsigned int cidx = counter->counter_index;
 912         unsigned int chan = CR_CHAN(gate_source);
 913         unsigned int gate2_reg = NITIO_GATE2_REG(cidx);
 914         unsigned int gate2_sel;
 915         unsigned int i;
 916
 917         switch (chan) {
 918         case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
 919         case NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT:
 920         case NI_GPCT_SELECTED_GATE_GATE_SELECT:
 921         case NI_GPCT_NEXT_OUT_GATE_SELECT:
 922         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
 923                 gate2_sel = chan & 0x1f;
 924                 break;
 925         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
 926                 gate2_sel = NI_660X_NEXT_SRC_GATE2_SEL;
 927                 break;
 928         default:
 929                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 930                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
 931                                 gate2_sel = chan & 0x1f;
 932                                 break;
 933                         }
 934                 }
 935                 if (i <= NI_660X_MAX_RTSI_CHAN)
 936                         break;
 937                 for (i = 0; i <= NI_660X_MAX_UP_DOWN_PIN; ++i) {
 938                         if (chan == NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i)) {
 939                                 gate2_sel = chan & 0x1f;
 940                                 break;
 941                         }
 942                 }
 943                 if (i <= NI_660X_MAX_UP_DOWN_PIN)
 944                         break;
 945                 return -EINVAL;
 946         }
 947         counter_dev->regs[gate2_reg] |= GI_GATE2_MODE;
 948         counter_dev->regs[gate2_reg] &= ~GI_GATE2_SEL_MASK;
 949         counter_dev->regs[gate2_reg] |= GI_GATE2_SEL(gate2_sel);
 950         ni_tio_write(counter, counter_dev->regs[gate2_reg], gate2_reg);
 951         return 0;
 952 }
 953
 954 static int ni_m_set_gate2(struct ni_gpct *counter, unsigned int gate_source)
 955 {
 956         struct ni_gpct_device *counter_dev = counter->counter_dev;
 957         unsigned int cidx = counter->counter_index;
 958         unsigned int chan = CR_CHAN(gate_source);
 959         unsigned int gate2_reg = NITIO_GATE2_REG(cidx);
 960         unsigned int gate2_sel;
 961
 962         /*
 963          * FIXME: We don't know what the m-series second gate codes are,
 964          * so we'll just pass the bits through for now.
 965          */
 966         switch (chan) {
 967         default:
 968                 gate2_sel = chan & 0x1f;
 969                 break;
 970         }
 971         counter_dev->regs[gate2_reg] |= GI_GATE2_MODE;
 972         counter_dev->regs[gate2_reg] &= ~GI_GATE2_SEL_MASK;
 973         counter_dev->regs[gate2_reg] |= GI_GATE2_SEL(gate2_sel);
 974         ni_tio_write(counter, counter_dev->regs[gate2_reg], gate2_reg);
 975         return 0;
 976 }
 977
 978 int ni_tio_set_gate_src(struct ni_gpct *counter,
 979                         unsigned int gate, unsigned int src)
 980 {
 981         struct ni_gpct_device *counter_dev = counter->counter_dev;
 982         unsigned int cidx = counter->counter_index;
 983         unsigned int chan = CR_CHAN(src);
 984         unsigned int gate2_reg = NITIO_GATE2_REG(cidx);
 985         unsigned int mode = 0;
 986
 987         switch (gate) {
 988         case 0:
 989                 if (chan == NI_GPCT_DISABLED_GATE_SELECT) {
 990                         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
 991                                         GI_GATING_MODE_MASK,
 992                                         GI_GATING_DISABLED);
 993                         return 0;
 994                 }
 995                 if (src & CR_INVERT)
 996                         mode |= GI_GATE_POL_INVERT;
 997                 if (src & CR_EDGE)
 998                         mode |= GI_RISING_EDGE_GATING;
 999                 else
1000                         mode |= GI_LEVEL_GATING;
1001                 ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
1002                                 GI_GATE_POL_INVERT | GI_GATING_MODE_MASK,
1003                                 mode);
1004                 switch (counter_dev->variant) {
1005                 case ni_gpct_variant_e_series:
1006                 case ni_gpct_variant_m_series:
1007                 default:
1008                         return ni_m_set_gate(counter, src);
1009                 case ni_gpct_variant_660x:
1010                         return ni_660x_set_gate(counter, src);
1011                 }
1012                 break;
1013         case 1:
1014                 if (!ni_tio_has_gate2_registers(counter_dev))
1015                         return -EINVAL;
1016
1017                 if (chan == NI_GPCT_DISABLED_GATE_SELECT) {
1018                         counter_dev->regs[gate2_reg] &= ~GI_GATE2_MODE;
1019                         ni_tio_write(counter, counter_dev->regs[gate2_reg],
1020                                      gate2_reg);
1021                         return 0;
1022                 }
1023                 if (src & CR_INVERT)
1024                         counter_dev->regs[gate2_reg] |= GI_GATE2_POL_INVERT;
1025                 else
1026                         counter_dev->regs[gate2_reg] &= ~GI_GATE2_POL_INVERT;
1027                 switch (counter_dev->variant) {
1028                 case ni_gpct_variant_m_series:
1029                         return ni_m_set_gate2(counter, src);
1030                 case ni_gpct_variant_660x:
1031                         return ni_660x_set_gate2(counter, src);
1032                 default:
1033                         return -EINVAL;
1034                 }
1035                 break;
1036         default:
1037                 return -EINVAL;
1038         }
1039         return 0;
1040 }
1041 EXPORT_SYMBOL_GPL(ni_tio_set_gate_src);
1042
1043 static int ni_tio_set_other_src(struct ni_gpct *counter, unsigned int index,
1044                                 unsigned int source)
1045 {
1046         struct ni_gpct_device *counter_dev = counter->counter_dev;
1047         unsigned int cidx = counter->counter_index;
1048         unsigned int abz_reg, shift, mask;
1049
1050         if (counter_dev->variant != ni_gpct_variant_m_series)
1051                 return -EINVAL;
1052
1053         abz_reg = NITIO_ABZ_REG(cidx);
1054         switch (index) {
1055         case NI_GPCT_SOURCE_ENCODER_A:
1056                 shift = 10;
1057                 break;
1058         case NI_GPCT_SOURCE_ENCODER_B:
1059                 shift = 5;
1060                 break;
1061         case NI_GPCT_SOURCE_ENCODER_Z:
1062                 shift = 0;
1063                 break;
1064         default:
1065                 return -EINVAL;
1066         }
1067         mask = 0x1f << shift;
1068         if (source > 0x1f)
1069                 source = 0x1f;  /* Disable gate */
1070
1071         counter_dev->regs[abz_reg] &= ~mask;
1072         counter_dev->regs[abz_reg] |= (source << shift) & mask;
1073         ni_tio_write(counter, counter_dev->regs[abz_reg], abz_reg);
1074         return 0;
1075 }
1076
1077 static int ni_660x_gate_to_generic_gate(unsigned int gate, unsigned int *src)
1078 {
1079         unsigned int source;
1080         unsigned int i;
1081
1082         switch (gate) {
1083         case NI_660X_SRC_PIN_I_GATE_SEL:
1084                 source = NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1085                 break;
1086         case NI_660X_GATE_PIN_I_GATE_SEL:
1087                 source = NI_GPCT_GATE_PIN_i_GATE_SELECT;
1088                 break;
1089         case NI_660X_NEXT_SRC_GATE_SEL:
1090                 source = NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1091                 break;
1092         case NI_660X_NEXT_OUT_GATE_SEL:
1093                 source = NI_GPCT_NEXT_OUT_GATE_SELECT;
1094                 break;
1095         case NI_660X_LOGIC_LOW_GATE_SEL:
1096                 source = NI_GPCT_LOGIC_LOW_GATE_SELECT;
1097                 break;
1098         default:
1099                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
1100                         if (gate == NI_660X_RTSI_GATE_SEL(i)) {
1101                                 source = NI_GPCT_RTSI_GATE_SELECT(i);
1102                                 break;
1103                         }
1104                 }
1105                 if (i <= NI_660X_MAX_RTSI_CHAN)
1106                         break;
1107                 for (i = 0; i <= NI_660X_MAX_GATE_PIN; ++i) {
1108                         if (gate == NI_660X_PIN_GATE_SEL(i)) {
1109                                 source = NI_GPCT_GATE_PIN_GATE_SELECT(i);
1110                                 break;
1111                         }
1112                 }
1113                 if (i <= NI_660X_MAX_GATE_PIN)
1114                         break;
1115                 return -EINVAL;
1116         }
1117         *src = source;
1118         return 0;
1119 };
1120
1121 static int ni_m_gate_to_generic_gate(unsigned int gate, unsigned int *src)
1122 {
1123         unsigned int source;
1124         unsigned int i;
1125
1126         switch (gate) {
1127         case NI_M_TIMESTAMP_MUX_GATE_SEL:
1128                 source = NI_GPCT_TIMESTAMP_MUX_GATE_SELECT;
1129                 break;
1130         case NI_M_AI_START2_GATE_SEL:
1131                 source = NI_GPCT_AI_START2_GATE_SELECT;
1132                 break;
1133         case NI_M_PXI_STAR_TRIGGER_GATE_SEL:
1134                 source = NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT;
1135                 break;
1136         case NI_M_NEXT_OUT_GATE_SEL:
1137                 source = NI_GPCT_NEXT_OUT_GATE_SELECT;
1138                 break;
1139         case NI_M_AI_START1_GATE_SEL:
1140                 source = NI_GPCT_AI_START1_GATE_SELECT;
1141                 break;
1142         case NI_M_NEXT_SRC_GATE_SEL:
1143                 source = NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1144                 break;
1145         case NI_M_ANALOG_TRIG_OUT_GATE_SEL:
1146                 source = NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT;
1147                 break;
1148         case NI_M_LOGIC_LOW_GATE_SEL:
1149                 source = NI_GPCT_LOGIC_LOW_GATE_SELECT;
1150                 break;
1151         default:
1152                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
1153                         if (gate == NI_M_RTSI_GATE_SEL(i)) {
1154                                 source = NI_GPCT_RTSI_GATE_SELECT(i);
1155                                 break;
1156                         }
1157                 }
1158                 if (i <= NI_M_MAX_RTSI_CHAN)
1159                         break;
1160                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
1161                         if (gate == NI_M_PFI_GATE_SEL(i)) {
1162                                 source = NI_GPCT_PFI_GATE_SELECT(i);
1163                                 break;
1164                         }
1165                 }
1166                 if (i <= NI_M_MAX_PFI_CHAN)
1167                         break;
1168                 return -EINVAL;
1169         }
1170         *src = source;
1171         return 0;
1172 };
1173
1174 static int ni_660x_gate2_to_generic_gate(unsigned int gate, unsigned int *src)
1175 {
1176         unsigned int source;
1177         unsigned int i;
1178
1179         switch (gate) {
1180         case NI_660X_SRC_PIN_I_GATE2_SEL:
1181                 source = NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1182                 break;
1183         case NI_660X_UD_PIN_I_GATE2_SEL:
1184                 source = NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT;
1185                 break;
1186         case NI_660X_NEXT_SRC_GATE2_SEL:
1187                 source = NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1188                 break;
1189         case NI_660X_NEXT_OUT_GATE2_SEL:
1190                 source = NI_GPCT_NEXT_OUT_GATE_SELECT;
1191                 break;
1192         case NI_660X_SELECTED_GATE2_SEL:
1193                 source = NI_GPCT_SELECTED_GATE_GATE_SELECT;
1194                 break;
1195         case NI_660X_LOGIC_LOW_GATE2_SEL:
1196                 source = NI_GPCT_LOGIC_LOW_GATE_SELECT;
1197                 break;
1198         default:
1199                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
1200                         if (gate == NI_660X_RTSI_GATE2_SEL(i)) {
1201                                 source = NI_GPCT_RTSI_GATE_SELECT(i);
1202                                 break;
1203                         }
1204                 }
1205                 if (i <= NI_660X_MAX_RTSI_CHAN)
1206                         break;
1207                 for (i = 0; i <= NI_660X_MAX_UP_DOWN_PIN; ++i) {
1208                         if (gate == NI_660X_UD_PIN_GATE2_SEL(i)) {
1209                                 source = NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i);
1210                                 break;
1211                         }
1212                 }
1213                 if (i <= NI_660X_MAX_UP_DOWN_PIN)
1214                         break;
1215                 return -EINVAL;
1216         }
1217         *src = source;
1218         return 0;
1219 };
1220
1221 static int ni_m_gate2_to_generic_gate(unsigned int gate, unsigned int *src)
1222 {
1223         /*
1224          * FIXME: the second gate sources for the m series are undocumented,
1225          * so we just return the raw bits for now.
1226          */
1227         *src = gate;
1228         return 0;
1229 };
1230
1231 static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned int gate_index,
1232                                unsigned int *gate_source)
1233 {
1234         struct ni_gpct_device *counter_dev = counter->counter_dev;
1235         unsigned int cidx = counter->counter_index;
1236         unsigned int mode;
1237         unsigned int reg;
1238         unsigned int gate;
1239         int ret;
1240
1241         mode = ni_tio_get_soft_copy(counter, NITIO_MODE_REG(cidx));
1242         if (((mode & GI_GATING_MODE_MASK) == GI_GATING_DISABLED) ||
1243             (gate_index == 1 &&
1244              !(counter_dev->regs[NITIO_GATE2_REG(cidx)] & GI_GATE2_MODE))) {
1245                 *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1246                 return 0;
1247         }
1248
1249         switch (gate_index) {
1250         case 0:
1251                 reg = NITIO_INPUT_SEL_REG(cidx);
1252                 gate = GI_BITS_TO_GATE(ni_tio_get_soft_copy(counter, reg));
1253
1254                 switch (counter_dev->variant) {
1255                 case ni_gpct_variant_e_series:
1256                 case ni_gpct_variant_m_series:
1257                 default:
1258                         ret = ni_m_gate_to_generic_gate(gate, gate_source);
1259                         break;
1260                 case ni_gpct_variant_660x:
1261                         ret = ni_660x_gate_to_generic_gate(gate, gate_source);
1262                         break;
1263                 }
1264                 if (ret)
1265                         return ret;
1266                 if (mode & GI_GATE_POL_INVERT)
1267                         *gate_source |= CR_INVERT;
1268                 if ((mode & GI_GATING_MODE_MASK) != GI_LEVEL_GATING)
1269                         *gate_source |= CR_EDGE;
1270                 break;
1271         case 1:
1272                 reg = NITIO_GATE2_REG(cidx);
1273                 gate = GI_BITS_TO_GATE2(counter_dev->regs[reg]);
1274
1275                 switch (counter_dev->variant) {
1276                 case ni_gpct_variant_e_series:
1277                 case ni_gpct_variant_m_series:
1278                 default:
1279                         ret = ni_m_gate2_to_generic_gate(gate, gate_source);
1280                         break;
1281                 case ni_gpct_variant_660x:
1282                         ret = ni_660x_gate2_to_generic_gate(gate, gate_source);
1283                         break;
1284                 }
1285                 if (ret)
1286                         return ret;
1287                 if (counter_dev->regs[reg] & GI_GATE2_POL_INVERT)
1288                         *gate_source |= CR_INVERT;
1289                 /* second gate can't have edge/level mode set independently */
1290                 if ((mode & GI_GATING_MODE_MASK) != GI_LEVEL_GATING)
1291                         *gate_source |= CR_EDGE;
1292                 break;
1293         default:
1294                 return -EINVAL;
1295         }
1296         return 0;
1297 }
1298
1299 int ni_tio_insn_config(struct comedi_device *dev,
1300                        struct comedi_subdevice *s,
1301                        struct comedi_insn *insn,
1302                        unsigned int *data)
1303 {
1304         struct ni_gpct *counter = s->private;
1305         unsigned int cidx = counter->counter_index;
1306         unsigned int status;
1307         int ret = 0;
1308
1309         switch (data[0]) {
1310         case INSN_CONFIG_SET_COUNTER_MODE:
1311                 ret = ni_tio_set_counter_mode(counter, data[1]);
1312                 break;
1313         case INSN_CONFIG_ARM:
1314                 ret = ni_tio_arm(counter, true, data[1]);
1315                 break;
1316         case INSN_CONFIG_DISARM:
1317                 ret = ni_tio_arm(counter, false, 0);
1318                 break;
1319         case INSN_CONFIG_GET_COUNTER_STATUS:
1320                 data[1] = 0;
1321                 status = ni_tio_read(counter, NITIO_SHARED_STATUS_REG(cidx));
1322                 if (status & GI_ARMED(cidx)) {
1323                         data[1] |= COMEDI_COUNTER_ARMED;
1324                         if (status & GI_COUNTING(cidx))
1325                                 data[1] |= COMEDI_COUNTER_COUNTING;
1326                 }
1327                 data[2] = COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING;
1328                 break;
1329         case INSN_CONFIG_SET_CLOCK_SRC:
1330                 ret = ni_tio_set_clock_src(counter, data[1], data[2]);
1331                 break;
1332         case INSN_CONFIG_GET_CLOCK_SRC:
1333                 ret = ni_tio_get_clock_src(counter, &data[1], &data[2]);
1334                 break;
1335         case INSN_CONFIG_SET_GATE_SRC:
1336                 ret = ni_tio_set_gate_src(counter, data[1], data[2]);
1337                 break;
1338         case INSN_CONFIG_GET_GATE_SRC:
1339                 ret = ni_tio_get_gate_src(counter, data[1], &data[2]);
1340                 break;
1341         case INSN_CONFIG_SET_OTHER_SRC:
1342                 ret = ni_tio_set_other_src(counter, data[1], data[2]);
1343                 break;
1344         case INSN_CONFIG_RESET:
1345                 ni_tio_reset_count_and_disarm(counter);
1346                 break;
1347         default:
1348                 return -EINVAL;
1349         }
1350         return ret ? ret : insn->n;
1351 }
1352 EXPORT_SYMBOL_GPL(ni_tio_insn_config);
1353
1354 static unsigned int ni_tio_read_sw_save_reg(struct comedi_device *dev,
1355                                             struct comedi_subdevice *s)
1356 {
1357         struct ni_gpct *counter = s->private;
1358         unsigned int cidx = counter->counter_index;
1359         unsigned int val;
1360
1361         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_SAVE_TRACE, 0);
1362         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
1363                         GI_SAVE_TRACE, GI_SAVE_TRACE);
1364
1365         /*
1366          * The count doesn't get latched until the next clock edge, so it is
1367          * possible the count may change (once) while we are reading. Since
1368          * the read of the SW_Save_Reg isn't atomic (apparently even when it's
1369          * a 32 bit register according to 660x docs), we need to read twice
1370          * and make sure the reading hasn't changed. If it has, a third read
1371          * will be correct since the count value will definitely have latched
1372          * by then.
1373          */
1374         val = ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx));
1375         if (val != ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx)))
1376                 val = ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx));
1377
1378         return val;
1379 }
1380
1381 int ni_tio_insn_read(struct comedi_device *dev,
1382                      struct comedi_subdevice *s,
1383                      struct comedi_insn *insn,
1384                      unsigned int *data)
1385 {
1386         struct ni_gpct *counter = s->private;
1387         struct ni_gpct_device *counter_dev = counter->counter_dev;
1388         unsigned int channel = CR_CHAN(insn->chanspec);
1389         unsigned int cidx = counter->counter_index;
1390         int i;
1391
1392         for (i = 0; i < insn->n; i++) {
1393                 switch (channel) {
1394                 case 0:
1395                         data[i] = ni_tio_read_sw_save_reg(dev, s);
1396                         break;
1397                 case 1:
1398                         data[i] = counter_dev->regs[NITIO_LOADA_REG(cidx)];
1399                         break;
1400                 case 2:
1401                         data[i] = counter_dev->regs[NITIO_LOADB_REG(cidx)];
1402                         break;
1403                 }
1404         }
1405         return insn->n;
1406 }
1407 EXPORT_SYMBOL_GPL(ni_tio_insn_read);
1408
1409 static unsigned int ni_tio_next_load_register(struct ni_gpct *counter)
1410 {
1411         unsigned int cidx = counter->counter_index;
1412         unsigned int bits = ni_tio_read(counter, NITIO_SHARED_STATUS_REG(cidx));
1413
1414         return (bits & GI_NEXT_LOAD_SRC(cidx))
1415                         ? NITIO_LOADB_REG(cidx)
1416                         : NITIO_LOADA_REG(cidx);
1417 }
1418
1419 int ni_tio_insn_write(struct comedi_device *dev,
1420                       struct comedi_subdevice *s,
1421                       struct comedi_insn *insn,
1422                       unsigned int *data)
1423 {
1424         struct ni_gpct *counter = s->private;
1425         struct ni_gpct_device *counter_dev = counter->counter_dev;
1426         unsigned int channel = CR_CHAN(insn->chanspec);
1427         unsigned int cidx = counter->counter_index;
1428         unsigned int load_reg;
1429
1430         if (insn->n < 1)
1431                 return 0;
1432         switch (channel) {
1433         case 0:
1434                 /*
1435                  * Unsafe if counter is armed.
1436                  * Should probably check status and return -EBUSY if armed.
1437                  */
1438
1439                 /*
1440                  * Don't disturb load source select, just use whichever
1441                  * load register is already selected.
1442                  */
1443                 load_reg = ni_tio_next_load_register(counter);
1444                 ni_tio_write(counter, data[0], load_reg);
1445                 ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
1446                                           0, 0, GI_LOAD);
1447                 /* restore load reg */
1448                 ni_tio_write(counter, counter_dev->regs[load_reg], load_reg);
1449                 break;
1450         case 1:
1451                 counter_dev->regs[NITIO_LOADA_REG(cidx)] = data[0];
1452                 ni_tio_write(counter, data[0], NITIO_LOADA_REG(cidx));
1453                 break;
1454         case 2:
1455                 counter_dev->regs[NITIO_LOADB_REG(cidx)] = data[0];
1456                 ni_tio_write(counter, data[0], NITIO_LOADB_REG(cidx));
1457                 break;
1458         default:
1459                 return -EINVAL;
1460         }
1461         return 0;
1462 }
1463 EXPORT_SYMBOL_GPL(ni_tio_insn_write);
1464
1465 void ni_tio_init_counter(struct ni_gpct *counter)
1466 {
1467         struct ni_gpct_device *counter_dev = counter->counter_dev;
1468         unsigned int cidx = counter->counter_index;
1469
1470         ni_tio_reset_count_and_disarm(counter);
1471
1472         /* initialize counter registers */
1473         counter_dev->regs[NITIO_AUTO_INC_REG(cidx)] = 0x0;
1474         ni_tio_write(counter, 0x0, NITIO_AUTO_INC_REG(cidx));
1475
1476         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
1477                         ~0, GI_SYNC_GATE);
1478
1479         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx), ~0, 0);
1480
1481         counter_dev->regs[NITIO_LOADA_REG(cidx)] = 0x0;
1482         ni_tio_write(counter, 0x0, NITIO_LOADA_REG(cidx));
1483
1484         counter_dev->regs[NITIO_LOADB_REG(cidx)] = 0x0;
1485         ni_tio_write(counter, 0x0, NITIO_LOADB_REG(cidx));
1486
1487         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), ~0, 0);
1488
1489         if (ni_tio_counting_mode_registers_present(counter_dev))
1490                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx), ~0, 0);
1491
1492         if (ni_tio_has_gate2_registers(counter_dev)) {
1493                 counter_dev->regs[NITIO_GATE2_REG(cidx)] = 0x0;
1494                 ni_tio_write(counter, 0x0, NITIO_GATE2_REG(cidx));
1495         }
1496
1497         ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), ~0, 0x0);
1498
1499         ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx), ~0, 0x0);
1500 }
1501 EXPORT_SYMBOL_GPL(ni_tio_init_counter);
1502
1503 struct ni_gpct_device *
1504 ni_gpct_device_construct(struct comedi_device *dev,
1505                          void (*write)(struct ni_gpct *counter,
1506                                        unsigned int value,
1507                                        enum ni_gpct_register reg),
1508                          unsigned int (*read)(struct ni_gpct *counter,
1509                                               enum ni_gpct_register reg),
1510                          enum ni_gpct_variant variant,
1511                          unsigned int num_counters)
1512 {
1513         struct ni_gpct_device *counter_dev;
1514         struct ni_gpct *counter;
1515         unsigned int i;
1516
1517         if (num_counters == 0)
1518                 return NULL;
1519
1520         counter_dev = kzalloc(sizeof(*counter_dev), GFP_KERNEL);
1521         if (!counter_dev)
1522                 return NULL;
1523
1524         counter_dev->dev = dev;
1525         counter_dev->write = write;
1526         counter_dev->read = read;
1527         counter_dev->variant = variant;
1528
1529         spin_lock_init(&counter_dev->regs_lock);
1530
1531         counter_dev->counters = kcalloc(num_counters, sizeof(*counter),
1532                                         GFP_KERNEL);
1533         if (!counter_dev->counters) {
1534                 kfree(counter_dev);
1535                 return NULL;
1536         }
1537
1538         for (i = 0; i < num_counters; ++i) {
1539                 counter = &counter_dev->counters[i];
1540                 counter->counter_dev = counter_dev;
1541                 spin_lock_init(&counter->lock);
1542         }
1543         counter_dev->num_counters = num_counters;
1544
1545         return counter_dev;
1546 }
1547 EXPORT_SYMBOL_GPL(ni_gpct_device_construct);
1548
1549 void ni_gpct_device_destroy(struct ni_gpct_device *counter_dev)
1550 {
1551         if (!counter_dev)
1552                 return;
1553         kfree(counter_dev->counters);
1554         kfree(counter_dev);
1555 }
1556 EXPORT_SYMBOL_GPL(ni_gpct_device_destroy);
1557
1558 static int __init ni_tio_init_module(void)
1559 {
1560         return 0;
1561 }
1562 module_init(ni_tio_init_module);
1563
1564 static void __exit ni_tio_cleanup_module(void)
1565 {
1566 }
1567 module_exit(ni_tio_cleanup_module);
1568
1569 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
1570 MODULE_DESCRIPTION("Comedi support for NI general-purpose counters");
1571 MODULE_LICENSE("GPL");