drivers/staging/dwc2/hcd.c

   1 /*
   2  * hcd.c - DesignWare HS OTG Controller host-mode routines
   3  *
   4  * Copyright (C) 2004-2013 Synopsys, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 /*
  38  * This file contains the core HCD code, and implements the Linux hc_driver
  39  * API
  40  */
  41 #include <linux/kernel.h>
  42 #include <linux/module.h>
  43 #include <linux/spinlock.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/dma-mapping.h>
  46 #include <linux/delay.h>
  47 #include <linux/io.h>
  48 #include <linux/slab.h>
  49 #include <linux/usb.h>
  50
  51 #include <linux/usb/hcd.h>
  52 #include <linux/usb/ch11.h>
  53
  54 #include "core.h"
  55 #include "hcd.h"
  56
  57 /**
  58  * dwc2_dump_channel_info() - Prints the state of a host channel
  59  *
  60  * @hsotg: Programming view of DWC_otg controller
  61  * @chan:  Pointer to the channel to dump
  62  *
  63  * Must be called with interrupt disabled and spinlock held
  64  *
  65  * NOTE: This function will be removed once the peripheral controller code
  66  * is integrated and the driver is stable
  67  */
  68 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
  69                                    struct dwc2_host_chan *chan)
  70 {
  71 #ifdef VERBOSE_DEBUG
  72         int num_channels = hsotg->core_params->host_channels;
  73         struct dwc2_qh *qh;
  74         u32 hcchar;
  75         u32 hcsplt;
  76         u32 hctsiz;
  77         u32 hc_dma;
  78         int i;
  79
  80         if (chan == NULL)
  81                 return;
  82
  83         hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
  84         hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num));
  85         hctsiz = readl(hsotg->regs + HCTSIZ(chan->hc_num));
  86         hc_dma = readl(hsotg->regs + HCDMA(chan->hc_num));
  87
  88         dev_dbg(hsotg->dev, "  Assigned to channel %p:\n", chan);
  89         dev_dbg(hsotg->dev, "    hcchar 0x%08x, hcsplt 0x%08x\n",
  90                 hcchar, hcsplt);
  91         dev_dbg(hsotg->dev, "    hctsiz 0x%08x, hc_dma 0x%08x\n",
  92                 hctsiz, hc_dma);
  93         dev_dbg(hsotg->dev, "    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
  94                 chan->dev_addr, chan->ep_num, chan->ep_is_in);
  95         dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
  96         dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
  97         dev_dbg(hsotg->dev, "    data_pid_start: %d\n", chan->data_pid_start);
  98         dev_dbg(hsotg->dev, "    xfer_started: %d\n", chan->xfer_started);
  99         dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
 100         dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
 101         dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
 102                 (unsigned long)chan->xfer_dma);
 103         dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
 104         dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
 105         dev_dbg(hsotg->dev, "  NP inactive sched:\n");
 106         list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
 107                             qh_list_entry)
 108                 dev_dbg(hsotg->dev, "    %p\n", qh);
 109         dev_dbg(hsotg->dev, "  NP active sched:\n");
 110         list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
 111                             qh_list_entry)
 112                 dev_dbg(hsotg->dev, "    %p\n", qh);
 113         dev_dbg(hsotg->dev, "  Channels:\n");
 114         for (i = 0; i < num_channels; i++) {
 115                 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
 116
 117                 dev_dbg(hsotg->dev, "    %2d: %p\n", i, chan);
 118         }
 119 #endif /* VERBOSE_DEBUG */
 120 }
 121
 122 /*
 123  * Processes all the URBs in a single list of QHs. Completes them with
 124  * -ETIMEDOUT and frees the QTD.
 125  *
 126  * Must be called with interrupt disabled and spinlock held
 127  */
 128 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
 129                                       struct list_head *qh_list)
 130 {
 131         struct dwc2_qh *qh, *qh_tmp;
 132         struct dwc2_qtd *qtd, *qtd_tmp;
 133
 134         list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
 135                 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
 136                                          qtd_list_entry) {
 137                         if (qtd->urb != NULL) {
 138                                 dwc2_host_complete(hsotg, qtd->urb->priv,
 139                                                    qtd->urb, -ETIMEDOUT);
 140                                 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 141                         }
 142                 }
 143         }
 144 }
 145
 146 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
 147                               struct list_head *qh_list)
 148 {
 149         struct dwc2_qtd *qtd, *qtd_tmp;
 150         struct dwc2_qh *qh, *qh_tmp;
 151         unsigned long flags;
 152
 153         if (!qh_list->next)
 154                 /* The list hasn't been initialized yet */
 155                 return;
 156
 157         spin_lock_irqsave(&hsotg->lock, flags);
 158
 159         /* Ensure there are no QTDs or URBs left */
 160         dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
 161
 162         list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
 163                 dwc2_hcd_qh_unlink(hsotg, qh);
 164
 165                 /* Free each QTD in the QH's QTD list */
 166                 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
 167                                          qtd_list_entry)
 168                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 169
 170                 spin_unlock_irqrestore(&hsotg->lock, flags);
 171                 dwc2_hcd_qh_free(hsotg, qh);
 172                 spin_lock_irqsave(&hsotg->lock, flags);
 173         }
 174
 175         spin_unlock_irqrestore(&hsotg->lock, flags);
 176 }
 177
 178 /*
 179  * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
 180  * and periodic schedules. The QTD associated with each URB is removed from
 181  * the schedule and freed. This function may be called when a disconnect is
 182  * detected or when the HCD is being stopped.
 183  *
 184  * Must be called with interrupt disabled and spinlock held
 185  */
 186 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
 187 {
 188         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
 189         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
 190         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
 191         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
 192         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
 193         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
 194 }
 195
 196 /**
 197  * dwc2_hcd_start() - Starts the HCD when switching to Host mode
 198  *
 199  * @hsotg: Pointer to struct dwc2_hsotg
 200  */
 201 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
 202 {
 203         u32 hprt0;
 204
 205         if (hsotg->op_state == OTG_STATE_B_HOST) {
 206                 /*
 207                  * Reset the port. During a HNP mode switch the reset
 208                  * needs to occur within 1ms and have a duration of at
 209                  * least 50ms.
 210                  */
 211                 hprt0 = dwc2_read_hprt0(hsotg);
 212                 hprt0 |= HPRT0_RST;
 213                 writel(hprt0, hsotg->regs + HPRT0);
 214         }
 215
 216         queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
 217                            msecs_to_jiffies(50));
 218 }
 219
 220 /* Must be called with interrupt disabled and spinlock held */
 221 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
 222 {
 223         int num_channels = hsotg->core_params->host_channels;
 224         struct dwc2_host_chan *channel;
 225         u32 hcchar;
 226         int i;
 227
 228         if (hsotg->core_params->dma_enable <= 0) {
 229                 /* Flush out any channel requests in slave mode */
 230                 for (i = 0; i < num_channels; i++) {
 231                         channel = hsotg->hc_ptr_array[i];
 232                         if (!list_empty(&channel->hc_list_entry))
 233                                 continue;
 234                         hcchar = readl(hsotg->regs + HCCHAR(i));
 235                         if (hcchar & HCCHAR_CHENA) {
 236                                 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
 237                                 hcchar |= HCCHAR_CHDIS;
 238                                 writel(hcchar, hsotg->regs + HCCHAR(i));
 239                         }
 240                 }
 241         }
 242
 243         for (i = 0; i < num_channels; i++) {
 244                 channel = hsotg->hc_ptr_array[i];
 245                 if (!list_empty(&channel->hc_list_entry))
 246                         continue;
 247                 hcchar = readl(hsotg->regs + HCCHAR(i));
 248                 if (hcchar & HCCHAR_CHENA) {
 249                         /* Halt the channel */
 250                         hcchar |= HCCHAR_CHDIS;
 251                         writel(hcchar, hsotg->regs + HCCHAR(i));
 252                 }
 253
 254                 dwc2_hc_cleanup(hsotg, channel);
 255                 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
 256                 /*
 257                  * Added for Descriptor DMA to prevent channel double cleanup in
 258                  * release_channel_ddma(), which is called from ep_disable when
 259                  * device disconnects
 260                  */
 261                 channel->qh = NULL;
 262         }
 263 }
 264
 265 /**
 266  * dwc2_hcd_disconnect() - Handles disconnect of the HCD
 267  *
 268  * @hsotg: Pointer to struct dwc2_hsotg
 269  *
 270  * Must be called with interrupt disabled and spinlock held
 271  */
 272 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg)
 273 {
 274         u32 intr;
 275
 276         /* Set status flags for the hub driver */
 277         hsotg->flags.b.port_connect_status_change = 1;
 278         hsotg->flags.b.port_connect_status = 0;
 279
 280         /*
 281          * Shutdown any transfers in process by clearing the Tx FIFO Empty
 282          * interrupt mask and status bits and disabling subsequent host
 283          * channel interrupts.
 284          */
 285         intr = readl(hsotg->regs + GINTMSK);
 286         intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
 287         writel(intr, hsotg->regs + GINTMSK);
 288         intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
 289         writel(intr, hsotg->regs + GINTSTS);
 290
 291         /*
 292          * Turn off the vbus power only if the core has transitioned to device
 293          * mode. If still in host mode, need to keep power on to detect a
 294          * reconnection.
 295          */
 296         if (dwc2_is_device_mode(hsotg)) {
 297                 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
 298                         dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
 299                         writel(0, hsotg->regs + HPRT0);
 300                 }
 301
 302                 dwc2_disable_host_interrupts(hsotg);
 303         }
 304
 305         /* Respond with an error status to all URBs in the schedule */
 306         dwc2_kill_all_urbs(hsotg);
 307
 308         if (dwc2_is_host_mode(hsotg))
 309                 /* Clean up any host channels that were in use */
 310                 dwc2_hcd_cleanup_channels(hsotg);
 311
 312         dwc2_host_disconnect(hsotg);
 313 }
 314
 315 /**
 316  * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
 317  *
 318  * @hsotg: Pointer to struct dwc2_hsotg
 319  */
 320 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
 321 {
 322         if (hsotg->lx_state == DWC2_L2)
 323                 hsotg->flags.b.port_suspend_change = 1;
 324         else
 325                 hsotg->flags.b.port_l1_change = 1;
 326 }
 327
 328 /**
 329  * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
 330  *
 331  * @hsotg: Pointer to struct dwc2_hsotg
 332  *
 333  * Must be called with interrupt disabled and spinlock held
 334  */
 335 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
 336 {
 337         dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
 338
 339         /*
 340          * The root hub should be disconnected before this function is called.
 341          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
 342          * and the QH lists (via ..._hcd_endpoint_disable).
 343          */
 344
 345         /* Turn off all host-specific interrupts */
 346         dwc2_disable_host_interrupts(hsotg);
 347
 348         /* Turn off the vbus power */
 349         dev_dbg(hsotg->dev, "PortPower off\n");
 350         writel(0, hsotg->regs + HPRT0);
 351 }
 352
 353 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
 354                                 struct dwc2_hcd_urb *urb, void **ep_handle,
 355                                 gfp_t mem_flags)
 356 {
 357         struct dwc2_qtd *qtd;
 358         unsigned long flags;
 359         u32 intr_mask;
 360         int retval;
 361
 362         if (!hsotg->flags.b.port_connect_status) {
 363                 /* No longer connected */
 364                 dev_err(hsotg->dev, "Not connected\n");
 365                 return -ENODEV;
 366         }
 367
 368         qtd = kzalloc(sizeof(*qtd), mem_flags);
 369         if (!qtd)
 370                 return -ENOMEM;
 371
 372         dwc2_hcd_qtd_init(qtd, urb);
 373         retval = dwc2_hcd_qtd_add(hsotg, qtd, (struct dwc2_qh **)ep_handle,
 374                                   mem_flags);
 375         if (retval < 0) {
 376                 dev_err(hsotg->dev,
 377                         "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
 378                         retval);
 379                 kfree(qtd);
 380                 return retval;
 381         }
 382
 383         intr_mask = readl(hsotg->regs + GINTMSK);
 384         if (!(intr_mask & GINTSTS_SOF) && retval == 0) {
 385                 enum dwc2_transaction_type tr_type;
 386
 387                 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
 388                     !(qtd->urb->flags & URB_GIVEBACK_ASAP))
 389                         /*
 390                          * Do not schedule SG transactions until qtd has
 391                          * URB_GIVEBACK_ASAP set
 392                          */
 393                         return 0;
 394
 395                 spin_lock_irqsave(&hsotg->lock, flags);
 396                 tr_type = dwc2_hcd_select_transactions(hsotg);
 397                 if (tr_type != DWC2_TRANSACTION_NONE)
 398                         dwc2_hcd_queue_transactions(hsotg, tr_type);
 399                 spin_unlock_irqrestore(&hsotg->lock, flags);
 400         }
 401
 402         return retval;
 403 }
 404
 405 /* Must be called with interrupt disabled and spinlock held */
 406 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
 407                                 struct dwc2_hcd_urb *urb)
 408 {
 409         struct dwc2_qh *qh;
 410         struct dwc2_qtd *urb_qtd;
 411
 412         urb_qtd = urb->qtd;
 413         if (!urb_qtd) {
 414                 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
 415                 return -EINVAL;
 416         }
 417
 418         qh = urb_qtd->qh;
 419         if (!qh) {
 420                 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
 421                 return -EINVAL;
 422         }
 423
 424         if (urb_qtd->in_process && qh->channel) {
 425                 dwc2_dump_channel_info(hsotg, qh->channel);
 426
 427                 /* The QTD is in process (it has been assigned to a channel) */
 428                 if (hsotg->flags.b.port_connect_status)
 429                         /*
 430                          * If still connected (i.e. in host mode), halt the
 431                          * channel so it can be used for other transfers. If
 432                          * no longer connected, the host registers can't be
 433                          * written to halt the channel since the core is in
 434                          * device mode.
 435                          */
 436                         dwc2_hc_halt(hsotg, qh->channel,
 437                                      DWC2_HC_XFER_URB_DEQUEUE);
 438         }
 439
 440         /*
 441          * Free the QTD and clean up the associated QH. Leave the QH in the
 442          * schedule if it has any remaining QTDs.
 443          */
 444         if (hsotg->core_params->dma_desc_enable <= 0) {
 445                 u8 in_process = urb_qtd->in_process;
 446
 447                 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
 448                 if (in_process) {
 449                         dwc2_hcd_qh_deactivate(hsotg, qh, 0);
 450                         qh->channel = NULL;
 451                 } else if (list_empty(&qh->qtd_list)) {
 452                         dwc2_hcd_qh_unlink(hsotg, qh);
 453                 }
 454         } else {
 455                 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
 456         }
 457
 458         return 0;
 459 }
 460
 461 /* Must NOT be called with interrupt disabled or spinlock held */
 462 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
 463                                      struct usb_host_endpoint *ep, int retry)
 464 {
 465         struct dwc2_qtd *qtd, *qtd_tmp;
 466         struct dwc2_qh *qh;
 467         unsigned long flags;
 468         int rc;
 469
 470         spin_lock_irqsave(&hsotg->lock, flags);
 471
 472         qh = ep->hcpriv;
 473         if (!qh) {
 474                 rc = -EINVAL;
 475                 goto err;
 476         }
 477
 478         while (!list_empty(&qh->qtd_list) && retry--) {
 479                 if (retry == 0) {
 480                         dev_err(hsotg->dev,
 481                                 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
 482                         rc = -EBUSY;
 483                         goto err;
 484                 }
 485
 486                 spin_unlock_irqrestore(&hsotg->lock, flags);
 487                 usleep_range(20000, 40000);
 488                 spin_lock_irqsave(&hsotg->lock, flags);
 489                 qh = ep->hcpriv;
 490                 if (!qh) {
 491                         rc = -EINVAL;
 492                         goto err;
 493                 }
 494         }
 495
 496         dwc2_hcd_qh_unlink(hsotg, qh);
 497
 498         /* Free each QTD in the QH's QTD list */
 499         list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
 500                 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 501
 502         ep->hcpriv = NULL;
 503         spin_unlock_irqrestore(&hsotg->lock, flags);
 504         dwc2_hcd_qh_free(hsotg, qh);
 505
 506         return 0;
 507
 508 err:
 509         ep->hcpriv = NULL;
 510         spin_unlock_irqrestore(&hsotg->lock, flags);
 511
 512         return rc;
 513 }
 514
 515 /* Must be called with interrupt disabled and spinlock held */
 516 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
 517                                    struct usb_host_endpoint *ep)
 518 {
 519         struct dwc2_qh *qh = ep->hcpriv;
 520
 521         if (!qh)
 522                 return -EINVAL;
 523
 524         qh->data_toggle = DWC2_HC_PID_DATA0;
 525
 526         return 0;
 527 }
 528
 529 /*
 530  * Initializes dynamic portions of the DWC_otg HCD state
 531  *
 532  * Must be called with interrupt disabled and spinlock held
 533  */
 534 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
 535 {
 536         struct dwc2_host_chan *chan, *chan_tmp;
 537         int num_channels;
 538         int i;
 539
 540         hsotg->flags.d32 = 0;
 541
 542         hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
 543         hsotg->non_periodic_channels = 0;
 544         hsotg->periodic_channels = 0;
 545
 546         /*
 547          * Put all channels in the free channel list and clean up channel
 548          * states
 549          */
 550         list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
 551                                  hc_list_entry)
 552                 list_del_init(&chan->hc_list_entry);
 553
 554         num_channels = hsotg->core_params->host_channels;
 555         for (i = 0; i < num_channels; i++) {
 556                 chan = hsotg->hc_ptr_array[i];
 557                 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
 558                 dwc2_hc_cleanup(hsotg, chan);
 559         }
 560
 561         /* Initialize the DWC core for host mode operation */
 562         dwc2_core_host_init(hsotg);
 563 }
 564
 565 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
 566                                struct dwc2_host_chan *chan,
 567                                struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
 568 {
 569         int hub_addr, hub_port;
 570
 571         chan->do_split = 1;
 572         chan->xact_pos = qtd->isoc_split_pos;
 573         chan->complete_split = qtd->complete_split;
 574         dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
 575         chan->hub_addr = (u8)hub_addr;
 576         chan->hub_port = (u8)hub_port;
 577 }
 578
 579 static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
 580                                struct dwc2_host_chan *chan,
 581                                struct dwc2_qtd *qtd, void *bufptr)
 582 {
 583         struct dwc2_hcd_urb *urb = qtd->urb;
 584         struct dwc2_hcd_iso_packet_desc *frame_desc;
 585
 586         switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
 587         case USB_ENDPOINT_XFER_CONTROL:
 588                 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
 589
 590                 switch (qtd->control_phase) {
 591                 case DWC2_CONTROL_SETUP:
 592                         dev_vdbg(hsotg->dev, "  Control setup transaction\n");
 593                         chan->do_ping = 0;
 594                         chan->ep_is_in = 0;
 595                         chan->data_pid_start = DWC2_HC_PID_SETUP;
 596                         if (hsotg->core_params->dma_enable > 0)
 597                                 chan->xfer_dma = urb->setup_dma;
 598                         else
 599                                 chan->xfer_buf = urb->setup_packet;
 600                         chan->xfer_len = 8;
 601                         bufptr = NULL;
 602                         break;
 603
 604                 case DWC2_CONTROL_DATA:
 605                         dev_vdbg(hsotg->dev, "  Control data transaction\n");
 606                         chan->data_pid_start = qtd->data_toggle;
 607                         break;
 608
 609                 case DWC2_CONTROL_STATUS:
 610                         /*
 611                          * Direction is opposite of data direction or IN if no
 612                          * data
 613                          */
 614                         dev_vdbg(hsotg->dev, "  Control status transaction\n");
 615                         if (urb->length == 0)
 616                                 chan->ep_is_in = 1;
 617                         else
 618                                 chan->ep_is_in =
 619                                         dwc2_hcd_is_pipe_out(&urb->pipe_info);
 620                         if (chan->ep_is_in)
 621                                 chan->do_ping = 0;
 622                         chan->data_pid_start = DWC2_HC_PID_DATA1;
 623                         chan->xfer_len = 0;
 624                         if (hsotg->core_params->dma_enable > 0)
 625                                 chan->xfer_dma = hsotg->status_buf_dma;
 626                         else
 627                                 chan->xfer_buf = hsotg->status_buf;
 628                         bufptr = NULL;
 629                         break;
 630                 }
 631                 break;
 632
 633         case USB_ENDPOINT_XFER_BULK:
 634                 chan->ep_type = USB_ENDPOINT_XFER_BULK;
 635                 break;
 636
 637         case USB_ENDPOINT_XFER_INT:
 638                 chan->ep_type = USB_ENDPOINT_XFER_INT;
 639                 break;
 640
 641         case USB_ENDPOINT_XFER_ISOC:
 642                 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
 643                 if (hsotg->core_params->dma_desc_enable > 0)
 644                         break;
 645
 646                 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
 647                 frame_desc->status = 0;
 648
 649                 if (hsotg->core_params->dma_enable > 0) {
 650                         chan->xfer_dma = urb->dma;
 651                         chan->xfer_dma += frame_desc->offset +
 652                                         qtd->isoc_split_offset;
 653                 } else {
 654                         chan->xfer_buf = urb->buf;
 655                         chan->xfer_buf += frame_desc->offset +
 656                                         qtd->isoc_split_offset;
 657                 }
 658
 659                 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
 660
 661                 /* For non-dword aligned buffers */
 662                 if (hsotg->core_params->dma_enable > 0 &&
 663                     (chan->xfer_dma & 0x3))
 664                         bufptr = (u8 *)urb->buf + frame_desc->offset +
 665                                         qtd->isoc_split_offset;
 666                 else
 667                         bufptr = NULL;
 668
 669                 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
 670                         if (chan->xfer_len <= 188)
 671                                 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
 672                         else
 673                                 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
 674                 }
 675                 break;
 676         }
 677
 678         return bufptr;
 679 }
 680
 681 static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
 682                                    struct dwc2_host_chan *chan, void *bufptr)
 683 {
 684         u32 buf_size;
 685
 686         if (chan->ep_type != USB_ENDPOINT_XFER_ISOC)
 687                 buf_size = hsotg->core_params->max_transfer_size;
 688         else
 689                 buf_size = 4096;
 690
 691         if (!qh->dw_align_buf) {
 692                 qh->dw_align_buf = dma_alloc_coherent(hsotg->dev, buf_size,
 693                                                       &qh->dw_align_buf_dma,
 694                                                       GFP_ATOMIC);
 695                 if (!qh->dw_align_buf)
 696                         return -ENOMEM;
 697         }
 698
 699         if (!chan->ep_is_in && chan->xfer_len) {
 700                 dma_sync_single_for_cpu(hsotg->dev, chan->xfer_dma, buf_size,
 701                                         DMA_TO_DEVICE);
 702                 memcpy(qh->dw_align_buf, bufptr, chan->xfer_len);
 703                 dma_sync_single_for_device(hsotg->dev, chan->xfer_dma, buf_size,
 704                                            DMA_TO_DEVICE);
 705         }
 706
 707         chan->align_buf = qh->dw_align_buf_dma;
 708         return 0;
 709 }
 710
 711 /**
 712  * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
 713  * channel and initializes the host channel to perform the transactions. The
 714  * host channel is removed from the free list.
 715  *
 716  * @hsotg: The HCD state structure
 717  * @qh:    Transactions from the first QTD for this QH are selected and assigned
 718  *         to a free host channel
 719  */
 720 static void dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg,
 721                                     struct dwc2_qh *qh)
 722 {
 723         struct dwc2_host_chan *chan;
 724         struct dwc2_hcd_urb *urb;
 725         struct dwc2_qtd *qtd;
 726         void *bufptr = NULL;
 727
 728         if (dbg_qh(qh))
 729                 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
 730
 731         if (list_empty(&qh->qtd_list)) {
 732                 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
 733                 return;
 734         }
 735
 736         if (list_empty(&hsotg->free_hc_list)) {
 737                 dev_dbg(hsotg->dev, "No free channel to assign\n");
 738                 return;
 739         }
 740
 741         chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
 742                                 hc_list_entry);
 743
 744         /* Remove the host channel from the free list */
 745         list_del_init(&chan->hc_list_entry);
 746
 747         qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
 748         urb = qtd->urb;
 749         qh->channel = chan;
 750         qtd->in_process = 1;
 751
 752         /*
 753          * Use usb_pipedevice to determine device address. This address is
 754          * 0 before the SET_ADDRESS command and the correct address afterward.
 755          */
 756         chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
 757         chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
 758         chan->speed = qh->dev_speed;
 759         chan->max_packet = dwc2_max_packet(qh->maxp);
 760
 761         chan->xfer_started = 0;
 762         chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
 763         chan->error_state = (qtd->error_count > 0);
 764         chan->halt_on_queue = 0;
 765         chan->halt_pending = 0;
 766         chan->requests = 0;
 767
 768         /*
 769          * The following values may be modified in the transfer type section
 770          * below. The xfer_len value may be reduced when the transfer is
 771          * started to accommodate the max widths of the XferSize and PktCnt
 772          * fields in the HCTSIZn register.
 773          */
 774
 775         chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
 776         if (chan->ep_is_in)
 777                 chan->do_ping = 0;
 778         else
 779                 chan->do_ping = qh->ping_state;
 780
 781         chan->data_pid_start = qh->data_toggle;
 782         chan->multi_count = 1;
 783
 784         if (hsotg->core_params->dma_enable > 0) {
 785                 chan->xfer_dma = urb->dma + urb->actual_length;
 786
 787                 /* For non-dword aligned case */
 788                 if (hsotg->core_params->dma_desc_enable <= 0 &&
 789                     (chan->xfer_dma & 0x3))
 790                         bufptr = (u8 *)urb->buf + urb->actual_length;
 791         } else {
 792                 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
 793         }
 794
 795         chan->xfer_len = urb->length - urb->actual_length;
 796         chan->xfer_count = 0;
 797
 798         /* Set the split attributes if required */
 799         if (qh->do_split)
 800                 dwc2_hc_init_split(hsotg, chan, qtd, urb);
 801         else
 802                 chan->do_split = 0;
 803
 804         /* Set the transfer attributes */
 805         bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, bufptr);
 806
 807         /* Non DWORD-aligned buffer case */
 808         if (bufptr) {
 809                 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
 810                 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, bufptr)) {
 811                         dev_err(hsotg->dev,
 812                                 "%s: Failed to allocate memory to handle non-dword aligned buffer\n",
 813                                 __func__);
 814                         /* Add channel back to free list */
 815                         chan->align_buf = 0;
 816                         chan->multi_count = 0;
 817                         list_add_tail(&chan->hc_list_entry,
 818                                       &hsotg->free_hc_list);
 819                         qtd->in_process = 0;
 820                         qh->channel = NULL;
 821                         return;
 822                 }
 823         } else {
 824                 chan->align_buf = 0;
 825         }
 826
 827         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
 828             chan->ep_type == USB_ENDPOINT_XFER_ISOC)
 829                 /*
 830                  * This value may be modified when the transfer is started
 831                  * to reflect the actual transfer length
 832                  */
 833                 chan->multi_count = dwc2_hb_mult(qh->maxp);
 834
 835         if (hsotg->core_params->dma_desc_enable > 0)
 836                 chan->desc_list_addr = qh->desc_list_dma;
 837
 838         dwc2_hc_init(hsotg, chan);
 839         chan->qh = qh;
 840 }
 841
 842 /**
 843  * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
 844  * schedule and assigns them to available host channels. Called from the HCD
 845  * interrupt handler functions.
 846  *
 847  * @hsotg: The HCD state structure
 848  *
 849  * Return: The types of new transactions that were assigned to host channels
 850  */
 851 enum dwc2_transaction_type dwc2_hcd_select_transactions(
 852                 struct dwc2_hsotg *hsotg)
 853 {
 854         enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
 855         struct list_head *qh_ptr;
 856         struct dwc2_qh *qh;
 857         int num_channels;
 858
 859 #ifdef DWC2_DEBUG_SOF
 860         dev_vdbg(hsotg->dev, "  Select Transactions\n");
 861 #endif
 862
 863         /* Process entries in the periodic ready list */
 864         qh_ptr = hsotg->periodic_sched_ready.next;
 865         while (qh_ptr != &hsotg->periodic_sched_ready) {
 866                 if (list_empty(&hsotg->free_hc_list))
 867                         break;
 868                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
 869                 dwc2_assign_and_init_hc(hsotg, qh);
 870
 871                 /*
 872                  * Move the QH from the periodic ready schedule to the
 873                  * periodic assigned schedule
 874                  */
 875                 qh_ptr = qh_ptr->next;
 876                 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned);
 877                 ret_val = DWC2_TRANSACTION_PERIODIC;
 878         }
 879
 880         /*
 881          * Process entries in the inactive portion of the non-periodic
 882          * schedule. Some free host channels may not be used if they are
 883          * reserved for periodic transfers.
 884          */
 885         num_channels = hsotg->core_params->host_channels;
 886         qh_ptr = hsotg->non_periodic_sched_inactive.next;
 887         while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
 888                 if (hsotg->non_periodic_channels >= num_channels -
 889                                                 hsotg->periodic_channels)
 890                         break;
 891                 if (list_empty(&hsotg->free_hc_list))
 892                         break;
 893                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
 894                 dwc2_assign_and_init_hc(hsotg, qh);
 895
 896                 /*
 897                  * Move the QH from the non-periodic inactive schedule to the
 898                  * non-periodic active schedule
 899                  */
 900                 qh_ptr = qh_ptr->next;
 901                 list_move(&qh->qh_list_entry,
 902                           &hsotg->non_periodic_sched_active);
 903
 904                 if (ret_val == DWC2_TRANSACTION_NONE)
 905                         ret_val = DWC2_TRANSACTION_NON_PERIODIC;
 906                 else
 907                         ret_val = DWC2_TRANSACTION_ALL;
 908
 909                 hsotg->non_periodic_channels++;
 910         }
 911
 912         return ret_val;
 913 }
 914
 915 /**
 916  * dwc2_queue_transaction() - Attempts to queue a single transaction request for
 917  * a host channel associated with either a periodic or non-periodic transfer
 918  *
 919  * @hsotg: The HCD state structure
 920  * @chan:  Host channel descriptor associated with either a periodic or
 921  *         non-periodic transfer
 922  * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
 923  *                     for periodic transfers or the non-periodic Tx FIFO
 924  *                     for non-periodic transfers
 925  *
 926  * Return: 1 if a request is queued and more requests may be needed to
 927  * complete the transfer, 0 if no more requests are required for this
 928  * transfer, -1 if there is insufficient space in the Tx FIFO
 929  *
 930  * This function assumes that there is space available in the appropriate
 931  * request queue. For an OUT transfer or SETUP transaction in Slave mode,
 932  * it checks whether space is available in the appropriate Tx FIFO.
 933  *
 934  * Must be called with interrupt disabled and spinlock held
 935  */
 936 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
 937                                   struct dwc2_host_chan *chan,
 938                                   u16 fifo_dwords_avail)
 939 {
 940         int retval = 0;
 941
 942         if (hsotg->core_params->dma_enable > 0) {
 943                 if (hsotg->core_params->dma_desc_enable > 0) {
 944                         if (!chan->xfer_started ||
 945                             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
 946                                 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
 947                                 chan->qh->ping_state = 0;
 948                         }
 949                 } else if (!chan->xfer_started) {
 950                         dwc2_hc_start_transfer(hsotg, chan);
 951                         chan->qh->ping_state = 0;
 952                 }
 953         } else if (chan->halt_pending) {
 954                 /* Don't queue a request if the channel has been halted */
 955         } else if (chan->halt_on_queue) {
 956                 dwc2_hc_halt(hsotg, chan, chan->halt_status);
 957         } else if (chan->do_ping) {
 958                 if (!chan->xfer_started)
 959                         dwc2_hc_start_transfer(hsotg, chan);
 960         } else if (!chan->ep_is_in ||
 961                    chan->data_pid_start == DWC2_HC_PID_SETUP) {
 962                 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
 963                         if (!chan->xfer_started) {
 964                                 dwc2_hc_start_transfer(hsotg, chan);
 965                                 retval = 1;
 966                         } else {
 967                                 retval = dwc2_hc_continue_transfer(hsotg, chan);
 968                         }
 969                 } else {
 970                         retval = -1;
 971                 }
 972         } else {
 973                 if (!chan->xfer_started) {
 974                         dwc2_hc_start_transfer(hsotg, chan);
 975                         retval = 1;
 976                 } else {
 977                         retval = dwc2_hc_continue_transfer(hsotg, chan);
 978                 }
 979         }
 980
 981         return retval;
 982 }
 983
 984 /*
 985  * Processes periodic channels for the next frame and queues transactions for
 986  * these channels to the DWC_otg controller. After queueing transactions, the
 987  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
 988  * to queue as Periodic Tx FIFO or request queue space becomes available.
 989  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
 990  *
 991  * Must be called with interrupt disabled and spinlock held
 992  */
 993 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
 994 {
 995         struct list_head *qh_ptr;
 996         struct dwc2_qh *qh;
 997         u32 tx_status;
 998         u32 fspcavail;
 999         u32 gintmsk;
1000         int status;
1001         int no_queue_space = 0;
1002         int no_fifo_space = 0;
1003         u32 qspcavail;
1004
1005         if (dbg_perio())
1006                 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
1007
1008         tx_status = readl(hsotg->regs + HPTXSTS);
1009         qspcavail = tx_status >> TXSTS_QSPCAVAIL_SHIFT &
1010                     TXSTS_QSPCAVAIL_MASK >> TXSTS_QSPCAVAIL_SHIFT;
1011         fspcavail = tx_status >> TXSTS_FSPCAVAIL_SHIFT &
1012                     TXSTS_FSPCAVAIL_MASK >> TXSTS_FSPCAVAIL_SHIFT;
1013
1014         if (dbg_perio()) {
1015                 dev_vdbg(hsotg->dev, "  P Tx Req Queue Space Avail (before queue): %d\n",
1016                          qspcavail);
1017                 dev_vdbg(hsotg->dev, "  P Tx FIFO Space Avail (before queue): %d\n",
1018                          fspcavail);
1019         }
1020
1021         qh_ptr = hsotg->periodic_sched_assigned.next;
1022         while (qh_ptr != &hsotg->periodic_sched_assigned) {
1023                 tx_status = readl(hsotg->regs + HPTXSTS);
1024                 if ((tx_status & TXSTS_QSPCAVAIL_MASK) == 0) {
1025                         no_queue_space = 1;
1026                         break;
1027                 }
1028
1029                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
1030                 if (!qh->channel) {
1031                         qh_ptr = qh_ptr->next;
1032                         continue;
1033                 }
1034
1035                 /* Make sure EP's TT buffer is clean before queueing qtds */
1036                 if (qh->tt_buffer_dirty) {
1037                         qh_ptr = qh_ptr->next;
1038                         continue;
1039                 }
1040
1041                 /*
1042                  * Set a flag if we're queuing high-bandwidth in slave mode.
1043                  * The flag prevents any halts to get into the request queue in
1044                  * the middle of multiple high-bandwidth packets getting queued.
1045                  */
1046                 if (hsotg->core_params->dma_enable <= 0 &&
1047                                 qh->channel->multi_count > 1)
1048                         hsotg->queuing_high_bandwidth = 1;
1049
1050                 fspcavail = tx_status >> TXSTS_FSPCAVAIL_SHIFT &
1051                             TXSTS_FSPCAVAIL_MASK >> TXSTS_FSPCAVAIL_SHIFT;
1052                 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1053                 if (status < 0) {
1054                         no_fifo_space = 1;
1055                         break;
1056                 }
1057
1058                 /*
1059                  * In Slave mode, stay on the current transfer until there is
1060                  * nothing more to do or the high-bandwidth request count is
1061                  * reached. In DMA mode, only need to queue one request. The
1062                  * controller automatically handles multiple packets for
1063                  * high-bandwidth transfers.
1064                  */
1065                 if (hsotg->core_params->dma_enable > 0 || status == 0 ||
1066                     qh->channel->requests == qh->channel->multi_count) {
1067                         qh_ptr = qh_ptr->next;
1068                         /*
1069                          * Move the QH from the periodic assigned schedule to
1070                          * the periodic queued schedule
1071                          */
1072                         list_move(&qh->qh_list_entry,
1073                                   &hsotg->periodic_sched_queued);
1074
1075                         /* done queuing high bandwidth */
1076                         hsotg->queuing_high_bandwidth = 0;
1077                 }
1078         }
1079
1080         if (hsotg->core_params->dma_enable <= 0) {
1081                 tx_status = readl(hsotg->regs + HPTXSTS);
1082                 qspcavail = tx_status >> TXSTS_QSPCAVAIL_SHIFT &
1083                             TXSTS_QSPCAVAIL_MASK >> TXSTS_QSPCAVAIL_SHIFT;
1084                 fspcavail = tx_status >> TXSTS_FSPCAVAIL_SHIFT &
1085                             TXSTS_FSPCAVAIL_MASK >> TXSTS_FSPCAVAIL_SHIFT;
1086                 if (dbg_perio()) {
1087                         dev_vdbg(hsotg->dev,
1088                                  "  P Tx Req Queue Space Avail (after queue): %d\n",
1089                                  qspcavail);
1090                         dev_vdbg(hsotg->dev,
1091                                  "  P Tx FIFO Space Avail (after queue): %d\n",
1092                                  fspcavail);
1093                 }
1094
1095                 if (!list_empty(&hsotg->periodic_sched_assigned) ||
1096                     no_queue_space || no_fifo_space) {
1097                         /*
1098                          * May need to queue more transactions as the request
1099                          * queue or Tx FIFO empties. Enable the periodic Tx
1100                          * FIFO empty interrupt. (Always use the half-empty
1101                          * level to ensure that new requests are loaded as
1102                          * soon as possible.)
1103                          */
1104                         gintmsk = readl(hsotg->regs + GINTMSK);
1105                         gintmsk |= GINTSTS_PTXFEMP;
1106                         writel(gintmsk, hsotg->regs + GINTMSK);
1107                 } else {
1108                         /*
1109                          * Disable the Tx FIFO empty interrupt since there are
1110                          * no more transactions that need to be queued right
1111                          * now. This function is called from interrupt
1112                          * handlers to queue more transactions as transfer
1113                          * states change.
1114                          */
1115                         gintmsk = readl(hsotg->regs + GINTMSK);
1116                         gintmsk &= ~GINTSTS_PTXFEMP;
1117                         writel(gintmsk, hsotg->regs + GINTMSK);
1118                 }
1119         }
1120 }
1121
1122 /*
1123  * Processes active non-periodic channels and queues transactions for these
1124  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1125  * FIFO Empty interrupt is enabled if there are more transactions to queue as
1126  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1127  * FIFO Empty interrupt is disabled.
1128  *
1129  * Must be called with interrupt disabled and spinlock held
1130  */
1131 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
1132 {
1133         struct list_head *orig_qh_ptr;
1134         struct dwc2_qh *qh;
1135         u32 tx_status;
1136         u32 qspcavail;
1137         u32 fspcavail;
1138         u32 gintmsk;
1139         int status;
1140         int no_queue_space = 0;
1141         int no_fifo_space = 0;
1142         int more_to_do = 0;
1143
1144         dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
1145
1146         tx_status = readl(hsotg->regs + GNPTXSTS);
1147         qspcavail = tx_status >> TXSTS_QSPCAVAIL_SHIFT &
1148                     TXSTS_QSPCAVAIL_MASK >> TXSTS_QSPCAVAIL_SHIFT;
1149         fspcavail = tx_status >> TXSTS_FSPCAVAIL_SHIFT &
1150                     TXSTS_FSPCAVAIL_MASK >> TXSTS_FSPCAVAIL_SHIFT;
1151         dev_vdbg(hsotg->dev, "  NP Tx Req Queue Space Avail (before queue): %d\n",
1152                  qspcavail);
1153         dev_vdbg(hsotg->dev, "  NP Tx FIFO Space Avail (before queue): %d\n",
1154                  fspcavail);
1155
1156         /*
1157          * Keep track of the starting point. Skip over the start-of-list
1158          * entry.
1159          */
1160         if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
1161                 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1162         orig_qh_ptr = hsotg->non_periodic_qh_ptr;
1163
1164         /*
1165          * Process once through the active list or until no more space is
1166          * available in the request queue or the Tx FIFO
1167          */
1168         do {
1169                 tx_status = readl(hsotg->regs + GNPTXSTS);
1170                 qspcavail = tx_status >> TXSTS_QSPCAVAIL_SHIFT &
1171                             TXSTS_QSPCAVAIL_MASK >> TXSTS_QSPCAVAIL_SHIFT;
1172                 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {
1173                         no_queue_space = 1;
1174                         break;
1175                 }
1176
1177                 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
1178                                 qh_list_entry);
1179                 if (!qh->channel)
1180                         goto next;
1181
1182                 /* Make sure EP's TT buffer is clean before queueing qtds */
1183                 if (qh->tt_buffer_dirty)
1184                         goto next;
1185
1186                 fspcavail = tx_status >> TXSTS_FSPCAVAIL_SHIFT &
1187                             TXSTS_FSPCAVAIL_MASK >> TXSTS_FSPCAVAIL_SHIFT;
1188                 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1189
1190                 if (status > 0) {
1191                         more_to_do = 1;
1192                 } else if (status < 0) {
1193                         no_fifo_space = 1;
1194                         break;
1195                 }
1196 next:
1197                 /* Advance to next QH, skipping start-of-list entry */
1198                 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1199                 if (hsotg->non_periodic_qh_ptr ==
1200                                 &hsotg->non_periodic_sched_active)
1201                         hsotg->non_periodic_qh_ptr =
1202                                         hsotg->non_periodic_qh_ptr->next;
1203         } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
1204
1205         if (hsotg->core_params->dma_enable <= 0) {
1206                 tx_status = readl(hsotg->regs + GNPTXSTS);
1207                 qspcavail = tx_status >> TXSTS_QSPCAVAIL_SHIFT &
1208                             TXSTS_QSPCAVAIL_MASK >> TXSTS_QSPCAVAIL_SHIFT;
1209                 fspcavail = tx_status >> TXSTS_FSPCAVAIL_SHIFT &
1210                             TXSTS_FSPCAVAIL_MASK >> TXSTS_FSPCAVAIL_SHIFT;
1211                 dev_vdbg(hsotg->dev,
1212                          "  NP Tx Req Queue Space Avail (after queue): %d\n",
1213                          qspcavail);
1214                 dev_vdbg(hsotg->dev,
1215                          "  NP Tx FIFO Space Avail (after queue): %d\n",
1216                          fspcavail);
1217
1218                 if (more_to_do || no_queue_space || no_fifo_space) {
1219                         /*
1220                          * May need to queue more transactions as the request
1221                          * queue or Tx FIFO empties. Enable the non-periodic
1222                          * Tx FIFO empty interrupt. (Always use the half-empty
1223                          * level to ensure that new requests are loaded as
1224                          * soon as possible.)
1225                          */
1226                         gintmsk = readl(hsotg->regs + GINTMSK);
1227                         gintmsk |= GINTSTS_NPTXFEMP;
1228                         writel(gintmsk, hsotg->regs + GINTMSK);
1229                 } else {
1230                         /*
1231                          * Disable the Tx FIFO empty interrupt since there are
1232                          * no more transactions that need to be queued right
1233                          * now. This function is called from interrupt
1234                          * handlers to queue more transactions as transfer
1235                          * states change.
1236                          */
1237                         gintmsk = readl(hsotg->regs + GINTMSK);
1238                         gintmsk &= ~GINTSTS_NPTXFEMP;
1239                         writel(gintmsk, hsotg->regs + GINTMSK);
1240                 }
1241         }
1242 }
1243
1244 /**
1245  * dwc2_hcd_queue_transactions() - Processes the currently active host channels
1246  * and queues transactions for these channels to the DWC_otg controller. Called
1247  * from the HCD interrupt handler functions.
1248  *
1249  * @hsotg:   The HCD state structure
1250  * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
1251  *           or both)
1252  *
1253  * Must be called with interrupt disabled and spinlock held
1254  */
1255 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
1256                                  enum dwc2_transaction_type tr_type)
1257 {
1258 #ifdef DWC2_DEBUG_SOF
1259         dev_vdbg(hsotg->dev, "Queue Transactions\n");
1260 #endif
1261         /* Process host channels associated with periodic transfers */
1262         if ((tr_type == DWC2_TRANSACTION_PERIODIC ||
1263              tr_type == DWC2_TRANSACTION_ALL) &&
1264             !list_empty(&hsotg->periodic_sched_assigned))
1265                 dwc2_process_periodic_channels(hsotg);
1266
1267         /* Process host channels associated with non-periodic transfers */
1268         if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
1269             tr_type == DWC2_TRANSACTION_ALL) {
1270                 if (!list_empty(&hsotg->non_periodic_sched_active)) {
1271                         dwc2_process_non_periodic_channels(hsotg);
1272                 } else {
1273                         /*
1274                          * Ensure NP Tx FIFO empty interrupt is disabled when
1275                          * there are no non-periodic transfers to process
1276                          */
1277                         u32 gintmsk = readl(hsotg->regs + GINTMSK);
1278
1279                         gintmsk &= ~GINTSTS_NPTXFEMP;
1280                         writel(gintmsk, hsotg->regs + GINTMSK);
1281                 }
1282         }
1283 }
1284
1285 static void dwc2_conn_id_status_change(struct work_struct *work)
1286 {
1287         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
1288                                                 wf_otg);
1289         u32 count = 0;
1290         u32 gotgctl;
1291
1292         dev_dbg(hsotg->dev, "%s()\n", __func__);
1293
1294         gotgctl = readl(hsotg->regs + GOTGCTL);
1295         dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
1296         dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
1297                 !!(gotgctl & GOTGCTL_CONID_B));
1298
1299         /* B-Device connector (Device Mode) */
1300         if (gotgctl & GOTGCTL_CONID_B) {
1301                 /* Wait for switch to device mode */
1302                 dev_dbg(hsotg->dev, "connId B\n");
1303                 while (!dwc2_is_device_mode(hsotg)) {
1304                         dev_info(hsotg->dev,
1305                                  "Waiting for Peripheral Mode, Mode=%s\n",
1306                                  dwc2_is_host_mode(hsotg) ? "Host" :
1307                                  "Peripheral");
1308                         usleep_range(20000, 40000);
1309                         if (++count > 250)
1310                                 break;
1311                 }
1312                 if (count > 250)
1313                         dev_err(hsotg->dev,
1314                                 "Connection id status change timed out");
1315                 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
1316                 dwc2_core_init(hsotg, false, -1);
1317                 dwc2_enable_global_interrupts(hsotg);
1318         } else {
1319                 /* A-Device connector (Host Mode) */
1320                 dev_dbg(hsotg->dev, "connId A\n");
1321                 while (!dwc2_is_host_mode(hsotg)) {
1322                         dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
1323                                  dwc2_is_host_mode(hsotg) ?
1324                                  "Host" : "Peripheral");
1325                         usleep_range(20000, 40000);
1326                         if (++count > 250)
1327                                 break;
1328                 }
1329                 if (count > 250)
1330                         dev_err(hsotg->dev,
1331                                 "Connection id status change timed out");
1332                 hsotg->op_state = OTG_STATE_A_HOST;
1333
1334                 /* Initialize the Core for Host mode */
1335                 dwc2_core_init(hsotg, false, -1);
1336                 dwc2_enable_global_interrupts(hsotg);
1337                 dwc2_hcd_start(hsotg);
1338         }
1339 }
1340
1341 static void dwc2_wakeup_detected(unsigned long data)
1342 {
1343         struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data;
1344         u32 hprt0;
1345
1346         dev_dbg(hsotg->dev, "%s()\n", __func__);
1347
1348         /*
1349          * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
1350          * so that OPT tests pass with all PHYs.)
1351          */
1352         hprt0 = dwc2_read_hprt0(hsotg);
1353         dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
1354         hprt0 &= ~HPRT0_RES;
1355         writel(hprt0, hsotg->regs + HPRT0);
1356         dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
1357                 readl(hsotg->regs + HPRT0));
1358
1359         dwc2_hcd_rem_wakeup(hsotg);
1360
1361         /* Change to L0 state */
1362         hsotg->lx_state = DWC2_L0;
1363 }
1364
1365 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
1366 {
1367         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
1368
1369         return hcd->self.b_hnp_enable;
1370 }
1371
1372 /* Must NOT be called with interrupt disabled or spinlock held */
1373 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
1374 {
1375         unsigned long flags;
1376         u32 hprt0;
1377         u32 pcgctl;
1378         u32 gotgctl;
1379
1380         dev_dbg(hsotg->dev, "%s()\n", __func__);
1381
1382         spin_lock_irqsave(&hsotg->lock, flags);
1383
1384         if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
1385                 gotgctl = readl(hsotg->regs + GOTGCTL);
1386                 gotgctl |= GOTGCTL_HSTSETHNPEN;
1387                 writel(gotgctl, hsotg->regs + GOTGCTL);
1388                 hsotg->op_state = OTG_STATE_A_SUSPEND;
1389         }
1390
1391         hprt0 = dwc2_read_hprt0(hsotg);
1392         hprt0 |= HPRT0_SUSP;
1393         writel(hprt0, hsotg->regs + HPRT0);
1394
1395         /* Update lx_state */
1396         hsotg->lx_state = DWC2_L2;
1397
1398         /* Suspend the Phy Clock */
1399         pcgctl = readl(hsotg->regs + PCGCTL);
1400         pcgctl |= PCGCTL_STOPPCLK;
1401         writel(pcgctl, hsotg->regs + PCGCTL);
1402         udelay(10);
1403
1404         /* For HNP the bus must be suspended for at least 200ms */
1405         if (dwc2_host_is_b_hnp_enabled(hsotg)) {
1406                 pcgctl = readl(hsotg->regs + PCGCTL);
1407                 pcgctl &= ~PCGCTL_STOPPCLK;
1408                 writel(pcgctl, hsotg->regs + PCGCTL);
1409
1410                 spin_unlock_irqrestore(&hsotg->lock, flags);
1411
1412                 usleep_range(200000, 250000);
1413         } else {
1414                 spin_unlock_irqrestore(&hsotg->lock, flags);
1415         }
1416 }
1417
1418 /* Handles hub class-specific requests */
1419 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
1420                                 u16 wvalue, u16 windex, char *buf, u16 wlength)
1421 {
1422         struct usb_hub_descriptor *hub_desc;
1423         int retval = 0;
1424         u32 hprt0;
1425         u32 port_status;
1426         u32 speed;
1427         u32 pcgctl;
1428
1429         switch (typereq) {
1430         case ClearHubFeature:
1431                 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
1432
1433                 switch (wvalue) {
1434                 case C_HUB_LOCAL_POWER:
1435                 case C_HUB_OVER_CURRENT:
1436                         /* Nothing required here */
1437                         break;
1438
1439                 default:
1440                         retval = -EINVAL;
1441                         dev_err(hsotg->dev,
1442                                 "ClearHubFeature request %1xh unknown\n",
1443                                 wvalue);
1444                 }
1445                 break;
1446
1447         case ClearPortFeature:
1448                 if (wvalue != USB_PORT_FEAT_L1)
1449                         if (!windex || windex > 1)
1450                                 goto error;
1451                 switch (wvalue) {
1452                 case USB_PORT_FEAT_ENABLE:
1453                         dev_dbg(hsotg->dev,
1454                                 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
1455                         hprt0 = dwc2_read_hprt0(hsotg);
1456                         hprt0 |= HPRT0_ENA;
1457                         writel(hprt0, hsotg->regs + HPRT0);
1458                         break;
1459
1460                 case USB_PORT_FEAT_SUSPEND:
1461                         dev_dbg(hsotg->dev,
1462                                 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
1463                         writel(0, hsotg->regs + PCGCTL);
1464                         usleep_range(20000, 40000);
1465
1466                         hprt0 = dwc2_read_hprt0(hsotg);
1467                         hprt0 |= HPRT0_RES;
1468                         writel(hprt0, hsotg->regs + HPRT0);
1469                         hprt0 &= ~HPRT0_SUSP;
1470                         usleep_range(100000, 150000);
1471
1472                         hprt0 &= ~HPRT0_RES;
1473                         writel(hprt0, hsotg->regs + HPRT0);
1474                         break;
1475
1476                 case USB_PORT_FEAT_POWER:
1477                         dev_dbg(hsotg->dev,
1478                                 "ClearPortFeature USB_PORT_FEAT_POWER\n");
1479                         hprt0 = dwc2_read_hprt0(hsotg);
1480                         hprt0 &= ~HPRT0_PWR;
1481                         writel(hprt0, hsotg->regs + HPRT0);
1482                         break;
1483
1484                 case USB_PORT_FEAT_INDICATOR:
1485                         dev_dbg(hsotg->dev,
1486                                 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
1487                         /* Port indicator not supported */
1488                         break;
1489
1490                 case USB_PORT_FEAT_C_CONNECTION:
1491                         /*
1492                          * Clears driver's internal Connect Status Change flag
1493                          */
1494                         dev_dbg(hsotg->dev,
1495                                 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
1496                         hsotg->flags.b.port_connect_status_change = 0;
1497                         break;
1498
1499                 case USB_PORT_FEAT_C_RESET:
1500                         /* Clears driver's internal Port Reset Change flag */
1501                         dev_dbg(hsotg->dev,
1502                                 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
1503                         hsotg->flags.b.port_reset_change = 0;
1504                         break;
1505
1506                 case USB_PORT_FEAT_C_ENABLE:
1507                         /*
1508                          * Clears the driver's internal Port Enable/Disable
1509                          * Change flag
1510                          */
1511                         dev_dbg(hsotg->dev,
1512                                 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
1513                         hsotg->flags.b.port_enable_change = 0;
1514                         break;
1515
1516                 case USB_PORT_FEAT_C_SUSPEND:
1517                         /*
1518                          * Clears the driver's internal Port Suspend Change
1519                          * flag, which is set when resume signaling on the host
1520                          * port is complete
1521                          */
1522                         dev_dbg(hsotg->dev,
1523                                 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
1524                         hsotg->flags.b.port_suspend_change = 0;
1525                         break;
1526
1527                 case USB_PORT_FEAT_C_PORT_L1:
1528                         dev_dbg(hsotg->dev,
1529                                 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
1530                         hsotg->flags.b.port_l1_change = 0;
1531                         break;
1532
1533                 case USB_PORT_FEAT_C_OVER_CURRENT:
1534                         dev_dbg(hsotg->dev,
1535                                 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
1536                         hsotg->flags.b.port_over_current_change = 0;
1537                         break;
1538
1539                 default:
1540                         retval = -EINVAL;
1541                         dev_err(hsotg->dev,
1542                                 "ClearPortFeature request %1xh unknown or unsupported\n",
1543                                 wvalue);
1544                 }
1545                 break;
1546
1547         case GetHubDescriptor:
1548                 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
1549                 hub_desc = (struct usb_hub_descriptor *)buf;
1550                 hub_desc->bDescLength = 9;
1551                 hub_desc->bDescriptorType = 0x29;
1552                 hub_desc->bNbrPorts = 1;
1553                 hub_desc->wHubCharacteristics = cpu_to_le16(0x08);
1554                 hub_desc->bPwrOn2PwrGood = 1;
1555                 hub_desc->bHubContrCurrent = 0;
1556                 hub_desc->u.hs.DeviceRemovable[0] = 0;
1557                 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
1558                 break;
1559
1560         case GetHubStatus:
1561                 dev_dbg(hsotg->dev, "GetHubStatus\n");
1562                 memset(buf, 0, 4);
1563                 break;
1564
1565         case GetPortStatus:
1566                 dev_dbg(hsotg->dev,
1567                         "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
1568                         hsotg->flags.d32);
1569                 if (!windex || windex > 1)
1570                         goto error;
1571
1572                 port_status = 0;
1573                 if (hsotg->flags.b.port_connect_status_change)
1574                         port_status |= USB_PORT_STAT_C_CONNECTION << 16;
1575                 if (hsotg->flags.b.port_enable_change)
1576                         port_status |= USB_PORT_STAT_C_ENABLE << 16;
1577                 if (hsotg->flags.b.port_suspend_change)
1578                         port_status |= USB_PORT_STAT_C_SUSPEND << 16;
1579                 if (hsotg->flags.b.port_l1_change)
1580                         port_status |= USB_PORT_STAT_C_L1 << 16;
1581                 if (hsotg->flags.b.port_reset_change)
1582                         port_status |= USB_PORT_STAT_C_RESET << 16;
1583                 if (hsotg->flags.b.port_over_current_change) {
1584                         dev_warn(hsotg->dev, "Overcurrent change detected\n");
1585                         port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1586                 }
1587
1588                 if (!hsotg->flags.b.port_connect_status) {
1589                         /*
1590                          * The port is disconnected, which means the core is
1591                          * either in device mode or it soon will be. Just
1592                          * return 0's for the remainder of the port status
1593                          * since the port register can't be read if the core
1594                          * is in device mode.
1595                          */
1596                         *(__le32 *)buf = cpu_to_le32(port_status);
1597                         break;
1598                 }
1599
1600                 hprt0 = readl(hsotg->regs + HPRT0);
1601                 dev_dbg(hsotg->dev, "  HPRT0: 0x%08x\n", hprt0);
1602
1603                 if (hprt0 & HPRT0_CONNSTS)
1604                         port_status |= USB_PORT_STAT_CONNECTION;
1605                 if (hprt0 & HPRT0_ENA)
1606                         port_status |= USB_PORT_STAT_ENABLE;
1607                 if (hprt0 & HPRT0_SUSP)
1608                         port_status |= USB_PORT_STAT_SUSPEND;
1609                 if (hprt0 & HPRT0_OVRCURRACT)
1610                         port_status |= USB_PORT_STAT_OVERCURRENT;
1611                 if (hprt0 & HPRT0_RST)
1612                         port_status |= USB_PORT_STAT_RESET;
1613                 if (hprt0 & HPRT0_PWR)
1614                         port_status |= USB_PORT_STAT_POWER;
1615
1616                 speed = hprt0 & HPRT0_SPD_MASK;
1617                 if (speed == HPRT0_SPD_HIGH_SPEED)
1618                         port_status |= USB_PORT_STAT_HIGH_SPEED;
1619                 else if (speed == HPRT0_SPD_LOW_SPEED)
1620                         port_status |= USB_PORT_STAT_LOW_SPEED;
1621
1622                 if (hprt0 & HPRT0_TSTCTL_MASK)
1623                         port_status |= USB_PORT_STAT_TEST;
1624                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
1625
1626                 dev_dbg(hsotg->dev, "port_status=%08x\n", port_status);
1627                 *(__le32 *)buf = cpu_to_le32(port_status);
1628                 break;
1629
1630         case SetHubFeature:
1631                 dev_dbg(hsotg->dev, "SetHubFeature\n");
1632                 /* No HUB features supported */
1633                 break;
1634
1635         case SetPortFeature:
1636                 dev_dbg(hsotg->dev, "SetPortFeature\n");
1637                 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
1638                         goto error;
1639
1640                 if (!hsotg->flags.b.port_connect_status) {
1641                         /*
1642                          * The port is disconnected, which means the core is
1643                          * either in device mode or it soon will be. Just
1644                          * return without doing anything since the port
1645                          * register can't be written if the core is in device
1646                          * mode.
1647                          */
1648                         break;
1649                 }
1650
1651                 switch (wvalue) {
1652                 case USB_PORT_FEAT_SUSPEND:
1653                         dev_dbg(hsotg->dev,
1654                                 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
1655                         if (windex != hsotg->otg_port)
1656                                 goto error;
1657                         dwc2_port_suspend(hsotg, windex);
1658                         break;
1659
1660                 case USB_PORT_FEAT_POWER:
1661                         dev_dbg(hsotg->dev,
1662                                 "SetPortFeature - USB_PORT_FEAT_POWER\n");
1663                         hprt0 = dwc2_read_hprt0(hsotg);
1664                         hprt0 |= HPRT0_PWR;
1665                         writel(hprt0, hsotg->regs + HPRT0);
1666                         break;
1667
1668                 case USB_PORT_FEAT_RESET:
1669                         hprt0 = dwc2_read_hprt0(hsotg);
1670                         dev_dbg(hsotg->dev,
1671                                 "SetPortFeature - USB_PORT_FEAT_RESET\n");
1672                         pcgctl = readl(hsotg->regs + PCGCTL);
1673                         pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
1674                         writel(pcgctl, hsotg->regs + PCGCTL);
1675                         /* ??? Original driver does this */
1676                         writel(0, hsotg->regs + PCGCTL);
1677
1678                         hprt0 = dwc2_read_hprt0(hsotg);
1679                         /* Clear suspend bit if resetting from suspend state */
1680                         hprt0 &= ~HPRT0_SUSP;
1681
1682                         /*
1683                          * When B-Host the Port reset bit is set in the Start
1684                          * HCD Callback function, so that the reset is started
1685                          * within 1ms of the HNP success interrupt
1686                          */
1687                         if (!dwc2_hcd_is_b_host(hsotg)) {
1688                                 hprt0 |= HPRT0_PWR | HPRT0_RST;
1689                                 dev_dbg(hsotg->dev,
1690                                         "In host mode, hprt0=%08x\n", hprt0);
1691                                 writel(hprt0, hsotg->regs + HPRT0);
1692                         }
1693
1694                         /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
1695                         usleep_range(50000, 70000);
1696                         hprt0 &= ~HPRT0_RST;
1697                         writel(hprt0, hsotg->regs + HPRT0);
1698                         hsotg->lx_state = DWC2_L0; /* Now back to On state */
1699                         break;
1700
1701                 case USB_PORT_FEAT_INDICATOR:
1702                         dev_dbg(hsotg->dev,
1703                                 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
1704                         /* Not supported */
1705                         break;
1706
1707                 default:
1708                         retval = -EINVAL;
1709                         dev_err(hsotg->dev,
1710                                 "SetPortFeature %1xh unknown or unsupported\n",
1711                                 wvalue);
1712                         break;
1713                 }
1714                 break;
1715
1716         default:
1717 error:
1718                 retval = -EINVAL;
1719                 dev_dbg(hsotg->dev,
1720                         "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
1721                         typereq, windex, wvalue);
1722                 break;
1723         }
1724
1725         return retval;
1726 }
1727
1728 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
1729 {
1730         int retval;
1731
1732         if (port != 1)
1733                 return -EINVAL;
1734
1735         retval = (hsotg->flags.b.port_connect_status_change ||
1736                   hsotg->flags.b.port_reset_change ||
1737                   hsotg->flags.b.port_enable_change ||
1738                   hsotg->flags.b.port_suspend_change ||
1739                   hsotg->flags.b.port_over_current_change);
1740
1741         if (retval) {
1742                 dev_dbg(hsotg->dev,
1743                         "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
1744                 dev_dbg(hsotg->dev, "  port_connect_status_change: %d\n",
1745                         hsotg->flags.b.port_connect_status_change);
1746                 dev_dbg(hsotg->dev, "  port_reset_change: %d\n",
1747                         hsotg->flags.b.port_reset_change);
1748                 dev_dbg(hsotg->dev, "  port_enable_change: %d\n",
1749                         hsotg->flags.b.port_enable_change);
1750                 dev_dbg(hsotg->dev, "  port_suspend_change: %d\n",
1751                         hsotg->flags.b.port_suspend_change);
1752                 dev_dbg(hsotg->dev, "  port_over_current_change: %d\n",
1753                         hsotg->flags.b.port_over_current_change);
1754         }
1755
1756         return retval;
1757 }
1758
1759 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1760 {
1761         u32 hfnum = readl(hsotg->regs + HFNUM);
1762
1763 #ifdef DWC2_DEBUG_SOF
1764         dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
1765                  hfnum >> HFNUM_FRNUM_SHIFT &
1766                  HFNUM_FRNUM_MASK >> HFNUM_FRNUM_SHIFT);
1767 #endif
1768         return hfnum >> HFNUM_FRNUM_SHIFT &
1769                HFNUM_FRNUM_MASK >> HFNUM_FRNUM_SHIFT;
1770 }
1771
1772 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
1773 {
1774         return (hsotg->op_state == OTG_STATE_B_HOST);
1775 }
1776
1777 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
1778                                                int iso_desc_count,
1779                                                gfp_t mem_flags)
1780 {
1781         struct dwc2_hcd_urb *urb;
1782         u32 size = sizeof(*urb) + iso_desc_count *
1783                    sizeof(struct dwc2_hcd_iso_packet_desc);
1784
1785         urb = kzalloc(size, mem_flags);
1786         if (urb)
1787                 urb->packet_count = iso_desc_count;
1788         return urb;
1789 }
1790
1791 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
1792                                       struct dwc2_hcd_urb *urb, u8 dev_addr,
1793                                       u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
1794 {
1795         if (dbg_perio() ||
1796             ep_type == USB_ENDPOINT_XFER_BULK ||
1797             ep_type == USB_ENDPOINT_XFER_CONTROL)
1798                 dev_vdbg(hsotg->dev,
1799                          "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
1800                          dev_addr, ep_num, ep_dir, ep_type, mps);
1801         urb->pipe_info.dev_addr = dev_addr;
1802         urb->pipe_info.ep_num = ep_num;
1803         urb->pipe_info.pipe_type = ep_type;
1804         urb->pipe_info.pipe_dir = ep_dir;
1805         urb->pipe_info.mps = mps;
1806 }
1807
1808 /*
1809  * NOTE: This function will be removed once the peripheral controller code
1810  * is integrated and the driver is stable
1811  */
1812 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
1813 {
1814 #ifdef DEBUG
1815         struct dwc2_host_chan *chan;
1816         struct dwc2_hcd_urb *urb;
1817         struct dwc2_qtd *qtd;
1818         int num_channels;
1819         u32 np_tx_status;
1820         u32 p_tx_status;
1821         int i;
1822
1823         num_channels = hsotg->core_params->host_channels;
1824         dev_dbg(hsotg->dev, "\n");
1825         dev_dbg(hsotg->dev,
1826                 "************************************************************\n");
1827         dev_dbg(hsotg->dev, "HCD State:\n");
1828         dev_dbg(hsotg->dev, "  Num channels: %d\n", num_channels);
1829
1830         for (i = 0; i < num_channels; i++) {
1831                 chan = hsotg->hc_ptr_array[i];
1832                 dev_dbg(hsotg->dev, "  Channel %d:\n", i);
1833                 dev_dbg(hsotg->dev,
1834                         "    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
1835                         chan->dev_addr, chan->ep_num, chan->ep_is_in);
1836                 dev_dbg(hsotg->dev, "    speed: %d\n", chan->speed);
1837                 dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
1838                 dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
1839                 dev_dbg(hsotg->dev, "    data_pid_start: %d\n",
1840                         chan->data_pid_start);
1841                 dev_dbg(hsotg->dev, "    multi_count: %d\n", chan->multi_count);
1842                 dev_dbg(hsotg->dev, "    xfer_started: %d\n",
1843                         chan->xfer_started);
1844                 dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
1845                 dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
1846                         (unsigned long)chan->xfer_dma);
1847                 dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
1848                 dev_dbg(hsotg->dev, "    xfer_count: %d\n", chan->xfer_count);
1849                 dev_dbg(hsotg->dev, "    halt_on_queue: %d\n",
1850                         chan->halt_on_queue);
1851                 dev_dbg(hsotg->dev, "    halt_pending: %d\n",
1852                         chan->halt_pending);
1853                 dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
1854                 dev_dbg(hsotg->dev, "    do_split: %d\n", chan->do_split);
1855                 dev_dbg(hsotg->dev, "    complete_split: %d\n",
1856                         chan->complete_split);
1857                 dev_dbg(hsotg->dev, "    hub_addr: %d\n", chan->hub_addr);
1858                 dev_dbg(hsotg->dev, "    hub_port: %d\n", chan->hub_port);
1859                 dev_dbg(hsotg->dev, "    xact_pos: %d\n", chan->xact_pos);
1860                 dev_dbg(hsotg->dev, "    requests: %d\n", chan->requests);
1861                 dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
1862
1863                 if (chan->xfer_started) {
1864                         u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
1865
1866                         hfnum = readl(hsotg->regs + HFNUM);
1867                         hcchar = readl(hsotg->regs + HCCHAR(i));
1868                         hctsiz = readl(hsotg->regs + HCTSIZ(i));
1869                         hcint = readl(hsotg->regs + HCINT(i));
1870                         hcintmsk = readl(hsotg->regs + HCINTMSK(i));
1871                         dev_dbg(hsotg->dev, "    hfnum: 0x%08x\n", hfnum);
1872                         dev_dbg(hsotg->dev, "    hcchar: 0x%08x\n", hcchar);
1873                         dev_dbg(hsotg->dev, "    hctsiz: 0x%08x\n", hctsiz);
1874                         dev_dbg(hsotg->dev, "    hcint: 0x%08x\n", hcint);
1875                         dev_dbg(hsotg->dev, "    hcintmsk: 0x%08x\n", hcintmsk);
1876                 }
1877
1878                 if (!(chan->xfer_started && chan->qh))
1879                         continue;
1880
1881                 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
1882                         if (!qtd->in_process)
1883                                 break;
1884                         urb = qtd->urb;
1885                         dev_dbg(hsotg->dev, "    URB Info:\n");
1886                         dev_dbg(hsotg->dev, "      qtd: %p, urb: %p\n",
1887                                 qtd, urb);
1888                         if (urb) {
1889                                 dev_dbg(hsotg->dev,
1890                                         "      Dev: %d, EP: %d %s\n",
1891                                         dwc2_hcd_get_dev_addr(&urb->pipe_info),
1892                                         dwc2_hcd_get_ep_num(&urb->pipe_info),
1893                                         dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
1894                                         "IN" : "OUT");
1895                                 dev_dbg(hsotg->dev,
1896                                         "      Max packet size: %d\n",
1897                                         dwc2_hcd_get_mps(&urb->pipe_info));
1898                                 dev_dbg(hsotg->dev,
1899                                         "      transfer_buffer: %p\n",
1900                                         urb->buf);
1901                                 dev_dbg(hsotg->dev,
1902                                         "      transfer_dma: %08lx\n",
1903                                         (unsigned long)urb->dma);
1904                                 dev_dbg(hsotg->dev,
1905                                         "      transfer_buffer_length: %d\n",
1906                                         urb->length);
1907                                 dev_dbg(hsotg->dev, "      actual_length: %d\n",
1908                                         urb->actual_length);
1909                         }
1910                 }
1911         }
1912
1913         dev_dbg(hsotg->dev, "  non_periodic_channels: %d\n",
1914                 hsotg->non_periodic_channels);
1915         dev_dbg(hsotg->dev, "  periodic_channels: %d\n",
1916                 hsotg->periodic_channels);
1917         dev_dbg(hsotg->dev, "  periodic_usecs: %d\n", hsotg->periodic_usecs);
1918         np_tx_status = readl(hsotg->regs + GNPTXSTS);
1919         dev_dbg(hsotg->dev, "  NP Tx Req Queue Space Avail: %d\n",
1920                 np_tx_status >> TXSTS_QSPCAVAIL_SHIFT &
1921                 TXSTS_QSPCAVAIL_MASK >> TXSTS_QSPCAVAIL_SHIFT);
1922         dev_dbg(hsotg->dev, "  NP Tx FIFO Space Avail: %d\n",
1923                 np_tx_status >> TXSTS_FSPCAVAIL_SHIFT &
1924                 TXSTS_FSPCAVAIL_MASK >> TXSTS_FSPCAVAIL_SHIFT);
1925         p_tx_status = readl(hsotg->regs + HPTXSTS);
1926         dev_dbg(hsotg->dev, "  P Tx Req Queue Space Avail: %d\n",
1927                 p_tx_status >> TXSTS_QSPCAVAIL_SHIFT &
1928                 TXSTS_QSPCAVAIL_MASK >> TXSTS_QSPCAVAIL_SHIFT);
1929         dev_dbg(hsotg->dev, "  P Tx FIFO Space Avail: %d\n",
1930                 p_tx_status >> TXSTS_FSPCAVAIL_SHIFT &
1931                 TXSTS_FSPCAVAIL_MASK >> TXSTS_FSPCAVAIL_SHIFT);
1932         dwc2_hcd_dump_frrem(hsotg);
1933         dwc2_dump_global_registers(hsotg);
1934         dwc2_dump_host_registers(hsotg);
1935         dev_dbg(hsotg->dev,
1936                 "************************************************************\n");
1937         dev_dbg(hsotg->dev, "\n");
1938 #endif
1939 }
1940
1941 /*
1942  * NOTE: This function will be removed once the peripheral controller code
1943  * is integrated and the driver is stable
1944  */
1945 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
1946 {
1947 #ifdef DWC2_DUMP_FRREM
1948         dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
1949         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1950                 hsotg->frrem_samples, hsotg->frrem_accum,
1951                 hsotg->frrem_samples > 0 ?
1952                 hsotg->frrem_accum / hsotg->frrem_samples : 0);
1953         dev_dbg(hsotg->dev, "\n");
1954         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
1955         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1956                 hsotg->hfnum_7_samples,
1957                 hsotg->hfnum_7_frrem_accum,
1958                 hsotg->hfnum_7_samples > 0 ?
1959                 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
1960         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
1961         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1962                 hsotg->hfnum_0_samples,
1963                 hsotg->hfnum_0_frrem_accum,
1964                 hsotg->hfnum_0_samples > 0 ?
1965                 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
1966         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
1967         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1968                 hsotg->hfnum_other_samples,
1969                 hsotg->hfnum_other_frrem_accum,
1970                 hsotg->hfnum_other_samples > 0 ?
1971                 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
1972                 0);
1973         dev_dbg(hsotg->dev, "\n");
1974         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
1975         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1976                 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
1977                 hsotg->hfnum_7_samples_a > 0 ?
1978                 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
1979         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
1980         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1981                 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
1982                 hsotg->hfnum_0_samples_a > 0 ?
1983                 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
1984         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
1985         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1986                 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
1987                 hsotg->hfnum_other_samples_a > 0 ?
1988                 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
1989                 : 0);
1990         dev_dbg(hsotg->dev, "\n");
1991         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
1992         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1993                 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
1994                 hsotg->hfnum_7_samples_b > 0 ?
1995                 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
1996         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
1997         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1998                 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
1999                 (hsotg->hfnum_0_samples_b > 0) ?
2000                 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
2001         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
2002         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2003                 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
2004                 (hsotg->hfnum_other_samples_b > 0) ?
2005                 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
2006                 : 0);
2007 #endif
2008 }
2009
2010 struct wrapper_priv_data {
2011         struct dwc2_hsotg *hsotg;
2012 };
2013
2014 /* Gets the dwc2_hsotg from a usb_hcd */
2015 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
2016 {
2017         struct wrapper_priv_data *p;
2018
2019         p = (struct wrapper_priv_data *) &hcd->hcd_priv;
2020         return p->hsotg;
2021 }
2022
2023 static int _dwc2_hcd_start(struct usb_hcd *hcd);
2024
2025 void dwc2_host_start(struct dwc2_hsotg *hsotg)
2026 {
2027         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2028
2029         hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
2030         _dwc2_hcd_start(hcd);
2031 }
2032
2033 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
2034 {
2035         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2036
2037         hcd->self.is_b_host = 0;
2038 }
2039
2040 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
2041                         int *hub_port)
2042 {
2043         struct urb *urb = context;
2044
2045         if (urb->dev->tt)
2046                 *hub_addr = urb->dev->tt->hub->devnum;
2047         else
2048                 *hub_addr = 0;
2049         *hub_port = urb->dev->ttport;
2050 }
2051
2052 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
2053 {
2054         struct urb *urb = context;
2055
2056         return urb->dev->speed;
2057 }
2058
2059 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2060                                         struct urb *urb)
2061 {
2062         struct usb_bus *bus = hcd_to_bus(hcd);
2063
2064         if (urb->interval)
2065                 bus->bandwidth_allocated += bw / urb->interval;
2066         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2067                 bus->bandwidth_isoc_reqs++;
2068         else
2069                 bus->bandwidth_int_reqs++;
2070 }
2071
2072 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2073                                     struct urb *urb)
2074 {
2075         struct usb_bus *bus = hcd_to_bus(hcd);
2076
2077         if (urb->interval)
2078                 bus->bandwidth_allocated -= bw / urb->interval;
2079         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2080                 bus->bandwidth_isoc_reqs--;
2081         else
2082                 bus->bandwidth_int_reqs--;
2083 }
2084
2085 /*
2086  * Sets the final status of an URB and returns it to the upper layer. Any
2087  * required cleanup of the URB is performed.
2088  *
2089  * Must be called with interrupt disabled and spinlock held
2090  */
2091 void dwc2_host_complete(struct dwc2_hsotg *hsotg, void *context,
2092                         struct dwc2_hcd_urb *dwc2_urb, int status)
2093 {
2094         struct urb *urb = context;
2095         int i;
2096
2097         if (!urb) {
2098                 dev_dbg(hsotg->dev, "## %s: context is NULL ##\n", __func__);
2099                 return;
2100         }
2101
2102         if (!dwc2_urb) {
2103                 dev_dbg(hsotg->dev, "## %s: dwc2_urb is NULL ##\n", __func__);
2104                 return;
2105         }
2106
2107         urb->actual_length = dwc2_hcd_urb_get_actual_length(dwc2_urb);
2108
2109         if (dbg_urb(urb))
2110                 dev_vdbg(hsotg->dev,
2111                          "%s: urb %p device %d ep %d-%s status %d actual %d\n",
2112                          __func__, urb, usb_pipedevice(urb->pipe),
2113                          usb_pipeendpoint(urb->pipe),
2114                          usb_pipein(urb->pipe) ? "IN" : "OUT", status,
2115                          urb->actual_length);
2116
2117         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
2118                 for (i = 0; i < urb->number_of_packets; i++)
2119                         dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
2120                                  i, urb->iso_frame_desc[i].status);
2121         }
2122
2123         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2124                 urb->error_count = dwc2_hcd_urb_get_error_count(dwc2_urb);
2125                 for (i = 0; i < urb->number_of_packets; ++i) {
2126                         urb->iso_frame_desc[i].actual_length =
2127                                 dwc2_hcd_urb_get_iso_desc_actual_length(
2128                                                 dwc2_urb, i);
2129                         urb->iso_frame_desc[i].status =
2130                                 dwc2_hcd_urb_get_iso_desc_status(dwc2_urb, i);
2131                 }
2132         }
2133
2134         urb->status = status;
2135         urb->hcpriv = NULL;
2136         if (!status) {
2137                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
2138                     urb->actual_length < urb->transfer_buffer_length)
2139                         urb->status = -EREMOTEIO;
2140         }
2141
2142         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2143             usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2144                 struct usb_host_endpoint *ep = urb->ep;
2145
2146                 if (ep)
2147                         dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
2148                                         dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2149                                         urb);
2150         }
2151
2152         kfree(dwc2_urb);
2153
2154         spin_unlock(&hsotg->lock);
2155         usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
2156         spin_lock(&hsotg->lock);
2157 }
2158
2159 /*
2160  * Work queue function for starting the HCD when A-Cable is connected
2161  */
2162 static void dwc2_hcd_start_func(struct work_struct *work)
2163 {
2164         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2165                                                 start_work.work);
2166
2167         dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
2168         dwc2_host_start(hsotg);
2169 }
2170
2171 /*
2172  * Reset work queue function
2173  */
2174 static void dwc2_hcd_reset_func(struct work_struct *work)
2175 {
2176         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2177                                                 reset_work.work);
2178         u32 hprt0;
2179
2180         dev_dbg(hsotg->dev, "USB RESET function called\n");
2181         hprt0 = dwc2_read_hprt0(hsotg);
2182         hprt0 &= ~HPRT0_RST;
2183         writel(hprt0, hsotg->regs + HPRT0);
2184         hsotg->flags.b.port_reset_change = 1;
2185 }
2186
2187 /*
2188  * =========================================================================
2189  *  Linux HC Driver Functions
2190  * =========================================================================
2191  */
2192
2193 /*
2194  * Initializes the DWC_otg controller and its root hub and prepares it for host
2195  * mode operation. Activates the root port. Returns 0 on success and a negative
2196  * error code on failure.
2197  */
2198 static int _dwc2_hcd_start(struct usb_hcd *hcd)
2199 {
2200         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2201         struct usb_bus *bus = hcd_to_bus(hcd);
2202         unsigned long flags;
2203
2204         dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
2205
2206         spin_lock_irqsave(&hsotg->lock, flags);
2207
2208         hcd->state = HC_STATE_RUNNING;
2209
2210         if (dwc2_is_device_mode(hsotg)) {
2211                 spin_unlock_irqrestore(&hsotg->lock, flags);
2212                 return 0;       /* why 0 ?? */
2213         }
2214
2215         dwc2_hcd_reinit(hsotg);
2216
2217         /* Initialize and connect root hub if one is not already attached */
2218         if (bus->root_hub) {
2219                 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
2220                 /* Inform the HUB driver to resume */
2221                 usb_hcd_resume_root_hub(hcd);
2222         }
2223
2224         spin_unlock_irqrestore(&hsotg->lock, flags);
2225         return 0;
2226 }
2227
2228 /*
2229  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
2230  * stopped.
2231  */
2232 static void _dwc2_hcd_stop(struct usb_hcd *hcd)
2233 {
2234         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2235         unsigned long flags;
2236
2237         spin_lock_irqsave(&hsotg->lock, flags);
2238         dwc2_hcd_stop(hsotg);
2239         spin_unlock_irqrestore(&hsotg->lock, flags);
2240
2241         usleep_range(1000, 3000);
2242 }
2243
2244 /* Returns the current frame number */
2245 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
2246 {
2247         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2248
2249         return dwc2_hcd_get_frame_number(hsotg);
2250 }
2251
2252 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
2253                                char *fn_name)
2254 {
2255 #ifdef VERBOSE_DEBUG
2256         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2257         char *pipetype;
2258         char *speed;
2259
2260         dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
2261         dev_vdbg(hsotg->dev, "  Device address: %d\n",
2262                  usb_pipedevice(urb->pipe));
2263         dev_vdbg(hsotg->dev, "  Endpoint: %d, %s\n",
2264                  usb_pipeendpoint(urb->pipe),
2265                  usb_pipein(urb->pipe) ? "IN" : "OUT");
2266
2267         switch (usb_pipetype(urb->pipe)) {
2268         case PIPE_CONTROL:
2269                 pipetype = "CONTROL";
2270                 break;
2271         case PIPE_BULK:
2272                 pipetype = "BULK";
2273                 break;
2274         case PIPE_INTERRUPT:
2275                 pipetype = "INTERRUPT";
2276                 break;
2277         case PIPE_ISOCHRONOUS:
2278                 pipetype = "ISOCHRONOUS";
2279                 break;
2280         default:
2281                 pipetype = "UNKNOWN";
2282                 break;
2283         }
2284
2285         dev_vdbg(hsotg->dev, "  Endpoint type: %s %s (%s)\n", pipetype,
2286                  usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
2287                  "IN" : "OUT");
2288
2289         switch (urb->dev->speed) {
2290         case USB_SPEED_HIGH:
2291                 speed = "HIGH";
2292                 break;
2293         case USB_SPEED_FULL:
2294                 speed = "FULL";
2295                 break;
2296         case USB_SPEED_LOW:
2297                 speed = "LOW";
2298                 break;
2299         default:
2300                 speed = "UNKNOWN";
2301                 break;
2302         }
2303
2304         dev_vdbg(hsotg->dev, "  Speed: %s\n", speed);
2305         dev_vdbg(hsotg->dev, "  Max packet size: %d\n",
2306                  usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
2307         dev_vdbg(hsotg->dev, "  Data buffer length: %d\n",
2308                  urb->transfer_buffer_length);
2309         dev_vdbg(hsotg->dev, "  Transfer buffer: %p, Transfer DMA: %08lx\n",
2310                  urb->transfer_buffer, (unsigned long)urb->transfer_dma);
2311         dev_vdbg(hsotg->dev, "  Setup buffer: %p, Setup DMA: %08lx\n",
2312                  urb->setup_packet, (unsigned long)urb->setup_dma);
2313         dev_vdbg(hsotg->dev, "  Interval: %d\n", urb->interval);
2314
2315         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2316                 int i;
2317
2318                 for (i = 0; i < urb->number_of_packets; i++) {
2319                         dev_vdbg(hsotg->dev, "  ISO Desc %d:\n", i);
2320                         dev_vdbg(hsotg->dev, "    offset: %d, length %d\n",
2321                                  urb->iso_frame_desc[i].offset,
2322                                  urb->iso_frame_desc[i].length);
2323                 }
2324         }
2325 #endif
2326 }
2327
2328 /*
2329  * Starts processing a USB transfer request specified by a USB Request Block
2330  * (URB). mem_flags indicates the type of memory allocation to use while
2331  * processing this URB.
2332  */
2333 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
2334                                  gfp_t mem_flags)
2335 {
2336         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2337         struct usb_host_endpoint *ep = urb->ep;
2338         struct dwc2_hcd_urb *dwc2_urb;
2339         int i;
2340         int alloc_bandwidth = 0;
2341         int retval = 0;
2342         u8 ep_type = 0;
2343         u32 tflags = 0;
2344         void *buf;
2345         unsigned long flags;
2346
2347         if (dbg_urb(urb)) {
2348                 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
2349                 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
2350         }
2351
2352         if (ep == NULL)
2353                 return -EINVAL;
2354
2355         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2356             usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2357                 spin_lock_irqsave(&hsotg->lock, flags);
2358                 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
2359                         alloc_bandwidth = 1;
2360                 spin_unlock_irqrestore(&hsotg->lock, flags);
2361         }
2362
2363         switch (usb_pipetype(urb->pipe)) {
2364         case PIPE_CONTROL:
2365                 ep_type = USB_ENDPOINT_XFER_CONTROL;
2366                 break;
2367         case PIPE_ISOCHRONOUS:
2368                 ep_type = USB_ENDPOINT_XFER_ISOC;
2369                 break;
2370         case PIPE_BULK:
2371                 ep_type = USB_ENDPOINT_XFER_BULK;
2372                 break;
2373         case PIPE_INTERRUPT:
2374                 ep_type = USB_ENDPOINT_XFER_INT;
2375                 break;
2376         default:
2377                 dev_warn(hsotg->dev, "Wrong ep type\n");
2378         }
2379
2380         dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
2381                                       mem_flags);
2382         if (!dwc2_urb)
2383                 return -ENOMEM;
2384
2385         dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
2386                                   usb_pipeendpoint(urb->pipe), ep_type,
2387                                   usb_pipein(urb->pipe),
2388                                   usb_maxpacket(urb->dev, urb->pipe,
2389                                                 !(usb_pipein(urb->pipe))));
2390
2391         buf = urb->transfer_buffer;
2392         if (hcd->self.uses_dma) {
2393                 /*
2394                  * Calculate virtual address from physical address, because
2395                  * some class driver may not fill transfer_buffer.
2396                  * In Buffer DMA mode virtual address is used, when handling
2397                  * non-DWORD aligned buffers.
2398                  */
2399                 buf = bus_to_virt(urb->transfer_dma);
2400         }
2401
2402         if (!(urb->transfer_flags & URB_NO_INTERRUPT))
2403                 tflags |= URB_GIVEBACK_ASAP;
2404         if (urb->transfer_flags & URB_ZERO_PACKET)
2405                 tflags |= URB_SEND_ZERO_PACKET;
2406
2407         dwc2_urb->priv = urb;
2408         dwc2_urb->buf = buf;
2409         dwc2_urb->dma = urb->transfer_dma;
2410         dwc2_urb->length = urb->transfer_buffer_length;
2411         dwc2_urb->setup_packet = urb->setup_packet;
2412         dwc2_urb->setup_dma = urb->setup_dma;
2413         dwc2_urb->flags = tflags;
2414         dwc2_urb->interval = urb->interval;
2415         dwc2_urb->status = -EINPROGRESS;
2416
2417         for (i = 0; i < urb->number_of_packets; ++i)
2418                 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
2419                                                  urb->iso_frame_desc[i].offset,
2420                                                  urb->iso_frame_desc[i].length);
2421
2422         urb->hcpriv = dwc2_urb;
2423         retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, &ep->hcpriv,
2424                                       mem_flags);
2425         if (retval) {
2426                 urb->hcpriv = NULL;
2427                 kfree(dwc2_urb);
2428         } else {
2429                 if (alloc_bandwidth) {
2430                         spin_lock_irqsave(&hsotg->lock, flags);
2431                         dwc2_allocate_bus_bandwidth(hcd,
2432                                         dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2433                                         urb);
2434                         spin_unlock_irqrestore(&hsotg->lock, flags);
2435                 }
2436         }
2437
2438         return retval;
2439 }
2440
2441 /*
2442  * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
2443  */
2444 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
2445                                  int status)
2446 {
2447         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2448         int rc = 0;
2449         unsigned long flags;
2450
2451         dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
2452         dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
2453
2454         spin_lock_irqsave(&hsotg->lock, flags);
2455
2456         if (!urb->hcpriv) {
2457                 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
2458                 goto out;
2459         }
2460
2461         rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
2462
2463         kfree(urb->hcpriv);
2464         urb->hcpriv = NULL;
2465
2466         /* Higher layer software sets URB status */
2467         spin_unlock(&hsotg->lock);
2468         usb_hcd_giveback_urb(hcd, urb, status);
2469         spin_lock(&hsotg->lock);
2470
2471         dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
2472         dev_dbg(hsotg->dev, "  urb->status = %d\n", urb->status);
2473 out:
2474         spin_unlock_irqrestore(&hsotg->lock, flags);
2475
2476         return rc;
2477 }
2478
2479 /*
2480  * Frees resources in the DWC_otg controller related to a given endpoint. Also
2481  * clears state in the HCD related to the endpoint. Any URBs for the endpoint
2482  * must already be dequeued.
2483  */
2484 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
2485                                        struct usb_host_endpoint *ep)
2486 {
2487         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2488
2489         dev_dbg(hsotg->dev,
2490                 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
2491                 ep->desc.bEndpointAddress, ep->hcpriv);
2492         dwc2_hcd_endpoint_disable(hsotg, ep, 250);
2493 }
2494
2495 /*
2496  * Resets endpoint specific parameter values, in current version used to reset
2497  * the data toggle (as a WA). This function can be called from usb_clear_halt
2498  * routine.
2499  */
2500 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
2501                                      struct usb_host_endpoint *ep)
2502 {
2503         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2504         int is_control = usb_endpoint_xfer_control(&ep->desc);
2505         int is_out = usb_endpoint_dir_out(&ep->desc);
2506         int epnum = usb_endpoint_num(&ep->desc);
2507         struct usb_device *udev;
2508         unsigned long flags;
2509
2510         dev_dbg(hsotg->dev,
2511                 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
2512                 ep->desc.bEndpointAddress);
2513
2514         udev = to_usb_device(hsotg->dev);
2515
2516         spin_lock_irqsave(&hsotg->lock, flags);
2517
2518         usb_settoggle(udev, epnum, is_out, 0);
2519         if (is_control)
2520                 usb_settoggle(udev, epnum, !is_out, 0);
2521         dwc2_hcd_endpoint_reset(hsotg, ep);
2522
2523         spin_unlock_irqrestore(&hsotg->lock, flags);
2524 }
2525
2526 /*
2527  * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
2528  * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
2529  * interrupt.
2530  *
2531  * This function is called by the USB core when an interrupt occurs
2532  */
2533 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
2534 {
2535         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2536         int retval = dwc2_hcd_intr(hsotg);
2537
2538         return IRQ_RETVAL(retval);
2539 }
2540
2541 /*
2542  * Creates Status Change bitmap for the root hub and root port. The bitmap is
2543  * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
2544  * is the status change indicator for the single root port. Returns 1 if either
2545  * change indicator is 1, otherwise returns 0.
2546  */
2547 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
2548 {
2549         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2550
2551         buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
2552         return buf[0] != 0;
2553 }
2554
2555 /* Handles hub class-specific requests */
2556 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
2557                                  u16 windex, char *buf, u16 wlength)
2558 {
2559         int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
2560                                           wvalue, windex, buf, wlength);
2561         return retval;
2562 }
2563
2564 /* Handles hub TT buffer clear completions */
2565 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
2566                                                struct usb_host_endpoint *ep)
2567 {
2568         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2569         struct dwc2_qh *qh;
2570         unsigned long flags;
2571
2572         qh = ep->hcpriv;
2573         if (!qh)
2574                 return;
2575
2576         spin_lock_irqsave(&hsotg->lock, flags);
2577         qh->tt_buffer_dirty = 0;
2578
2579         if (hsotg->flags.b.port_connect_status)
2580                 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
2581
2582         spin_unlock_irqrestore(&hsotg->lock, flags);
2583 }
2584
2585 static struct hc_driver dwc2_hc_driver = {
2586         .description = "dwc2_hsotg",
2587         .product_desc = "DWC OTG Controller",
2588         .hcd_priv_size = sizeof(struct wrapper_priv_data),
2589
2590         .irq = _dwc2_hcd_irq,
2591         .flags = HCD_MEMORY | HCD_USB2,
2592
2593         .start = _dwc2_hcd_start,
2594         .stop = _dwc2_hcd_stop,
2595         .urb_enqueue = _dwc2_hcd_urb_enqueue,
2596         .urb_dequeue = _dwc2_hcd_urb_dequeue,
2597         .endpoint_disable = _dwc2_hcd_endpoint_disable,
2598         .endpoint_reset = _dwc2_hcd_endpoint_reset,
2599         .get_frame_number = _dwc2_hcd_get_frame_number,
2600
2601         .hub_status_data = _dwc2_hcd_hub_status_data,
2602         .hub_control = _dwc2_hcd_hub_control,
2603         .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
2604 };
2605
2606 /*
2607  * Frees secondary storage associated with the dwc2_hsotg structure contained
2608  * in the struct usb_hcd field
2609  */
2610 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
2611 {
2612         u32 ahbcfg;
2613         u32 dctl;
2614         int i;
2615
2616         dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
2617
2618         /* Free memory for QH/QTD lists */
2619         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
2620         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
2621         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
2622         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
2623         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
2624         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
2625
2626         /* Free memory for the host channels */
2627         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
2628                 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
2629
2630                 if (chan != NULL) {
2631                         dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
2632                                 i, chan);
2633                         hsotg->hc_ptr_array[i] = NULL;
2634                         kfree(chan);
2635                 }
2636         }
2637
2638         if (hsotg->core_params->dma_enable > 0) {
2639                 if (hsotg->status_buf) {
2640                         dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
2641                                           hsotg->status_buf,
2642                                           hsotg->status_buf_dma);
2643                         hsotg->status_buf = NULL;
2644                 }
2645         } else {
2646                 kfree(hsotg->status_buf);
2647                 hsotg->status_buf = NULL;
2648         }
2649
2650         ahbcfg = readl(hsotg->regs + GAHBCFG);
2651
2652         /* Disable all interrupts */
2653         ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
2654         writel(ahbcfg, hsotg->regs + GAHBCFG);
2655         writel(0, hsotg->regs + GINTMSK);
2656
2657         if (hsotg->snpsid >= DWC2_CORE_REV_3_00a) {
2658                 dctl = readl(hsotg->regs + DCTL);
2659                 dctl |= DCTL_SFTDISCON;
2660                 writel(dctl, hsotg->regs + DCTL);
2661         }
2662
2663         if (hsotg->wq_otg) {
2664                 if (!cancel_work_sync(&hsotg->wf_otg))
2665                         flush_workqueue(hsotg->wq_otg);
2666                 destroy_workqueue(hsotg->wq_otg);
2667         }
2668
2669         kfree(hsotg->core_params);
2670         hsotg->core_params = NULL;
2671         del_timer(&hsotg->wkp_timer);
2672 }
2673
2674 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
2675 {
2676         /* Turn off all host-specific interrupts */
2677         dwc2_disable_host_interrupts(hsotg);
2678
2679         dwc2_hcd_free(hsotg);
2680 }
2681
2682 static void dwc2_set_uninitialized(int *p, int size)
2683 {
2684         int i;
2685
2686         for (i = 0; i < size; i++)
2687                 p[i] = -1;
2688 }
2689
2690 /*
2691  * Initializes the HCD. This function allocates memory for and initializes the
2692  * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
2693  * USB bus with the core and calls the hc_driver->start() function. It returns
2694  * a negative error on failure.
2695  */
2696 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq,
2697                   struct dwc2_core_params *params)
2698 {
2699         struct usb_hcd *hcd;
2700         struct dwc2_host_chan *channel;
2701         u32 snpsid, gusbcfg, hcfg;
2702         int i, num_channels;
2703         int retval = -ENOMEM;
2704
2705         dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
2706
2707         /*
2708          * Attempt to ensure this device is really a DWC_otg Controller.
2709          * Read and verify the GSNPSID register contents. The value should be
2710          * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3",
2711          * as in "OTG version 2.xx" or "OTG version 3.xx".
2712          */
2713         snpsid = readl(hsotg->regs + GSNPSID);
2714         if ((snpsid & 0xfffff000) != 0x4f542000 &&
2715             (snpsid & 0xfffff000) != 0x4f543000) {
2716                 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", snpsid);
2717                 retval = -ENODEV;
2718                 goto error1;
2719         }
2720
2721         /*
2722          * Store the contents of the hardware configuration registers here for
2723          * easy access later
2724          */
2725         hsotg->hwcfg1 = readl(hsotg->regs + GHWCFG1);
2726         hsotg->hwcfg2 = readl(hsotg->regs + GHWCFG2);
2727         hsotg->hwcfg3 = readl(hsotg->regs + GHWCFG3);
2728         hsotg->hwcfg4 = readl(hsotg->regs + GHWCFG4);
2729
2730         dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hsotg->hwcfg1);
2731         dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hsotg->hwcfg2);
2732         dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hsotg->hwcfg3);
2733         dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hsotg->hwcfg4);
2734
2735         /* Force host mode to get HPTXFSIZ exact power on value */
2736         gusbcfg = readl(hsotg->regs + GUSBCFG);
2737         gusbcfg |= GUSBCFG_FORCEHOSTMODE;
2738         writel(gusbcfg, hsotg->regs + GUSBCFG);
2739         usleep_range(100000, 150000);
2740
2741         hsotg->hptxfsiz = readl(hsotg->regs + HPTXFSIZ);
2742         dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hsotg->hptxfsiz);
2743         gusbcfg = readl(hsotg->regs + GUSBCFG);
2744         gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
2745         writel(gusbcfg, hsotg->regs + GUSBCFG);
2746         usleep_range(100000, 150000);
2747
2748         hcfg = readl(hsotg->regs + HCFG);
2749         dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
2750         dev_dbg(hsotg->dev, "op_mode=%0x\n",
2751                 hsotg->hwcfg2 >> GHWCFG2_OP_MODE_SHIFT &
2752                 GHWCFG2_OP_MODE_MASK >> GHWCFG2_OP_MODE_SHIFT);
2753         dev_dbg(hsotg->dev, "arch=%0x\n",
2754                 hsotg->hwcfg2 >> GHWCFG2_ARCHITECTURE_SHIFT &
2755                 GHWCFG2_ARCHITECTURE_MASK >> GHWCFG2_ARCHITECTURE_SHIFT);
2756         dev_dbg(hsotg->dev, "num_dev_ep=%d\n",
2757                 hsotg->hwcfg2 >> GHWCFG2_NUM_DEV_EP_SHIFT &
2758                 GHWCFG2_NUM_DEV_EP_MASK >> GHWCFG2_NUM_DEV_EP_SHIFT);
2759         dev_dbg(hsotg->dev, "max_host_chan=%d\n",
2760                 hsotg->hwcfg2 >> GHWCFG2_NUM_HOST_CHAN_SHIFT &
2761                 GHWCFG2_NUM_HOST_CHAN_MASK >> GHWCFG2_NUM_HOST_CHAN_SHIFT);
2762         dev_dbg(hsotg->dev, "nonperio_tx_q_depth=0x%0x\n",
2763                 hsotg->hwcfg2 >> GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT &
2764                 GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK >>
2765                                 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT);
2766         dev_dbg(hsotg->dev, "host_perio_tx_q_depth=0x%0x\n",
2767                 hsotg->hwcfg2 >> GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT &
2768                 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK >>
2769                                 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT);
2770         dev_dbg(hsotg->dev, "dev_token_q_depth=0x%0x\n",
2771                 hsotg->hwcfg2 >> GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT &
2772                 GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK >>
2773                                 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT);
2774
2775 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2776         hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
2777                                          FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
2778         if (!hsotg->frame_num_array)
2779                 goto error1;
2780         hsotg->last_frame_num_array = kzalloc(
2781                         sizeof(*hsotg->last_frame_num_array) *
2782                         FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
2783         if (!hsotg->last_frame_num_array)
2784                 goto error1;
2785         hsotg->last_frame_num = HFNUM_MAX_FRNUM;
2786 #endif
2787
2788         hsotg->core_params = kzalloc(sizeof(*hsotg->core_params), GFP_KERNEL);
2789         if (!hsotg->core_params)
2790                 goto error1;
2791
2792         dwc2_set_uninitialized((int *)hsotg->core_params,
2793                                sizeof(*hsotg->core_params) / sizeof(int));
2794
2795         /* Validate parameter values */
2796         dwc2_set_parameters(hsotg, params);
2797
2798         /* Set device flags indicating whether the HCD supports DMA */
2799         if (hsotg->core_params->dma_enable > 0) {
2800                 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(31)) < 0)
2801                         dev_warn(hsotg->dev,
2802                                  "can't enable workaround for >2GB RAM\n");
2803                 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(31)) < 0)
2804                         dev_warn(hsotg->dev,
2805                                  "can't enable workaround for >2GB RAM\n");
2806         } else {
2807                 dma_set_mask(hsotg->dev, 0);
2808                 dma_set_coherent_mask(hsotg->dev, 0);
2809         }
2810
2811         hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
2812         if (!hcd)
2813                 goto error1;
2814
2815         hcd->has_tt = 1;
2816
2817         spin_lock_init(&hsotg->lock);
2818         ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg;
2819         hsotg->priv = hcd;
2820
2821         /*
2822          * Disable the global interrupt until all the interrupt handlers are
2823          * installed
2824          */
2825         dwc2_disable_global_interrupts(hsotg);
2826
2827         /* Initialize the DWC_otg core, and select the Phy type */
2828         retval = dwc2_core_init(hsotg, true, irq);
2829         if (retval)
2830                 goto error2;
2831
2832         /* Create new workqueue and init work */
2833         hsotg->wq_otg = create_singlethread_workqueue("dwc_otg");
2834         if (!hsotg->wq_otg) {
2835                 dev_err(hsotg->dev, "Failed to create workqueue\n");
2836                 goto error2;
2837         }
2838         INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
2839
2840         hsotg->snpsid = readl(hsotg->regs + GSNPSID);
2841         dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x\n",
2842                 hsotg->snpsid >> 12 & 0xf, hsotg->snpsid >> 8 & 0xf,
2843                 hsotg->snpsid >> 4 & 0xf, hsotg->snpsid & 0xf);
2844
2845         setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected,
2846                     (unsigned long)hsotg);
2847
2848         /* Initialize the non-periodic schedule */
2849         INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
2850         INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
2851
2852         /* Initialize the periodic schedule */
2853         INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
2854         INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
2855         INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
2856         INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
2857
2858         /*
2859          * Create a host channel descriptor for each host channel implemented
2860          * in the controller. Initialize the channel descriptor array.
2861          */
2862         INIT_LIST_HEAD(&hsotg->free_hc_list);
2863         num_channels = hsotg->core_params->host_channels;
2864         memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
2865
2866         for (i = 0; i < num_channels; i++) {
2867                 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
2868                 if (channel == NULL)
2869                         goto error3;
2870                 channel->hc_num = i;
2871                 hsotg->hc_ptr_array[i] = channel;
2872         }
2873
2874         /* Initialize hsotg start work */
2875         INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
2876
2877         /* Initialize port reset work */
2878         INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
2879
2880         /*
2881          * Allocate space for storing data on status transactions. Normally no
2882          * data is sent, but this space acts as a bit bucket. This must be
2883          * done after usb_add_hcd since that function allocates the DMA buffer
2884          * pool.
2885          */
2886         if (hsotg->core_params->dma_enable > 0)
2887                 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
2888                                         DWC2_HCD_STATUS_BUF_SIZE,
2889                                         &hsotg->status_buf_dma, GFP_KERNEL);
2890         else
2891                 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
2892                                           GFP_KERNEL);
2893
2894         if (!hsotg->status_buf)
2895                 goto error3;
2896
2897         hsotg->otg_port = 1;
2898         hsotg->frame_list = NULL;
2899         hsotg->frame_list_dma = 0;
2900         hsotg->periodic_qh_count = 0;
2901
2902         /* Initiate lx_state to L3 disconnected state */
2903         hsotg->lx_state = DWC2_L3;
2904
2905         hcd->self.otg_port = hsotg->otg_port;
2906
2907         /* Don't support SG list at this point */
2908         hcd->self.sg_tablesize = 0;
2909
2910         /*
2911          * Finish generic HCD initialization and start the HCD. This function
2912          * allocates the DMA buffer pool, registers the USB bus, requests the
2913          * IRQ line, and calls hcd_start method.
2914          */
2915         retval = usb_add_hcd(hcd, irq, IRQF_SHARED | IRQF_DISABLED);
2916         if (retval < 0)
2917                 goto error3;
2918
2919         dwc2_dump_global_registers(hsotg);
2920         dwc2_dump_host_registers(hsotg);
2921         dwc2_hcd_dump_state(hsotg);
2922
2923         dwc2_enable_global_interrupts(hsotg);
2924
2925         return 0;
2926
2927 error3:
2928         dwc2_hcd_release(hsotg);
2929 error2:
2930         usb_put_hcd(hcd);
2931 error1:
2932         kfree(hsotg->core_params);
2933
2934 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2935         kfree(hsotg->last_frame_num_array);
2936         kfree(hsotg->frame_num_array);
2937 #endif
2938
2939         dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
2940         return retval;
2941 }
2942 EXPORT_SYMBOL_GPL(dwc2_hcd_init);
2943
2944 /*
2945  * Removes the HCD.
2946  * Frees memory and resources associated with the HCD and deregisters the bus.
2947  */
2948 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
2949 {
2950         struct usb_hcd *hcd;
2951
2952         dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
2953
2954         hcd = dwc2_hsotg_to_hcd(hsotg);
2955         dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
2956
2957         if (!hcd) {
2958                 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
2959                         __func__);
2960                 return;
2961         }
2962
2963         usb_remove_hcd(hcd);
2964         hsotg->priv = NULL;
2965         dwc2_hcd_release(hsotg);
2966         usb_put_hcd(hcd);
2967
2968 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2969         kfree(hsotg->last_frame_num_array);
2970         kfree(hsotg->frame_num_array);
2971 #endif
2972 }
2973 EXPORT_SYMBOL_GPL(dwc2_hcd_remove);