drivers/staging/gma500/psb_drv.c

   1 /**************************************************************************
   2  * Copyright (c) 2007, Intel Corporation.
   3  * All Rights Reserved.
   4  * Copyright (c) 2008, Tungsten Graphics, Inc. Cedar Park, TX., USA.
   5  * All Rights Reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  **************************************************************************/
  21
  22 #include <drm/drmP.h>
  23 #include <drm/drm.h>
  24 #include "psb_drm.h"
  25 #include "psb_drv.h"
  26 #include "psb_fb.h"
  27 #include "psb_reg.h"
  28 #include "psb_intel_reg.h"
  29 #include "psb_intel_bios.h"
  30 #include <drm/drm_pciids.h>
  31 #include "psb_powermgmt.h"
  32 #include <linux/cpu.h>
  33 #include <linux/notifier.h>
  34 #include <linux/spinlock.h>
  35 #include <linux/pm_runtime.h>
  36 #include <acpi/video.h>
  37
  38 int drm_psb_debug;
  39 static int drm_psb_trap_pagefaults;
  40
  41 int drm_psb_disable_vsync = 1;
  42 int drm_psb_no_fb;
  43 int gfxrtdelay = 2 * 1000;
  44
  45 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
  46
  47 MODULE_PARM_DESC(debug, "Enable debug output");
  48 MODULE_PARM_DESC(no_fb, "Disable FBdev");
  49 MODULE_PARM_DESC(trap_pagefaults, "Error and reset on MMU pagefaults");
  50 MODULE_PARM_DESC(disable_vsync, "Disable vsync interrupts");
  51 MODULE_PARM_DESC(force_pipeb, "Forces PIPEB to become primary fb");
  52 MODULE_PARM_DESC(ta_mem_size, "TA memory size in kiB");
  53 MODULE_PARM_DESC(ospm, "switch for ospm support");
  54 MODULE_PARM_DESC(rtpm, "Specifies Runtime PM delay for GFX");
  55 MODULE_PARM_DESC(hdmi_edid, "EDID info for HDMI monitor");
  56 module_param_named(debug, drm_psb_debug, int, 0600);
  57 module_param_named(no_fb, drm_psb_no_fb, int, 0600);
  58 module_param_named(trap_pagefaults, drm_psb_trap_pagefaults, int, 0600);
  59 module_param_named(rtpm, gfxrtdelay, int, 0600);
  60
  61
  62 static struct pci_device_id pciidlist[] = {
  63         { 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8108 },
  64         { 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8109 },
  65         { 0, 0, 0}
  66 };
  67 MODULE_DEVICE_TABLE(pci, pciidlist);
  68
  69 /*
  70  * Standard IOCTLs.
  71  */
  72
  73 #define DRM_IOCTL_PSB_KMS_OFF   \
  74                 DRM_IO(DRM_PSB_KMS_OFF + DRM_COMMAND_BASE)
  75 #define DRM_IOCTL_PSB_KMS_ON    \
  76                 DRM_IO(DRM_PSB_KMS_ON + DRM_COMMAND_BASE)
  77 #define DRM_IOCTL_PSB_VT_LEAVE  \
  78                 DRM_IO(DRM_PSB_VT_LEAVE + DRM_COMMAND_BASE)
  79 #define DRM_IOCTL_PSB_VT_ENTER  \
  80                 DRM_IO(DRM_PSB_VT_ENTER + DRM_COMMAND_BASE)
  81 #define DRM_IOCTL_PSB_SIZES     \
  82                 DRM_IOR(DRM_PSB_SIZES + DRM_COMMAND_BASE, \
  83                         struct drm_psb_sizes_arg)
  84 #define DRM_IOCTL_PSB_FUSE_REG  \
  85                 DRM_IOWR(DRM_PSB_FUSE_REG + DRM_COMMAND_BASE, uint32_t)
  86 #define DRM_IOCTL_PSB_DC_STATE  \
  87                 DRM_IOW(DRM_PSB_DC_STATE + DRM_COMMAND_BASE, \
  88                         struct drm_psb_dc_state_arg)
  89 #define DRM_IOCTL_PSB_ADB       \
  90                 DRM_IOWR(DRM_PSB_ADB + DRM_COMMAND_BASE, uint32_t)
  91 #define DRM_IOCTL_PSB_MODE_OPERATION    \
  92                 DRM_IOWR(DRM_PSB_MODE_OPERATION + DRM_COMMAND_BASE, \
  93                          struct drm_psb_mode_operation_arg)
  94 #define DRM_IOCTL_PSB_STOLEN_MEMORY     \
  95                 DRM_IOWR(DRM_PSB_STOLEN_MEMORY + DRM_COMMAND_BASE, \
  96                          struct drm_psb_stolen_memory_arg)
  97 #define DRM_IOCTL_PSB_REGISTER_RW       \
  98                 DRM_IOWR(DRM_PSB_REGISTER_RW + DRM_COMMAND_BASE, \
  99                          struct drm_psb_register_rw_arg)
 100 #define DRM_IOCTL_PSB_GTT_MAP   \
 101                 DRM_IOWR(DRM_PSB_GTT_MAP + DRM_COMMAND_BASE, \
 102                          struct psb_gtt_mapping_arg)
 103 #define DRM_IOCTL_PSB_GTT_UNMAP \
 104                 DRM_IOW(DRM_PSB_GTT_UNMAP + DRM_COMMAND_BASE, \
 105                         struct psb_gtt_mapping_arg)
 106 #define DRM_IOCTL_PSB_GETPAGEADDRS      \
 107                 DRM_IOWR(DRM_COMMAND_BASE + DRM_PSB_GETPAGEADDRS,\
 108                          struct drm_psb_getpageaddrs_arg)
 109 #define DRM_IOCTL_PSB_UPDATE_GUARD      \
 110                 DRM_IOWR(DRM_PSB_UPDATE_GUARD + DRM_COMMAND_BASE, \
 111                          uint32_t)
 112 #define DRM_IOCTL_PSB_DPST      \
 113                 DRM_IOWR(DRM_PSB_DPST + DRM_COMMAND_BASE, \
 114                          uint32_t)
 115 #define DRM_IOCTL_PSB_GAMMA     \
 116                 DRM_IOWR(DRM_PSB_GAMMA + DRM_COMMAND_BASE, \
 117                          struct drm_psb_dpst_lut_arg)
 118 #define DRM_IOCTL_PSB_DPST_BL   \
 119                 DRM_IOWR(DRM_PSB_DPST_BL + DRM_COMMAND_BASE, \
 120                          uint32_t)
 121 #define DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID     \
 122                 DRM_IOWR(DRM_PSB_GET_PIPE_FROM_CRTC_ID + DRM_COMMAND_BASE, \
 123                          struct drm_psb_get_pipe_from_crtc_id_arg)
 124
 125 /*
 126  * TTM execbuf extension.
 127  */
 128
 129 #define DRM_PSB_CMDBUF            0x23
 130 #define DRM_PSB_SCENE_UNREF       0x24
 131 #define DRM_IOCTL_PSB_KMS_OFF     DRM_IO(DRM_PSB_KMS_OFF + DRM_COMMAND_BASE)
 132 #define DRM_IOCTL_PSB_KMS_ON      DRM_IO(DRM_PSB_KMS_ON + DRM_COMMAND_BASE)
 133 /*
 134  * TTM placement user extension.
 135  */
 136
 137 #define DRM_PSB_PLACEMENT_OFFSET   (DRM_PSB_SCENE_UNREF + 1)
 138
 139 #define DRM_PSB_TTM_PL_CREATE    (TTM_PL_CREATE + DRM_PSB_PLACEMENT_OFFSET)
 140 #define DRM_PSB_TTM_PL_REFERENCE (TTM_PL_REFERENCE + DRM_PSB_PLACEMENT_OFFSET)
 141 #define DRM_PSB_TTM_PL_UNREF     (TTM_PL_UNREF + DRM_PSB_PLACEMENT_OFFSET)
 142 #define DRM_PSB_TTM_PL_SYNCCPU   (TTM_PL_SYNCCPU + DRM_PSB_PLACEMENT_OFFSET)
 143 #define DRM_PSB_TTM_PL_WAITIDLE  (TTM_PL_WAITIDLE + DRM_PSB_PLACEMENT_OFFSET)
 144 #define DRM_PSB_TTM_PL_SETSTATUS (TTM_PL_SETSTATUS + DRM_PSB_PLACEMENT_OFFSET)
 145 #define DRM_PSB_TTM_PL_CREATE_UB (TTM_PL_CREATE_UB + DRM_PSB_PLACEMENT_OFFSET)
 146
 147 /*
 148  * TTM fence extension.
 149  */
 150
 151 #define DRM_PSB_FENCE_OFFSET       (DRM_PSB_TTM_PL_CREATE_UB + 1)
 152 #define DRM_PSB_TTM_FENCE_SIGNALED (TTM_FENCE_SIGNALED + DRM_PSB_FENCE_OFFSET)
 153 #define DRM_PSB_TTM_FENCE_FINISH   (TTM_FENCE_FINISH + DRM_PSB_FENCE_OFFSET)
 154 #define DRM_PSB_TTM_FENCE_UNREF    (TTM_FENCE_UNREF + DRM_PSB_FENCE_OFFSET)
 155
 156 #define DRM_PSB_FLIP       (DRM_PSB_TTM_FENCE_UNREF + 1)        /*20*/
 157
 158 #define DRM_IOCTL_PSB_TTM_PL_CREATE    \
 159         DRM_IOWR(DRM_COMMAND_BASE + DRM_PSB_TTM_PL_CREATE,\
 160                  union ttm_pl_create_arg)
 161 #define DRM_IOCTL_PSB_TTM_PL_REFERENCE \
 162         DRM_IOWR(DRM_COMMAND_BASE + DRM_PSB_TTM_PL_REFERENCE,\
 163                  union ttm_pl_reference_arg)
 164 #define DRM_IOCTL_PSB_TTM_PL_UNREF    \
 165         DRM_IOW(DRM_COMMAND_BASE + DRM_PSB_TTM_PL_UNREF,\
 166                 struct ttm_pl_reference_req)
 167 #define DRM_IOCTL_PSB_TTM_PL_SYNCCPU    \
 168         DRM_IOW(DRM_COMMAND_BASE + DRM_PSB_TTM_PL_SYNCCPU,\
 169                 struct ttm_pl_synccpu_arg)
 170 #define DRM_IOCTL_PSB_TTM_PL_WAITIDLE    \
 171         DRM_IOW(DRM_COMMAND_BASE + DRM_PSB_TTM_PL_WAITIDLE,\
 172                 struct ttm_pl_waitidle_arg)
 173 #define DRM_IOCTL_PSB_TTM_PL_SETSTATUS \
 174         DRM_IOWR(DRM_COMMAND_BASE + DRM_PSB_TTM_PL_SETSTATUS,\
 175                  union ttm_pl_setstatus_arg)
 176 #define DRM_IOCTL_PSB_TTM_PL_CREATE_UB    \
 177         DRM_IOWR(DRM_COMMAND_BASE + DRM_PSB_TTM_PL_CREATE_UB,\
 178                  union ttm_pl_create_ub_arg)
 179 #define DRM_IOCTL_PSB_TTM_FENCE_SIGNALED \
 180         DRM_IOWR(DRM_COMMAND_BASE + DRM_PSB_TTM_FENCE_SIGNALED, \
 181                   union ttm_fence_signaled_arg)
 182 #define DRM_IOCTL_PSB_TTM_FENCE_FINISH \
 183         DRM_IOWR(DRM_COMMAND_BASE + DRM_PSB_TTM_FENCE_FINISH,   \
 184                  union ttm_fence_finish_arg)
 185 #define DRM_IOCTL_PSB_TTM_FENCE_UNREF \
 186         DRM_IOW(DRM_COMMAND_BASE + DRM_PSB_TTM_FENCE_UNREF,     \
 187                  struct ttm_fence_unref_arg)
 188
 189 static int psb_vt_leave_ioctl(struct drm_device *dev, void *data,
 190                               struct drm_file *file_priv);
 191 static int psb_vt_enter_ioctl(struct drm_device *dev, void *data,
 192                               struct drm_file *file_priv);
 193 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
 194                            struct drm_file *file_priv);
 195 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
 196                               struct drm_file *file_priv);
 197 static int psb_adb_ioctl(struct drm_device *dev, void *data,
 198                          struct drm_file *file_priv);
 199 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
 200                                     struct drm_file *file_priv);
 201 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
 202                                    struct drm_file *file_priv);
 203 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
 204                                  struct drm_file *file_priv);
 205 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
 206                           struct drm_file *file_priv);
 207 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
 208                            struct drm_file *file_priv);
 209 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
 210                              struct drm_file *file_priv);
 211
 212 #define PSB_IOCTL_DEF(ioctl, func, flags) \
 213         [DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, flags, func}
 214
 215 static struct drm_ioctl_desc psb_ioctls[] = {
 216         PSB_IOCTL_DEF(DRM_IOCTL_PSB_KMS_OFF, psbfb_kms_off_ioctl,
 217                       DRM_ROOT_ONLY),
 218         PSB_IOCTL_DEF(DRM_IOCTL_PSB_KMS_ON,
 219                         psbfb_kms_on_ioctl,
 220                         DRM_ROOT_ONLY),
 221         PSB_IOCTL_DEF(DRM_IOCTL_PSB_VT_LEAVE, psb_vt_leave_ioctl,
 222                       DRM_ROOT_ONLY),
 223         PSB_IOCTL_DEF(DRM_IOCTL_PSB_VT_ENTER,
 224                         psb_vt_enter_ioctl,
 225                         DRM_ROOT_ONLY),
 226         PSB_IOCTL_DEF(DRM_IOCTL_PSB_SIZES, psb_sizes_ioctl, DRM_AUTH),
 227         PSB_IOCTL_DEF(DRM_IOCTL_PSB_DC_STATE, psb_dc_state_ioctl, DRM_AUTH),
 228         PSB_IOCTL_DEF(DRM_IOCTL_PSB_ADB, psb_adb_ioctl, DRM_AUTH),
 229         PSB_IOCTL_DEF(DRM_IOCTL_PSB_MODE_OPERATION, psb_mode_operation_ioctl,
 230                       DRM_AUTH),
 231         PSB_IOCTL_DEF(DRM_IOCTL_PSB_STOLEN_MEMORY, psb_stolen_memory_ioctl,
 232                       DRM_AUTH),
 233         PSB_IOCTL_DEF(DRM_IOCTL_PSB_REGISTER_RW, psb_register_rw_ioctl,
 234                       DRM_AUTH),
 235         PSB_IOCTL_DEF(DRM_IOCTL_PSB_GTT_MAP,
 236                         psb_gtt_map_meminfo_ioctl,
 237                         DRM_AUTH),
 238         PSB_IOCTL_DEF(DRM_IOCTL_PSB_GTT_UNMAP,
 239                         psb_gtt_unmap_meminfo_ioctl,
 240                         DRM_AUTH),
 241         PSB_IOCTL_DEF(DRM_IOCTL_PSB_GETPAGEADDRS,
 242                         psb_getpageaddrs_ioctl,
 243                         DRM_AUTH),
 244         PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST, psb_dpst_ioctl, DRM_AUTH),
 245         PSB_IOCTL_DEF(DRM_IOCTL_PSB_GAMMA, psb_gamma_ioctl, DRM_AUTH),
 246         PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST_BL, psb_dpst_bl_ioctl, DRM_AUTH),
 247         PSB_IOCTL_DEF(DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID,
 248                                         psb_intel_get_pipe_from_crtc_id, 0),
 249
 250         PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_PL_CREATE, psb_pl_create_ioctl,
 251                       DRM_AUTH),
 252         PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_PL_REFERENCE, psb_pl_reference_ioctl,
 253                       DRM_AUTH),
 254         PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_PL_UNREF, psb_pl_unref_ioctl,
 255                       DRM_AUTH),
 256         PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_PL_SYNCCPU, psb_pl_synccpu_ioctl,
 257                       DRM_AUTH),
 258         PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_PL_WAITIDLE, psb_pl_waitidle_ioctl,
 259                       DRM_AUTH),
 260         PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_PL_SETSTATUS, psb_pl_setstatus_ioctl,
 261                       DRM_AUTH),
 262         PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_PL_CREATE_UB, psb_pl_ub_create_ioctl,
 263                       DRM_AUTH),
 264         PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_FENCE_SIGNALED,
 265                       psb_fence_signaled_ioctl, DRM_AUTH),
 266         PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_FENCE_FINISH, psb_fence_finish_ioctl,
 267                       DRM_AUTH),
 268         PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_FENCE_UNREF, psb_fence_unref_ioctl,
 269                       DRM_AUTH),
 270 };
 271
 272 static void psb_set_uopt(struct drm_psb_uopt *uopt)
 273 {
 274         return;
 275 }
 276
 277 static void psb_lastclose(struct drm_device *dev)
 278 {
 279         struct drm_psb_private *dev_priv =
 280             (struct drm_psb_private *) dev->dev_private;
 281
 282         return;
 283
 284         if (!dev->dev_private)
 285                 return;
 286
 287         mutex_lock(&dev_priv->cmdbuf_mutex);
 288         if (dev_priv->context.buffers) {
 289                 vfree(dev_priv->context.buffers);
 290                 dev_priv->context.buffers = NULL;
 291         }
 292         mutex_unlock(&dev_priv->cmdbuf_mutex);
 293 }
 294
 295 static void psb_do_takedown(struct drm_device *dev)
 296 {
 297         struct drm_psb_private *dev_priv =
 298             (struct drm_psb_private *) dev->dev_private;
 299         struct ttm_bo_device *bdev = &dev_priv->bdev;
 300
 301
 302         if (dev_priv->have_mem_mmu) {
 303                 ttm_bo_clean_mm(bdev, DRM_PSB_MEM_MMU);
 304                 dev_priv->have_mem_mmu = 0;
 305         }
 306
 307         if (dev_priv->have_tt) {
 308                 ttm_bo_clean_mm(bdev, TTM_PL_TT);
 309                 dev_priv->have_tt = 0;
 310         }
 311
 312         if (dev_priv->have_camera) {
 313                 ttm_bo_clean_mm(bdev, TTM_PL_CI);
 314                 dev_priv->have_camera = 0;
 315         }
 316         if (dev_priv->have_rar) {
 317                 ttm_bo_clean_mm(bdev, TTM_PL_RAR);
 318                 dev_priv->have_rar = 0;
 319         }
 320
 321 }
 322
 323 void mrst_get_fuse_settings(struct drm_device *dev)
 324 {
 325         struct drm_psb_private *dev_priv = dev->dev_private;
 326         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 327         uint32_t fuse_value = 0;
 328         uint32_t fuse_value_tmp = 0;
 329
 330 #define FB_REG06 0xD0810600
 331 #define FB_MIPI_DISABLE  (1 << 11)
 332 #define FB_REG09 0xD0810900
 333 #define FB_REG09 0xD0810900
 334 #define FB_SKU_MASK  0x7000
 335 #define FB_SKU_SHIFT 12
 336 #define FB_SKU_100 0
 337 #define FB_SKU_100L 1
 338 #define FB_SKU_83 2
 339         pci_write_config_dword(pci_root, 0xD0, FB_REG06);
 340         pci_read_config_dword(pci_root, 0xD4, &fuse_value);
 341
 342         dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
 343
 344         DRM_INFO("internal display is %s\n",
 345                  dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
 346
 347          /*prevent Runtime suspend at start*/
 348          if (dev_priv->iLVDS_enable) {
 349                 dev_priv->is_lvds_on = true;
 350                 dev_priv->is_mipi_on = false;
 351         }
 352         else {
 353                 dev_priv->is_mipi_on = true;
 354                 dev_priv->is_lvds_on = false;
 355         }
 356
 357         dev_priv->video_device_fuse = fuse_value;
 358
 359         pci_write_config_dword(pci_root, 0xD0, FB_REG09);
 360         pci_read_config_dword(pci_root, 0xD4, &fuse_value);
 361
 362         DRM_INFO("SKU values is 0x%x. \n", fuse_value);
 363         fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
 364
 365         dev_priv->fuse_reg_value = fuse_value;
 366
 367         switch (fuse_value_tmp) {
 368         case FB_SKU_100:
 369                 dev_priv->core_freq = 200;
 370                 break;
 371         case FB_SKU_100L:
 372                 dev_priv->core_freq = 100;
 373                 break;
 374         case FB_SKU_83:
 375                 dev_priv->core_freq = 166;
 376                 break;
 377         default:
 378                 DRM_ERROR("Invalid SKU values, SKU value = 0x%08x\n", fuse_value_tmp);
 379                 dev_priv->core_freq = 0;
 380         }
 381         DRM_INFO("LNC core clk is %dMHz.\n", dev_priv->core_freq);
 382         pci_dev_put(pci_root);
 383 }
 384
 385 void mid_get_pci_revID (struct drm_psb_private *dev_priv)
 386 {
 387         uint32_t platform_rev_id = 0;
 388         struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
 389
 390         /*get the revison ID, B0:D2:F0;0x08 */
 391         pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
 392         dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
 393         pci_dev_put(pci_gfx_root);
 394         PSB_DEBUG_ENTRY("platform_rev_id is %x\n",      dev_priv->platform_rev_id);
 395 }
 396
 397 void mrst_get_vbt_data(struct drm_psb_private *dev_priv)
 398 {
 399         struct mrst_vbt *vbt = &dev_priv->vbt_data;
 400         u32 platform_config_address;
 401         u16 new_size;
 402         u8 *vbt_virtual;
 403         u8 bpi;
 404         u8 number_desc = 0;
 405         struct mrst_timing_info *dp_ti = &dev_priv->gct_data.DTD;
 406         struct gct_r10_timing_info ti;
 407         void *pGCT;
 408         struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
 409
 410         /*get the address of the platform config vbt, B0:D2:F0;0xFC */
 411         pci_read_config_dword(pci_gfx_root, 0xFC, &platform_config_address);
 412         pci_dev_put(pci_gfx_root);
 413         DRM_INFO("drm platform config address is %x\n",
 414                         platform_config_address);
 415
 416         /* check for platform config address == 0. */
 417         /* this means fw doesn't support vbt */
 418
 419         if (platform_config_address == 0) {
 420                 vbt->size = 0;
 421                 return;
 422         }
 423
 424         /* get the virtual address of the vbt */
 425         vbt_virtual = ioremap(platform_config_address, sizeof(*vbt));
 426
 427         memcpy(vbt, vbt_virtual, sizeof(*vbt));
 428         iounmap(vbt_virtual); /* Free virtual address space */
 429
 430         printk(KERN_ALERT "GCT revision is %x\n", vbt->revision);
 431
 432         switch (vbt->revision) {
 433         case 0:
 434                 vbt->mrst_gct = NULL;
 435                 vbt->mrst_gct = \
 436                         ioremap(platform_config_address + sizeof(*vbt) - 4,
 437                                         vbt->size - sizeof(*vbt) + 4);
 438                 pGCT = vbt->mrst_gct;
 439                 bpi = ((struct mrst_gct_v1 *)pGCT)->PD.BootPanelIndex;
 440                 dev_priv->gct_data.bpi = bpi;
 441                 dev_priv->gct_data.pt =
 442                         ((struct mrst_gct_v1 *)pGCT)->PD.PanelType;
 443                 memcpy(&dev_priv->gct_data.DTD,
 444                         &((struct mrst_gct_v1 *)pGCT)->panel[bpi].DTD,
 445                                 sizeof(struct mrst_timing_info));
 446                 dev_priv->gct_data.Panel_Port_Control =
 447                   ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_Port_Control;
 448                 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
 449                   ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
 450                 break;
 451         case 1:
 452                 vbt->mrst_gct = NULL;
 453                 vbt->mrst_gct = \
 454                         ioremap(platform_config_address + sizeof(*vbt) - 4,
 455                                         vbt->size - sizeof(*vbt) + 4);
 456                 pGCT = vbt->mrst_gct;
 457                 bpi = ((struct mrst_gct_v2 *)pGCT)->PD.BootPanelIndex;
 458                 dev_priv->gct_data.bpi = bpi;
 459                 dev_priv->gct_data.pt =
 460                         ((struct mrst_gct_v2 *)pGCT)->PD.PanelType;
 461                 memcpy(&dev_priv->gct_data.DTD,
 462                         &((struct mrst_gct_v2 *)pGCT)->panel[bpi].DTD,
 463                                 sizeof(struct mrst_timing_info));
 464                 dev_priv->gct_data.Panel_Port_Control =
 465                   ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_Port_Control;
 466                 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
 467                   ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
 468                 break;
 469         case 0x10:
 470                 /*header definition changed from rev 01 (v2) to rev 10h. */
 471                 /*so, some values have changed location*/
 472                 new_size = vbt->checksum; /*checksum contains lo size byte*/
 473                 /*LSB of mrst_gct contains hi size byte*/
 474                 new_size |= ((0xff & (unsigned int)vbt->mrst_gct)) << 8;
 475
 476                 vbt->checksum = vbt->size; /*size contains the checksum*/
 477                 if (new_size > 0xff)
 478                         vbt->size = 0xff; /*restrict size to 255*/
 479                 else
 480                         vbt->size = new_size;
 481
 482                 /* number of descriptors defined in the GCT */
 483                 number_desc = ((0xff00 & (unsigned int)vbt->mrst_gct)) >> 8;
 484                 bpi = ((0xff0000 & (unsigned int)vbt->mrst_gct)) >> 16;
 485                 vbt->mrst_gct = NULL;
 486                 vbt->mrst_gct = \
 487                         ioremap(platform_config_address + GCT_R10_HEADER_SIZE,
 488                                 GCT_R10_DISPLAY_DESC_SIZE * number_desc);
 489                 pGCT = vbt->mrst_gct;
 490                 pGCT = (u8 *)pGCT + (bpi*GCT_R10_DISPLAY_DESC_SIZE);
 491                 dev_priv->gct_data.bpi = bpi; /*save boot panel id*/
 492
 493                 /*copy the GCT display timings into a temp structure*/
 494                 memcpy(&ti, pGCT, sizeof(struct gct_r10_timing_info));
 495
 496                 /*now copy the temp struct into the dev_priv->gct_data*/
 497                 dp_ti->pixel_clock = ti.pixel_clock;
 498                 dp_ti->hactive_hi = ti.hactive_hi;
 499                 dp_ti->hactive_lo = ti.hactive_lo;
 500                 dp_ti->hblank_hi = ti.hblank_hi;
 501                 dp_ti->hblank_lo = ti.hblank_lo;
 502                 dp_ti->hsync_offset_hi = ti.hsync_offset_hi;
 503                 dp_ti->hsync_offset_lo = ti.hsync_offset_lo;
 504                 dp_ti->hsync_pulse_width_hi = ti.hsync_pulse_width_hi;
 505                 dp_ti->hsync_pulse_width_lo = ti.hsync_pulse_width_lo;
 506                 dp_ti->vactive_hi = ti.vactive_hi;
 507                 dp_ti->vactive_lo = ti.vactive_lo;
 508                 dp_ti->vblank_hi = ti.vblank_hi;
 509                 dp_ti->vblank_lo = ti.vblank_lo;
 510                 dp_ti->vsync_offset_hi = ti.vsync_offset_hi;
 511                 dp_ti->vsync_offset_lo = ti.vsync_offset_lo;
 512                 dp_ti->vsync_pulse_width_hi = ti.vsync_pulse_width_hi;
 513                 dp_ti->vsync_pulse_width_lo = ti.vsync_pulse_width_lo;
 514
 515                 /*mov the MIPI_Display_Descriptor data from GCT to dev priv*/
 516                 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
 517                                                         *((u8 *)pGCT + 0x0d);
 518                 dev_priv->gct_data.Panel_MIPI_Display_Descriptor |=
 519                                                 (*((u8 *)pGCT + 0x0e)) << 8;
 520                 break;
 521         default:
 522                 printk(KERN_ERR "Unknown revision of GCT!\n");
 523                 vbt->size = 0;
 524         }
 525 }
 526
 527 static void psb_get_core_freq(struct drm_device *dev)
 528 {
 529         uint32_t clock;
 530         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 531         struct drm_psb_private *dev_priv = dev->dev_private;
 532
 533         /*pci_write_config_dword(pci_root, 0xD4, 0x00C32004);*/
 534         /*pci_write_config_dword(pci_root, 0xD0, 0xE0033000);*/
 535
 536         pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
 537         pci_read_config_dword(pci_root, 0xD4, &clock);
 538         pci_dev_put(pci_root);
 539
 540         switch (clock & 0x07) {
 541         case 0:
 542                 dev_priv->core_freq = 100;
 543                 break;
 544         case 1:
 545                 dev_priv->core_freq = 133;
 546                 break;
 547         case 2:
 548                 dev_priv->core_freq = 150;
 549                 break;
 550         case 3:
 551                 dev_priv->core_freq = 178;
 552                 break;
 553         case 4:
 554                 dev_priv->core_freq = 200;
 555                 break;
 556         case 5:
 557         case 6:
 558         case 7:
 559                 dev_priv->core_freq = 266;
 560         default:
 561                 dev_priv->core_freq = 0;
 562         }
 563 }
 564
 565 static int psb_do_init(struct drm_device *dev)
 566 {
 567         struct drm_psb_private *dev_priv =
 568             (struct drm_psb_private *) dev->dev_private;
 569         struct ttm_bo_device *bdev = &dev_priv->bdev;
 570         struct psb_gtt *pg = dev_priv->pg;
 571
 572         uint32_t stolen_gtt;
 573         uint32_t tt_start;
 574         uint32_t tt_pages;
 575
 576         int ret = -ENOMEM;
 577
 578
 579         /*
 580          * Initialize sequence numbers for the different command
 581          * submission mechanisms.
 582          */
 583
 584         dev_priv->sequence[PSB_ENGINE_2D] = 0;
 585         dev_priv->sequence[PSB_ENGINE_VIDEO] = 0;
 586         dev_priv->sequence[LNC_ENGINE_ENCODE] = 0;
 587
 588         if (pg->mmu_gatt_start & 0x0FFFFFFF) {
 589                 DRM_ERROR("Gatt must be 256M aligned. This is a bug.\n");
 590                 ret = -EINVAL;
 591                 goto out_err;
 592         }
 593
 594
 595         stolen_gtt = (pg->stolen_size >> PAGE_SHIFT) * 4;
 596         stolen_gtt = (stolen_gtt + PAGE_SIZE - 1) >> PAGE_SHIFT;
 597         stolen_gtt =
 598             (stolen_gtt < pg->gtt_pages) ? stolen_gtt : pg->gtt_pages;
 599
 600         dev_priv->gatt_free_offset = pg->mmu_gatt_start +
 601             (stolen_gtt << PAGE_SHIFT) * 1024;
 602
 603         if (1 || drm_debug) {
 604                 uint32_t core_id = PSB_RSGX32(PSB_CR_CORE_ID);
 605                 uint32_t core_rev = PSB_RSGX32(PSB_CR_CORE_REVISION);
 606                 DRM_INFO("SGX core id = 0x%08x\n", core_id);
 607                 DRM_INFO("SGX core rev major = 0x%02x, minor = 0x%02x\n",
 608                          (core_rev & _PSB_CC_REVISION_MAJOR_MASK) >>
 609                          _PSB_CC_REVISION_MAJOR_SHIFT,
 610                          (core_rev & _PSB_CC_REVISION_MINOR_MASK) >>
 611                          _PSB_CC_REVISION_MINOR_SHIFT);
 612                 DRM_INFO
 613                     ("SGX core rev maintenance = 0x%02x, designer = 0x%02x\n",
 614                      (core_rev & _PSB_CC_REVISION_MAINTENANCE_MASK) >>
 615                      _PSB_CC_REVISION_MAINTENANCE_SHIFT,
 616                      (core_rev & _PSB_CC_REVISION_DESIGNER_MASK) >>
 617                      _PSB_CC_REVISION_DESIGNER_SHIFT);
 618         }
 619
 620
 621         spin_lock_init(&dev_priv->irqmask_lock);
 622
 623         tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
 624             pg->gatt_pages : PSB_TT_PRIV0_PLIMIT;
 625         tt_start = dev_priv->gatt_free_offset - pg->mmu_gatt_start;
 626         tt_pages -= tt_start >> PAGE_SHIFT;
 627         dev_priv->sizes.ta_mem_size = 0;
 628
 629         PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0);
 630         PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1);
 631         PSB_RSGX32(PSB_CR_BIF_BANK1);
 632         PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) | _PSB_MMU_ER_MASK,
 633                                                         PSB_CR_BIF_CTRL);
 634         psb_spank(dev_priv);
 635
 636         PSB_WSGX32(pg->mmu_gatt_start, PSB_CR_BIF_TWOD_REQ_BASE);
 637
 638         /* TT region managed by TTM. */
 639         if (!ttm_bo_init_mm(bdev, TTM_PL_TT,
 640                         pg->gatt_pages -
 641                         (pg->ci_start >> PAGE_SHIFT) -
 642                         ((dev_priv->ci_region_size + dev_priv->rar_region_size)
 643                          >> PAGE_SHIFT))) {
 644
 645                 dev_priv->have_tt = 1;
 646                 dev_priv->sizes.tt_size =
 647                         (tt_pages << PAGE_SHIFT) / (1024 * 1024) / 2;
 648         }
 649
 650         if (!ttm_bo_init_mm(bdev,
 651                         DRM_PSB_MEM_MMU,
 652                         PSB_MEM_TT_START >> PAGE_SHIFT)) {
 653                 dev_priv->have_mem_mmu = 1;
 654                 dev_priv->sizes.mmu_size =
 655                         PSB_MEM_TT_START / (1024*1024);
 656         }
 657
 658         PSB_DEBUG_INIT("Init MSVDX\n");
 659         return 0;
 660 out_err:
 661         psb_do_takedown(dev);
 662         return ret;
 663 }
 664
 665 static int psb_driver_unload(struct drm_device *dev)
 666 {
 667         struct drm_psb_private *dev_priv =
 668             (struct drm_psb_private *) dev->dev_private;
 669
 670         /* Kill vblank etc here */
 671
 672         psb_backlight_exit(); /*writes minimum value to backlight HW reg */
 673
 674         if (drm_psb_no_fb == 0)
 675                 psb_modeset_cleanup(dev);
 676
 677         if (dev_priv) {
 678                 psb_lid_timer_takedown(dev_priv);
 679
 680                 psb_do_takedown(dev);
 681
 682
 683                 if (dev_priv->pf_pd) {
 684                         psb_mmu_free_pagedir(dev_priv->pf_pd);
 685                         dev_priv->pf_pd = NULL;
 686                 }
 687                 if (dev_priv->mmu) {
 688                         struct psb_gtt *pg = dev_priv->pg;
 689
 690                         down_read(&pg->sem);
 691                         psb_mmu_remove_pfn_sequence(
 692                                         psb_mmu_get_default_pd
 693                                         (dev_priv->mmu),
 694                                         pg->mmu_gatt_start,
 695                                         pg->vram_stolen_size >> PAGE_SHIFT);
 696                         if (pg->ci_stolen_size != 0)
 697                                 psb_mmu_remove_pfn_sequence(
 698                                         psb_mmu_get_default_pd
 699                                         (dev_priv->mmu),
 700                                         pg->ci_start,
 701                                         pg->ci_stolen_size >> PAGE_SHIFT);
 702                         if (pg->rar_stolen_size != 0)
 703                                 psb_mmu_remove_pfn_sequence(
 704                                         psb_mmu_get_default_pd
 705                                         (dev_priv->mmu),
 706                                         pg->rar_start,
 707                                         pg->rar_stolen_size >> PAGE_SHIFT);
 708                         up_read(&pg->sem);
 709                         psb_mmu_driver_takedown(dev_priv->mmu);
 710                         dev_priv->mmu = NULL;
 711                 }
 712                 psb_gtt_takedown(dev_priv->pg, 1);
 713                 if (dev_priv->scratch_page) {
 714                         __free_page(dev_priv->scratch_page);
 715                         dev_priv->scratch_page = NULL;
 716                 }
 717                 if (dev_priv->has_bo_device) {
 718                         ttm_bo_device_release(&dev_priv->bdev);
 719                         dev_priv->has_bo_device = 0;
 720                 }
 721                 if (dev_priv->has_fence_device) {
 722                         ttm_fence_device_release(&dev_priv->fdev);
 723                         dev_priv->has_fence_device = 0;
 724                 }
 725                 if (dev_priv->vdc_reg) {
 726                         iounmap(dev_priv->vdc_reg);
 727                         dev_priv->vdc_reg = NULL;
 728                 }
 729                 if (dev_priv->sgx_reg) {
 730                         iounmap(dev_priv->sgx_reg);
 731                         dev_priv->sgx_reg = NULL;
 732                 }
 733
 734                 if (dev_priv->tdev)
 735                         ttm_object_device_release(&dev_priv->tdev);
 736
 737                 if (dev_priv->has_global)
 738                         psb_ttm_global_release(dev_priv);
 739
 740                 kfree(dev_priv);
 741                 dev->dev_private = NULL;
 742
 743                 /*destory VBT data*/
 744                 psb_intel_destroy_bios(dev);
 745         }
 746
 747         ospm_power_uninit();
 748
 749         return 0;
 750 }
 751
 752
 753 static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
 754 {
 755         struct drm_psb_private *dev_priv;
 756         struct ttm_bo_device *bdev;
 757         unsigned long resource_start;
 758         struct psb_gtt *pg;
 759         unsigned long irqflags;
 760         int ret = -ENOMEM;
 761         uint32_t tt_pages;
 762
 763         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 764         if (dev_priv == NULL)
 765                 return -ENOMEM;
 766         INIT_LIST_HEAD(&dev_priv->video_ctx);
 767
 768         if (IS_MRST(dev))
 769                 dev_priv->num_pipe = 1;
 770         else
 771                 dev_priv->num_pipe = 2;
 772
 773         dev_priv->dev = dev;
 774         bdev = &dev_priv->bdev;
 775
 776         ret = psb_ttm_global_init(dev_priv);
 777         if (unlikely(ret != 0))
 778                 goto out_err;
 779         dev_priv->has_global = 1;
 780
 781         dev_priv->tdev = ttm_object_device_init
 782                 (dev_priv->mem_global_ref.object, PSB_OBJECT_HASH_ORDER);
 783         if (unlikely(dev_priv->tdev == NULL))
 784                 goto out_err;
 785
 786         mutex_init(&dev_priv->temp_mem);
 787         mutex_init(&dev_priv->cmdbuf_mutex);
 788         mutex_init(&dev_priv->reset_mutex);
 789         INIT_LIST_HEAD(&dev_priv->context.validate_list);
 790         INIT_LIST_HEAD(&dev_priv->context.kern_validate_list);
 791
 792 /*      mutex_init(&dev_priv->dsr_mutex); */
 793
 794         spin_lock_init(&dev_priv->reloc_lock);
 795
 796         DRM_INIT_WAITQUEUE(&dev_priv->rel_mapped_queue);
 797
 798         dev->dev_private = (void *) dev_priv;
 799         dev_priv->chipset = chipset;
 800         psb_set_uopt(&dev_priv->uopt);
 801
 802         PSB_DEBUG_INIT("Mapping MMIO\n");
 803         resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE);
 804
 805         dev_priv->vdc_reg =
 806             ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE);
 807         if (!dev_priv->vdc_reg)
 808                 goto out_err;
 809
 810         dev_priv->sgx_reg = ioremap(resource_start + PSB_SGX_OFFSET,
 811                                                         PSB_SGX_SIZE);
 812
 813         if (!dev_priv->sgx_reg)
 814                 goto out_err;
 815
 816         if (IS_MRST(dev)) {
 817                 mrst_get_fuse_settings(dev);
 818                 mrst_get_vbt_data(dev_priv);
 819                 mid_get_pci_revID(dev_priv);
 820         } else {
 821                 psb_get_core_freq(dev);
 822                 psb_intel_opregion_init(dev);
 823                 psb_intel_init_bios(dev);
 824         }
 825
 826         PSB_DEBUG_INIT("Init TTM fence and BO driver\n");
 827
 828         /* Init OSPM support */
 829         ospm_power_init(dev);
 830
 831         ret = psb_ttm_fence_device_init(&dev_priv->fdev);
 832         if (unlikely(ret != 0))
 833                 goto out_err;
 834
 835         dev_priv->has_fence_device = 1;
 836         ret = ttm_bo_device_init(bdev,
 837                                  dev_priv->bo_global_ref.ref.object,
 838                                  &psb_ttm_bo_driver,
 839                                  DRM_PSB_FILE_PAGE_OFFSET, false);
 840         if (unlikely(ret != 0))
 841                 goto out_err;
 842         dev_priv->has_bo_device = 1;
 843         ttm_lock_init(&dev_priv->ttm_lock);
 844
 845         ret = -ENOMEM;
 846
 847         dev_priv->scratch_page = alloc_page(GFP_DMA32 | __GFP_ZERO);
 848         if (!dev_priv->scratch_page)
 849                 goto out_err;
 850
 851         set_pages_uc(dev_priv->scratch_page, 1);
 852
 853         dev_priv->pg = psb_gtt_alloc(dev);
 854         if (!dev_priv->pg)
 855                 goto out_err;
 856
 857         ret = psb_gtt_init(dev_priv->pg, 0);
 858         if (ret)
 859                 goto out_err;
 860
 861         ret = psb_gtt_mm_init(dev_priv->pg);
 862         if (ret)
 863                 goto out_err;
 864
 865         dev_priv->mmu = psb_mmu_driver_init((void *)0,
 866                                         drm_psb_trap_pagefaults, 0,
 867                                         dev_priv);
 868         if (!dev_priv->mmu)
 869                 goto out_err;
 870
 871         pg = dev_priv->pg;
 872
 873         tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
 874                 (pg->gatt_pages) : PSB_TT_PRIV0_PLIMIT;
 875
 876         /* CI/RAR use the lower half of TT. */
 877         pg->ci_start = (tt_pages / 2) << PAGE_SHIFT;
 878         pg->rar_start = pg->ci_start + pg->ci_stolen_size;
 879
 880
 881         /*
 882          * Make MSVDX/TOPAZ MMU aware of the CI stolen memory area.
 883          */
 884         if (dev_priv->pg->ci_stolen_size != 0) {
 885                 down_read(&pg->sem);
 886                 ret = psb_mmu_insert_pfn_sequence(psb_mmu_get_default_pd
 887                                 (dev_priv->mmu),
 888                                 dev_priv->ci_region_start >> PAGE_SHIFT,
 889                                 pg->mmu_gatt_start + pg->ci_start,
 890                                 pg->ci_stolen_size >> PAGE_SHIFT, 0);
 891                 up_read(&pg->sem);
 892                 if (ret)
 893                         goto out_err;
 894         }
 895
 896         /*
 897          * Make MSVDX/TOPAZ MMU aware of the rar stolen memory area.
 898          */
 899         if (dev_priv->pg->rar_stolen_size != 0) {
 900                 down_read(&pg->sem);
 901                 ret = psb_mmu_insert_pfn_sequence(
 902                                 psb_mmu_get_default_pd(dev_priv->mmu),
 903                                 dev_priv->rar_region_start >> PAGE_SHIFT,
 904                                 pg->mmu_gatt_start + pg->rar_start,
 905                                 pg->rar_stolen_size >> PAGE_SHIFT, 0);
 906                 up_read(&pg->sem);
 907                 if (ret)
 908                         goto out_err;
 909         }
 910
 911         dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0);
 912         if (!dev_priv->pf_pd)
 913                 goto out_err;
 914
 915         psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0);
 916         psb_mmu_set_pd_context(dev_priv->pf_pd, 1);
 917
 918         spin_lock_init(&dev_priv->sequence_lock);
 919
 920         PSB_DEBUG_INIT("Begin to init MSVDX/Topaz\n");
 921
 922         ret = psb_do_init(dev);
 923         if (ret)
 924                 return ret;
 925
 926 /*      igd_opregion_init(&dev_priv->opregion_dev); */
 927         acpi_video_register();
 928         if (dev_priv->lid_state)
 929                 psb_lid_timer_init(dev_priv);
 930
 931         ret = drm_vblank_init(dev, dev_priv->num_pipe);
 932         if (ret)
 933                 goto out_err;
 934
 935         /*
 936          * Install interrupt handlers prior to powering off SGX or else we will
 937          * crash.
 938          */
 939         dev_priv->vdc_irq_mask = 0;
 940         dev_priv->pipestat[0] = 0;
 941         dev_priv->pipestat[1] = 0;
 942         dev_priv->pipestat[2] = 0;
 943         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 944         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 945         PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
 946         PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R);
 947         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 948         if (drm_core_check_feature(dev, DRIVER_MODESET))
 949                 drm_irq_install(dev);
 950
 951         dev->vblank_disable_allowed = 1;
 952
 953         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
 954
 955         dev->driver->get_vblank_counter = psb_get_vblank_counter;
 956
 957         if (drm_psb_no_fb == 0) {
 958                 psb_modeset_init(dev);
 959                 psb_fbdev_init(dev);
 960                 drm_kms_helper_poll_init(dev);
 961         }
 962
 963         ret = psb_backlight_init(dev);
 964         if (ret)
 965                 return ret;
 966 #if 0
 967         /*enable runtime pm at last*/
 968         pm_runtime_enable(&dev->pdev->dev);
 969         pm_runtime_set_active(&dev->pdev->dev);
 970 #endif
 971         /*Intel drm driver load is done, continue doing pvr load*/
 972         DRM_DEBUG("Pvr driver load\n");
 973
 974 /*      if (PVRCore_Init() < 0)
 975                 goto out_err; */
 976 /*      if (MRSTLFBInit(dev) < 0)
 977                 goto out_err;*/
 978         return 0;
 979 out_err:
 980         psb_driver_unload(dev);
 981         return ret;
 982 }
 983
 984 int psb_driver_device_is_agp(struct drm_device *dev)
 985 {
 986         return 0;
 987 }
 988
 989
 990 static int psb_vt_leave_ioctl(struct drm_device *dev, void *data,
 991                               struct drm_file *file_priv)
 992 {
 993         struct drm_psb_private *dev_priv = psb_priv(dev);
 994         struct ttm_bo_device *bdev = &dev_priv->bdev;
 995         struct ttm_mem_type_manager *man;
 996         int ret;
 997
 998         ret = ttm_vt_lock(&dev_priv->ttm_lock, 1,
 999                              psb_fpriv(file_priv)->tfile);
1000         if (unlikely(ret != 0))
1001                 return ret;
1002
1003         ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_TT);
1004         if (unlikely(ret != 0))
1005                 goto out_unlock;
1006
1007         man = &bdev->man[TTM_PL_TT];
1008
1009 #if 0           /* What to do with this ? */
1010         if (unlikely(!drm_mm_clean(&man->manager)))
1011                 DRM_INFO("Warning: GATT was not clean after VT switch.\n");
1012 #endif
1013
1014         ttm_bo_swapout_all(&dev_priv->bdev);
1015
1016         return 0;
1017 out_unlock:
1018         (void) ttm_vt_unlock(&dev_priv->ttm_lock);
1019         return ret;
1020 }
1021
1022 static int psb_vt_enter_ioctl(struct drm_device *dev, void *data,
1023                               struct drm_file *file_priv)
1024 {
1025         struct drm_psb_private *dev_priv = psb_priv(dev);
1026         return ttm_vt_unlock(&dev_priv->ttm_lock);
1027 }
1028
1029 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
1030                            struct drm_file *file_priv)
1031 {
1032         struct drm_psb_private *dev_priv = psb_priv(dev);
1033         struct drm_psb_sizes_arg *arg =
1034                 (struct drm_psb_sizes_arg *) data;
1035
1036         *arg = dev_priv->sizes;
1037         return 0;
1038 }
1039
1040 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
1041                                 struct drm_file *file_priv)
1042 {
1043         uint32_t flags;
1044         uint32_t obj_id;
1045         struct drm_mode_object *obj;
1046         struct drm_connector *connector;
1047         struct drm_crtc *crtc;
1048         struct drm_psb_dc_state_arg *arg =
1049                 (struct drm_psb_dc_state_arg *)data;
1050
1051         flags = arg->flags;
1052         obj_id = arg->obj_id;
1053
1054         if (flags & PSB_DC_CRTC_MASK) {
1055                 obj = drm_mode_object_find(dev, obj_id,
1056                                 DRM_MODE_OBJECT_CRTC);
1057                 if (!obj) {
1058                         DRM_DEBUG("Invalid CRTC object.\n");
1059                         return -EINVAL;
1060                 }
1061
1062                 crtc = obj_to_crtc(obj);
1063
1064                 mutex_lock(&dev->mode_config.mutex);
1065                 if (drm_helper_crtc_in_use(crtc)) {
1066                         if (flags & PSB_DC_CRTC_SAVE)
1067                                 crtc->funcs->save(crtc);
1068                         else
1069                                 crtc->funcs->restore(crtc);
1070                 }
1071                 mutex_unlock(&dev->mode_config.mutex);
1072
1073                 return 0;
1074         } else if (flags & PSB_DC_OUTPUT_MASK) {
1075                 obj = drm_mode_object_find(dev, obj_id,
1076                                 DRM_MODE_OBJECT_CONNECTOR);
1077                 if (!obj) {
1078                         DRM_DEBUG("Invalid connector id.\n");
1079                         return -EINVAL;
1080                 }
1081
1082                 connector = obj_to_connector(obj);
1083                 if (flags & PSB_DC_OUTPUT_SAVE)
1084                         connector->funcs->save(connector);
1085                 else
1086                         connector->funcs->restore(connector);
1087
1088                 return 0;
1089         }
1090
1091         DRM_DEBUG("Bad flags 0x%x\n", flags);
1092         return -EINVAL;
1093 }
1094
1095 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
1096                        struct drm_file *file_priv)
1097 {
1098         struct drm_psb_private *dev_priv = psb_priv(dev);
1099         uint32_t *arg = data;
1100         struct backlight_device bd;
1101         dev_priv->blc_adj2 = *arg;
1102
1103 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
1104         bd.props.brightness = psb_get_brightness(&bd);
1105         psb_set_brightness(&bd);
1106 #endif
1107         return 0;
1108 }
1109
1110 static int psb_adb_ioctl(struct drm_device *dev, void *data,
1111                         struct drm_file *file_priv)
1112 {
1113         struct drm_psb_private *dev_priv = psb_priv(dev);
1114         uint32_t *arg = data;
1115         struct backlight_device bd;
1116         dev_priv->blc_adj1 = *arg;
1117
1118 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
1119         bd.props.brightness = psb_get_brightness(&bd);
1120         psb_set_brightness(&bd);
1121 #endif
1122         return 0;
1123 }
1124
1125 /* return the current mode to the dpst module */
1126 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
1127                           struct drm_file *file_priv)
1128 {
1129         struct drm_psb_private *dev_priv = psb_priv(dev);
1130         uint32_t *arg = data;
1131         uint32_t x;
1132         uint32_t y;
1133         uint32_t reg;
1134
1135         if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
1136                                                         OSPM_UHB_ONLY_IF_ON))
1137                 return 0;
1138
1139         reg = PSB_RVDC32(PIPEASRC);
1140
1141         ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
1142
1143         /* horizontal is the left 16 bits */
1144         x = reg >> 16;
1145         /* vertical is the right 16 bits */
1146         y = reg & 0x0000ffff;
1147
1148         /* the values are the image size minus one */
1149         x++;
1150         y++;
1151
1152         *arg = (x << 16) | y;
1153
1154         return 0;
1155 }
1156 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
1157                            struct drm_file *file_priv)
1158 {
1159         struct drm_psb_dpst_lut_arg *lut_arg = data;
1160         struct drm_mode_object *obj;
1161         struct drm_crtc *crtc;
1162         struct drm_connector *connector;
1163         struct psb_intel_crtc *psb_intel_crtc;
1164         int i = 0;
1165         int32_t obj_id;
1166
1167         obj_id = lut_arg->output_id;
1168         obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_CONNECTOR);
1169         if (!obj) {
1170                 DRM_DEBUG("Invalid Connector object.\n");
1171                 return -EINVAL;
1172         }
1173
1174         connector = obj_to_connector(obj);
1175         crtc = connector->encoder->crtc;
1176         psb_intel_crtc = to_psb_intel_crtc(crtc);
1177
1178         for (i = 0; i < 256; i++)
1179                 psb_intel_crtc->lut_adj[i] = lut_arg->lut[i];
1180
1181         psb_intel_crtc_load_lut(crtc);
1182
1183         return 0;
1184 }
1185
1186 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
1187                                 struct drm_file *file_priv)
1188 {
1189         uint32_t obj_id;
1190         uint16_t op;
1191         struct drm_mode_modeinfo *umode;
1192         struct drm_display_mode *mode = NULL;
1193         struct drm_psb_mode_operation_arg *arg;
1194         struct drm_mode_object *obj;
1195         struct drm_connector *connector;
1196         struct drm_framebuffer *drm_fb;
1197         struct psb_framebuffer *psb_fb;
1198         struct drm_connector_helper_funcs *connector_funcs;
1199         int ret = 0;
1200         int resp = MODE_OK;
1201         struct drm_psb_private *dev_priv = psb_priv(dev);
1202
1203         arg = (struct drm_psb_mode_operation_arg *)data;
1204         obj_id = arg->obj_id;
1205         op = arg->operation;
1206
1207         switch (op) {
1208         case PSB_MODE_OPERATION_SET_DC_BASE:
1209                 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_FB);
1210                 if (!obj) {
1211                         DRM_ERROR("Invalid FB id %d\n", obj_id);
1212                         return -EINVAL;
1213                 }
1214
1215                 drm_fb = obj_to_fb(obj);
1216                 psb_fb = to_psb_fb(drm_fb);
1217
1218                 if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
1219                                               OSPM_UHB_ONLY_IF_ON)) {
1220                         REG_WRITE(DSPASURF, psb_fb->offset);
1221                         REG_READ(DSPASURF);
1222                         ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
1223                 } else {
1224                         dev_priv->saveDSPASURF = psb_fb->offset;
1225                 }
1226
1227                 return 0;
1228         case PSB_MODE_OPERATION_MODE_VALID:
1229                 umode = &arg->mode;
1230
1231                 mutex_lock(&dev->mode_config.mutex);
1232
1233                 obj = drm_mode_object_find(dev, obj_id,
1234                                         DRM_MODE_OBJECT_CONNECTOR);
1235                 if (!obj) {
1236                         ret = -EINVAL;
1237                         goto mode_op_out;
1238                 }
1239
1240                 connector = obj_to_connector(obj);
1241
1242                 mode = drm_mode_create(dev);
1243                 if (!mode) {
1244                         ret = -ENOMEM;
1245                         goto mode_op_out;
1246                 }
1247
1248                 /* drm_crtc_convert_umode(mode, umode); */
1249                 {
1250                         mode->clock = umode->clock;
1251                         mode->hdisplay = umode->hdisplay;
1252                         mode->hsync_start = umode->hsync_start;
1253                         mode->hsync_end = umode->hsync_end;
1254                         mode->htotal = umode->htotal;
1255                         mode->hskew = umode->hskew;
1256                         mode->vdisplay = umode->vdisplay;
1257                         mode->vsync_start = umode->vsync_start;
1258                         mode->vsync_end = umode->vsync_end;
1259                         mode->vtotal = umode->vtotal;
1260                         mode->vscan = umode->vscan;
1261                         mode->vrefresh = umode->vrefresh;
1262                         mode->flags = umode->flags;
1263                         mode->type = umode->type;
1264                         strncpy(mode->name, umode->name, DRM_DISPLAY_MODE_LEN);
1265                         mode->name[DRM_DISPLAY_MODE_LEN-1] = 0;
1266                 }
1267
1268                 connector_funcs = (struct drm_connector_helper_funcs *)
1269                                    connector->helper_private;
1270
1271                 if (connector_funcs->mode_valid) {
1272                         resp = connector_funcs->mode_valid(connector, mode);
1273                         arg->data = (void *)resp;
1274                 }
1275
1276                 /*do some clean up work*/
1277                 if (mode)
1278                         drm_mode_destroy(dev, mode);
1279 mode_op_out:
1280                 mutex_unlock(&dev->mode_config.mutex);
1281                 return ret;
1282
1283         default:
1284                 DRM_DEBUG("Unsupported psb mode operation");
1285                 return -EOPNOTSUPP;
1286         }
1287
1288         return 0;
1289 }
1290
1291 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
1292                                    struct drm_file *file_priv)
1293 {
1294         struct drm_psb_private *dev_priv = psb_priv(dev);
1295         struct drm_psb_stolen_memory_arg *arg = data;
1296
1297         arg->base = dev_priv->pg->stolen_base;
1298         arg->size = dev_priv->pg->vram_stolen_size;
1299
1300         return 0;
1301 }
1302
1303 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
1304                                  struct drm_file *file_priv)
1305 {
1306         struct drm_psb_private *dev_priv = psb_priv(dev);
1307         struct drm_psb_register_rw_arg *arg = data;
1308         UHBUsage usage =
1309           arg->b_force_hw_on ? OSPM_UHB_FORCE_POWER_ON : OSPM_UHB_ONLY_IF_ON;
1310
1311         if (arg->display_write_mask != 0) {
1312                 if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
1313                         if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
1314                                 PSB_WVDC32(arg->display.pfit_controls,
1315                                            PFIT_CONTROL);
1316                         if (arg->display_write_mask &
1317                             REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1318                                 PSB_WVDC32(arg->display.pfit_autoscale_ratios,
1319                                            PFIT_AUTO_RATIOS);
1320                         if (arg->display_write_mask &
1321                             REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1322                                 PSB_WVDC32(
1323                                    arg->display.pfit_programmed_scale_ratios,
1324                                    PFIT_PGM_RATIOS);
1325                         if (arg->display_write_mask & REGRWBITS_PIPEASRC)
1326                                 PSB_WVDC32(arg->display.pipeasrc,
1327                                            PIPEASRC);
1328                         if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
1329                                 PSB_WVDC32(arg->display.pipebsrc,
1330                                            PIPEBSRC);
1331                         if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
1332                                 PSB_WVDC32(arg->display.vtotal_a,
1333                                            VTOTAL_A);
1334                         if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
1335                                 PSB_WVDC32(arg->display.vtotal_b,
1336                                            VTOTAL_B);
1337                         ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
1338                 } else {
1339                         if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
1340                                 dev_priv->savePFIT_CONTROL =
1341                                                 arg->display.pfit_controls;
1342                         if (arg->display_write_mask &
1343                             REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1344                                 dev_priv->savePFIT_AUTO_RATIOS =
1345                                         arg->display.pfit_autoscale_ratios;
1346                         if (arg->display_write_mask &
1347                             REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1348                                 dev_priv->savePFIT_PGM_RATIOS =
1349                                    arg->display.pfit_programmed_scale_ratios;
1350                         if (arg->display_write_mask & REGRWBITS_PIPEASRC)
1351                                 dev_priv->savePIPEASRC = arg->display.pipeasrc;
1352                         if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
1353                                 dev_priv->savePIPEBSRC = arg->display.pipebsrc;
1354                         if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
1355                                 dev_priv->saveVTOTAL_A = arg->display.vtotal_a;
1356                         if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
1357                                 dev_priv->saveVTOTAL_B = arg->display.vtotal_b;
1358                 }
1359         }
1360
1361         if (arg->display_read_mask != 0) {
1362                 if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
1363                         if (arg->display_read_mask &
1364                             REGRWBITS_PFIT_CONTROLS)
1365                                 arg->display.pfit_controls =
1366                                                 PSB_RVDC32(PFIT_CONTROL);
1367                         if (arg->display_read_mask &
1368                             REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1369                                 arg->display.pfit_autoscale_ratios =
1370                                                 PSB_RVDC32(PFIT_AUTO_RATIOS);
1371                         if (arg->display_read_mask &
1372                             REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1373                                 arg->display.pfit_programmed_scale_ratios =
1374                                                 PSB_RVDC32(PFIT_PGM_RATIOS);
1375                         if (arg->display_read_mask & REGRWBITS_PIPEASRC)
1376                                 arg->display.pipeasrc = PSB_RVDC32(PIPEASRC);
1377                         if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
1378                                 arg->display.pipebsrc = PSB_RVDC32(PIPEBSRC);
1379                         if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
1380                                 arg->display.vtotal_a = PSB_RVDC32(VTOTAL_A);
1381                         if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
1382                                 arg->display.vtotal_b = PSB_RVDC32(VTOTAL_B);
1383                         ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
1384                 } else {
1385                         if (arg->display_read_mask &
1386                             REGRWBITS_PFIT_CONTROLS)
1387                                 arg->display.pfit_controls =
1388                                                 dev_priv->savePFIT_CONTROL;
1389                         if (arg->display_read_mask &
1390                             REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1391                                 arg->display.pfit_autoscale_ratios =
1392                                                 dev_priv->savePFIT_AUTO_RATIOS;
1393                         if (arg->display_read_mask &
1394                             REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1395                                 arg->display.pfit_programmed_scale_ratios =
1396                                                 dev_priv->savePFIT_PGM_RATIOS;
1397                         if (arg->display_read_mask & REGRWBITS_PIPEASRC)
1398                                 arg->display.pipeasrc = dev_priv->savePIPEASRC;
1399                         if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
1400                                 arg->display.pipebsrc = dev_priv->savePIPEBSRC;
1401                         if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
1402                                 arg->display.vtotal_a = dev_priv->saveVTOTAL_A;
1403                         if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
1404                                 arg->display.vtotal_b = dev_priv->saveVTOTAL_B;
1405                 }
1406         }
1407
1408         if (arg->overlay_write_mask != 0) {
1409                 if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
1410                         if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
1411                                 PSB_WVDC32(arg->overlay.OGAMC5, OV_OGAMC5);
1412                                 PSB_WVDC32(arg->overlay.OGAMC4, OV_OGAMC4);
1413                                 PSB_WVDC32(arg->overlay.OGAMC3, OV_OGAMC3);
1414                                 PSB_WVDC32(arg->overlay.OGAMC2, OV_OGAMC2);
1415                                 PSB_WVDC32(arg->overlay.OGAMC1, OV_OGAMC1);
1416                                 PSB_WVDC32(arg->overlay.OGAMC0, OV_OGAMC0);
1417                         }
1418                         if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
1419                                 PSB_WVDC32(arg->overlay.OGAMC5, OVC_OGAMC5);
1420                                 PSB_WVDC32(arg->overlay.OGAMC4, OVC_OGAMC4);
1421                                 PSB_WVDC32(arg->overlay.OGAMC3, OVC_OGAMC3);
1422                                 PSB_WVDC32(arg->overlay.OGAMC2, OVC_OGAMC2);
1423                                 PSB_WVDC32(arg->overlay.OGAMC1, OVC_OGAMC1);
1424                                 PSB_WVDC32(arg->overlay.OGAMC0, OVC_OGAMC0);
1425                         }
1426
1427                         if (arg->overlay_write_mask & OV_REGRWBITS_OVADD) {
1428                                 PSB_WVDC32(arg->overlay.OVADD, OV_OVADD);
1429
1430                                 if (arg->overlay.b_wait_vblank) {
1431                                         /* Wait for 20ms.*/
1432                                         unsigned long vblank_timeout = jiffies
1433                                                                 + HZ/50;
1434                                         uint32_t temp;
1435                                         while (time_before_eq(jiffies,
1436                                                         vblank_timeout)) {
1437                                                 temp = PSB_RVDC32(OV_DOVASTA);
1438                                                 if ((temp & (0x1 << 31)) != 0)
1439                                                         break;
1440                                                 cpu_relax();
1441                                         }
1442                                 }
1443                         }
1444                         if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD) {
1445                                 PSB_WVDC32(arg->overlay.OVADD, OVC_OVADD);
1446                                 if (arg->overlay.b_wait_vblank) {
1447                                         /* Wait for 20ms.*/
1448                                         unsigned long vblank_timeout =
1449                                                         jiffies + HZ/50;
1450                                         uint32_t temp;
1451                                         while (time_before_eq(jiffies,
1452                                                         vblank_timeout)) {
1453                                                 temp = PSB_RVDC32(OVC_DOVCSTA);
1454                                                 if ((temp & (0x1 << 31)) != 0)
1455                                                         break;
1456                                                 cpu_relax();
1457                                         }
1458                                 }
1459                         }
1460                         ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
1461                 } else {
1462                         if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
1463                                 dev_priv->saveOV_OGAMC5 = arg->overlay.OGAMC5;
1464                                 dev_priv->saveOV_OGAMC4 = arg->overlay.OGAMC4;
1465                                 dev_priv->saveOV_OGAMC3 = arg->overlay.OGAMC3;
1466                                 dev_priv->saveOV_OGAMC2 = arg->overlay.OGAMC2;
1467                                 dev_priv->saveOV_OGAMC1 = arg->overlay.OGAMC1;
1468                                 dev_priv->saveOV_OGAMC0 = arg->overlay.OGAMC0;
1469                         }
1470                         if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
1471                                 dev_priv->saveOVC_OGAMC5 = arg->overlay.OGAMC5;
1472                                 dev_priv->saveOVC_OGAMC4 = arg->overlay.OGAMC4;
1473                                 dev_priv->saveOVC_OGAMC3 = arg->overlay.OGAMC3;
1474                                 dev_priv->saveOVC_OGAMC2 = arg->overlay.OGAMC2;
1475                                 dev_priv->saveOVC_OGAMC1 = arg->overlay.OGAMC1;
1476                                 dev_priv->saveOVC_OGAMC0 = arg->overlay.OGAMC0;
1477                         }
1478                         if (arg->overlay_write_mask & OV_REGRWBITS_OVADD)
1479                                 dev_priv->saveOV_OVADD = arg->overlay.OVADD;
1480                         if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD)
1481                                 dev_priv->saveOVC_OVADD = arg->overlay.OVADD;
1482                 }
1483         }
1484
1485         if (arg->overlay_read_mask != 0) {
1486                 if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
1487                         if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
1488                                 arg->overlay.OGAMC5 = PSB_RVDC32(OV_OGAMC5);
1489                                 arg->overlay.OGAMC4 = PSB_RVDC32(OV_OGAMC4);
1490                                 arg->overlay.OGAMC3 = PSB_RVDC32(OV_OGAMC3);
1491                                 arg->overlay.OGAMC2 = PSB_RVDC32(OV_OGAMC2);
1492                                 arg->overlay.OGAMC1 = PSB_RVDC32(OV_OGAMC1);
1493                                 arg->overlay.OGAMC0 = PSB_RVDC32(OV_OGAMC0);
1494                         }
1495                         if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
1496                                 arg->overlay.OGAMC5 = PSB_RVDC32(OVC_OGAMC5);
1497                                 arg->overlay.OGAMC4 = PSB_RVDC32(OVC_OGAMC4);
1498                                 arg->overlay.OGAMC3 = PSB_RVDC32(OVC_OGAMC3);
1499                                 arg->overlay.OGAMC2 = PSB_RVDC32(OVC_OGAMC2);
1500                                 arg->overlay.OGAMC1 = PSB_RVDC32(OVC_OGAMC1);
1501                                 arg->overlay.OGAMC0 = PSB_RVDC32(OVC_OGAMC0);
1502                         }
1503                         if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
1504                                 arg->overlay.OVADD = PSB_RVDC32(OV_OVADD);
1505                         if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
1506                                 arg->overlay.OVADD = PSB_RVDC32(OVC_OVADD);
1507                         ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
1508                 } else {
1509                         if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
1510                                 arg->overlay.OGAMC5 = dev_priv->saveOV_OGAMC5;
1511                                 arg->overlay.OGAMC4 = dev_priv->saveOV_OGAMC4;
1512                                 arg->overlay.OGAMC3 = dev_priv->saveOV_OGAMC3;
1513                                 arg->overlay.OGAMC2 = dev_priv->saveOV_OGAMC2;
1514                                 arg->overlay.OGAMC1 = dev_priv->saveOV_OGAMC1;
1515                                 arg->overlay.OGAMC0 = dev_priv->saveOV_OGAMC0;
1516                         }
1517                         if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
1518                                 arg->overlay.OGAMC5 = dev_priv->saveOVC_OGAMC5;
1519                                 arg->overlay.OGAMC4 = dev_priv->saveOVC_OGAMC4;
1520                                 arg->overlay.OGAMC3 = dev_priv->saveOVC_OGAMC3;
1521                                 arg->overlay.OGAMC2 = dev_priv->saveOVC_OGAMC2;
1522                                 arg->overlay.OGAMC1 = dev_priv->saveOVC_OGAMC1;
1523                                 arg->overlay.OGAMC0 = dev_priv->saveOVC_OGAMC0;
1524                         }
1525                         if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
1526                                 arg->overlay.OVADD = dev_priv->saveOV_OVADD;
1527                         if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
1528                                 arg->overlay.OVADD = dev_priv->saveOVC_OVADD;
1529                 }
1530         }
1531
1532         if (arg->sprite_enable_mask != 0) {
1533                 if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
1534                         PSB_WVDC32(0x1F3E, DSPARB);
1535                         PSB_WVDC32(arg->sprite.dspa_control
1536                                         | PSB_RVDC32(DSPACNTR), DSPACNTR);
1537                         PSB_WVDC32(arg->sprite.dspa_key_value, DSPAKEYVAL);
1538                         PSB_WVDC32(arg->sprite.dspa_key_mask, DSPAKEYMASK);
1539                         PSB_WVDC32(PSB_RVDC32(DSPASURF), DSPASURF);
1540                         PSB_RVDC32(DSPASURF);
1541                         PSB_WVDC32(arg->sprite.dspc_control, DSPCCNTR);
1542                         PSB_WVDC32(arg->sprite.dspc_stride, DSPCSTRIDE);
1543                         PSB_WVDC32(arg->sprite.dspc_position, DSPCPOS);
1544                         PSB_WVDC32(arg->sprite.dspc_linear_offset, DSPCLINOFF);
1545                         PSB_WVDC32(arg->sprite.dspc_size, DSPCSIZE);
1546                         PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
1547                         PSB_RVDC32(DSPCSURF);
1548                         ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
1549                 }
1550         }
1551
1552         if (arg->sprite_disable_mask != 0) {
1553                 if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
1554                         PSB_WVDC32(0x3F3E, DSPARB);
1555                         PSB_WVDC32(0x0, DSPCCNTR);
1556                         PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
1557                         PSB_RVDC32(DSPCSURF);
1558                         ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
1559                 }
1560         }
1561
1562         if (arg->subpicture_enable_mask != 0) {
1563                 if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
1564                         uint32_t temp;
1565                         if (arg->subpicture_enable_mask & REGRWBITS_DSPACNTR) {
1566                                 temp =  PSB_RVDC32(DSPACNTR);
1567                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1568                                 temp &= ~DISPPLANE_BOTTOM;
1569                                 temp |= DISPPLANE_32BPP;
1570                                 PSB_WVDC32(temp, DSPACNTR);
1571
1572                                 temp =  PSB_RVDC32(DSPABASE);
1573                                 PSB_WVDC32(temp, DSPABASE);
1574                                 PSB_RVDC32(DSPABASE);
1575                                 temp =  PSB_RVDC32(DSPASURF);
1576                                 PSB_WVDC32(temp, DSPASURF);
1577                                 PSB_RVDC32(DSPASURF);
1578                         }
1579                         if (arg->subpicture_enable_mask & REGRWBITS_DSPBCNTR) {
1580                                 temp =  PSB_RVDC32(DSPBCNTR);
1581                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1582                                 temp &= ~DISPPLANE_BOTTOM;
1583                                 temp |= DISPPLANE_32BPP;
1584                                 PSB_WVDC32(temp, DSPBCNTR);
1585
1586                                 temp =  PSB_RVDC32(DSPBBASE);
1587                                 PSB_WVDC32(temp, DSPBBASE);
1588                                 PSB_RVDC32(DSPBBASE);
1589                                 temp =  PSB_RVDC32(DSPBSURF);
1590                                 PSB_WVDC32(temp, DSPBSURF);
1591                                 PSB_RVDC32(DSPBSURF);
1592                         }
1593                         if (arg->subpicture_enable_mask & REGRWBITS_DSPCCNTR) {
1594                                 temp =  PSB_RVDC32(DSPCCNTR);
1595                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1596                                 temp &= ~DISPPLANE_BOTTOM;
1597                                 temp |= DISPPLANE_32BPP;
1598                                 PSB_WVDC32(temp, DSPCCNTR);
1599
1600                                 temp =  PSB_RVDC32(DSPCBASE);
1601                                 PSB_WVDC32(temp, DSPCBASE);
1602                                 PSB_RVDC32(DSPCBASE);
1603                                 temp =  PSB_RVDC32(DSPCSURF);
1604                                 PSB_WVDC32(temp, DSPCSURF);
1605                                 PSB_RVDC32(DSPCSURF);
1606                         }
1607                         ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
1608                 }
1609         }
1610
1611         if (arg->subpicture_disable_mask != 0) {
1612                 if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
1613                         uint32_t temp;
1614                         if (arg->subpicture_disable_mask & REGRWBITS_DSPACNTR) {
1615                                 temp =  PSB_RVDC32(DSPACNTR);
1616                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1617                                 temp |= DISPPLANE_32BPP_NO_ALPHA;
1618                                 PSB_WVDC32(temp, DSPACNTR);
1619
1620                                 temp =  PSB_RVDC32(DSPABASE);
1621                                 PSB_WVDC32(temp, DSPABASE);
1622                                 PSB_RVDC32(DSPABASE);
1623                                 temp =  PSB_RVDC32(DSPASURF);
1624                                 PSB_WVDC32(temp, DSPASURF);
1625                                 PSB_RVDC32(DSPASURF);
1626                         }
1627                         if (arg->subpicture_disable_mask & REGRWBITS_DSPBCNTR) {
1628                                 temp =  PSB_RVDC32(DSPBCNTR);
1629                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1630                                 temp |= DISPPLANE_32BPP_NO_ALPHA;
1631                                 PSB_WVDC32(temp, DSPBCNTR);
1632
1633                                 temp =  PSB_RVDC32(DSPBBASE);
1634                                 PSB_WVDC32(temp, DSPBBASE);
1635                                 PSB_RVDC32(DSPBBASE);
1636                                 temp =  PSB_RVDC32(DSPBSURF);
1637                                 PSB_WVDC32(temp, DSPBSURF);
1638                                 PSB_RVDC32(DSPBSURF);
1639                         }
1640                         if (arg->subpicture_disable_mask & REGRWBITS_DSPCCNTR) {
1641                                 temp =  PSB_RVDC32(DSPCCNTR);
1642                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1643                                 temp |= DISPPLANE_32BPP_NO_ALPHA;
1644                                 PSB_WVDC32(temp, DSPCCNTR);
1645
1646                                 temp =  PSB_RVDC32(DSPCBASE);
1647                                 PSB_WVDC32(temp, DSPCBASE);
1648                                 PSB_RVDC32(DSPCBASE);
1649                                 temp =  PSB_RVDC32(DSPCSURF);
1650                                 PSB_WVDC32(temp, DSPCSURF);
1651                                 PSB_RVDC32(DSPCSURF);
1652                         }
1653                         ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
1654                 }
1655         }
1656
1657         return 0;
1658 }
1659
1660 /* always available as we are SIGIO'd */
1661 static unsigned int psb_poll(struct file *filp,
1662                              struct poll_table_struct *wait)
1663 {
1664         return POLLIN | POLLRDNORM;
1665 }
1666
1667 /* Not sure what we will need yet - in the PVR driver this disappears into
1668    a tangle of abstracted handlers and per process crap */
1669
1670 struct psb_priv {
1671         int dummy;
1672 };
1673
1674 static int psb_driver_open(struct drm_device *dev, struct drm_file *priv)
1675 {
1676         struct psb_priv *psb = kzalloc(sizeof(struct psb_priv), GFP_KERNEL);
1677         if (psb == NULL)
1678                 return -ENOMEM;
1679         priv->driver_priv = psb;
1680         DRM_DEBUG("\n");
1681         /*return PVRSRVOpen(dev, priv);*/
1682         return 0;
1683 }
1684
1685 static void psb_driver_close(struct drm_device *dev, struct drm_file *priv)
1686 {
1687         kfree(priv->driver_priv);
1688         priv->driver_priv = NULL;
1689 }
1690
1691 static long psb_unlocked_ioctl(struct file *filp, unsigned int cmd,
1692                                unsigned long arg)
1693 {
1694         struct drm_file *file_priv = filp->private_data;
1695         struct drm_device *dev = file_priv->minor->dev;
1696         struct drm_psb_private *dev_priv = dev->dev_private;
1697         static unsigned int runtime_allowed;
1698         unsigned int nr = DRM_IOCTL_NR(cmd);
1699
1700         DRM_DEBUG("cmd = %x, nr = %x\n", cmd, nr);
1701
1702         if (runtime_allowed == 1 && dev_priv->is_lvds_on) {
1703                 runtime_allowed++;
1704                 pm_runtime_allow(&dev->pdev->dev);
1705                 dev_priv->rpm_enabled = 1;
1706         }
1707         /*
1708          * The driver private ioctls and TTM ioctls should be
1709          * thread-safe.
1710          */
1711
1712         if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1713              && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1714                 struct drm_ioctl_desc *ioctl =
1715                                         &psb_ioctls[nr - DRM_COMMAND_BASE];
1716
1717                 if (unlikely(ioctl->cmd != cmd)) {
1718                         DRM_ERROR(
1719                                 "Invalid drm cmnd %d ioctl->cmd %x, cmd %x\n",
1720                                 nr - DRM_COMMAND_BASE, ioctl->cmd, cmd);
1721                         return -EINVAL;
1722                 }
1723
1724                 return drm_ioctl(filp, cmd, arg);
1725         }
1726         /*
1727          * Not all old drm ioctls are thread-safe.
1728          */
1729
1730         return drm_ioctl(filp, cmd, arg);
1731 }
1732
1733
1734 /* When a client dies:
1735  *    - Check for and clean up flipped page state
1736  */
1737 void psb_driver_preclose(struct drm_device *dev, struct drm_file *priv)
1738 {
1739 }
1740
1741 static void psb_remove(struct pci_dev *pdev)
1742 {
1743         struct drm_device *dev = pci_get_drvdata(pdev);
1744         drm_put_dev(dev);
1745 }
1746
1747
1748 static const struct dev_pm_ops psb_pm_ops = {
1749         .runtime_suspend = psb_runtime_suspend,
1750         .runtime_resume = psb_runtime_resume,
1751         .runtime_idle = psb_runtime_idle,
1752 };
1753
1754 static struct drm_driver driver = {
1755         .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | \
1756                            DRIVER_IRQ_VBL | DRIVER_MODESET,
1757         .load = psb_driver_load,
1758         .unload = psb_driver_unload,
1759
1760         .ioctls = psb_ioctls,
1761         .num_ioctls = DRM_ARRAY_SIZE(psb_ioctls),
1762         .device_is_agp = psb_driver_device_is_agp,
1763         .irq_preinstall = psb_irq_preinstall,
1764         .irq_postinstall = psb_irq_postinstall,
1765         .irq_uninstall = psb_irq_uninstall,
1766         .irq_handler = psb_irq_handler,
1767         .enable_vblank = psb_enable_vblank,
1768         .disable_vblank = psb_disable_vblank,
1769         .get_vblank_counter = psb_get_vblank_counter,
1770         .firstopen = NULL,
1771         .lastclose = psb_lastclose,
1772         .open = psb_driver_open,
1773         .postclose = psb_driver_close,
1774 #if 0   /* ACFIXME */
1775         .get_map_ofs = drm_core_get_map_ofs,
1776         .get_reg_ofs = drm_core_get_reg_ofs,
1777         .proc_init = psb_proc_init,
1778         .proc_cleanup = psb_proc_cleanup,
1779 #endif
1780         .preclose = psb_driver_preclose,
1781         .fops = {
1782                  .owner = THIS_MODULE,
1783                  .open = psb_open,
1784                  .release = psb_release,
1785                  .unlocked_ioctl = psb_unlocked_ioctl,
1786                  .mmap = psb_mmap,
1787                  .poll = psb_poll,
1788                  .fasync = drm_fasync,
1789                  .read = drm_read,
1790                  },
1791         .name = DRIVER_NAME,
1792         .desc = DRIVER_DESC,
1793         .date = PSB_DRM_DRIVER_DATE,
1794         .major = PSB_DRM_DRIVER_MAJOR,
1795         .minor = PSB_DRM_DRIVER_MINOR,
1796         .patchlevel = PSB_DRM_DRIVER_PATCHLEVEL
1797 };
1798
1799 static struct pci_driver psb_pci_driver = {
1800         .name = DRIVER_NAME,
1801         .id_table = pciidlist,
1802         .resume = ospm_power_resume,
1803         .suspend = ospm_power_suspend,
1804         .probe = psb_probe,
1805         .remove = psb_remove,
1806 #ifdef CONFIG_PM
1807         .driver.pm = &psb_pm_ops,
1808 #endif
1809 };
1810
1811 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1812 {
1813         /* MLD Added this from Inaky's patch */
1814         if (pci_enable_msi(pdev))
1815                 DRM_ERROR("Enable MSI failed!\n");
1816         return drm_get_pci_dev(pdev, ent, &driver);
1817 }
1818
1819 static int __init psb_init(void)
1820 {
1821         return drm_pci_init(&driver, &psb_pci_driver);
1822 }
1823
1824 static void __exit psb_exit(void)
1825 {
1826         drm_pci_exit(&driver, &psb_pci_driver);
1827 }
1828
1829 late_initcall(psb_init);
1830 module_exit(psb_exit);
1831
1832 MODULE_AUTHOR(DRIVER_AUTHOR);
1833 MODULE_DESCRIPTION(DRIVER_DESC);
1834 MODULE_LICENSE("GPL");