drivers/staging/iio/accel/lis3l02dq_core.c

   1 /*
   2  * lis3l02dq.c  support STMicroelectronics LISD02DQ
   3  *              3d 2g Linear Accelerometers via SPI
   4  *
   5  * Copyright (c) 2007 Jonathan Cameron <jic23@kernel.org>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * Settings:
  12  * 16 bit left justified mode used.
  13  */
  14
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/gpio.h>
  18 #include <linux/mutex.h>
  19 #include <linux/device.h>
  20 #include <linux/kernel.h>
  21 #include <linux/spi/spi.h>
  22 #include <linux/slab.h>
  23 #include <linux/sysfs.h>
  24 #include <linux/module.h>
  25
  26 #include <linux/iio/iio.h>
  27 #include <linux/iio/sysfs.h>
  28 #include <linux/iio/events.h>
  29 #include <linux/iio/buffer.h>
  30
  31 #include "lis3l02dq.h"
  32
  33 /* At the moment the spi framework doesn't allow global setting of cs_change.
  34  * It's in the likely to be added comment at the top of spi.h.
  35  * This means that use cannot be made of spi_write etc.
  36  */
  37 /* direct copy of the irq_default_primary_handler */
  38 #ifndef CONFIG_IIO_BUFFER
  39 static irqreturn_t lis3l02dq_nobuffer(int irq, void *private)
  40 {
  41         return IRQ_WAKE_THREAD;
  42 }
  43 #endif
  44
  45 /**
  46  * lis3l02dq_spi_read_reg_8() - read single byte from a single register
  47  * @indio_dev: iio_dev for this actual device
  48  * @reg_address: the address of the register to be read
  49  * @val: pass back the resulting value
  50  **/
  51 int lis3l02dq_spi_read_reg_8(struct iio_dev *indio_dev,
  52                              u8 reg_address, u8 *val)
  53 {
  54         struct lis3l02dq_state *st = iio_priv(indio_dev);
  55         struct spi_message msg;
  56         int ret;
  57         struct spi_transfer xfer = {
  58                 .tx_buf = st->tx,
  59                 .rx_buf = st->rx,
  60                 .bits_per_word = 8,
  61                 .len = 2,
  62         };
  63
  64         mutex_lock(&st->buf_lock);
  65         st->tx[0] = LIS3L02DQ_READ_REG(reg_address);
  66         st->tx[1] = 0;
  67
  68         spi_message_init(&msg);
  69         spi_message_add_tail(&xfer, &msg);
  70         ret = spi_sync(st->us, &msg);
  71         *val = st->rx[1];
  72         mutex_unlock(&st->buf_lock);
  73
  74         return ret;
  75 }
  76
  77 /**
  78  * lis3l02dq_spi_write_reg_8() - write single byte to a register
  79  * @indio_dev: iio_dev for this device
  80  * @reg_address: the address of the register to be written
  81  * @val: the value to write
  82  **/
  83 int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev,
  84                               u8 reg_address,
  85                               u8 val)
  86 {
  87         int ret;
  88         struct lis3l02dq_state *st = iio_priv(indio_dev);
  89
  90         mutex_lock(&st->buf_lock);
  91         st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address);
  92         st->tx[1] = val;
  93         ret = spi_write(st->us, st->tx, 2);
  94         mutex_unlock(&st->buf_lock);
  95
  96         return ret;
  97 }
  98
  99 /**
 100  * lisl302dq_spi_write_reg_s16() - write 2 bytes to a pair of registers
 101  * @indio_dev: iio_dev for this device
 102  * @lower_reg_address: the address of the lower of the two registers.
 103  *               Second register is assumed to have address one greater.
 104  * @value: value to be written
 105  **/
 106 static int lis3l02dq_spi_write_reg_s16(struct iio_dev *indio_dev,
 107                                        u8 lower_reg_address,
 108                                        s16 value)
 109 {
 110         int ret;
 111         struct spi_message msg;
 112         struct lis3l02dq_state *st = iio_priv(indio_dev);
 113         struct spi_transfer xfers[] = { {
 114                         .tx_buf = st->tx,
 115                         .bits_per_word = 8,
 116                         .len = 2,
 117                         .cs_change = 1,
 118                 }, {
 119                         .tx_buf = st->tx + 2,
 120                         .bits_per_word = 8,
 121                         .len = 2,
 122                 },
 123         };
 124
 125         mutex_lock(&st->buf_lock);
 126         st->tx[0] = LIS3L02DQ_WRITE_REG(lower_reg_address);
 127         st->tx[1] = value & 0xFF;
 128         st->tx[2] = LIS3L02DQ_WRITE_REG(lower_reg_address + 1);
 129         st->tx[3] = (value >> 8) & 0xFF;
 130
 131         spi_message_init(&msg);
 132         spi_message_add_tail(&xfers[0], &msg);
 133         spi_message_add_tail(&xfers[1], &msg);
 134         ret = spi_sync(st->us, &msg);
 135         mutex_unlock(&st->buf_lock);
 136
 137         return ret;
 138 }
 139
 140 static int lis3l02dq_read_reg_s16(struct iio_dev *indio_dev,
 141                                   u8 lower_reg_address,
 142                                   int *val)
 143 {
 144         struct lis3l02dq_state *st = iio_priv(indio_dev);
 145
 146         struct spi_message msg;
 147         int ret;
 148         s16 tempval;
 149         struct spi_transfer xfers[] = { {
 150                         .tx_buf = st->tx,
 151                         .rx_buf = st->rx,
 152                         .bits_per_word = 8,
 153                         .len = 2,
 154                         .cs_change = 1,
 155                 }, {
 156                         .tx_buf = st->tx + 2,
 157                         .rx_buf = st->rx + 2,
 158                         .bits_per_word = 8,
 159                         .len = 2,
 160                 },
 161         };
 162
 163         mutex_lock(&st->buf_lock);
 164         st->tx[0] = LIS3L02DQ_READ_REG(lower_reg_address);
 165         st->tx[1] = 0;
 166         st->tx[2] = LIS3L02DQ_READ_REG(lower_reg_address + 1);
 167         st->tx[3] = 0;
 168
 169         spi_message_init(&msg);
 170         spi_message_add_tail(&xfers[0], &msg);
 171         spi_message_add_tail(&xfers[1], &msg);
 172         ret = spi_sync(st->us, &msg);
 173         if (ret) {
 174                 dev_err(&st->us->dev, "problem when reading 16 bit register");
 175                 goto error_ret;
 176         }
 177         tempval = (s16)(st->rx[1]) | ((s16)(st->rx[3]) << 8);
 178
 179         *val = tempval;
 180 error_ret:
 181         mutex_unlock(&st->buf_lock);
 182         return ret;
 183 }
 184
 185 enum lis3l02dq_rm_ind {
 186         LIS3L02DQ_ACCEL,
 187         LIS3L02DQ_GAIN,
 188         LIS3L02DQ_BIAS,
 189 };
 190
 191 static u8 lis3l02dq_axis_map[3][3] = {
 192         [LIS3L02DQ_ACCEL] = { LIS3L02DQ_REG_OUT_X_L_ADDR,
 193                               LIS3L02DQ_REG_OUT_Y_L_ADDR,
 194                               LIS3L02DQ_REG_OUT_Z_L_ADDR },
 195         [LIS3L02DQ_GAIN] = { LIS3L02DQ_REG_GAIN_X_ADDR,
 196                              LIS3L02DQ_REG_GAIN_Y_ADDR,
 197                              LIS3L02DQ_REG_GAIN_Z_ADDR },
 198         [LIS3L02DQ_BIAS] = { LIS3L02DQ_REG_OFFSET_X_ADDR,
 199                              LIS3L02DQ_REG_OFFSET_Y_ADDR,
 200                              LIS3L02DQ_REG_OFFSET_Z_ADDR }
 201 };
 202
 203 static int lis3l02dq_read_thresh(struct iio_dev *indio_dev,
 204                                  u64 e,
 205                                  int *val)
 206 {
 207         return lis3l02dq_read_reg_s16(indio_dev, LIS3L02DQ_REG_THS_L_ADDR, val);
 208 }
 209
 210 static int lis3l02dq_write_thresh(struct iio_dev *indio_dev,
 211                                   u64 event_code,
 212                                   int val)
 213 {
 214         u16 value = val;
 215         return lis3l02dq_spi_write_reg_s16(indio_dev,
 216                                            LIS3L02DQ_REG_THS_L_ADDR,
 217                                            value);
 218 }
 219
 220 static int lis3l02dq_write_raw(struct iio_dev *indio_dev,
 221                                struct iio_chan_spec const *chan,
 222                                int val,
 223                                int val2,
 224                                long mask)
 225 {
 226         int ret = -EINVAL, reg;
 227         u8 uval;
 228         s8 sval;
 229         switch (mask) {
 230         case IIO_CHAN_INFO_CALIBBIAS:
 231                 if (val > 255 || val < -256)
 232                         return -EINVAL;
 233                 sval = val;
 234                 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
 235                 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, sval);
 236                 break;
 237         case IIO_CHAN_INFO_CALIBSCALE:
 238                 if (val & ~0xFF)
 239                         return -EINVAL;
 240                 uval = val;
 241                 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
 242                 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, uval);
 243                 break;
 244         }
 245         return ret;
 246 }
 247
 248 static int lis3l02dq_read_raw(struct iio_dev *indio_dev,
 249                               struct iio_chan_spec const *chan,
 250                               int *val,
 251                               int *val2,
 252                               long mask)
 253 {
 254         u8 utemp;
 255         s8 stemp;
 256         ssize_t ret = 0;
 257         u8 reg;
 258
 259         switch (mask) {
 260         case IIO_CHAN_INFO_RAW:
 261                 /* Take the iio_dev status lock */
 262                 mutex_lock(&indio_dev->mlock);
 263                 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) {
 264                         ret = -EBUSY;
 265                 } else {
 266                         reg = lis3l02dq_axis_map
 267                                 [LIS3L02DQ_ACCEL][chan->address];
 268                         ret = lis3l02dq_read_reg_s16(indio_dev, reg, val);
 269                 }
 270                 mutex_unlock(&indio_dev->mlock);
 271                 return IIO_VAL_INT;
 272         case IIO_CHAN_INFO_SCALE:
 273                 *val = 0;
 274                 *val2 = 9580;
 275                 return IIO_VAL_INT_PLUS_MICRO;
 276         case IIO_CHAN_INFO_CALIBSCALE:
 277                 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
 278                 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, &utemp);
 279                 if (ret)
 280                         goto error_ret;
 281                 /* to match with what previous code does */
 282                 *val = utemp;
 283                 return IIO_VAL_INT;
 284
 285         case IIO_CHAN_INFO_CALIBBIAS:
 286                 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
 287                 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, (u8 *)&stemp);
 288                 /* to match with what previous code does */
 289                 *val = stemp;
 290                 return IIO_VAL_INT;
 291         }
 292 error_ret:
 293         return ret;
 294 }
 295
 296 static ssize_t lis3l02dq_read_frequency(struct device *dev,
 297                                         struct device_attribute *attr,
 298                                         char *buf)
 299 {
 300         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 301         int ret, len = 0;
 302         s8 t;
 303         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 304                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 305                                        (u8 *)&t);
 306         if (ret)
 307                 return ret;
 308         t &= LIS3L02DQ_DEC_MASK;
 309         switch (t) {
 310         case LIS3L02DQ_REG_CTRL_1_DF_128:
 311                 len = sprintf(buf, "280\n");
 312                 break;
 313         case LIS3L02DQ_REG_CTRL_1_DF_64:
 314                 len = sprintf(buf, "560\n");
 315                 break;
 316         case LIS3L02DQ_REG_CTRL_1_DF_32:
 317                 len = sprintf(buf, "1120\n");
 318                 break;
 319         case LIS3L02DQ_REG_CTRL_1_DF_8:
 320                 len = sprintf(buf, "4480\n");
 321                 break;
 322         }
 323         return len;
 324 }
 325
 326 static ssize_t lis3l02dq_write_frequency(struct device *dev,
 327                                          struct device_attribute *attr,
 328                                          const char *buf,
 329                                          size_t len)
 330 {
 331         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 332         unsigned long val;
 333         int ret;
 334         u8 t;
 335
 336         ret = kstrtoul(buf, 10, &val);
 337         if (ret)
 338                 return ret;
 339
 340         mutex_lock(&indio_dev->mlock);
 341         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 342                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 343                                        &t);
 344         if (ret)
 345                 goto error_ret_mutex;
 346         /* Wipe the bits clean */
 347         t &= ~LIS3L02DQ_DEC_MASK;
 348         switch (val) {
 349         case 280:
 350                 t |= LIS3L02DQ_REG_CTRL_1_DF_128;
 351                 break;
 352         case 560:
 353                 t |= LIS3L02DQ_REG_CTRL_1_DF_64;
 354                 break;
 355         case 1120:
 356                 t |= LIS3L02DQ_REG_CTRL_1_DF_32;
 357                 break;
 358         case 4480:
 359                 t |= LIS3L02DQ_REG_CTRL_1_DF_8;
 360                 break;
 361         default:
 362                 ret = -EINVAL;
 363                 goto error_ret_mutex;
 364         }
 365
 366         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 367                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 368                                         t);
 369
 370 error_ret_mutex:
 371         mutex_unlock(&indio_dev->mlock);
 372
 373         return ret ? ret : len;
 374 }
 375
 376 static int lis3l02dq_initial_setup(struct iio_dev *indio_dev)
 377 {
 378         struct lis3l02dq_state *st = iio_priv(indio_dev);
 379         int ret;
 380         u8 val, valtest;
 381
 382         st->us->mode = SPI_MODE_3;
 383
 384         spi_setup(st->us);
 385
 386         val = LIS3L02DQ_DEFAULT_CTRL1;
 387         /* Write suitable defaults to ctrl1 */
 388         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 389                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 390                                         val);
 391         if (ret) {
 392                 dev_err(&st->us->dev, "problem with setup control register 1");
 393                 goto err_ret;
 394         }
 395         /* Repeat as sometimes doesn't work first time? */
 396         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 397                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 398                                         val);
 399         if (ret) {
 400                 dev_err(&st->us->dev, "problem with setup control register 1");
 401                 goto err_ret;
 402         }
 403
 404         /* Read back to check this has worked acts as loose test of correct
 405          * chip */
 406         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 407                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 408                                        &valtest);
 409         if (ret || (valtest != val)) {
 410                 dev_err(&indio_dev->dev,
 411                         "device not playing ball %d %d\n", valtest, val);
 412                 ret = -EINVAL;
 413                 goto err_ret;
 414         }
 415
 416         val = LIS3L02DQ_DEFAULT_CTRL2;
 417         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 418                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 419                                         val);
 420         if (ret) {
 421                 dev_err(&st->us->dev, "problem with setup control register 2");
 422                 goto err_ret;
 423         }
 424
 425         val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC;
 426         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 427                                         LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 428                                         val);
 429         if (ret)
 430                 dev_err(&st->us->dev, "problem with interrupt cfg register");
 431 err_ret:
 432
 433         return ret;
 434 }
 435
 436 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
 437                               lis3l02dq_read_frequency,
 438                               lis3l02dq_write_frequency);
 439
 440 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("280 560 1120 4480");
 441
 442 static irqreturn_t lis3l02dq_event_handler(int irq, void *private)
 443 {
 444         struct iio_dev *indio_dev = private;
 445         u8 t;
 446
 447         s64 timestamp = iio_get_time_ns();
 448
 449         lis3l02dq_spi_read_reg_8(indio_dev,
 450                                  LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
 451                                  &t);
 452
 453         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_HIGH)
 454                 iio_push_event(indio_dev,
 455                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 456                                                   0,
 457                                                   IIO_MOD_Z,
 458                                                   IIO_EV_TYPE_THRESH,
 459                                                   IIO_EV_DIR_RISING),
 460                                timestamp);
 461
 462         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_LOW)
 463                 iio_push_event(indio_dev,
 464                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 465                                                   0,
 466                                                   IIO_MOD_Z,
 467                                                   IIO_EV_TYPE_THRESH,
 468                                                   IIO_EV_DIR_FALLING),
 469                                timestamp);
 470
 471         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_HIGH)
 472                 iio_push_event(indio_dev,
 473                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 474                                                   0,
 475                                                   IIO_MOD_Y,
 476                                                   IIO_EV_TYPE_THRESH,
 477                                                   IIO_EV_DIR_RISING),
 478                                timestamp);
 479
 480         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_LOW)
 481                 iio_push_event(indio_dev,
 482                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 483                                                   0,
 484                                                   IIO_MOD_Y,
 485                                                   IIO_EV_TYPE_THRESH,
 486                                                   IIO_EV_DIR_FALLING),
 487                                timestamp);
 488
 489         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_HIGH)
 490                 iio_push_event(indio_dev,
 491                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 492                                                   0,
 493                                                   IIO_MOD_X,
 494                                                   IIO_EV_TYPE_THRESH,
 495                                                   IIO_EV_DIR_RISING),
 496                                timestamp);
 497
 498         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_LOW)
 499                 iio_push_event(indio_dev,
 500                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 501                                                   0,
 502                                                   IIO_MOD_X,
 503                                                   IIO_EV_TYPE_THRESH,
 504                                                   IIO_EV_DIR_FALLING),
 505                                timestamp);
 506
 507         /* Ack and allow for new interrupts */
 508         lis3l02dq_spi_read_reg_8(indio_dev,
 509                                  LIS3L02DQ_REG_WAKE_UP_ACK_ADDR,
 510                                  &t);
 511
 512         return IRQ_HANDLED;
 513 }
 514
 515 #define LIS3L02DQ_INFO_MASK                             \
 516         (IIO_CHAN_INFO_RAW_SEPARATE_BIT |               \
 517          IIO_CHAN_INFO_SCALE_SHARED_BIT |               \
 518          IIO_CHAN_INFO_CALIBSCALE_SEPARATE_BIT |        \
 519          IIO_CHAN_INFO_CALIBBIAS_SEPARATE_BIT)
 520
 521 #define LIS3L02DQ_EVENT_MASK                                    \
 522         (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) |    \
 523          IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
 524
 525 #define LIS3L02DQ_CHAN(index, mod)                              \
 526         {                                                       \
 527                 .type = IIO_ACCEL,                              \
 528                 .modified = 1,                                  \
 529                 .channel2 = mod,                                \
 530                 .info_mask =  LIS3L02DQ_INFO_MASK,              \
 531                 .address = index,                               \
 532                 .scan_index = index,                            \
 533                 .scan_type = {                                  \
 534                         .sign = 's',                            \
 535                         .realbits = 12,                         \
 536                         .storagebits = 16,                      \
 537                 },                                              \
 538                 .event_mask = LIS3L02DQ_EVENT_MASK,             \
 539          }
 540
 541 static const struct iio_chan_spec lis3l02dq_channels[] = {
 542         LIS3L02DQ_CHAN(0, IIO_MOD_X),
 543         LIS3L02DQ_CHAN(1, IIO_MOD_Y),
 544         LIS3L02DQ_CHAN(2, IIO_MOD_Z),
 545         IIO_CHAN_SOFT_TIMESTAMP(3)
 546 };
 547
 548
 549 static int lis3l02dq_read_event_config(struct iio_dev *indio_dev,
 550                                            u64 event_code)
 551 {
 552
 553         u8 val;
 554         int ret;
 555         u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
 556                          (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
 557                           IIO_EV_DIR_RISING)));
 558         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 559                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 560                                        &val);
 561         if (ret < 0)
 562                 return ret;
 563
 564         return !!(val & mask);
 565 }
 566
 567 int lis3l02dq_disable_all_events(struct iio_dev *indio_dev)
 568 {
 569         int ret;
 570         u8 control, val;
 571
 572         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 573                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 574                                        &control);
 575
 576         control &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT;
 577         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 578                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 579                                         control);
 580         if (ret)
 581                 goto error_ret;
 582         /* Also for consistency clear the mask */
 583         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 584                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 585                                        &val);
 586         if (ret)
 587                 goto error_ret;
 588         val &= ~0x3f;
 589
 590         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 591                                         LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 592                                         val);
 593         if (ret)
 594                 goto error_ret;
 595
 596         ret = control;
 597 error_ret:
 598         return ret;
 599 }
 600
 601 static int lis3l02dq_write_event_config(struct iio_dev *indio_dev,
 602                                         u64 event_code,
 603                                         int state)
 604 {
 605         int ret = 0;
 606         u8 val, control;
 607         u8 currentlyset;
 608         bool changed = false;
 609         u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
 610                          (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
 611                           IIO_EV_DIR_RISING)));
 612
 613         mutex_lock(&indio_dev->mlock);
 614         /* read current control */
 615         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 616                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 617                                        &control);
 618         if (ret)
 619                 goto error_ret;
 620         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 621                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 622                                        &val);
 623         if (ret < 0)
 624                 goto error_ret;
 625         currentlyset = val & mask;
 626
 627         if (!currentlyset && state) {
 628                 changed = true;
 629                 val |= mask;
 630         } else if (currentlyset && !state) {
 631                 changed = true;
 632                 val &= ~mask;
 633         }
 634
 635         if (changed) {
 636                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 637                                                 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 638                                                 val);
 639                 if (ret)
 640                         goto error_ret;
 641                 control = val & 0x3f ?
 642                         (control | LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT) :
 643                         (control & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
 644                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 645                                                LIS3L02DQ_REG_CTRL_2_ADDR,
 646                                                control);
 647                 if (ret)
 648                         goto error_ret;
 649         }
 650
 651 error_ret:
 652         mutex_unlock(&indio_dev->mlock);
 653         return ret;
 654 }
 655
 656 static struct attribute *lis3l02dq_attributes[] = {
 657         &iio_dev_attr_sampling_frequency.dev_attr.attr,
 658         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
 659         NULL
 660 };
 661
 662 static const struct attribute_group lis3l02dq_attribute_group = {
 663         .attrs = lis3l02dq_attributes,
 664 };
 665
 666 static const struct iio_info lis3l02dq_info = {
 667         .read_raw = &lis3l02dq_read_raw,
 668         .write_raw = &lis3l02dq_write_raw,
 669         .read_event_value = &lis3l02dq_read_thresh,
 670         .write_event_value = &lis3l02dq_write_thresh,
 671         .write_event_config = &lis3l02dq_write_event_config,
 672         .read_event_config = &lis3l02dq_read_event_config,
 673         .driver_module = THIS_MODULE,
 674         .attrs = &lis3l02dq_attribute_group,
 675 };
 676
 677 static int __devinit lis3l02dq_probe(struct spi_device *spi)
 678 {
 679         int ret;
 680         struct lis3l02dq_state *st;
 681         struct iio_dev *indio_dev;
 682
 683         indio_dev = iio_device_alloc(sizeof *st);
 684         if (indio_dev == NULL) {
 685                 ret = -ENOMEM;
 686                 goto error_ret;
 687         }
 688         st = iio_priv(indio_dev);
 689         /* this is only used for removal purposes */
 690         spi_set_drvdata(spi, indio_dev);
 691
 692         st->us = spi;
 693         mutex_init(&st->buf_lock);
 694         indio_dev->name = spi->dev.driver->name;
 695         indio_dev->dev.parent = &spi->dev;
 696         indio_dev->info = &lis3l02dq_info;
 697         indio_dev->channels = lis3l02dq_channels;
 698         indio_dev->num_channels = ARRAY_SIZE(lis3l02dq_channels);
 699
 700         indio_dev->modes = INDIO_DIRECT_MODE;
 701
 702         ret = lis3l02dq_configure_buffer(indio_dev);
 703         if (ret)
 704                 goto error_free_dev;
 705
 706         ret = iio_buffer_register(indio_dev,
 707                                   lis3l02dq_channels,
 708                                   ARRAY_SIZE(lis3l02dq_channels));
 709         if (ret) {
 710                 printk(KERN_ERR "failed to initialize the buffer\n");
 711                 goto error_unreg_buffer_funcs;
 712         }
 713
 714         if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0) {
 715                 ret = request_threaded_irq(st->us->irq,
 716                                            &lis3l02dq_th,
 717                                            &lis3l02dq_event_handler,
 718                                            IRQF_TRIGGER_RISING,
 719                                            "lis3l02dq",
 720                                            indio_dev);
 721                 if (ret)
 722                         goto error_uninitialize_buffer;
 723
 724                 ret = lis3l02dq_probe_trigger(indio_dev);
 725                 if (ret)
 726                         goto error_free_interrupt;
 727         }
 728
 729         /* Get the device into a sane initial state */
 730         ret = lis3l02dq_initial_setup(indio_dev);
 731         if (ret)
 732                 goto error_remove_trigger;
 733
 734         ret = iio_device_register(indio_dev);
 735         if (ret)
 736                 goto error_remove_trigger;
 737
 738         return 0;
 739
 740 error_remove_trigger:
 741         if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)))
 742                 lis3l02dq_remove_trigger(indio_dev);
 743 error_free_interrupt:
 744         if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
 745                 free_irq(st->us->irq, indio_dev);
 746 error_uninitialize_buffer:
 747         iio_buffer_unregister(indio_dev);
 748 error_unreg_buffer_funcs:
 749         lis3l02dq_unconfigure_buffer(indio_dev);
 750 error_free_dev:
 751         iio_device_free(indio_dev);
 752 error_ret:
 753         return ret;
 754 }
 755
 756 /* Power down the device */
 757 static int lis3l02dq_stop_device(struct iio_dev *indio_dev)
 758 {
 759         int ret;
 760         struct lis3l02dq_state *st = iio_priv(indio_dev);
 761         u8 val = 0;
 762
 763         mutex_lock(&indio_dev->mlock);
 764         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 765                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 766                                         val);
 767         if (ret) {
 768                 dev_err(&st->us->dev, "problem with turning device off: ctrl1");
 769                 goto err_ret;
 770         }
 771
 772         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 773                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 774                                         val);
 775         if (ret)
 776                 dev_err(&st->us->dev, "problem with turning device off: ctrl2");
 777 err_ret:
 778         mutex_unlock(&indio_dev->mlock);
 779         return ret;
 780 }
 781
 782 /* fixme, confirm ordering in this function */
 783 static int __devexit lis3l02dq_remove(struct spi_device *spi)
 784 {
 785         int ret;
 786         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 787         struct lis3l02dq_state *st = iio_priv(indio_dev);
 788
 789         iio_device_unregister(indio_dev);
 790
 791         ret = lis3l02dq_disable_all_events(indio_dev);
 792         if (ret)
 793                 goto err_ret;
 794
 795         ret = lis3l02dq_stop_device(indio_dev);
 796         if (ret)
 797                 goto err_ret;
 798
 799         if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
 800                 free_irq(st->us->irq, indio_dev);
 801
 802         lis3l02dq_remove_trigger(indio_dev);
 803         iio_buffer_unregister(indio_dev);
 804         lis3l02dq_unconfigure_buffer(indio_dev);
 805
 806         iio_device_free(indio_dev);
 807 err_ret:
 808         return ret;
 809 }
 810
 811 static struct spi_driver lis3l02dq_driver = {
 812         .driver = {
 813                 .name = "lis3l02dq",
 814                 .owner = THIS_MODULE,
 815         },
 816         .probe = lis3l02dq_probe,
 817         .remove = __devexit_p(lis3l02dq_remove),
 818 };
 819 module_spi_driver(lis3l02dq_driver);
 820
 821 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
 822 MODULE_DESCRIPTION("ST LIS3L02DQ Accelerometer SPI driver");
 823 MODULE_LICENSE("GPL v2");
 824 MODULE_ALIAS("spi:lis3l02dq");