2 * lis3l02dq.c support STMicroelectronics LISD02DQ
3 * 3d 2g Linear Accelerometers via SPI
5 * Copyright (c) 2007 Jonathan Cameron <jic23@kernel.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 * 16 bit left justified mode used.
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/gpio.h>
18 #include <linux/mutex.h>
19 #include <linux/device.h>
20 #include <linux/kernel.h>
21 #include <linux/spi/spi.h>
22 #include <linux/slab.h>
23 #include <linux/sysfs.h>
24 #include <linux/module.h>
26 #include <linux/iio/iio.h>
27 #include <linux/iio/sysfs.h>
28 #include <linux/iio/events.h>
29 #include <linux/iio/buffer.h>
31 #include "lis3l02dq.h"
33 /* At the moment the spi framework doesn't allow global setting of cs_change.
34 * It's in the likely to be added comment at the top of spi.h.
35 * This means that use cannot be made of spi_write etc.
37 /* direct copy of the irq_default_primary_handler */
38 #ifndef CONFIG_IIO_BUFFER
39 static irqreturn_t lis3l02dq_nobuffer(int irq, void *private)
41 return IRQ_WAKE_THREAD;
46 * lis3l02dq_spi_read_reg_8() - read single byte from a single register
47 * @indio_dev: iio_dev for this actual device
48 * @reg_address: the address of the register to be read
49 * @val: pass back the resulting value
51 int lis3l02dq_spi_read_reg_8(struct iio_dev *indio_dev,
52 u8 reg_address, u8 *val)
54 struct lis3l02dq_state *st = iio_priv(indio_dev);
55 struct spi_message msg;
57 struct spi_transfer xfer = {
64 mutex_lock(&st->buf_lock);
65 st->tx[0] = LIS3L02DQ_READ_REG(reg_address);
68 spi_message_init(&msg);
69 spi_message_add_tail(&xfer, &msg);
70 ret = spi_sync(st->us, &msg);
72 mutex_unlock(&st->buf_lock);
78 * lis3l02dq_spi_write_reg_8() - write single byte to a register
79 * @indio_dev: iio_dev for this device
80 * @reg_address: the address of the register to be written
81 * @val: the value to write
83 int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev,
88 struct lis3l02dq_state *st = iio_priv(indio_dev);
90 mutex_lock(&st->buf_lock);
91 st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address);
93 ret = spi_write(st->us, st->tx, 2);
94 mutex_unlock(&st->buf_lock);
100 * lisl302dq_spi_write_reg_s16() - write 2 bytes to a pair of registers
101 * @indio_dev: iio_dev for this device
102 * @lower_reg_address: the address of the lower of the two registers.
103 * Second register is assumed to have address one greater.
104 * @value: value to be written
106 static int lis3l02dq_spi_write_reg_s16(struct iio_dev *indio_dev,
107 u8 lower_reg_address,
111 struct spi_message msg;
112 struct lis3l02dq_state *st = iio_priv(indio_dev);
113 struct spi_transfer xfers[] = { {
119 .tx_buf = st->tx + 2,
125 mutex_lock(&st->buf_lock);
126 st->tx[0] = LIS3L02DQ_WRITE_REG(lower_reg_address);
127 st->tx[1] = value & 0xFF;
128 st->tx[2] = LIS3L02DQ_WRITE_REG(lower_reg_address + 1);
129 st->tx[3] = (value >> 8) & 0xFF;
131 spi_message_init(&msg);
132 spi_message_add_tail(&xfers[0], &msg);
133 spi_message_add_tail(&xfers[1], &msg);
134 ret = spi_sync(st->us, &msg);
135 mutex_unlock(&st->buf_lock);
140 static int lis3l02dq_read_reg_s16(struct iio_dev *indio_dev,
141 u8 lower_reg_address,
144 struct lis3l02dq_state *st = iio_priv(indio_dev);
146 struct spi_message msg;
149 struct spi_transfer xfers[] = { {
156 .tx_buf = st->tx + 2,
157 .rx_buf = st->rx + 2,
163 mutex_lock(&st->buf_lock);
164 st->tx[0] = LIS3L02DQ_READ_REG(lower_reg_address);
166 st->tx[2] = LIS3L02DQ_READ_REG(lower_reg_address + 1);
169 spi_message_init(&msg);
170 spi_message_add_tail(&xfers[0], &msg);
171 spi_message_add_tail(&xfers[1], &msg);
172 ret = spi_sync(st->us, &msg);
174 dev_err(&st->us->dev, "problem when reading 16 bit register");
177 tempval = (s16)(st->rx[1]) | ((s16)(st->rx[3]) << 8);
181 mutex_unlock(&st->buf_lock);
185 enum lis3l02dq_rm_ind {
191 static u8 lis3l02dq_axis_map[3][3] = {
192 [LIS3L02DQ_ACCEL] = { LIS3L02DQ_REG_OUT_X_L_ADDR,
193 LIS3L02DQ_REG_OUT_Y_L_ADDR,
194 LIS3L02DQ_REG_OUT_Z_L_ADDR },
195 [LIS3L02DQ_GAIN] = { LIS3L02DQ_REG_GAIN_X_ADDR,
196 LIS3L02DQ_REG_GAIN_Y_ADDR,
197 LIS3L02DQ_REG_GAIN_Z_ADDR },
198 [LIS3L02DQ_BIAS] = { LIS3L02DQ_REG_OFFSET_X_ADDR,
199 LIS3L02DQ_REG_OFFSET_Y_ADDR,
200 LIS3L02DQ_REG_OFFSET_Z_ADDR }
203 static int lis3l02dq_read_thresh(struct iio_dev *indio_dev,
207 return lis3l02dq_read_reg_s16(indio_dev, LIS3L02DQ_REG_THS_L_ADDR, val);
210 static int lis3l02dq_write_thresh(struct iio_dev *indio_dev,
215 return lis3l02dq_spi_write_reg_s16(indio_dev,
216 LIS3L02DQ_REG_THS_L_ADDR,
220 static int lis3l02dq_write_raw(struct iio_dev *indio_dev,
221 struct iio_chan_spec const *chan,
226 int ret = -EINVAL, reg;
230 case IIO_CHAN_INFO_CALIBBIAS:
231 if (val > 255 || val < -256)
234 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
235 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, sval);
237 case IIO_CHAN_INFO_CALIBSCALE:
241 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
242 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, uval);
248 static int lis3l02dq_read_raw(struct iio_dev *indio_dev,
249 struct iio_chan_spec const *chan,
260 case IIO_CHAN_INFO_RAW:
261 /* Take the iio_dev status lock */
262 mutex_lock(&indio_dev->mlock);
263 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) {
266 reg = lis3l02dq_axis_map
267 [LIS3L02DQ_ACCEL][chan->address];
268 ret = lis3l02dq_read_reg_s16(indio_dev, reg, val);
270 mutex_unlock(&indio_dev->mlock);
272 case IIO_CHAN_INFO_SCALE:
275 return IIO_VAL_INT_PLUS_MICRO;
276 case IIO_CHAN_INFO_CALIBSCALE:
277 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
278 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, &utemp);
281 /* to match with what previous code does */
285 case IIO_CHAN_INFO_CALIBBIAS:
286 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
287 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, (u8 *)&stemp);
288 /* to match with what previous code does */
296 static ssize_t lis3l02dq_read_frequency(struct device *dev,
297 struct device_attribute *attr,
300 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
303 ret = lis3l02dq_spi_read_reg_8(indio_dev,
304 LIS3L02DQ_REG_CTRL_1_ADDR,
308 t &= LIS3L02DQ_DEC_MASK;
310 case LIS3L02DQ_REG_CTRL_1_DF_128:
311 len = sprintf(buf, "280\n");
313 case LIS3L02DQ_REG_CTRL_1_DF_64:
314 len = sprintf(buf, "560\n");
316 case LIS3L02DQ_REG_CTRL_1_DF_32:
317 len = sprintf(buf, "1120\n");
319 case LIS3L02DQ_REG_CTRL_1_DF_8:
320 len = sprintf(buf, "4480\n");
326 static ssize_t lis3l02dq_write_frequency(struct device *dev,
327 struct device_attribute *attr,
331 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
336 ret = kstrtoul(buf, 10, &val);
340 mutex_lock(&indio_dev->mlock);
341 ret = lis3l02dq_spi_read_reg_8(indio_dev,
342 LIS3L02DQ_REG_CTRL_1_ADDR,
345 goto error_ret_mutex;
346 /* Wipe the bits clean */
347 t &= ~LIS3L02DQ_DEC_MASK;
350 t |= LIS3L02DQ_REG_CTRL_1_DF_128;
353 t |= LIS3L02DQ_REG_CTRL_1_DF_64;
356 t |= LIS3L02DQ_REG_CTRL_1_DF_32;
359 t |= LIS3L02DQ_REG_CTRL_1_DF_8;
363 goto error_ret_mutex;
366 ret = lis3l02dq_spi_write_reg_8(indio_dev,
367 LIS3L02DQ_REG_CTRL_1_ADDR,
371 mutex_unlock(&indio_dev->mlock);
373 return ret ? ret : len;
376 static int lis3l02dq_initial_setup(struct iio_dev *indio_dev)
378 struct lis3l02dq_state *st = iio_priv(indio_dev);
382 st->us->mode = SPI_MODE_3;
386 val = LIS3L02DQ_DEFAULT_CTRL1;
387 /* Write suitable defaults to ctrl1 */
388 ret = lis3l02dq_spi_write_reg_8(indio_dev,
389 LIS3L02DQ_REG_CTRL_1_ADDR,
392 dev_err(&st->us->dev, "problem with setup control register 1");
395 /* Repeat as sometimes doesn't work first time? */
396 ret = lis3l02dq_spi_write_reg_8(indio_dev,
397 LIS3L02DQ_REG_CTRL_1_ADDR,
400 dev_err(&st->us->dev, "problem with setup control register 1");
404 /* Read back to check this has worked acts as loose test of correct
406 ret = lis3l02dq_spi_read_reg_8(indio_dev,
407 LIS3L02DQ_REG_CTRL_1_ADDR,
409 if (ret || (valtest != val)) {
410 dev_err(&indio_dev->dev,
411 "device not playing ball %d %d\n", valtest, val);
416 val = LIS3L02DQ_DEFAULT_CTRL2;
417 ret = lis3l02dq_spi_write_reg_8(indio_dev,
418 LIS3L02DQ_REG_CTRL_2_ADDR,
421 dev_err(&st->us->dev, "problem with setup control register 2");
425 val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC;
426 ret = lis3l02dq_spi_write_reg_8(indio_dev,
427 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
430 dev_err(&st->us->dev, "problem with interrupt cfg register");
436 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
437 lis3l02dq_read_frequency,
438 lis3l02dq_write_frequency);
440 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("280 560 1120 4480");
442 static irqreturn_t lis3l02dq_event_handler(int irq, void *private)
444 struct iio_dev *indio_dev = private;
447 s64 timestamp = iio_get_time_ns();
449 lis3l02dq_spi_read_reg_8(indio_dev,
450 LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
453 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_HIGH)
454 iio_push_event(indio_dev,
455 IIO_MOD_EVENT_CODE(IIO_ACCEL,
462 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_LOW)
463 iio_push_event(indio_dev,
464 IIO_MOD_EVENT_CODE(IIO_ACCEL,
471 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_HIGH)
472 iio_push_event(indio_dev,
473 IIO_MOD_EVENT_CODE(IIO_ACCEL,
480 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_LOW)
481 iio_push_event(indio_dev,
482 IIO_MOD_EVENT_CODE(IIO_ACCEL,
489 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_HIGH)
490 iio_push_event(indio_dev,
491 IIO_MOD_EVENT_CODE(IIO_ACCEL,
498 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_LOW)
499 iio_push_event(indio_dev,
500 IIO_MOD_EVENT_CODE(IIO_ACCEL,
507 /* Ack and allow for new interrupts */
508 lis3l02dq_spi_read_reg_8(indio_dev,
509 LIS3L02DQ_REG_WAKE_UP_ACK_ADDR,
515 #define LIS3L02DQ_INFO_MASK \
516 (IIO_CHAN_INFO_RAW_SEPARATE_BIT | \
517 IIO_CHAN_INFO_SCALE_SHARED_BIT | \
518 IIO_CHAN_INFO_CALIBSCALE_SEPARATE_BIT | \
519 IIO_CHAN_INFO_CALIBBIAS_SEPARATE_BIT)
521 #define LIS3L02DQ_EVENT_MASK \
522 (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) | \
523 IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
525 #define LIS3L02DQ_CHAN(index, mod) \
530 .info_mask = LIS3L02DQ_INFO_MASK, \
532 .scan_index = index, \
538 .event_mask = LIS3L02DQ_EVENT_MASK, \
541 static const struct iio_chan_spec lis3l02dq_channels[] = {
542 LIS3L02DQ_CHAN(0, IIO_MOD_X),
543 LIS3L02DQ_CHAN(1, IIO_MOD_Y),
544 LIS3L02DQ_CHAN(2, IIO_MOD_Z),
545 IIO_CHAN_SOFT_TIMESTAMP(3)
549 static int lis3l02dq_read_event_config(struct iio_dev *indio_dev,
555 u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
556 (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
557 IIO_EV_DIR_RISING)));
558 ret = lis3l02dq_spi_read_reg_8(indio_dev,
559 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
564 return !!(val & mask);
567 int lis3l02dq_disable_all_events(struct iio_dev *indio_dev)
572 ret = lis3l02dq_spi_read_reg_8(indio_dev,
573 LIS3L02DQ_REG_CTRL_2_ADDR,
576 control &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT;
577 ret = lis3l02dq_spi_write_reg_8(indio_dev,
578 LIS3L02DQ_REG_CTRL_2_ADDR,
582 /* Also for consistency clear the mask */
583 ret = lis3l02dq_spi_read_reg_8(indio_dev,
584 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
590 ret = lis3l02dq_spi_write_reg_8(indio_dev,
591 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
601 static int lis3l02dq_write_event_config(struct iio_dev *indio_dev,
608 bool changed = false;
609 u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
610 (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
611 IIO_EV_DIR_RISING)));
613 mutex_lock(&indio_dev->mlock);
614 /* read current control */
615 ret = lis3l02dq_spi_read_reg_8(indio_dev,
616 LIS3L02DQ_REG_CTRL_2_ADDR,
620 ret = lis3l02dq_spi_read_reg_8(indio_dev,
621 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
625 currentlyset = val & mask;
627 if (!currentlyset && state) {
630 } else if (currentlyset && !state) {
636 ret = lis3l02dq_spi_write_reg_8(indio_dev,
637 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
641 control = val & 0x3f ?
642 (control | LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT) :
643 (control & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
644 ret = lis3l02dq_spi_write_reg_8(indio_dev,
645 LIS3L02DQ_REG_CTRL_2_ADDR,
652 mutex_unlock(&indio_dev->mlock);
656 static struct attribute *lis3l02dq_attributes[] = {
657 &iio_dev_attr_sampling_frequency.dev_attr.attr,
658 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
662 static const struct attribute_group lis3l02dq_attribute_group = {
663 .attrs = lis3l02dq_attributes,
666 static const struct iio_info lis3l02dq_info = {
667 .read_raw = &lis3l02dq_read_raw,
668 .write_raw = &lis3l02dq_write_raw,
669 .read_event_value = &lis3l02dq_read_thresh,
670 .write_event_value = &lis3l02dq_write_thresh,
671 .write_event_config = &lis3l02dq_write_event_config,
672 .read_event_config = &lis3l02dq_read_event_config,
673 .driver_module = THIS_MODULE,
674 .attrs = &lis3l02dq_attribute_group,
677 static int __devinit lis3l02dq_probe(struct spi_device *spi)
680 struct lis3l02dq_state *st;
681 struct iio_dev *indio_dev;
683 indio_dev = iio_device_alloc(sizeof *st);
684 if (indio_dev == NULL) {
688 st = iio_priv(indio_dev);
689 /* this is only used for removal purposes */
690 spi_set_drvdata(spi, indio_dev);
693 mutex_init(&st->buf_lock);
694 indio_dev->name = spi->dev.driver->name;
695 indio_dev->dev.parent = &spi->dev;
696 indio_dev->info = &lis3l02dq_info;
697 indio_dev->channels = lis3l02dq_channels;
698 indio_dev->num_channels = ARRAY_SIZE(lis3l02dq_channels);
700 indio_dev->modes = INDIO_DIRECT_MODE;
702 ret = lis3l02dq_configure_buffer(indio_dev);
706 ret = iio_buffer_register(indio_dev,
708 ARRAY_SIZE(lis3l02dq_channels));
710 printk(KERN_ERR "failed to initialize the buffer\n");
711 goto error_unreg_buffer_funcs;
714 if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0) {
715 ret = request_threaded_irq(st->us->irq,
717 &lis3l02dq_event_handler,
722 goto error_uninitialize_buffer;
724 ret = lis3l02dq_probe_trigger(indio_dev);
726 goto error_free_interrupt;
729 /* Get the device into a sane initial state */
730 ret = lis3l02dq_initial_setup(indio_dev);
732 goto error_remove_trigger;
734 ret = iio_device_register(indio_dev);
736 goto error_remove_trigger;
740 error_remove_trigger:
741 if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)))
742 lis3l02dq_remove_trigger(indio_dev);
743 error_free_interrupt:
744 if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
745 free_irq(st->us->irq, indio_dev);
746 error_uninitialize_buffer:
747 iio_buffer_unregister(indio_dev);
748 error_unreg_buffer_funcs:
749 lis3l02dq_unconfigure_buffer(indio_dev);
751 iio_device_free(indio_dev);
756 /* Power down the device */
757 static int lis3l02dq_stop_device(struct iio_dev *indio_dev)
760 struct lis3l02dq_state *st = iio_priv(indio_dev);
763 mutex_lock(&indio_dev->mlock);
764 ret = lis3l02dq_spi_write_reg_8(indio_dev,
765 LIS3L02DQ_REG_CTRL_1_ADDR,
768 dev_err(&st->us->dev, "problem with turning device off: ctrl1");
772 ret = lis3l02dq_spi_write_reg_8(indio_dev,
773 LIS3L02DQ_REG_CTRL_2_ADDR,
776 dev_err(&st->us->dev, "problem with turning device off: ctrl2");
778 mutex_unlock(&indio_dev->mlock);
782 /* fixme, confirm ordering in this function */
783 static int __devexit lis3l02dq_remove(struct spi_device *spi)
786 struct iio_dev *indio_dev = spi_get_drvdata(spi);
787 struct lis3l02dq_state *st = iio_priv(indio_dev);
789 iio_device_unregister(indio_dev);
791 ret = lis3l02dq_disable_all_events(indio_dev);
795 ret = lis3l02dq_stop_device(indio_dev);
799 if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
800 free_irq(st->us->irq, indio_dev);
802 lis3l02dq_remove_trigger(indio_dev);
803 iio_buffer_unregister(indio_dev);
804 lis3l02dq_unconfigure_buffer(indio_dev);
806 iio_device_free(indio_dev);
811 static struct spi_driver lis3l02dq_driver = {
814 .owner = THIS_MODULE,
816 .probe = lis3l02dq_probe,
817 .remove = __devexit_p(lis3l02dq_remove),
819 module_spi_driver(lis3l02dq_driver);
821 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
822 MODULE_DESCRIPTION("ST LIS3L02DQ Accelerometer SPI driver");
823 MODULE_LICENSE("GPL v2");
824 MODULE_ALIAS("spi:lis3l02dq");