drivers/tty/serial/8250/8250_ingenic.c

   1 /*
   2  * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de>
   3  * Copyright (C) 2015 Imagination Technologies
   4  *
   5  * Ingenic SoC UART support
   6  *
   7  * Author: Paul Burton <paul.burton@imgtec.com>
   8  *
   9  * This program is free software; you can redistribute   it and/or modify it
  10  * under  the terms of   the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the   License, or (at your
  12  * option) any later version.
  13  *
  14  * You should have received a copy of the  GNU General Public License along
  15  * with this program; if not, write  to the Free Software Foundation, Inc.,
  16  * 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/console.h>
  21 #include <linux/io.h>
  22 #include <linux/libfdt.h>
  23 #include <linux/init.h>
  24 #include <linux/of.h>
  25 #include <linux/of_fdt.h>
  26 #include <linux/of_device.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/serial_8250.h>
  29 #include <linux/serial_core.h>
  30 #include <linux/serial_reg.h>
  31
  32 #include "8250.h"
  33
  34 /** ingenic_uart_config: SOC specific config data. */
  35 struct ingenic_uart_config {
  36         int tx_loadsz;
  37         int fifosize;
  38 };
  39
  40 struct ingenic_uart_data {
  41         struct clk      *clk_module;
  42         struct clk      *clk_baud;
  43         int             line;
  44 };
  45
  46 static const struct of_device_id of_match[];
  47
  48 #define UART_FCR_UME    BIT(4)
  49
  50 #define UART_MCR_MDCE   BIT(7)
  51 #define UART_MCR_FCM    BIT(6)
  52
  53 #ifdef CONFIG_SERIAL_EARLYCON
  54 static struct earlycon_device *early_device;
  55
  56 static uint8_t __init early_in(struct uart_port *port, int offset)
  57 {
  58         return readl(port->membase + (offset << 2));
  59 }
  60
  61 static void __init early_out(struct uart_port *port, int offset, uint8_t value)
  62 {
  63         writel(value, port->membase + (offset << 2));
  64 }
  65
  66 static void __init ingenic_early_console_putc(struct uart_port *port, int c)
  67 {
  68         uint8_t lsr;
  69
  70         do {
  71                 lsr = early_in(port, UART_LSR);
  72         } while ((lsr & UART_LSR_TEMT) == 0);
  73
  74         early_out(port, UART_TX, c);
  75 }
  76
  77 static void __init ingenic_early_console_write(struct console *console,
  78                                               const char *s, unsigned int count)
  79 {
  80         uart_console_write(&early_device->port, s, count,
  81                            ingenic_early_console_putc);
  82 }
  83
  84 static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev)
  85 {
  86         void *fdt = initial_boot_params;
  87         const __be32 *prop;
  88         int offset;
  89
  90         offset = fdt_path_offset(fdt, "/ext");
  91         if (offset < 0)
  92                 return;
  93
  94         prop = fdt_getprop(fdt, offset, "clock-frequency", NULL);
  95         if (!prop)
  96                 return;
  97
  98         dev->port.uartclk = be32_to_cpup(prop);
  99 }
 100
 101 static int __init ingenic_early_console_setup(struct earlycon_device *dev,
 102                                               const char *opt)
 103 {
 104         struct uart_port *port = &dev->port;
 105         unsigned int baud, divisor;
 106
 107         if (!dev->port.membase)
 108                 return -ENODEV;
 109
 110         ingenic_early_console_setup_clock(dev);
 111
 112         baud = dev->baud ?: 115200;
 113         divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * baud);
 114
 115         early_out(port, UART_IER, 0);
 116         early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
 117         early_out(port, UART_DLL, 0);
 118         early_out(port, UART_DLM, 0);
 119         early_out(port, UART_LCR, UART_LCR_WLEN8);
 120         early_out(port, UART_FCR, UART_FCR_UME | UART_FCR_CLEAR_XMIT |
 121                         UART_FCR_CLEAR_RCVR | UART_FCR_ENABLE_FIFO);
 122         early_out(port, UART_MCR, UART_MCR_RTS | UART_MCR_DTR);
 123
 124         early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
 125         early_out(port, UART_DLL, divisor & 0xff);
 126         early_out(port, UART_DLM, (divisor >> 8) & 0xff);
 127         early_out(port, UART_LCR, UART_LCR_WLEN8);
 128
 129         early_device = dev;
 130         dev->con->write = ingenic_early_console_write;
 131
 132         return 0;
 133 }
 134
 135 EARLYCON_DECLARE(jz4740_uart, ingenic_early_console_setup);
 136 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
 137                     ingenic_early_console_setup);
 138
 139 EARLYCON_DECLARE(jz4775_uart, ingenic_early_console_setup);
 140 OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
 141                     ingenic_early_console_setup);
 142
 143 EARLYCON_DECLARE(jz4780_uart, ingenic_early_console_setup);
 144 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
 145                     ingenic_early_console_setup);
 146 #endif /* CONFIG_SERIAL_EARLYCON */
 147
 148 static void ingenic_uart_serial_out(struct uart_port *p, int offset, int value)
 149 {
 150         int ier;
 151
 152         switch (offset) {
 153         case UART_FCR:
 154                 /* UART module enable */
 155                 value |= UART_FCR_UME;
 156                 break;
 157
 158         case UART_IER:
 159                 /*
 160                  * Enable receive timeout interrupt with the receive line
 161                  * status interrupt.
 162                  */
 163                 value |= (value & 0x4) << 2;
 164                 break;
 165
 166         case UART_MCR:
 167                 /*
 168                  * If we have enabled modem status IRQs we should enable
 169                  * modem mode.
 170                  */
 171                 ier = p->serial_in(p, UART_IER);
 172
 173                 if (ier & UART_IER_MSI)
 174                         value |= UART_MCR_MDCE | UART_MCR_FCM;
 175                 else
 176                         value &= ~(UART_MCR_MDCE | UART_MCR_FCM);
 177                 break;
 178
 179         default:
 180                 break;
 181         }
 182
 183         writeb(value, p->membase + (offset << p->regshift));
 184 }
 185
 186 static unsigned int ingenic_uart_serial_in(struct uart_port *p, int offset)
 187 {
 188         unsigned int value;
 189
 190         value = readb(p->membase + (offset << p->regshift));
 191
 192         /* Hide non-16550 compliant bits from higher levels */
 193         switch (offset) {
 194         case UART_FCR:
 195                 value &= ~UART_FCR_UME;
 196                 break;
 197
 198         case UART_MCR:
 199                 value &= ~(UART_MCR_MDCE | UART_MCR_FCM);
 200                 break;
 201
 202         default:
 203                 break;
 204         }
 205         return value;
 206 }
 207
 208 static int ingenic_uart_probe(struct platform_device *pdev)
 209 {
 210         struct uart_8250_port uart = {};
 211         struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 212         struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 213         struct ingenic_uart_data *data;
 214         const struct ingenic_uart_config *cdata;
 215         const struct of_device_id *match;
 216         int err, line;
 217
 218         match = of_match_device(of_match, &pdev->dev);
 219         if (!match) {
 220                 dev_err(&pdev->dev, "Error: No device match found\n");
 221                 return -ENODEV;
 222         }
 223         cdata = match->data;
 224
 225         if (!regs || !irq) {
 226                 dev_err(&pdev->dev, "no registers/irq defined\n");
 227                 return -EINVAL;
 228         }
 229
 230         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 231         if (!data)
 232                 return -ENOMEM;
 233
 234         spin_lock_init(&uart.port.lock);
 235         uart.port.type = PORT_16550A;
 236         uart.port.flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE;
 237         uart.port.iotype = UPIO_MEM;
 238         uart.port.mapbase = regs->start;
 239         uart.port.regshift = 2;
 240         uart.port.serial_out = ingenic_uart_serial_out;
 241         uart.port.serial_in = ingenic_uart_serial_in;
 242         uart.port.irq = irq->start;
 243         uart.port.dev = &pdev->dev;
 244         uart.port.fifosize = cdata->fifosize;
 245         uart.tx_loadsz = cdata->tx_loadsz;
 246         uart.capabilities = UART_CAP_FIFO | UART_CAP_RTOIE;
 247
 248         /* Check for a fixed line number */
 249         line = of_alias_get_id(pdev->dev.of_node, "serial");
 250         if (line >= 0)
 251                 uart.port.line = line;
 252
 253         uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
 254                                          resource_size(regs));
 255         if (!uart.port.membase)
 256                 return -ENOMEM;
 257
 258         data->clk_module = devm_clk_get(&pdev->dev, "module");
 259         if (IS_ERR(data->clk_module)) {
 260                 err = PTR_ERR(data->clk_module);
 261                 if (err != -EPROBE_DEFER)
 262                         dev_err(&pdev->dev,
 263                                 "unable to get module clock: %d\n", err);
 264                 return err;
 265         }
 266
 267         data->clk_baud = devm_clk_get(&pdev->dev, "baud");
 268         if (IS_ERR(data->clk_baud)) {
 269                 err = PTR_ERR(data->clk_baud);
 270                 if (err != -EPROBE_DEFER)
 271                         dev_err(&pdev->dev,
 272                                 "unable to get baud clock: %d\n", err);
 273                 return err;
 274         }
 275
 276         err = clk_prepare_enable(data->clk_module);
 277         if (err) {
 278                 dev_err(&pdev->dev, "could not enable module clock: %d\n", err);
 279                 goto out;
 280         }
 281
 282         err = clk_prepare_enable(data->clk_baud);
 283         if (err) {
 284                 dev_err(&pdev->dev, "could not enable baud clock: %d\n", err);
 285                 goto out_disable_moduleclk;
 286         }
 287         uart.port.uartclk = clk_get_rate(data->clk_baud);
 288
 289         data->line = serial8250_register_8250_port(&uart);
 290         if (data->line < 0) {
 291                 err = data->line;
 292                 goto out_disable_baudclk;
 293         }
 294
 295         platform_set_drvdata(pdev, data);
 296         return 0;
 297
 298 out_disable_baudclk:
 299         clk_disable_unprepare(data->clk_baud);
 300 out_disable_moduleclk:
 301         clk_disable_unprepare(data->clk_module);
 302 out:
 303         return err;
 304 }
 305
 306 static const struct ingenic_uart_config jz4740_uart_config = {
 307         .tx_loadsz = 8,
 308         .fifosize = 16,
 309 };
 310
 311 static const struct ingenic_uart_config jz4760_uart_config = {
 312         .tx_loadsz = 16,
 313         .fifosize = 32,
 314 };
 315
 316 static const struct ingenic_uart_config jz4780_uart_config = {
 317         .tx_loadsz = 32,
 318         .fifosize = 64,
 319 };
 320
 321 static const struct of_device_id of_match[] = {
 322         { .compatible = "ingenic,jz4740-uart", .data = &jz4740_uart_config },
 323         { .compatible = "ingenic,jz4760-uart", .data = &jz4760_uart_config },
 324         { .compatible = "ingenic,jz4775-uart", .data = &jz4760_uart_config },
 325         { .compatible = "ingenic,jz4780-uart", .data = &jz4780_uart_config },
 326         { /* sentinel */ }
 327 };
 328
 329 static struct platform_driver ingenic_uart_platform_driver = {
 330         .driver = {
 331                 .name                   = "ingenic-uart",
 332                 .of_match_table         = of_match,
 333                 .suppress_bind_attrs    = true,
 334         },
 335         .probe                  = ingenic_uart_probe,
 336 };
 337 builtin_platform_driver(ingenic_uart_platform_driver);