drivers/tty/serial/8250/8250_pci.c

   1 /*
   2  *  Probe module for 8250/16550-type PCI serial ports.
   3  *
   4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  */
  12 #include <linux/module.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/tty.h>
  20 #include <linux/serial_reg.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/8250_pci.h>
  23 #include <linux/bitops.h>
  24
  25 #include <asm/byteorder.h>
  26 #include <asm/io.h>
  27
  28 #include "8250.h"
  29
  30 #undef SERIAL_DEBUG_PCI
  31
  32 /*
  33  * init function returns:
  34  *  > 0 - number of ports
  35  *  = 0 - use board->num_ports
  36  *  < 0 - error
  37  */
  38 struct pci_serial_quirk {
  39         u32     vendor;
  40         u32     device;
  41         u32     subvendor;
  42         u32     subdevice;
  43         int     (*probe)(struct pci_dev *dev);
  44         int     (*init)(struct pci_dev *dev);
  45         int     (*setup)(struct serial_private *,
  46                          const struct pciserial_board *,
  47                          struct uart_8250_port *, int);
  48         void    (*exit)(struct pci_dev *dev);
  49 };
  50
  51 #define PCI_NUM_BAR_RESOURCES   6
  52
  53 struct serial_private {
  54         struct pci_dev          *dev;
  55         unsigned int            nr;
  56         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  57         struct pci_serial_quirk *quirk;
  58         int                     line[0];
  59 };
  60
  61 static int pci_default_setup(struct serial_private*,
  62           const struct pciserial_board*, struct uart_8250_port *, int);
  63
  64 static void moan_device(const char *str, struct pci_dev *dev)
  65 {
  66         printk(KERN_WARNING
  67                "%s: %s\n"
  68                "Please send the output of lspci -vv, this\n"
  69                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  70                "manufacturer and name of serial board or\n"
  71                "modem board to rmk+serial@arm.linux.org.uk.\n",
  72                pci_name(dev), str, dev->vendor, dev->device,
  73                dev->subsystem_vendor, dev->subsystem_device);
  74 }
  75
  76 static int
  77 setup_port(struct serial_private *priv, struct uart_8250_port *port,
  78            int bar, int offset, int regshift)
  79 {
  80         struct pci_dev *dev = priv->dev;
  81         unsigned long base, len;
  82
  83         if (bar >= PCI_NUM_BAR_RESOURCES)
  84                 return -EINVAL;
  85
  86         base = pci_resource_start(dev, bar);
  87
  88         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  89                 len =  pci_resource_len(dev, bar);
  90
  91                 if (!priv->remapped_bar[bar])
  92                         priv->remapped_bar[bar] = ioremap_nocache(base, len);
  93                 if (!priv->remapped_bar[bar])
  94                         return -ENOMEM;
  95
  96                 port->port.iotype = UPIO_MEM;
  97                 port->port.iobase = 0;
  98                 port->port.mapbase = base + offset;
  99                 port->port.membase = priv->remapped_bar[bar] + offset;
 100                 port->port.regshift = regshift;
 101         } else {
 102                 port->port.iotype = UPIO_PORT;
 103                 port->port.iobase = base + offset;
 104                 port->port.mapbase = 0;
 105                 port->port.membase = NULL;
 106                 port->port.regshift = 0;
 107         }
 108         return 0;
 109 }
 110
 111 /*
 112  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 113  */
 114 static int addidata_apci7800_setup(struct serial_private *priv,
 115                                 const struct pciserial_board *board,
 116                                 struct uart_8250_port *port, int idx)
 117 {
 118         unsigned int bar = 0, offset = board->first_offset;
 119         bar = FL_GET_BASE(board->flags);
 120
 121         if (idx < 2) {
 122                 offset += idx * board->uart_offset;
 123         } else if ((idx >= 2) && (idx < 4)) {
 124                 bar += 1;
 125                 offset += ((idx - 2) * board->uart_offset);
 126         } else if ((idx >= 4) && (idx < 6)) {
 127                 bar += 2;
 128                 offset += ((idx - 4) * board->uart_offset);
 129         } else if (idx >= 6) {
 130                 bar += 3;
 131                 offset += ((idx - 6) * board->uart_offset);
 132         }
 133
 134         return setup_port(priv, port, bar, offset, board->reg_shift);
 135 }
 136
 137 /*
 138  * AFAVLAB uses a different mixture of BARs and offsets
 139  * Not that ugly ;) -- HW
 140  */
 141 static int
 142 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 143               struct uart_8250_port *port, int idx)
 144 {
 145         unsigned int bar, offset = board->first_offset;
 146
 147         bar = FL_GET_BASE(board->flags);
 148         if (idx < 4)
 149                 bar += idx;
 150         else {
 151                 bar = 4;
 152                 offset += (idx - 4) * board->uart_offset;
 153         }
 154
 155         return setup_port(priv, port, bar, offset, board->reg_shift);
 156 }
 157
 158 /*
 159  * HP's Remote Management Console.  The Diva chip came in several
 160  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 161  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 162  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 163  * one Diva chip, but it has been expanded to 5 UARTs.
 164  */
 165 static int pci_hp_diva_init(struct pci_dev *dev)
 166 {
 167         int rc = 0;
 168
 169         switch (dev->subsystem_device) {
 170         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 171         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 172         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 173         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 174                 rc = 3;
 175                 break;
 176         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 177                 rc = 2;
 178                 break;
 179         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 180                 rc = 4;
 181                 break;
 182         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 183         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 184                 rc = 1;
 185                 break;
 186         }
 187
 188         return rc;
 189 }
 190
 191 /*
 192  * HP's Diva chip puts the 4th/5th serial port further out, and
 193  * some serial ports are supposed to be hidden on certain models.
 194  */
 195 static int
 196 pci_hp_diva_setup(struct serial_private *priv,
 197                 const struct pciserial_board *board,
 198                 struct uart_8250_port *port, int idx)
 199 {
 200         unsigned int offset = board->first_offset;
 201         unsigned int bar = FL_GET_BASE(board->flags);
 202
 203         switch (priv->dev->subsystem_device) {
 204         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 205                 if (idx == 3)
 206                         idx++;
 207                 break;
 208         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 209                 if (idx > 0)
 210                         idx++;
 211                 if (idx > 2)
 212                         idx++;
 213                 break;
 214         }
 215         if (idx > 2)
 216                 offset = 0x18;
 217
 218         offset += idx * board->uart_offset;
 219
 220         return setup_port(priv, port, bar, offset, board->reg_shift);
 221 }
 222
 223 /*
 224  * Added for EKF Intel i960 serial boards
 225  */
 226 static int pci_inteli960ni_init(struct pci_dev *dev)
 227 {
 228         unsigned long oldval;
 229
 230         if (!(dev->subsystem_device & 0x1000))
 231                 return -ENODEV;
 232
 233         /* is firmware started? */
 234         pci_read_config_dword(dev, 0x44, (void *)&oldval);
 235         if (oldval == 0x00001000L) { /* RESET value */
 236                 printk(KERN_DEBUG "Local i960 firmware missing");
 237                 return -ENODEV;
 238         }
 239         return 0;
 240 }
 241
 242 /*
 243  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 244  * that the card interrupt be explicitly enabled or disabled.  This
 245  * seems to be mainly needed on card using the PLX which also use I/O
 246  * mapped memory.
 247  */
 248 static int pci_plx9050_init(struct pci_dev *dev)
 249 {
 250         u8 irq_config;
 251         void __iomem *p;
 252
 253         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 254                 moan_device("no memory in bar 0", dev);
 255                 return 0;
 256         }
 257
 258         irq_config = 0x41;
 259         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 260             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 261                 irq_config = 0x43;
 262
 263         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 264             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 265                 /*
 266                  * As the megawolf cards have the int pins active
 267                  * high, and have 2 UART chips, both ints must be
 268                  * enabled on the 9050. Also, the UARTS are set in
 269                  * 16450 mode by default, so we have to enable the
 270                  * 16C950 'enhanced' mode so that we can use the
 271                  * deep FIFOs
 272                  */
 273                 irq_config = 0x5b;
 274         /*
 275          * enable/disable interrupts
 276          */
 277         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 278         if (p == NULL)
 279                 return -ENOMEM;
 280         writel(irq_config, p + 0x4c);
 281
 282         /*
 283          * Read the register back to ensure that it took effect.
 284          */
 285         readl(p + 0x4c);
 286         iounmap(p);
 287
 288         return 0;
 289 }
 290
 291 static void pci_plx9050_exit(struct pci_dev *dev)
 292 {
 293         u8 __iomem *p;
 294
 295         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 296                 return;
 297
 298         /*
 299          * disable interrupts
 300          */
 301         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 302         if (p != NULL) {
 303                 writel(0, p + 0x4c);
 304
 305                 /*
 306                  * Read the register back to ensure that it took effect.
 307                  */
 308                 readl(p + 0x4c);
 309                 iounmap(p);
 310         }
 311 }
 312
 313 #define NI8420_INT_ENABLE_REG   0x38
 314 #define NI8420_INT_ENABLE_BIT   0x2000
 315
 316 static void pci_ni8420_exit(struct pci_dev *dev)
 317 {
 318         void __iomem *p;
 319         unsigned long base, len;
 320         unsigned int bar = 0;
 321
 322         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 323                 moan_device("no memory in bar", dev);
 324                 return;
 325         }
 326
 327         base = pci_resource_start(dev, bar);
 328         len =  pci_resource_len(dev, bar);
 329         p = ioremap_nocache(base, len);
 330         if (p == NULL)
 331                 return;
 332
 333         /* Disable the CPU Interrupt */
 334         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 335                p + NI8420_INT_ENABLE_REG);
 336         iounmap(p);
 337 }
 338
 339
 340 /* MITE registers */
 341 #define MITE_IOWBSR1    0xc4
 342 #define MITE_IOWCR1     0xf4
 343 #define MITE_LCIMR1     0x08
 344 #define MITE_LCIMR2     0x10
 345
 346 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 347
 348 static void pci_ni8430_exit(struct pci_dev *dev)
 349 {
 350         void __iomem *p;
 351         unsigned long base, len;
 352         unsigned int bar = 0;
 353
 354         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 355                 moan_device("no memory in bar", dev);
 356                 return;
 357         }
 358
 359         base = pci_resource_start(dev, bar);
 360         len =  pci_resource_len(dev, bar);
 361         p = ioremap_nocache(base, len);
 362         if (p == NULL)
 363                 return;
 364
 365         /* Disable the CPU Interrupt */
 366         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 367         iounmap(p);
 368 }
 369
 370 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 371 static int
 372 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 373                 struct uart_8250_port *port, int idx)
 374 {
 375         unsigned int bar, offset = board->first_offset;
 376
 377         bar = 0;
 378
 379         if (idx < 4) {
 380                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 381                 offset += idx * board->uart_offset;
 382         } else if (idx < 8) {
 383                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 384                 offset += idx * board->uart_offset + 0xC00;
 385         } else /* we have only 8 ports on PMC-OCTALPRO */
 386                 return 1;
 387
 388         return setup_port(priv, port, bar, offset, board->reg_shift);
 389 }
 390
 391 /*
 392 * This does initialization for PMC OCTALPRO cards:
 393 * maps the device memory, resets the UARTs (needed, bc
 394 * if the module is removed and inserted again, the card
 395 * is in the sleep mode) and enables global interrupt.
 396 */
 397
 398 /* global control register offset for SBS PMC-OctalPro */
 399 #define OCT_REG_CR_OFF          0x500
 400
 401 static int sbs_init(struct pci_dev *dev)
 402 {
 403         u8 __iomem *p;
 404
 405         p = pci_ioremap_bar(dev, 0);
 406
 407         if (p == NULL)
 408                 return -ENOMEM;
 409         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 410         writeb(0x10, p + OCT_REG_CR_OFF);
 411         udelay(50);
 412         writeb(0x0, p + OCT_REG_CR_OFF);
 413
 414         /* Set bit-2 (INTENABLE) of Control Register */
 415         writeb(0x4, p + OCT_REG_CR_OFF);
 416         iounmap(p);
 417
 418         return 0;
 419 }
 420
 421 /*
 422  * Disables the global interrupt of PMC-OctalPro
 423  */
 424
 425 static void sbs_exit(struct pci_dev *dev)
 426 {
 427         u8 __iomem *p;
 428
 429         p = pci_ioremap_bar(dev, 0);
 430         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 431         if (p != NULL)
 432                 writeb(0, p + OCT_REG_CR_OFF);
 433         iounmap(p);
 434 }
 435
 436 /*
 437  * SIIG serial cards have an PCI interface chip which also controls
 438  * the UART clocking frequency. Each UART can be clocked independently
 439  * (except cards equipped with 4 UARTs) and initial clocking settings
 440  * are stored in the EEPROM chip. It can cause problems because this
 441  * version of serial driver doesn't support differently clocked UART's
 442  * on single PCI card. To prevent this, initialization functions set
 443  * high frequency clocking for all UART's on given card. It is safe (I
 444  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 445  * with other OSes (like M$ DOS).
 446  *
 447  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 448  *
 449  * There is two family of SIIG serial cards with different PCI
 450  * interface chip and different configuration methods:
 451  *     - 10x cards have control registers in IO and/or memory space;
 452  *     - 20x cards have control registers in standard PCI configuration space.
 453  *
 454  * Note: all 10x cards have PCI device ids 0x10..
 455  *       all 20x cards have PCI device ids 0x20..
 456  *
 457  * There are also Quartet Serial cards which use Oxford Semiconductor
 458  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 459  *
 460  * Note: some SIIG cards are probed by the parport_serial object.
 461  */
 462
 463 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 464 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 465
 466 static int pci_siig10x_init(struct pci_dev *dev)
 467 {
 468         u16 data;
 469         void __iomem *p;
 470
 471         switch (dev->device & 0xfff8) {
 472         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 473                 data = 0xffdf;
 474                 break;
 475         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 476                 data = 0xf7ff;
 477                 break;
 478         default:                        /* 1S1P, 4S */
 479                 data = 0xfffb;
 480                 break;
 481         }
 482
 483         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 484         if (p == NULL)
 485                 return -ENOMEM;
 486
 487         writew(readw(p + 0x28) & data, p + 0x28);
 488         readw(p + 0x28);
 489         iounmap(p);
 490         return 0;
 491 }
 492
 493 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 494 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 495
 496 static int pci_siig20x_init(struct pci_dev *dev)
 497 {
 498         u8 data;
 499
 500         /* Change clock frequency for the first UART. */
 501         pci_read_config_byte(dev, 0x6f, &data);
 502         pci_write_config_byte(dev, 0x6f, data & 0xef);
 503
 504         /* If this card has 2 UART, we have to do the same with second UART. */
 505         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 506             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 507                 pci_read_config_byte(dev, 0x73, &data);
 508                 pci_write_config_byte(dev, 0x73, data & 0xef);
 509         }
 510         return 0;
 511 }
 512
 513 static int pci_siig_init(struct pci_dev *dev)
 514 {
 515         unsigned int type = dev->device & 0xff00;
 516
 517         if (type == 0x1000)
 518                 return pci_siig10x_init(dev);
 519         else if (type == 0x2000)
 520                 return pci_siig20x_init(dev);
 521
 522         moan_device("Unknown SIIG card", dev);
 523         return -ENODEV;
 524 }
 525
 526 static int pci_siig_setup(struct serial_private *priv,
 527                           const struct pciserial_board *board,
 528                           struct uart_8250_port *port, int idx)
 529 {
 530         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 531
 532         if (idx > 3) {
 533                 bar = 4;
 534                 offset = (idx - 4) * 8;
 535         }
 536
 537         return setup_port(priv, port, bar, offset, 0);
 538 }
 539
 540 /*
 541  * Timedia has an explosion of boards, and to avoid the PCI table from
 542  * growing *huge*, we use this function to collapse some 70 entries
 543  * in the PCI table into one, for sanity's and compactness's sake.
 544  */
 545 static const unsigned short timedia_single_port[] = {
 546         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 547 };
 548
 549 static const unsigned short timedia_dual_port[] = {
 550         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 551         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 552         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 553         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 554         0xD079, 0
 555 };
 556
 557 static const unsigned short timedia_quad_port[] = {
 558         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 559         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 560         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 561         0xB157, 0
 562 };
 563
 564 static const unsigned short timedia_eight_port[] = {
 565         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 566         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 567 };
 568
 569 static const struct timedia_struct {
 570         int num;
 571         const unsigned short *ids;
 572 } timedia_data[] = {
 573         { 1, timedia_single_port },
 574         { 2, timedia_dual_port },
 575         { 4, timedia_quad_port },
 576         { 8, timedia_eight_port }
 577 };
 578
 579 /*
 580  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
 581  * listing them individually, this driver merely grabs them all with
 582  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
 583  * and should be left free to be claimed by parport_serial instead.
 584  */
 585 static int pci_timedia_probe(struct pci_dev *dev)
 586 {
 587         /*
 588          * Check the third digit of the subdevice ID
 589          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
 590          */
 591         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
 592                 dev_info(&dev->dev,
 593                         "ignoring Timedia subdevice %04x for parport_serial\n",
 594                         dev->subsystem_device);
 595                 return -ENODEV;
 596         }
 597
 598         return 0;
 599 }
 600
 601 static int pci_timedia_init(struct pci_dev *dev)
 602 {
 603         const unsigned short *ids;
 604         int i, j;
 605
 606         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 607                 ids = timedia_data[i].ids;
 608                 for (j = 0; ids[j]; j++)
 609                         if (dev->subsystem_device == ids[j])
 610                                 return timedia_data[i].num;
 611         }
 612         return 0;
 613 }
 614
 615 /*
 616  * Timedia/SUNIX uses a mixture of BARs and offsets
 617  * Ugh, this is ugly as all hell --- TYT
 618  */
 619 static int
 620 pci_timedia_setup(struct serial_private *priv,
 621                   const struct pciserial_board *board,
 622                   struct uart_8250_port *port, int idx)
 623 {
 624         unsigned int bar = 0, offset = board->first_offset;
 625
 626         switch (idx) {
 627         case 0:
 628                 bar = 0;
 629                 break;
 630         case 1:
 631                 offset = board->uart_offset;
 632                 bar = 0;
 633                 break;
 634         case 2:
 635                 bar = 1;
 636                 break;
 637         case 3:
 638                 offset = board->uart_offset;
 639                 /* FALLTHROUGH */
 640         case 4: /* BAR 2 */
 641         case 5: /* BAR 3 */
 642         case 6: /* BAR 4 */
 643         case 7: /* BAR 5 */
 644                 bar = idx - 2;
 645         }
 646
 647         return setup_port(priv, port, bar, offset, board->reg_shift);
 648 }
 649
 650 /*
 651  * Some Titan cards are also a little weird
 652  */
 653 static int
 654 titan_400l_800l_setup(struct serial_private *priv,
 655                       const struct pciserial_board *board,
 656                       struct uart_8250_port *port, int idx)
 657 {
 658         unsigned int bar, offset = board->first_offset;
 659
 660         switch (idx) {
 661         case 0:
 662                 bar = 1;
 663                 break;
 664         case 1:
 665                 bar = 2;
 666                 break;
 667         default:
 668                 bar = 4;
 669                 offset = (idx - 2) * board->uart_offset;
 670         }
 671
 672         return setup_port(priv, port, bar, offset, board->reg_shift);
 673 }
 674
 675 static int pci_xircom_init(struct pci_dev *dev)
 676 {
 677         msleep(100);
 678         return 0;
 679 }
 680
 681 static int pci_ni8420_init(struct pci_dev *dev)
 682 {
 683         void __iomem *p;
 684         unsigned long base, len;
 685         unsigned int bar = 0;
 686
 687         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 688                 moan_device("no memory in bar", dev);
 689                 return 0;
 690         }
 691
 692         base = pci_resource_start(dev, bar);
 693         len =  pci_resource_len(dev, bar);
 694         p = ioremap_nocache(base, len);
 695         if (p == NULL)
 696                 return -ENOMEM;
 697
 698         /* Enable CPU Interrupt */
 699         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 700                p + NI8420_INT_ENABLE_REG);
 701
 702         iounmap(p);
 703         return 0;
 704 }
 705
 706 #define MITE_IOWBSR1_WSIZE      0xa
 707 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 708 #define MITE_IOWBSR1_WENAB      (1 << 7)
 709 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 710 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 711 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 712
 713 static int pci_ni8430_init(struct pci_dev *dev)
 714 {
 715         void __iomem *p;
 716         unsigned long base, len;
 717         u32 device_window;
 718         unsigned int bar = 0;
 719
 720         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 721                 moan_device("no memory in bar", dev);
 722                 return 0;
 723         }
 724
 725         base = pci_resource_start(dev, bar);
 726         len =  pci_resource_len(dev, bar);
 727         p = ioremap_nocache(base, len);
 728         if (p == NULL)
 729                 return -ENOMEM;
 730
 731         /* Set device window address and size in BAR0 */
 732         device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 733                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 734         writel(device_window, p + MITE_IOWBSR1);
 735
 736         /* Set window access to go to RAMSEL IO address space */
 737         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 738                p + MITE_IOWCR1);
 739
 740         /* Enable IO Bus Interrupt 0 */
 741         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 742
 743         /* Enable CPU Interrupt */
 744         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 745
 746         iounmap(p);
 747         return 0;
 748 }
 749
 750 /* UART Port Control Register */
 751 #define NI8430_PORTCON  0x0f
 752 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 753
 754 static int
 755 pci_ni8430_setup(struct serial_private *priv,
 756                  const struct pciserial_board *board,
 757                  struct uart_8250_port *port, int idx)
 758 {
 759         void __iomem *p;
 760         unsigned long base, len;
 761         unsigned int bar, offset = board->first_offset;
 762
 763         if (idx >= board->num_ports)
 764                 return 1;
 765
 766         bar = FL_GET_BASE(board->flags);
 767         offset += idx * board->uart_offset;
 768
 769         base = pci_resource_start(priv->dev, bar);
 770         len =  pci_resource_len(priv->dev, bar);
 771         p = ioremap_nocache(base, len);
 772
 773         /* enable the transceiver */
 774         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 775                p + offset + NI8430_PORTCON);
 776
 777         iounmap(p);
 778
 779         return setup_port(priv, port, bar, offset, board->reg_shift);
 780 }
 781
 782 static int pci_netmos_9900_setup(struct serial_private *priv,
 783                                 const struct pciserial_board *board,
 784                                 struct uart_8250_port *port, int idx)
 785 {
 786         unsigned int bar;
 787
 788         if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
 789                 /* netmos apparently orders BARs by datasheet layout, so serial
 790                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 791                  */
 792                 bar = 3 * idx;
 793
 794                 return setup_port(priv, port, bar, 0, board->reg_shift);
 795         } else {
 796                 return pci_default_setup(priv, board, port, idx);
 797         }
 798 }
 799
 800 /* the 99xx series comes with a range of device IDs and a variety
 801  * of capabilities:
 802  *
 803  * 9900 has varying capabilities and can cascade to sub-controllers
 804  *   (cascading should be purely internal)
 805  * 9904 is hardwired with 4 serial ports
 806  * 9912 and 9922 are hardwired with 2 serial ports
 807  */
 808 static int pci_netmos_9900_numports(struct pci_dev *dev)
 809 {
 810         unsigned int c = dev->class;
 811         unsigned int pi;
 812         unsigned short sub_serports;
 813
 814         pi = (c & 0xff);
 815
 816         if (pi == 2) {
 817                 return 1;
 818         } else if ((pi == 0) &&
 819                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 820                 /* two possibilities: 0x30ps encodes number of parallel and
 821                  * serial ports, or 0x1000 indicates *something*. This is not
 822                  * immediately obvious, since the 2s1p+4s configuration seems
 823                  * to offer all functionality on functions 0..2, while still
 824                  * advertising the same function 3 as the 4s+2s1p config.
 825                  */
 826                 sub_serports = dev->subsystem_device & 0xf;
 827                 if (sub_serports > 0) {
 828                         return sub_serports;
 829                 } else {
 830                         printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 831                         return 0;
 832                 }
 833         }
 834
 835         moan_device("unknown NetMos/Mostech program interface", dev);
 836         return 0;
 837 }
 838
 839 static int pci_netmos_init(struct pci_dev *dev)
 840 {
 841         /* subdevice 0x00PS means <P> parallel, <S> serial */
 842         unsigned int num_serial = dev->subsystem_device & 0xf;
 843
 844         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 845                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 846                 return 0;
 847
 848         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 849                         dev->subsystem_device == 0x0299)
 850                 return 0;
 851
 852         switch (dev->device) { /* FALLTHROUGH on all */
 853                 case PCI_DEVICE_ID_NETMOS_9904:
 854                 case PCI_DEVICE_ID_NETMOS_9912:
 855                 case PCI_DEVICE_ID_NETMOS_9922:
 856                 case PCI_DEVICE_ID_NETMOS_9900:
 857                         num_serial = pci_netmos_9900_numports(dev);
 858                         break;
 859
 860                 default:
 861                         if (num_serial == 0 ) {
 862                                 moan_device("unknown NetMos/Mostech device", dev);
 863                         }
 864         }
 865
 866         if (num_serial == 0)
 867                 return -ENODEV;
 868
 869         return num_serial;
 870 }
 871
 872 /*
 873  * These chips are available with optionally one parallel port and up to
 874  * two serial ports. Unfortunately they all have the same product id.
 875  *
 876  * Basic configuration is done over a region of 32 I/O ports. The base
 877  * ioport is called INTA or INTC, depending on docs/other drivers.
 878  *
 879  * The region of the 32 I/O ports is configured in POSIO0R...
 880  */
 881
 882 /* registers */
 883 #define ITE_887x_MISCR          0x9c
 884 #define ITE_887x_INTCBAR        0x78
 885 #define ITE_887x_UARTBAR        0x7c
 886 #define ITE_887x_PS0BAR         0x10
 887 #define ITE_887x_POSIO0         0x60
 888
 889 /* I/O space size */
 890 #define ITE_887x_IOSIZE         32
 891 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 892 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 893 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 894 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 895 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 896 #define ITE_887x_POSIO_SPEED            (3 << 29)
 897 /* enable IO_Space bit */
 898 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 899
 900 static int pci_ite887x_init(struct pci_dev *dev)
 901 {
 902         /* inta_addr are the configuration addresses of the ITE */
 903         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 904                                                         0x200, 0x280, 0 };
 905         int ret, i, type;
 906         struct resource *iobase = NULL;
 907         u32 miscr, uartbar, ioport;
 908
 909         /* search for the base-ioport */
 910         i = 0;
 911         while (inta_addr[i] && iobase == NULL) {
 912                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 913                                                                 "ite887x");
 914                 if (iobase != NULL) {
 915                         /* write POSIO0R - speed | size | ioport */
 916                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 917                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 918                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 919                         /* write INTCBAR - ioport */
 920                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 921                                                                 inta_addr[i]);
 922                         ret = inb(inta_addr[i]);
 923                         if (ret != 0xff) {
 924                                 /* ioport connected */
 925                                 break;
 926                         }
 927                         release_region(iobase->start, ITE_887x_IOSIZE);
 928                         iobase = NULL;
 929                 }
 930                 i++;
 931         }
 932
 933         if (!inta_addr[i]) {
 934                 printk(KERN_ERR "ite887x: could not find iobase\n");
 935                 return -ENODEV;
 936         }
 937
 938         /* start of undocumented type checking (see parport_pc.c) */
 939         type = inb(iobase->start + 0x18) & 0x0f;
 940
 941         switch (type) {
 942         case 0x2:       /* ITE8871 (1P) */
 943         case 0xa:       /* ITE8875 (1P) */
 944                 ret = 0;
 945                 break;
 946         case 0xe:       /* ITE8872 (2S1P) */
 947                 ret = 2;
 948                 break;
 949         case 0x6:       /* ITE8873 (1S) */
 950                 ret = 1;
 951                 break;
 952         case 0x8:       /* ITE8874 (2S) */
 953                 ret = 2;
 954                 break;
 955         default:
 956                 moan_device("Unknown ITE887x", dev);
 957                 ret = -ENODEV;
 958         }
 959
 960         /* configure all serial ports */
 961         for (i = 0; i < ret; i++) {
 962                 /* read the I/O port from the device */
 963                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 964                                                                 &ioport);
 965                 ioport &= 0x0000FF00;   /* the actual base address */
 966                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 967                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 968                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 969
 970                 /* write the ioport to the UARTBAR */
 971                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 972                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 973                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 974                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 975
 976                 /* get current config */
 977                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 978                 /* disable interrupts (UARTx_Routing[3:0]) */
 979                 miscr &= ~(0xf << (12 - 4 * i));
 980                 /* activate the UART (UARTx_En) */
 981                 miscr |= 1 << (23 - i);
 982                 /* write new config with activated UART */
 983                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 984         }
 985
 986         if (ret <= 0) {
 987                 /* the device has no UARTs if we get here */
 988                 release_region(iobase->start, ITE_887x_IOSIZE);
 989         }
 990
 991         return ret;
 992 }
 993
 994 static void pci_ite887x_exit(struct pci_dev *dev)
 995 {
 996         u32 ioport;
 997         /* the ioport is bit 0-15 in POSIO0R */
 998         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 999         ioport &= 0xffff;
1000         release_region(ioport, ITE_887x_IOSIZE);
1001 }
1002
1003 /*
1004  * Oxford Semiconductor Inc.
1005  * Check that device is part of the Tornado range of devices, then determine
1006  * the number of ports available on the device.
1007  */
1008 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1009 {
1010         u8 __iomem *p;
1011         unsigned long deviceID;
1012         unsigned int  number_uarts = 0;
1013
1014         /* OxSemi Tornado devices are all 0xCxxx */
1015         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1016             (dev->device & 0xF000) != 0xC000)
1017                 return 0;
1018
1019         p = pci_iomap(dev, 0, 5);
1020         if (p == NULL)
1021                 return -ENOMEM;
1022
1023         deviceID = ioread32(p);
1024         /* Tornado device */
1025         if (deviceID == 0x07000200) {
1026                 number_uarts = ioread8(p + 4);
1027                 printk(KERN_DEBUG
1028                         "%d ports detected on Oxford PCI Express device\n",
1029                                                                 number_uarts);
1030         }
1031         pci_iounmap(dev, p);
1032         return number_uarts;
1033 }
1034
1035 static int pci_asix_setup(struct serial_private *priv,
1036                   const struct pciserial_board *board,
1037                   struct uart_8250_port *port, int idx)
1038 {
1039         port->bugs |= UART_BUG_PARITY;
1040         return pci_default_setup(priv, board, port, idx);
1041 }
1042
1043 static int pci_default_setup(struct serial_private *priv,
1044                   const struct pciserial_board *board,
1045                   struct uart_8250_port *port, int idx)
1046 {
1047         unsigned int bar, offset = board->first_offset, maxnr;
1048
1049         bar = FL_GET_BASE(board->flags);
1050         if (board->flags & FL_BASE_BARS)
1051                 bar += idx;
1052         else
1053                 offset += idx * board->uart_offset;
1054
1055         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1056                 (board->reg_shift + 3);
1057
1058         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1059                 return 1;
1060
1061         return setup_port(priv, port, bar, offset, board->reg_shift);
1062 }
1063
1064 static int
1065 ce4100_serial_setup(struct serial_private *priv,
1066                   const struct pciserial_board *board,
1067                   struct uart_8250_port *port, int idx)
1068 {
1069         int ret;
1070
1071         ret = setup_port(priv, port, idx, 0, board->reg_shift);
1072         port->port.iotype = UPIO_MEM32;
1073         port->port.type = PORT_XSCALE;
1074         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1075         port->port.regshift = 2;
1076
1077         return ret;
1078 }
1079
1080 static int
1081 pci_omegapci_setup(struct serial_private *priv,
1082                       const struct pciserial_board *board,
1083                       struct uart_8250_port *port, int idx)
1084 {
1085         return setup_port(priv, port, 2, idx * 8, 0);
1086 }
1087
1088 static int skip_tx_en_setup(struct serial_private *priv,
1089                         const struct pciserial_board *board,
1090                         struct uart_8250_port *port, int idx)
1091 {
1092         port->port.flags |= UPF_NO_TXEN_TEST;
1093         printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1094                           "[%04x:%04x] subsystem [%04x:%04x]\n",
1095                           priv->dev->vendor,
1096                           priv->dev->device,
1097                           priv->dev->subsystem_vendor,
1098                           priv->dev->subsystem_device);
1099
1100         return pci_default_setup(priv, board, port, idx);
1101 }
1102
1103 static void kt_handle_break(struct uart_port *p)
1104 {
1105         struct uart_8250_port *up =
1106                 container_of(p, struct uart_8250_port, port);
1107         /*
1108          * On receipt of a BI, serial device in Intel ME (Intel
1109          * management engine) needs to have its fifos cleared for sane
1110          * SOL (Serial Over Lan) output.
1111          */
1112         serial8250_clear_and_reinit_fifos(up);
1113 }
1114
1115 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1116 {
1117         struct uart_8250_port *up =
1118                 container_of(p, struct uart_8250_port, port);
1119         unsigned int val;
1120
1121         /*
1122          * When the Intel ME (management engine) gets reset its serial
1123          * port registers could return 0 momentarily.  Functions like
1124          * serial8250_console_write, read and save the IER, perform
1125          * some operation and then restore it.  In order to avoid
1126          * setting IER register inadvertently to 0, if the value read
1127          * is 0, double check with ier value in uart_8250_port and use
1128          * that instead.  up->ier should be the same value as what is
1129          * currently configured.
1130          */
1131         val = inb(p->iobase + offset);
1132         if (offset == UART_IER) {
1133                 if (val == 0)
1134                         val = up->ier;
1135         }
1136         return val;
1137 }
1138
1139 static int kt_serial_setup(struct serial_private *priv,
1140                            const struct pciserial_board *board,
1141                            struct uart_8250_port *port, int idx)
1142 {
1143         port->port.flags |= UPF_BUG_THRE;
1144         port->port.serial_in = kt_serial_in;
1145         port->port.handle_break = kt_handle_break;
1146         return skip_tx_en_setup(priv, board, port, idx);
1147 }
1148
1149 static int pci_eg20t_init(struct pci_dev *dev)
1150 {
1151 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1152         return -ENODEV;
1153 #else
1154         return 0;
1155 #endif
1156 }
1157
1158 static int
1159 pci_xr17c154_setup(struct serial_private *priv,
1160                   const struct pciserial_board *board,
1161                   struct uart_8250_port *port, int idx)
1162 {
1163         port->port.flags |= UPF_EXAR_EFR;
1164         return pci_default_setup(priv, board, port, idx);
1165 }
1166
1167 static int
1168 pci_xr17v35x_setup(struct serial_private *priv,
1169                   const struct pciserial_board *board,
1170                   struct uart_8250_port *port, int idx)
1171 {
1172         u8 __iomem *p;
1173
1174         p = pci_ioremap_bar(priv->dev, 0);
1175         if (p == NULL)
1176                 return -ENOMEM;
1177
1178         port->port.flags |= UPF_EXAR_EFR;
1179
1180         /*
1181          * Setup Multipurpose Input/Output pins.
1182          */
1183         if (idx == 0) {
1184                 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1185                 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1186                 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1187                 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1188                 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1189                 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1190                 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1191                 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1192                 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1193                 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1194                 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1195                 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1196         }
1197         writeb(0x00, p + UART_EXAR_8XMODE);
1198         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1199         writeb(128, p + UART_EXAR_TXTRG);
1200         writeb(128, p + UART_EXAR_RXTRG);
1201         iounmap(p);
1202
1203         return pci_default_setup(priv, board, port, idx);
1204 }
1205
1206 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1207 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1208 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1209 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1210
1211 static int
1212 pci_fastcom335_setup(struct serial_private *priv,
1213                   const struct pciserial_board *board,
1214                   struct uart_8250_port *port, int idx)
1215 {
1216         u8 __iomem *p;
1217
1218         p = pci_ioremap_bar(priv->dev, 0);
1219         if (p == NULL)
1220                 return -ENOMEM;
1221
1222         port->port.flags |= UPF_EXAR_EFR;
1223
1224         /*
1225          * Setup Multipurpose Input/Output pins.
1226          */
1227         if (idx == 0) {
1228                 switch (priv->dev->device) {
1229                 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1230                 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1231                         writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1232                         writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1233                         writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1234                         break;
1235                 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1236                 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1237                         writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1238                         writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1239                         writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1240                         break;
1241                 }
1242                 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1243                 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1244                 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1245         }
1246         writeb(0x00, p + UART_EXAR_8XMODE);
1247         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1248         writeb(32, p + UART_EXAR_TXTRG);
1249         writeb(32, p + UART_EXAR_RXTRG);
1250         iounmap(p);
1251
1252         return pci_default_setup(priv, board, port, idx);
1253 }
1254
1255 static int
1256 pci_wch_ch353_setup(struct serial_private *priv,
1257                     const struct pciserial_board *board,
1258                     struct uart_8250_port *port, int idx)
1259 {
1260         port->port.flags |= UPF_FIXED_TYPE;
1261         port->port.type = PORT_16550A;
1262         return pci_default_setup(priv, board, port, idx);
1263 }
1264
1265 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1266 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1267 #define PCI_DEVICE_ID_OCTPRO            0x0001
1268 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1269 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1270 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1271 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1272 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
1273 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
1274 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1275 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1276 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1277 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1278 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1279 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1280 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1281 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1282 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1283 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1284 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1285 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1286 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1287 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1288 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1289 #define PCI_DEVICE_ID_TITAN_400V3       0xA310
1290 #define PCI_DEVICE_ID_TITAN_410V3       0xA312
1291 #define PCI_DEVICE_ID_TITAN_800V3       0xA314
1292 #define PCI_DEVICE_ID_TITAN_800V3B      0xA315
1293 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1294 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1295 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1296 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1297 #define PCI_VENDOR_ID_WCH               0x4348
1298 #define PCI_DEVICE_ID_WCH_CH353_4S      0x3453
1299 #define PCI_DEVICE_ID_WCH_CH353_2S1PF   0x5046
1300 #define PCI_DEVICE_ID_WCH_CH353_2S1P    0x7053
1301 #define PCI_VENDOR_ID_AGESTAR           0x5372
1302 #define PCI_DEVICE_ID_AGESTAR_9375      0x6872
1303 #define PCI_VENDOR_ID_ASIX              0x9710
1304 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0019
1305 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1306 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1307
1308
1309 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1310 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1311
1312 /*
1313  * Master list of serial port init/setup/exit quirks.
1314  * This does not describe the general nature of the port.
1315  * (ie, baud base, number and location of ports, etc)
1316  *
1317  * This list is ordered alphabetically by vendor then device.
1318  * Specific entries must come before more generic entries.
1319  */
1320 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1321         /*
1322         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1323         */
1324         {
1325                 .vendor         = PCI_VENDOR_ID_ADDIDATA_OLD,
1326                 .device         = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1327                 .subvendor      = PCI_ANY_ID,
1328                 .subdevice      = PCI_ANY_ID,
1329                 .setup          = addidata_apci7800_setup,
1330         },
1331         /*
1332          * AFAVLAB cards - these may be called via parport_serial
1333          *  It is not clear whether this applies to all products.
1334          */
1335         {
1336                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1337                 .device         = PCI_ANY_ID,
1338                 .subvendor      = PCI_ANY_ID,
1339                 .subdevice      = PCI_ANY_ID,
1340                 .setup          = afavlab_setup,
1341         },
1342         /*
1343          * HP Diva
1344          */
1345         {
1346                 .vendor         = PCI_VENDOR_ID_HP,
1347                 .device         = PCI_DEVICE_ID_HP_DIVA,
1348                 .subvendor      = PCI_ANY_ID,
1349                 .subdevice      = PCI_ANY_ID,
1350                 .init           = pci_hp_diva_init,
1351                 .setup          = pci_hp_diva_setup,
1352         },
1353         /*
1354          * Intel
1355          */
1356         {
1357                 .vendor         = PCI_VENDOR_ID_INTEL,
1358                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1359                 .subvendor      = 0xe4bf,
1360                 .subdevice      = PCI_ANY_ID,
1361                 .init           = pci_inteli960ni_init,
1362                 .setup          = pci_default_setup,
1363         },
1364         {
1365                 .vendor         = PCI_VENDOR_ID_INTEL,
1366                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1367                 .subvendor      = PCI_ANY_ID,
1368                 .subdevice      = PCI_ANY_ID,
1369                 .setup          = skip_tx_en_setup,
1370         },
1371         {
1372                 .vendor         = PCI_VENDOR_ID_INTEL,
1373                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1374                 .subvendor      = PCI_ANY_ID,
1375                 .subdevice      = PCI_ANY_ID,
1376                 .setup          = skip_tx_en_setup,
1377         },
1378         {
1379                 .vendor         = PCI_VENDOR_ID_INTEL,
1380                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
1381                 .subvendor      = PCI_ANY_ID,
1382                 .subdevice      = PCI_ANY_ID,
1383                 .setup          = skip_tx_en_setup,
1384         },
1385         {
1386                 .vendor         = PCI_VENDOR_ID_INTEL,
1387                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
1388                 .subvendor      = PCI_ANY_ID,
1389                 .subdevice      = PCI_ANY_ID,
1390                 .setup          = ce4100_serial_setup,
1391         },
1392         {
1393                 .vendor         = PCI_VENDOR_ID_INTEL,
1394                 .device         = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1395                 .subvendor      = PCI_ANY_ID,
1396                 .subdevice      = PCI_ANY_ID,
1397                 .setup          = kt_serial_setup,
1398         },
1399         /*
1400          * ITE
1401          */
1402         {
1403                 .vendor         = PCI_VENDOR_ID_ITE,
1404                 .device         = PCI_DEVICE_ID_ITE_8872,
1405                 .subvendor      = PCI_ANY_ID,
1406                 .subdevice      = PCI_ANY_ID,
1407                 .init           = pci_ite887x_init,
1408                 .setup          = pci_default_setup,
1409                 .exit           = pci_ite887x_exit,
1410         },
1411         /*
1412          * National Instruments
1413          */
1414         {
1415                 .vendor         = PCI_VENDOR_ID_NI,
1416                 .device         = PCI_DEVICE_ID_NI_PCI23216,
1417                 .subvendor      = PCI_ANY_ID,
1418                 .subdevice      = PCI_ANY_ID,
1419                 .init           = pci_ni8420_init,
1420                 .setup          = pci_default_setup,
1421                 .exit           = pci_ni8420_exit,
1422         },
1423         {
1424                 .vendor         = PCI_VENDOR_ID_NI,
1425                 .device         = PCI_DEVICE_ID_NI_PCI2328,
1426                 .subvendor      = PCI_ANY_ID,
1427                 .subdevice      = PCI_ANY_ID,
1428                 .init           = pci_ni8420_init,
1429                 .setup          = pci_default_setup,
1430                 .exit           = pci_ni8420_exit,
1431         },
1432         {
1433                 .vendor         = PCI_VENDOR_ID_NI,
1434                 .device         = PCI_DEVICE_ID_NI_PCI2324,
1435                 .subvendor      = PCI_ANY_ID,
1436                 .subdevice      = PCI_ANY_ID,
1437                 .init           = pci_ni8420_init,
1438                 .setup          = pci_default_setup,
1439                 .exit           = pci_ni8420_exit,
1440         },
1441         {
1442                 .vendor         = PCI_VENDOR_ID_NI,
1443                 .device         = PCI_DEVICE_ID_NI_PCI2322,
1444                 .subvendor      = PCI_ANY_ID,
1445                 .subdevice      = PCI_ANY_ID,
1446                 .init           = pci_ni8420_init,
1447                 .setup          = pci_default_setup,
1448                 .exit           = pci_ni8420_exit,
1449         },
1450         {
1451                 .vendor         = PCI_VENDOR_ID_NI,
1452                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
1453                 .subvendor      = PCI_ANY_ID,
1454                 .subdevice      = PCI_ANY_ID,
1455                 .init           = pci_ni8420_init,
1456                 .setup          = pci_default_setup,
1457                 .exit           = pci_ni8420_exit,
1458         },
1459         {
1460                 .vendor         = PCI_VENDOR_ID_NI,
1461                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
1462                 .subvendor      = PCI_ANY_ID,
1463                 .subdevice      = PCI_ANY_ID,
1464                 .init           = pci_ni8420_init,
1465                 .setup          = pci_default_setup,
1466                 .exit           = pci_ni8420_exit,
1467         },
1468         {
1469                 .vendor         = PCI_VENDOR_ID_NI,
1470                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
1471                 .subvendor      = PCI_ANY_ID,
1472                 .subdevice      = PCI_ANY_ID,
1473                 .init           = pci_ni8420_init,
1474                 .setup          = pci_default_setup,
1475                 .exit           = pci_ni8420_exit,
1476         },
1477         {
1478                 .vendor         = PCI_VENDOR_ID_NI,
1479                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
1480                 .subvendor      = PCI_ANY_ID,
1481                 .subdevice      = PCI_ANY_ID,
1482                 .init           = pci_ni8420_init,
1483                 .setup          = pci_default_setup,
1484                 .exit           = pci_ni8420_exit,
1485         },
1486         {
1487                 .vendor         = PCI_VENDOR_ID_NI,
1488                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
1489                 .subvendor      = PCI_ANY_ID,
1490                 .subdevice      = PCI_ANY_ID,
1491                 .init           = pci_ni8420_init,
1492                 .setup          = pci_default_setup,
1493                 .exit           = pci_ni8420_exit,
1494         },
1495         {
1496                 .vendor         = PCI_VENDOR_ID_NI,
1497                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
1498                 .subvendor      = PCI_ANY_ID,
1499                 .subdevice      = PCI_ANY_ID,
1500                 .init           = pci_ni8420_init,
1501                 .setup          = pci_default_setup,
1502                 .exit           = pci_ni8420_exit,
1503         },
1504         {
1505                 .vendor         = PCI_VENDOR_ID_NI,
1506                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
1507                 .subvendor      = PCI_ANY_ID,
1508                 .subdevice      = PCI_ANY_ID,
1509                 .init           = pci_ni8420_init,
1510                 .setup          = pci_default_setup,
1511                 .exit           = pci_ni8420_exit,
1512         },
1513         {
1514                 .vendor         = PCI_VENDOR_ID_NI,
1515                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
1516                 .subvendor      = PCI_ANY_ID,
1517                 .subdevice      = PCI_ANY_ID,
1518                 .init           = pci_ni8420_init,
1519                 .setup          = pci_default_setup,
1520                 .exit           = pci_ni8420_exit,
1521         },
1522         {
1523                 .vendor         = PCI_VENDOR_ID_NI,
1524                 .device         = PCI_ANY_ID,
1525                 .subvendor      = PCI_ANY_ID,
1526                 .subdevice      = PCI_ANY_ID,
1527                 .init           = pci_ni8430_init,
1528                 .setup          = pci_ni8430_setup,
1529                 .exit           = pci_ni8430_exit,
1530         },
1531         /*
1532          * Panacom
1533          */
1534         {
1535                 .vendor         = PCI_VENDOR_ID_PANACOM,
1536                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1537                 .subvendor      = PCI_ANY_ID,
1538                 .subdevice      = PCI_ANY_ID,
1539                 .init           = pci_plx9050_init,
1540                 .setup          = pci_default_setup,
1541                 .exit           = pci_plx9050_exit,
1542         },
1543         {
1544                 .vendor         = PCI_VENDOR_ID_PANACOM,
1545                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1546                 .subvendor      = PCI_ANY_ID,
1547                 .subdevice      = PCI_ANY_ID,
1548                 .init           = pci_plx9050_init,
1549                 .setup          = pci_default_setup,
1550                 .exit           = pci_plx9050_exit,
1551         },
1552         /*
1553          * PLX
1554          */
1555         {
1556                 .vendor         = PCI_VENDOR_ID_PLX,
1557                 .device         = PCI_DEVICE_ID_PLX_9030,
1558                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
1559                 .subdevice      = PCI_ANY_ID,
1560                 .setup          = pci_default_setup,
1561         },
1562         {
1563                 .vendor         = PCI_VENDOR_ID_PLX,
1564                 .device         = PCI_DEVICE_ID_PLX_9050,
1565                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
1566                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
1567                 .init           = pci_plx9050_init,
1568                 .setup          = pci_default_setup,
1569                 .exit           = pci_plx9050_exit,
1570         },
1571         {
1572                 .vendor         = PCI_VENDOR_ID_PLX,
1573                 .device         = PCI_DEVICE_ID_PLX_9050,
1574                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
1575                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1576                 .init           = pci_plx9050_init,
1577                 .setup          = pci_default_setup,
1578                 .exit           = pci_plx9050_exit,
1579         },
1580         {
1581                 .vendor         = PCI_VENDOR_ID_PLX,
1582                 .device         = PCI_DEVICE_ID_PLX_9050,
1583                 .subvendor      = PCI_VENDOR_ID_PLX,
1584                 .subdevice      = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1585                 .init           = pci_plx9050_init,
1586                 .setup          = pci_default_setup,
1587                 .exit           = pci_plx9050_exit,
1588         },
1589         {
1590                 .vendor         = PCI_VENDOR_ID_PLX,
1591                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
1592                 .subvendor      = PCI_VENDOR_ID_PLX,
1593                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
1594                 .init           = pci_plx9050_init,
1595                 .setup          = pci_default_setup,
1596                 .exit           = pci_plx9050_exit,
1597         },
1598         /*
1599          * SBS Technologies, Inc., PMC-OCTALPRO 232
1600          */
1601         {
1602                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1603                 .device         = PCI_DEVICE_ID_OCTPRO,
1604                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1605                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
1606                 .init           = sbs_init,
1607                 .setup          = sbs_setup,
1608                 .exit           = sbs_exit,
1609         },
1610         /*
1611          * SBS Technologies, Inc., PMC-OCTALPRO 422
1612          */
1613         {
1614                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1615                 .device         = PCI_DEVICE_ID_OCTPRO,
1616                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1617                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
1618                 .init           = sbs_init,
1619                 .setup          = sbs_setup,
1620                 .exit           = sbs_exit,
1621         },
1622         /*
1623          * SBS Technologies, Inc., P-Octal 232
1624          */
1625         {
1626                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1627                 .device         = PCI_DEVICE_ID_OCTPRO,
1628                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1629                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
1630                 .init           = sbs_init,
1631                 .setup          = sbs_setup,
1632                 .exit           = sbs_exit,
1633         },
1634         /*
1635          * SBS Technologies, Inc., P-Octal 422
1636          */
1637         {
1638                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1639                 .device         = PCI_DEVICE_ID_OCTPRO,
1640                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1641                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
1642                 .init           = sbs_init,
1643                 .setup          = sbs_setup,
1644                 .exit           = sbs_exit,
1645         },
1646         /*
1647          * SIIG cards - these may be called via parport_serial
1648          */
1649         {
1650                 .vendor         = PCI_VENDOR_ID_SIIG,
1651                 .device         = PCI_ANY_ID,
1652                 .subvendor      = PCI_ANY_ID,
1653                 .subdevice      = PCI_ANY_ID,
1654                 .init           = pci_siig_init,
1655                 .setup          = pci_siig_setup,
1656         },
1657         /*
1658          * Titan cards
1659          */
1660         {
1661                 .vendor         = PCI_VENDOR_ID_TITAN,
1662                 .device         = PCI_DEVICE_ID_TITAN_400L,
1663                 .subvendor      = PCI_ANY_ID,
1664                 .subdevice      = PCI_ANY_ID,
1665                 .setup          = titan_400l_800l_setup,
1666         },
1667         {
1668                 .vendor         = PCI_VENDOR_ID_TITAN,
1669                 .device         = PCI_DEVICE_ID_TITAN_800L,
1670                 .subvendor      = PCI_ANY_ID,
1671                 .subdevice      = PCI_ANY_ID,
1672                 .setup          = titan_400l_800l_setup,
1673         },
1674         /*
1675          * Timedia cards
1676          */
1677         {
1678                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1679                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
1680                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
1681                 .subdevice      = PCI_ANY_ID,
1682                 .probe          = pci_timedia_probe,
1683                 .init           = pci_timedia_init,
1684                 .setup          = pci_timedia_setup,
1685         },
1686         {
1687                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1688                 .device         = PCI_ANY_ID,
1689                 .subvendor      = PCI_ANY_ID,
1690                 .subdevice      = PCI_ANY_ID,
1691                 .setup          = pci_timedia_setup,
1692         },
1693         /*
1694          * Exar cards
1695          */
1696         {
1697                 .vendor = PCI_VENDOR_ID_EXAR,
1698                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1699                 .subvendor      = PCI_ANY_ID,
1700                 .subdevice      = PCI_ANY_ID,
1701                 .setup          = pci_xr17c154_setup,
1702         },
1703         {
1704                 .vendor = PCI_VENDOR_ID_EXAR,
1705                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1706                 .subvendor      = PCI_ANY_ID,
1707                 .subdevice      = PCI_ANY_ID,
1708                 .setup          = pci_xr17c154_setup,
1709         },
1710         {
1711                 .vendor = PCI_VENDOR_ID_EXAR,
1712                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1713                 .subvendor      = PCI_ANY_ID,
1714                 .subdevice      = PCI_ANY_ID,
1715                 .setup          = pci_xr17c154_setup,
1716         },
1717         {
1718                 .vendor = PCI_VENDOR_ID_EXAR,
1719                 .device = PCI_DEVICE_ID_EXAR_XR17V352,
1720                 .subvendor      = PCI_ANY_ID,
1721                 .subdevice      = PCI_ANY_ID,
1722                 .setup          = pci_xr17v35x_setup,
1723         },
1724         {
1725                 .vendor = PCI_VENDOR_ID_EXAR,
1726                 .device = PCI_DEVICE_ID_EXAR_XR17V354,
1727                 .subvendor      = PCI_ANY_ID,
1728                 .subdevice      = PCI_ANY_ID,
1729                 .setup          = pci_xr17v35x_setup,
1730         },
1731         {
1732                 .vendor = PCI_VENDOR_ID_EXAR,
1733                 .device = PCI_DEVICE_ID_EXAR_XR17V358,
1734                 .subvendor      = PCI_ANY_ID,
1735                 .subdevice      = PCI_ANY_ID,
1736                 .setup          = pci_xr17v35x_setup,
1737         },
1738         /*
1739          * Xircom cards
1740          */
1741         {
1742                 .vendor         = PCI_VENDOR_ID_XIRCOM,
1743                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1744                 .subvendor      = PCI_ANY_ID,
1745                 .subdevice      = PCI_ANY_ID,
1746                 .init           = pci_xircom_init,
1747                 .setup          = pci_default_setup,
1748         },
1749         /*
1750          * Netmos cards - these may be called via parport_serial
1751          */
1752         {
1753                 .vendor         = PCI_VENDOR_ID_NETMOS,
1754                 .device         = PCI_ANY_ID,
1755                 .subvendor      = PCI_ANY_ID,
1756                 .subdevice      = PCI_ANY_ID,
1757                 .init           = pci_netmos_init,
1758                 .setup          = pci_netmos_9900_setup,
1759         },
1760         /*
1761          * For Oxford Semiconductor Tornado based devices
1762          */
1763         {
1764                 .vendor         = PCI_VENDOR_ID_OXSEMI,
1765                 .device         = PCI_ANY_ID,
1766                 .subvendor      = PCI_ANY_ID,
1767                 .subdevice      = PCI_ANY_ID,
1768                 .init           = pci_oxsemi_tornado_init,
1769                 .setup          = pci_default_setup,
1770         },
1771         {
1772                 .vendor         = PCI_VENDOR_ID_MAINPINE,
1773                 .device         = PCI_ANY_ID,
1774                 .subvendor      = PCI_ANY_ID,
1775                 .subdevice      = PCI_ANY_ID,
1776                 .init           = pci_oxsemi_tornado_init,
1777                 .setup          = pci_default_setup,
1778         },
1779         {
1780                 .vendor         = PCI_VENDOR_ID_DIGI,
1781                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1782                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
1783                 .subdevice              = PCI_ANY_ID,
1784                 .init                   = pci_oxsemi_tornado_init,
1785                 .setup          = pci_default_setup,
1786         },
1787         {
1788                 .vendor         = PCI_VENDOR_ID_INTEL,
1789                 .device         = 0x8811,
1790                 .subvendor      = PCI_ANY_ID,
1791                 .subdevice      = PCI_ANY_ID,
1792                 .init           = pci_eg20t_init,
1793                 .setup          = pci_default_setup,
1794         },
1795         {
1796                 .vendor         = PCI_VENDOR_ID_INTEL,
1797                 .device         = 0x8812,
1798                 .subvendor      = PCI_ANY_ID,
1799                 .subdevice      = PCI_ANY_ID,
1800                 .init           = pci_eg20t_init,
1801                 .setup          = pci_default_setup,
1802         },
1803         {
1804                 .vendor         = PCI_VENDOR_ID_INTEL,
1805                 .device         = 0x8813,
1806                 .subvendor      = PCI_ANY_ID,
1807                 .subdevice      = PCI_ANY_ID,
1808                 .init           = pci_eg20t_init,
1809                 .setup          = pci_default_setup,
1810         },
1811         {
1812                 .vendor         = PCI_VENDOR_ID_INTEL,
1813                 .device         = 0x8814,
1814                 .subvendor      = PCI_ANY_ID,
1815                 .subdevice      = PCI_ANY_ID,
1816                 .init           = pci_eg20t_init,
1817                 .setup          = pci_default_setup,
1818         },
1819         {
1820                 .vendor         = 0x10DB,
1821                 .device         = 0x8027,
1822                 .subvendor      = PCI_ANY_ID,
1823                 .subdevice      = PCI_ANY_ID,
1824                 .init           = pci_eg20t_init,
1825                 .setup          = pci_default_setup,
1826         },
1827         {
1828                 .vendor         = 0x10DB,
1829                 .device         = 0x8028,
1830                 .subvendor      = PCI_ANY_ID,
1831                 .subdevice      = PCI_ANY_ID,
1832                 .init           = pci_eg20t_init,
1833                 .setup          = pci_default_setup,
1834         },
1835         {
1836                 .vendor         = 0x10DB,
1837                 .device         = 0x8029,
1838                 .subvendor      = PCI_ANY_ID,
1839                 .subdevice      = PCI_ANY_ID,
1840                 .init           = pci_eg20t_init,
1841                 .setup          = pci_default_setup,
1842         },
1843         {
1844                 .vendor         = 0x10DB,
1845                 .device         = 0x800C,
1846                 .subvendor      = PCI_ANY_ID,
1847                 .subdevice      = PCI_ANY_ID,
1848                 .init           = pci_eg20t_init,
1849                 .setup          = pci_default_setup,
1850         },
1851         {
1852                 .vendor         = 0x10DB,
1853                 .device         = 0x800D,
1854                 .subvendor      = PCI_ANY_ID,
1855                 .subdevice      = PCI_ANY_ID,
1856                 .init           = pci_eg20t_init,
1857                 .setup          = pci_default_setup,
1858         },
1859         /*
1860          * Cronyx Omega PCI (PLX-chip based)
1861          */
1862         {
1863                 .vendor         = PCI_VENDOR_ID_PLX,
1864                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1865                 .subvendor      = PCI_ANY_ID,
1866                 .subdevice      = PCI_ANY_ID,
1867                 .setup          = pci_omegapci_setup,
1868         },
1869         /* WCH CH353 2S1P card (16550 clone) */
1870         {
1871                 .vendor         = PCI_VENDOR_ID_WCH,
1872                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1P,
1873                 .subvendor      = PCI_ANY_ID,
1874                 .subdevice      = PCI_ANY_ID,
1875                 .setup          = pci_wch_ch353_setup,
1876         },
1877         /* WCH CH353 4S card (16550 clone) */
1878         {
1879                 .vendor         = PCI_VENDOR_ID_WCH,
1880                 .device         = PCI_DEVICE_ID_WCH_CH353_4S,
1881                 .subvendor      = PCI_ANY_ID,
1882                 .subdevice      = PCI_ANY_ID,
1883                 .setup          = pci_wch_ch353_setup,
1884         },
1885         /* WCH CH353 2S1PF card (16550 clone) */
1886         {
1887                 .vendor         = PCI_VENDOR_ID_WCH,
1888                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1PF,
1889                 .subvendor      = PCI_ANY_ID,
1890                 .subdevice      = PCI_ANY_ID,
1891                 .setup          = pci_wch_ch353_setup,
1892         },
1893         /*
1894          * ASIX devices with FIFO bug
1895          */
1896         {
1897                 .vendor         = PCI_VENDOR_ID_ASIX,
1898                 .device         = PCI_ANY_ID,
1899                 .subvendor      = PCI_ANY_ID,
1900                 .subdevice      = PCI_ANY_ID,
1901                 .setup          = pci_asix_setup,
1902         },
1903         /*
1904          * Commtech, Inc. Fastcom adapters
1905          *
1906          */
1907         {
1908                 .vendor = PCI_VENDOR_ID_COMMTECH,
1909                 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
1910                 .subvendor      = PCI_ANY_ID,
1911                 .subdevice      = PCI_ANY_ID,
1912                 .setup          = pci_fastcom335_setup,
1913         },
1914         {
1915                 .vendor = PCI_VENDOR_ID_COMMTECH,
1916                 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
1917                 .subvendor      = PCI_ANY_ID,
1918                 .subdevice      = PCI_ANY_ID,
1919                 .setup          = pci_fastcom335_setup,
1920         },
1921         {
1922                 .vendor = PCI_VENDOR_ID_COMMTECH,
1923                 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
1924                 .subvendor      = PCI_ANY_ID,
1925                 .subdevice      = PCI_ANY_ID,
1926                 .setup          = pci_fastcom335_setup,
1927         },
1928         {
1929                 .vendor = PCI_VENDOR_ID_COMMTECH,
1930                 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
1931                 .subvendor      = PCI_ANY_ID,
1932                 .subdevice      = PCI_ANY_ID,
1933                 .setup          = pci_fastcom335_setup,
1934         },
1935         {
1936                 .vendor = PCI_VENDOR_ID_COMMTECH,
1937                 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
1938                 .subvendor      = PCI_ANY_ID,
1939                 .subdevice      = PCI_ANY_ID,
1940                 .setup          = pci_xr17v35x_setup,
1941         },
1942         {
1943                 .vendor = PCI_VENDOR_ID_COMMTECH,
1944                 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
1945                 .subvendor      = PCI_ANY_ID,
1946                 .subdevice      = PCI_ANY_ID,
1947                 .setup          = pci_xr17v35x_setup,
1948         },
1949         {
1950                 .vendor = PCI_VENDOR_ID_COMMTECH,
1951                 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
1952                 .subvendor      = PCI_ANY_ID,
1953                 .subdevice      = PCI_ANY_ID,
1954                 .setup          = pci_xr17v35x_setup,
1955         },
1956         /*
1957          * Default "match everything" terminator entry
1958          */
1959         {
1960                 .vendor         = PCI_ANY_ID,
1961                 .device         = PCI_ANY_ID,
1962                 .subvendor      = PCI_ANY_ID,
1963                 .subdevice      = PCI_ANY_ID,
1964                 .setup          = pci_default_setup,
1965         }
1966 };
1967
1968 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1969 {
1970         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1971 }
1972
1973 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1974 {
1975         struct pci_serial_quirk *quirk;
1976
1977         for (quirk = pci_serial_quirks; ; quirk++)
1978                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1979                     quirk_id_matches(quirk->device, dev->device) &&
1980                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1981                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1982                         break;
1983         return quirk;
1984 }
1985
1986 static inline int get_pci_irq(struct pci_dev *dev,
1987                                 const struct pciserial_board *board)
1988 {
1989         if (board->flags & FL_NOIRQ)
1990                 return 0;
1991         else
1992                 return dev->irq;
1993 }
1994
1995 /*
1996  * This is the configuration table for all of the PCI serial boards
1997  * which we support.  It is directly indexed by the pci_board_num_t enum
1998  * value, which is encoded in the pci_device_id PCI probe table's
1999  * driver_data member.
2000  *
2001  * The makeup of these names are:
2002  *  pbn_bn{_bt}_n_baud{_offsetinhex}
2003  *
2004  *  bn          = PCI BAR number
2005  *  bt          = Index using PCI BARs
2006  *  n           = number of serial ports
2007  *  baud        = baud rate
2008  *  offsetinhex = offset for each sequential port (in hex)
2009  *
2010  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2011  *
2012  * Please note: in theory if n = 1, _bt infix should make no difference.
2013  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2014  */
2015 enum pci_board_num_t {
2016         pbn_default = 0,
2017
2018         pbn_b0_1_115200,
2019         pbn_b0_2_115200,
2020         pbn_b0_4_115200,
2021         pbn_b0_5_115200,
2022         pbn_b0_8_115200,
2023
2024         pbn_b0_1_921600,
2025         pbn_b0_2_921600,
2026         pbn_b0_4_921600,
2027
2028         pbn_b0_2_1130000,
2029
2030         pbn_b0_4_1152000,
2031
2032         pbn_b0_2_1152000_200,
2033         pbn_b0_4_1152000_200,
2034         pbn_b0_8_1152000_200,
2035
2036         pbn_b0_2_1843200,
2037         pbn_b0_4_1843200,
2038
2039         pbn_b0_2_1843200_200,
2040         pbn_b0_4_1843200_200,
2041         pbn_b0_8_1843200_200,
2042
2043         pbn_b0_1_4000000,
2044
2045         pbn_b0_bt_1_115200,
2046         pbn_b0_bt_2_115200,
2047         pbn_b0_bt_4_115200,
2048         pbn_b0_bt_8_115200,
2049
2050         pbn_b0_bt_1_460800,
2051         pbn_b0_bt_2_460800,
2052         pbn_b0_bt_4_460800,
2053
2054         pbn_b0_bt_1_921600,
2055         pbn_b0_bt_2_921600,
2056         pbn_b0_bt_4_921600,
2057         pbn_b0_bt_8_921600,
2058
2059         pbn_b1_1_115200,
2060         pbn_b1_2_115200,
2061         pbn_b1_4_115200,
2062         pbn_b1_8_115200,
2063         pbn_b1_16_115200,
2064
2065         pbn_b1_1_921600,
2066         pbn_b1_2_921600,
2067         pbn_b1_4_921600,
2068         pbn_b1_8_921600,
2069
2070         pbn_b1_2_1250000,
2071
2072         pbn_b1_bt_1_115200,
2073         pbn_b1_bt_2_115200,
2074         pbn_b1_bt_4_115200,
2075
2076         pbn_b1_bt_2_921600,
2077
2078         pbn_b1_1_1382400,
2079         pbn_b1_2_1382400,
2080         pbn_b1_4_1382400,
2081         pbn_b1_8_1382400,
2082
2083         pbn_b2_1_115200,
2084         pbn_b2_2_115200,
2085         pbn_b2_4_115200,
2086         pbn_b2_8_115200,
2087
2088         pbn_b2_1_460800,
2089         pbn_b2_4_460800,
2090         pbn_b2_8_460800,
2091         pbn_b2_16_460800,
2092
2093         pbn_b2_1_921600,
2094         pbn_b2_4_921600,
2095         pbn_b2_8_921600,
2096
2097         pbn_b2_8_1152000,
2098
2099         pbn_b2_bt_1_115200,
2100         pbn_b2_bt_2_115200,
2101         pbn_b2_bt_4_115200,
2102
2103         pbn_b2_bt_2_921600,
2104         pbn_b2_bt_4_921600,
2105
2106         pbn_b3_2_115200,
2107         pbn_b3_4_115200,
2108         pbn_b3_8_115200,
2109
2110         pbn_b4_bt_2_921600,
2111         pbn_b4_bt_4_921600,
2112         pbn_b4_bt_8_921600,
2113
2114         /*
2115          * Board-specific versions.
2116          */
2117         pbn_panacom,
2118         pbn_panacom2,
2119         pbn_panacom4,
2120         pbn_plx_romulus,
2121         pbn_oxsemi,
2122         pbn_oxsemi_1_4000000,
2123         pbn_oxsemi_2_4000000,
2124         pbn_oxsemi_4_4000000,
2125         pbn_oxsemi_8_4000000,
2126         pbn_intel_i960,
2127         pbn_sgi_ioc3,
2128         pbn_computone_4,
2129         pbn_computone_6,
2130         pbn_computone_8,
2131         pbn_sbsxrsio,
2132         pbn_exar_XR17C152,
2133         pbn_exar_XR17C154,
2134         pbn_exar_XR17C158,
2135         pbn_exar_XR17V352,
2136         pbn_exar_XR17V354,
2137         pbn_exar_XR17V358,
2138         pbn_exar_ibm_saturn,
2139         pbn_pasemi_1682M,
2140         pbn_ni8430_2,
2141         pbn_ni8430_4,
2142         pbn_ni8430_8,
2143         pbn_ni8430_16,
2144         pbn_ADDIDATA_PCIe_1_3906250,
2145         pbn_ADDIDATA_PCIe_2_3906250,
2146         pbn_ADDIDATA_PCIe_4_3906250,
2147         pbn_ADDIDATA_PCIe_8_3906250,
2148         pbn_ce4100_1_115200,
2149         pbn_omegapci,
2150         pbn_NETMOS9900_2s_115200,
2151 };
2152
2153 /*
2154  * uart_offset - the space between channels
2155  * reg_shift   - describes how the UART registers are mapped
2156  *               to PCI memory by the card.
2157  * For example IER register on SBS, Inc. PMC-OctPro is located at
2158  * offset 0x10 from the UART base, while UART_IER is defined as 1
2159  * in include/linux/serial_reg.h,
2160  * see first lines of serial_in() and serial_out() in 8250.c
2161 */
2162
2163 static struct pciserial_board pci_boards[] = {
2164         [pbn_default] = {
2165                 .flags          = FL_BASE0,
2166                 .num_ports      = 1,
2167                 .base_baud      = 115200,
2168                 .uart_offset    = 8,
2169         },
2170         [pbn_b0_1_115200] = {
2171                 .flags          = FL_BASE0,
2172                 .num_ports      = 1,
2173                 .base_baud      = 115200,
2174                 .uart_offset    = 8,
2175         },
2176         [pbn_b0_2_115200] = {
2177                 .flags          = FL_BASE0,
2178                 .num_ports      = 2,
2179                 .base_baud      = 115200,
2180                 .uart_offset    = 8,
2181         },
2182         [pbn_b0_4_115200] = {
2183                 .flags          = FL_BASE0,
2184                 .num_ports      = 4,
2185                 .base_baud      = 115200,
2186                 .uart_offset    = 8,
2187         },
2188         [pbn_b0_5_115200] = {
2189                 .flags          = FL_BASE0,
2190                 .num_ports      = 5,
2191                 .base_baud      = 115200,
2192                 .uart_offset    = 8,
2193         },
2194         [pbn_b0_8_115200] = {
2195                 .flags          = FL_BASE0,
2196                 .num_ports      = 8,
2197                 .base_baud      = 115200,
2198                 .uart_offset    = 8,
2199         },
2200         [pbn_b0_1_921600] = {
2201                 .flags          = FL_BASE0,
2202                 .num_ports      = 1,
2203                 .base_baud      = 921600,
2204                 .uart_offset    = 8,
2205         },
2206         [pbn_b0_2_921600] = {
2207                 .flags          = FL_BASE0,
2208                 .num_ports      = 2,
2209                 .base_baud      = 921600,
2210                 .uart_offset    = 8,
2211         },
2212         [pbn_b0_4_921600] = {
2213                 .flags          = FL_BASE0,
2214                 .num_ports      = 4,
2215                 .base_baud      = 921600,
2216                 .uart_offset    = 8,
2217         },
2218
2219         [pbn_b0_2_1130000] = {
2220                 .flags          = FL_BASE0,
2221                 .num_ports      = 2,
2222                 .base_baud      = 1130000,
2223                 .uart_offset    = 8,
2224         },
2225
2226         [pbn_b0_4_1152000] = {
2227                 .flags          = FL_BASE0,
2228                 .num_ports      = 4,
2229                 .base_baud      = 1152000,
2230                 .uart_offset    = 8,
2231         },
2232
2233         [pbn_b0_2_1152000_200] = {
2234                 .flags          = FL_BASE0,
2235                 .num_ports      = 2,
2236                 .base_baud      = 1152000,
2237                 .uart_offset    = 0x200,
2238         },
2239
2240         [pbn_b0_4_1152000_200] = {
2241                 .flags          = FL_BASE0,
2242                 .num_ports      = 4,
2243                 .base_baud      = 1152000,
2244                 .uart_offset    = 0x200,
2245         },
2246
2247         [pbn_b0_8_1152000_200] = {
2248                 .flags          = FL_BASE0,
2249                 .num_ports      = 2,
2250                 .base_baud      = 1152000,
2251                 .uart_offset    = 0x200,
2252         },
2253
2254         [pbn_b0_2_1843200] = {
2255                 .flags          = FL_BASE0,
2256                 .num_ports      = 2,
2257                 .base_baud      = 1843200,
2258                 .uart_offset    = 8,
2259         },
2260         [pbn_b0_4_1843200] = {
2261                 .flags          = FL_BASE0,
2262                 .num_ports      = 4,
2263                 .base_baud      = 1843200,
2264                 .uart_offset    = 8,
2265         },
2266
2267         [pbn_b0_2_1843200_200] = {
2268                 .flags          = FL_BASE0,
2269                 .num_ports      = 2,
2270                 .base_baud      = 1843200,
2271                 .uart_offset    = 0x200,
2272         },
2273         [pbn_b0_4_1843200_200] = {
2274                 .flags          = FL_BASE0,
2275                 .num_ports      = 4,
2276                 .base_baud      = 1843200,
2277                 .uart_offset    = 0x200,
2278         },
2279         [pbn_b0_8_1843200_200] = {
2280                 .flags          = FL_BASE0,
2281                 .num_ports      = 8,
2282                 .base_baud      = 1843200,
2283                 .uart_offset    = 0x200,
2284         },
2285         [pbn_b0_1_4000000] = {
2286                 .flags          = FL_BASE0,
2287                 .num_ports      = 1,
2288                 .base_baud      = 4000000,
2289                 .uart_offset    = 8,
2290         },
2291
2292         [pbn_b0_bt_1_115200] = {
2293                 .flags          = FL_BASE0|FL_BASE_BARS,
2294                 .num_ports      = 1,
2295                 .base_baud      = 115200,
2296                 .uart_offset    = 8,
2297         },
2298         [pbn_b0_bt_2_115200] = {
2299                 .flags          = FL_BASE0|FL_BASE_BARS,
2300                 .num_ports      = 2,
2301                 .base_baud      = 115200,
2302                 .uart_offset    = 8,
2303         },
2304         [pbn_b0_bt_4_115200] = {
2305                 .flags          = FL_BASE0|FL_BASE_BARS,
2306                 .num_ports      = 4,
2307                 .base_baud      = 115200,
2308                 .uart_offset    = 8,
2309         },
2310         [pbn_b0_bt_8_115200] = {
2311                 .flags          = FL_BASE0|FL_BASE_BARS,
2312                 .num_ports      = 8,
2313                 .base_baud      = 115200,
2314                 .uart_offset    = 8,
2315         },
2316
2317         [pbn_b0_bt_1_460800] = {
2318                 .flags          = FL_BASE0|FL_BASE_BARS,
2319                 .num_ports      = 1,
2320                 .base_baud      = 460800,
2321                 .uart_offset    = 8,
2322         },
2323         [pbn_b0_bt_2_460800] = {
2324                 .flags          = FL_BASE0|FL_BASE_BARS,
2325                 .num_ports      = 2,
2326                 .base_baud      = 460800,
2327                 .uart_offset    = 8,
2328         },
2329         [pbn_b0_bt_4_460800] = {
2330                 .flags          = FL_BASE0|FL_BASE_BARS,
2331                 .num_ports      = 4,
2332                 .base_baud      = 460800,
2333                 .uart_offset    = 8,
2334         },
2335
2336         [pbn_b0_bt_1_921600] = {
2337                 .flags          = FL_BASE0|FL_BASE_BARS,
2338                 .num_ports      = 1,
2339                 .base_baud      = 921600,
2340                 .uart_offset    = 8,
2341         },
2342         [pbn_b0_bt_2_921600] = {
2343                 .flags          = FL_BASE0|FL_BASE_BARS,
2344                 .num_ports      = 2,
2345                 .base_baud      = 921600,
2346                 .uart_offset    = 8,
2347         },
2348         [pbn_b0_bt_4_921600] = {
2349                 .flags          = FL_BASE0|FL_BASE_BARS,
2350                 .num_ports      = 4,
2351                 .base_baud      = 921600,
2352                 .uart_offset    = 8,
2353         },
2354         [pbn_b0_bt_8_921600] = {
2355                 .flags          = FL_BASE0|FL_BASE_BARS,
2356                 .num_ports      = 8,
2357                 .base_baud      = 921600,
2358                 .uart_offset    = 8,
2359         },
2360
2361         [pbn_b1_1_115200] = {
2362                 .flags          = FL_BASE1,
2363                 .num_ports      = 1,
2364                 .base_baud      = 115200,
2365                 .uart_offset    = 8,
2366         },
2367         [pbn_b1_2_115200] = {
2368                 .flags          = FL_BASE1,
2369                 .num_ports      = 2,
2370                 .base_baud      = 115200,
2371                 .uart_offset    = 8,
2372         },
2373         [pbn_b1_4_115200] = {
2374                 .flags          = FL_BASE1,
2375                 .num_ports      = 4,
2376                 .base_baud      = 115200,
2377                 .uart_offset    = 8,
2378         },
2379         [pbn_b1_8_115200] = {
2380                 .flags          = FL_BASE1,
2381                 .num_ports      = 8,
2382                 .base_baud      = 115200,
2383                 .uart_offset    = 8,
2384         },
2385         [pbn_b1_16_115200] = {
2386                 .flags          = FL_BASE1,
2387                 .num_ports      = 16,
2388                 .base_baud      = 115200,
2389                 .uart_offset    = 8,
2390         },
2391
2392         [pbn_b1_1_921600] = {
2393                 .flags          = FL_BASE1,
2394                 .num_ports      = 1,
2395                 .base_baud      = 921600,
2396                 .uart_offset    = 8,
2397         },
2398         [pbn_b1_2_921600] = {
2399                 .flags          = FL_BASE1,
2400                 .num_ports      = 2,
2401                 .base_baud      = 921600,
2402                 .uart_offset    = 8,
2403         },
2404         [pbn_b1_4_921600] = {
2405                 .flags          = FL_BASE1,
2406                 .num_ports      = 4,
2407                 .base_baud      = 921600,
2408                 .uart_offset    = 8,
2409         },
2410         [pbn_b1_8_921600] = {
2411                 .flags          = FL_BASE1,
2412                 .num_ports      = 8,
2413                 .base_baud      = 921600,
2414                 .uart_offset    = 8,
2415         },
2416         [pbn_b1_2_1250000] = {
2417                 .flags          = FL_BASE1,
2418                 .num_ports      = 2,
2419                 .base_baud      = 1250000,
2420                 .uart_offset    = 8,
2421         },
2422
2423         [pbn_b1_bt_1_115200] = {
2424                 .flags          = FL_BASE1|FL_BASE_BARS,
2425                 .num_ports      = 1,
2426                 .base_baud      = 115200,
2427                 .uart_offset    = 8,
2428         },
2429         [pbn_b1_bt_2_115200] = {
2430                 .flags          = FL_BASE1|FL_BASE_BARS,
2431                 .num_ports      = 2,
2432                 .base_baud      = 115200,
2433                 .uart_offset    = 8,
2434         },
2435         [pbn_b1_bt_4_115200] = {
2436                 .flags          = FL_BASE1|FL_BASE_BARS,
2437                 .num_ports      = 4,
2438                 .base_baud      = 115200,
2439                 .uart_offset    = 8,
2440         },
2441
2442         [pbn_b1_bt_2_921600] = {
2443                 .flags          = FL_BASE1|FL_BASE_BARS,
2444                 .num_ports      = 2,
2445                 .base_baud      = 921600,
2446                 .uart_offset    = 8,
2447         },
2448
2449         [pbn_b1_1_1382400] = {
2450                 .flags          = FL_BASE1,
2451                 .num_ports      = 1,
2452                 .base_baud      = 1382400,
2453                 .uart_offset    = 8,
2454         },
2455         [pbn_b1_2_1382400] = {
2456                 .flags          = FL_BASE1,
2457                 .num_ports      = 2,
2458                 .base_baud      = 1382400,
2459                 .uart_offset    = 8,
2460         },
2461         [pbn_b1_4_1382400] = {
2462                 .flags          = FL_BASE1,
2463                 .num_ports      = 4,
2464                 .base_baud      = 1382400,
2465                 .uart_offset    = 8,
2466         },
2467         [pbn_b1_8_1382400] = {
2468                 .flags          = FL_BASE1,
2469                 .num_ports      = 8,
2470                 .base_baud      = 1382400,
2471                 .uart_offset    = 8,
2472         },
2473
2474         [pbn_b2_1_115200] = {
2475                 .flags          = FL_BASE2,
2476                 .num_ports      = 1,
2477                 .base_baud      = 115200,
2478                 .uart_offset    = 8,
2479         },
2480         [pbn_b2_2_115200] = {
2481                 .flags          = FL_BASE2,
2482                 .num_ports      = 2,
2483                 .base_baud      = 115200,
2484                 .uart_offset    = 8,
2485         },
2486         [pbn_b2_4_115200] = {
2487                 .flags          = FL_BASE2,
2488                 .num_ports      = 4,
2489                 .base_baud      = 115200,
2490                 .uart_offset    = 8,
2491         },
2492         [pbn_b2_8_115200] = {
2493                 .flags          = FL_BASE2,
2494                 .num_ports      = 8,
2495                 .base_baud      = 115200,
2496                 .uart_offset    = 8,
2497         },
2498
2499         [pbn_b2_1_460800] = {
2500                 .flags          = FL_BASE2,
2501                 .num_ports      = 1,
2502                 .base_baud      = 460800,
2503                 .uart_offset    = 8,
2504         },
2505         [pbn_b2_4_460800] = {
2506                 .flags          = FL_BASE2,
2507                 .num_ports      = 4,
2508                 .base_baud      = 460800,
2509                 .uart_offset    = 8,
2510         },
2511         [pbn_b2_8_460800] = {
2512                 .flags          = FL_BASE2,
2513                 .num_ports      = 8,
2514                 .base_baud      = 460800,
2515                 .uart_offset    = 8,
2516         },
2517         [pbn_b2_16_460800] = {
2518                 .flags          = FL_BASE2,
2519                 .num_ports      = 16,
2520                 .base_baud      = 460800,
2521                 .uart_offset    = 8,
2522          },
2523
2524         [pbn_b2_1_921600] = {
2525                 .flags          = FL_BASE2,
2526                 .num_ports      = 1,
2527                 .base_baud      = 921600,
2528                 .uart_offset    = 8,
2529         },
2530         [pbn_b2_4_921600] = {
2531                 .flags          = FL_BASE2,
2532                 .num_ports      = 4,
2533                 .base_baud      = 921600,
2534                 .uart_offset    = 8,
2535         },
2536         [pbn_b2_8_921600] = {
2537                 .flags          = FL_BASE2,
2538                 .num_ports      = 8,
2539                 .base_baud      = 921600,
2540                 .uart_offset    = 8,
2541         },
2542
2543         [pbn_b2_8_1152000] = {
2544                 .flags          = FL_BASE2,
2545                 .num_ports      = 8,
2546                 .base_baud      = 1152000,
2547                 .uart_offset    = 8,
2548         },
2549
2550         [pbn_b2_bt_1_115200] = {
2551                 .flags          = FL_BASE2|FL_BASE_BARS,
2552                 .num_ports      = 1,
2553                 .base_baud      = 115200,
2554                 .uart_offset    = 8,
2555         },
2556         [pbn_b2_bt_2_115200] = {
2557                 .flags          = FL_BASE2|FL_BASE_BARS,
2558                 .num_ports      = 2,
2559                 .base_baud      = 115200,
2560                 .uart_offset    = 8,
2561         },
2562         [pbn_b2_bt_4_115200] = {
2563                 .flags          = FL_BASE2|FL_BASE_BARS,
2564                 .num_ports      = 4,
2565                 .base_baud      = 115200,
2566                 .uart_offset    = 8,
2567         },
2568
2569         [pbn_b2_bt_2_921600] = {
2570                 .flags          = FL_BASE2|FL_BASE_BARS,
2571                 .num_ports      = 2,
2572                 .base_baud      = 921600,
2573                 .uart_offset    = 8,
2574         },
2575         [pbn_b2_bt_4_921600] = {
2576                 .flags          = FL_BASE2|FL_BASE_BARS,
2577                 .num_ports      = 4,
2578                 .base_baud      = 921600,
2579                 .uart_offset    = 8,
2580         },
2581
2582         [pbn_b3_2_115200] = {
2583                 .flags          = FL_BASE3,
2584                 .num_ports      = 2,
2585                 .base_baud      = 115200,
2586                 .uart_offset    = 8,
2587         },
2588         [pbn_b3_4_115200] = {
2589                 .flags          = FL_BASE3,
2590                 .num_ports      = 4,
2591                 .base_baud      = 115200,
2592                 .uart_offset    = 8,
2593         },
2594         [pbn_b3_8_115200] = {
2595                 .flags          = FL_BASE3,
2596                 .num_ports      = 8,
2597                 .base_baud      = 115200,
2598                 .uart_offset    = 8,
2599         },
2600
2601         [pbn_b4_bt_2_921600] = {
2602                 .flags          = FL_BASE4,
2603                 .num_ports      = 2,
2604                 .base_baud      = 921600,
2605                 .uart_offset    = 8,
2606         },
2607         [pbn_b4_bt_4_921600] = {
2608                 .flags          = FL_BASE4,
2609                 .num_ports      = 4,
2610                 .base_baud      = 921600,
2611                 .uart_offset    = 8,
2612         },
2613         [pbn_b4_bt_8_921600] = {
2614                 .flags          = FL_BASE4,
2615                 .num_ports      = 8,
2616                 .base_baud      = 921600,
2617                 .uart_offset    = 8,
2618         },
2619
2620         /*
2621          * Entries following this are board-specific.
2622          */
2623
2624         /*
2625          * Panacom - IOMEM
2626          */
2627         [pbn_panacom] = {
2628                 .flags          = FL_BASE2,
2629                 .num_ports      = 2,
2630                 .base_baud      = 921600,
2631                 .uart_offset    = 0x400,
2632                 .reg_shift      = 7,
2633         },
2634         [pbn_panacom2] = {
2635                 .flags          = FL_BASE2|FL_BASE_BARS,
2636                 .num_ports      = 2,
2637                 .base_baud      = 921600,
2638                 .uart_offset    = 0x400,
2639                 .reg_shift      = 7,
2640         },
2641         [pbn_panacom4] = {
2642                 .flags          = FL_BASE2|FL_BASE_BARS,
2643                 .num_ports      = 4,
2644                 .base_baud      = 921600,
2645                 .uart_offset    = 0x400,
2646                 .reg_shift      = 7,
2647         },
2648
2649         /* I think this entry is broken - the first_offset looks wrong --rmk */
2650         [pbn_plx_romulus] = {
2651                 .flags          = FL_BASE2,
2652                 .num_ports      = 4,
2653                 .base_baud      = 921600,
2654                 .uart_offset    = 8 << 2,
2655                 .reg_shift      = 2,
2656                 .first_offset   = 0x03,
2657         },
2658
2659         /*
2660          * This board uses the size of PCI Base region 0 to
2661          * signal now many ports are available
2662          */
2663         [pbn_oxsemi] = {
2664                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
2665                 .num_ports      = 32,
2666                 .base_baud      = 115200,
2667                 .uart_offset    = 8,
2668         },
2669         [pbn_oxsemi_1_4000000] = {
2670                 .flags          = FL_BASE0,
2671                 .num_ports      = 1,
2672                 .base_baud      = 4000000,
2673                 .uart_offset    = 0x200,
2674                 .first_offset   = 0x1000,
2675         },
2676         [pbn_oxsemi_2_4000000] = {
2677                 .flags          = FL_BASE0,
2678                 .num_ports      = 2,
2679                 .base_baud      = 4000000,
2680                 .uart_offset    = 0x200,
2681                 .first_offset   = 0x1000,
2682         },
2683         [pbn_oxsemi_4_4000000] = {
2684                 .flags          = FL_BASE0,
2685                 .num_ports      = 4,
2686                 .base_baud      = 4000000,
2687                 .uart_offset    = 0x200,
2688                 .first_offset   = 0x1000,
2689         },
2690         [pbn_oxsemi_8_4000000] = {
2691                 .flags          = FL_BASE0,
2692                 .num_ports      = 8,
2693                 .base_baud      = 4000000,
2694                 .uart_offset    = 0x200,
2695                 .first_offset   = 0x1000,
2696         },
2697
2698
2699         /*
2700          * EKF addition for i960 Boards form EKF with serial port.
2701          * Max 256 ports.
2702          */
2703         [pbn_intel_i960] = {
2704                 .flags          = FL_BASE0,
2705                 .num_ports      = 32,
2706                 .base_baud      = 921600,
2707                 .uart_offset    = 8 << 2,
2708                 .reg_shift      = 2,
2709                 .first_offset   = 0x10000,
2710         },
2711         [pbn_sgi_ioc3] = {
2712                 .flags          = FL_BASE0|FL_NOIRQ,
2713                 .num_ports      = 1,
2714                 .base_baud      = 458333,
2715                 .uart_offset    = 8,
2716                 .reg_shift      = 0,
2717                 .first_offset   = 0x20178,
2718         },
2719
2720         /*
2721          * Computone - uses IOMEM.
2722          */
2723         [pbn_computone_4] = {
2724                 .flags          = FL_BASE0,
2725                 .num_ports      = 4,
2726                 .base_baud      = 921600,
2727                 .uart_offset    = 0x40,
2728                 .reg_shift      = 2,
2729                 .first_offset   = 0x200,
2730         },
2731         [pbn_computone_6] = {
2732                 .flags          = FL_BASE0,
2733                 .num_ports      = 6,
2734                 .base_baud      = 921600,
2735                 .uart_offset    = 0x40,
2736                 .reg_shift      = 2,
2737                 .first_offset   = 0x200,
2738         },
2739         [pbn_computone_8] = {
2740                 .flags          = FL_BASE0,
2741                 .num_ports      = 8,
2742                 .base_baud      = 921600,
2743                 .uart_offset    = 0x40,
2744                 .reg_shift      = 2,
2745                 .first_offset   = 0x200,
2746         },
2747         [pbn_sbsxrsio] = {
2748                 .flags          = FL_BASE0,
2749                 .num_ports      = 8,
2750                 .base_baud      = 460800,
2751                 .uart_offset    = 256,
2752                 .reg_shift      = 4,
2753         },
2754         /*
2755          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2756          *  Only basic 16550A support.
2757          *  XR17C15[24] are not tested, but they should work.
2758          */
2759         [pbn_exar_XR17C152] = {
2760                 .flags          = FL_BASE0,
2761                 .num_ports      = 2,
2762                 .base_baud      = 921600,
2763                 .uart_offset    = 0x200,
2764         },
2765         [pbn_exar_XR17C154] = {
2766                 .flags          = FL_BASE0,
2767                 .num_ports      = 4,
2768                 .base_baud      = 921600,
2769                 .uart_offset    = 0x200,
2770         },
2771         [pbn_exar_XR17C158] = {
2772                 .flags          = FL_BASE0,
2773                 .num_ports      = 8,
2774                 .base_baud      = 921600,
2775                 .uart_offset    = 0x200,
2776         },
2777         [pbn_exar_XR17V352] = {
2778                 .flags          = FL_BASE0,
2779                 .num_ports      = 2,
2780                 .base_baud      = 7812500,
2781                 .uart_offset    = 0x400,
2782                 .reg_shift      = 0,
2783                 .first_offset   = 0,
2784         },
2785         [pbn_exar_XR17V354] = {
2786                 .flags          = FL_BASE0,
2787                 .num_ports      = 4,
2788                 .base_baud      = 7812500,
2789                 .uart_offset    = 0x400,
2790                 .reg_shift      = 0,
2791                 .first_offset   = 0,
2792         },
2793         [pbn_exar_XR17V358] = {
2794                 .flags          = FL_BASE0,
2795                 .num_ports      = 8,
2796                 .base_baud      = 7812500,
2797                 .uart_offset    = 0x400,
2798                 .reg_shift      = 0,
2799                 .first_offset   = 0,
2800         },
2801         [pbn_exar_ibm_saturn] = {
2802                 .flags          = FL_BASE0,
2803                 .num_ports      = 1,
2804                 .base_baud      = 921600,
2805                 .uart_offset    = 0x200,
2806         },
2807
2808         /*
2809          * PA Semi PWRficient PA6T-1682M on-chip UART
2810          */
2811         [pbn_pasemi_1682M] = {
2812                 .flags          = FL_BASE0,
2813                 .num_ports      = 1,
2814                 .base_baud      = 8333333,
2815         },
2816         /*
2817          * National Instruments 843x
2818          */
2819         [pbn_ni8430_16] = {
2820                 .flags          = FL_BASE0,
2821                 .num_ports      = 16,
2822                 .base_baud      = 3686400,
2823                 .uart_offset    = 0x10,
2824                 .first_offset   = 0x800,
2825         },
2826         [pbn_ni8430_8] = {
2827                 .flags          = FL_BASE0,
2828                 .num_ports      = 8,
2829                 .base_baud      = 3686400,
2830                 .uart_offset    = 0x10,
2831                 .first_offset   = 0x800,
2832         },
2833         [pbn_ni8430_4] = {
2834                 .flags          = FL_BASE0,
2835                 .num_ports      = 4,
2836                 .base_baud      = 3686400,
2837                 .uart_offset    = 0x10,
2838                 .first_offset   = 0x800,
2839         },
2840         [pbn_ni8430_2] = {
2841                 .flags          = FL_BASE0,
2842                 .num_ports      = 2,
2843                 .base_baud      = 3686400,
2844                 .uart_offset    = 0x10,
2845                 .first_offset   = 0x800,
2846         },
2847         /*
2848          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2849          */
2850         [pbn_ADDIDATA_PCIe_1_3906250] = {
2851                 .flags          = FL_BASE0,
2852                 .num_ports      = 1,
2853                 .base_baud      = 3906250,
2854                 .uart_offset    = 0x200,
2855                 .first_offset   = 0x1000,
2856         },
2857         [pbn_ADDIDATA_PCIe_2_3906250] = {
2858                 .flags          = FL_BASE0,
2859                 .num_ports      = 2,
2860                 .base_baud      = 3906250,
2861                 .uart_offset    = 0x200,
2862                 .first_offset   = 0x1000,
2863         },
2864         [pbn_ADDIDATA_PCIe_4_3906250] = {
2865                 .flags          = FL_BASE0,
2866                 .num_ports      = 4,
2867                 .base_baud      = 3906250,
2868                 .uart_offset    = 0x200,
2869                 .first_offset   = 0x1000,
2870         },
2871         [pbn_ADDIDATA_PCIe_8_3906250] = {
2872                 .flags          = FL_BASE0,
2873                 .num_ports      = 8,
2874                 .base_baud      = 3906250,
2875                 .uart_offset    = 0x200,
2876                 .first_offset   = 0x1000,
2877         },
2878         [pbn_ce4100_1_115200] = {
2879                 .flags          = FL_BASE_BARS,
2880                 .num_ports      = 2,
2881                 .base_baud      = 921600,
2882                 .reg_shift      = 2,
2883         },
2884         [pbn_omegapci] = {
2885                 .flags          = FL_BASE0,
2886                 .num_ports      = 8,
2887                 .base_baud      = 115200,
2888                 .uart_offset    = 0x200,
2889         },
2890         [pbn_NETMOS9900_2s_115200] = {
2891                 .flags          = FL_BASE0,
2892                 .num_ports      = 2,
2893                 .base_baud      = 115200,
2894         },
2895 };
2896
2897 static const struct pci_device_id blacklist[] = {
2898         /* softmodems */
2899         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2900         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2901         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2902
2903         /* multi-io cards handled by parport_serial */
2904         { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
2905 };
2906
2907 /*
2908  * Given a complete unknown PCI device, try to use some heuristics to
2909  * guess what the configuration might be, based on the pitiful PCI
2910  * serial specs.  Returns 0 on success, 1 on failure.
2911  */
2912 static int
2913 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2914 {
2915         const struct pci_device_id *bldev;
2916         int num_iomem, num_port, first_port = -1, i;
2917
2918         /*
2919          * If it is not a communications device or the programming
2920          * interface is greater than 6, give up.
2921          *
2922          * (Should we try to make guesses for multiport serial devices
2923          * later?)
2924          */
2925         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2926              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2927             (dev->class & 0xff) > 6)
2928                 return -ENODEV;
2929
2930         /*
2931          * Do not access blacklisted devices that are known not to
2932          * feature serial ports or are handled by other modules.
2933          */
2934         for (bldev = blacklist;
2935              bldev < blacklist + ARRAY_SIZE(blacklist);
2936              bldev++) {
2937                 if (dev->vendor == bldev->vendor &&
2938                     dev->device == bldev->device)
2939                         return -ENODEV;
2940         }
2941
2942         num_iomem = num_port = 0;
2943         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2944                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2945                         num_port++;
2946                         if (first_port == -1)
2947                                 first_port = i;
2948                 }
2949                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2950                         num_iomem++;
2951         }
2952
2953         /*
2954          * If there is 1 or 0 iomem regions, and exactly one port,
2955          * use it.  We guess the number of ports based on the IO
2956          * region size.
2957          */
2958         if (num_iomem <= 1 && num_port == 1) {
2959                 board->flags = first_port;
2960                 board->num_ports = pci_resource_len(dev, first_port) / 8;
2961                 return 0;
2962         }
2963
2964         /*
2965          * Now guess if we've got a board which indexes by BARs.
2966          * Each IO BAR should be 8 bytes, and they should follow
2967          * consecutively.
2968          */
2969         first_port = -1;
2970         num_port = 0;
2971         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2972                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2973                     pci_resource_len(dev, i) == 8 &&
2974                     (first_port == -1 || (first_port + num_port) == i)) {
2975                         num_port++;
2976                         if (first_port == -1)
2977                                 first_port = i;
2978                 }
2979         }
2980
2981         if (num_port > 1) {
2982                 board->flags = first_port | FL_BASE_BARS;
2983                 board->num_ports = num_port;
2984                 return 0;
2985         }
2986
2987         return -ENODEV;
2988 }
2989
2990 static inline int
2991 serial_pci_matches(const struct pciserial_board *board,
2992                    const struct pciserial_board *guessed)
2993 {
2994         return
2995             board->num_ports == guessed->num_ports &&
2996             board->base_baud == guessed->base_baud &&
2997             board->uart_offset == guessed->uart_offset &&
2998             board->reg_shift == guessed->reg_shift &&
2999             board->first_offset == guessed->first_offset;
3000 }
3001
3002 struct serial_private *
3003 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3004 {
3005         struct uart_8250_port uart;
3006         struct serial_private *priv;
3007         struct pci_serial_quirk *quirk;
3008         int rc, nr_ports, i;
3009
3010         nr_ports = board->num_ports;
3011
3012         /*
3013          * Find an init and setup quirks.
3014          */
3015         quirk = find_quirk(dev);
3016
3017         /*
3018          * Run the new-style initialization function.
3019          * The initialization function returns:
3020          *  <0  - error
3021          *   0  - use board->num_ports
3022          *  >0  - number of ports
3023          */
3024         if (quirk->init) {
3025                 rc = quirk->init(dev);
3026                 if (rc < 0) {
3027                         priv = ERR_PTR(rc);
3028                         goto err_out;
3029                 }
3030                 if (rc)
3031                         nr_ports = rc;
3032         }
3033
3034         priv = kzalloc(sizeof(struct serial_private) +
3035                        sizeof(unsigned int) * nr_ports,
3036                        GFP_KERNEL);
3037         if (!priv) {
3038                 priv = ERR_PTR(-ENOMEM);
3039                 goto err_deinit;
3040         }
3041
3042         priv->dev = dev;
3043         priv->quirk = quirk;
3044
3045         memset(&uart, 0, sizeof(uart));
3046         uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3047         uart.port.uartclk = board->base_baud * 16;
3048         uart.port.irq = get_pci_irq(dev, board);
3049         uart.port.dev = &dev->dev;
3050
3051         for (i = 0; i < nr_ports; i++) {
3052                 if (quirk->setup(priv, board, &uart, i))
3053                         break;
3054
3055 #ifdef SERIAL_DEBUG_PCI
3056                 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
3057                        uart.port.iobase, uart.port.irq, uart.port.iotype);
3058 #endif
3059
3060                 priv->line[i] = serial8250_register_8250_port(&uart);
3061                 if (priv->line[i] < 0) {
3062                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
3063                         break;
3064                 }
3065         }
3066         priv->nr = i;
3067         return priv;
3068
3069 err_deinit:
3070         if (quirk->exit)
3071                 quirk->exit(dev);
3072 err_out:
3073         return priv;
3074 }
3075 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3076
3077 void pciserial_remove_ports(struct serial_private *priv)
3078 {
3079         struct pci_serial_quirk *quirk;
3080         int i;
3081
3082         for (i = 0; i < priv->nr; i++)
3083                 serial8250_unregister_port(priv->line[i]);
3084
3085         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3086                 if (priv->remapped_bar[i])
3087                         iounmap(priv->remapped_bar[i]);
3088                 priv->remapped_bar[i] = NULL;
3089         }
3090
3091         /*
3092          * Find the exit quirks.
3093          */
3094         quirk = find_quirk(priv->dev);
3095         if (quirk->exit)
3096                 quirk->exit(priv->dev);
3097
3098         kfree(priv);
3099 }
3100 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3101
3102 void pciserial_suspend_ports(struct serial_private *priv)
3103 {
3104         int i;
3105
3106         for (i = 0; i < priv->nr; i++)
3107                 if (priv->line[i] >= 0)
3108                         serial8250_suspend_port(priv->line[i]);
3109
3110         /*
3111          * Ensure that every init quirk is properly torn down
3112          */
3113         if (priv->quirk->exit)
3114                 priv->quirk->exit(priv->dev);
3115 }
3116 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3117
3118 void pciserial_resume_ports(struct serial_private *priv)
3119 {
3120         int i;
3121
3122         /*
3123          * Ensure that the board is correctly configured.
3124          */
3125         if (priv->quirk->init)
3126                 priv->quirk->init(priv->dev);
3127
3128         for (i = 0; i < priv->nr; i++)
3129                 if (priv->line[i] >= 0)
3130                         serial8250_resume_port(priv->line[i]);
3131 }
3132 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3133
3134 /*
3135  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
3136  * to the arrangement of serial ports on a PCI card.
3137  */
3138 static int
3139 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3140 {
3141         struct pci_serial_quirk *quirk;
3142         struct serial_private *priv;
3143         const struct pciserial_board *board;
3144         struct pciserial_board tmp;
3145         int rc;
3146
3147         quirk = find_quirk(dev);
3148         if (quirk->probe) {
3149                 rc = quirk->probe(dev);
3150                 if (rc)
3151                         return rc;
3152         }
3153
3154         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3155                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
3156                         ent->driver_data);
3157                 return -EINVAL;
3158         }
3159
3160         board = &pci_boards[ent->driver_data];
3161
3162         rc = pci_enable_device(dev);
3163         pci_save_state(dev);
3164         if (rc)
3165                 return rc;
3166
3167         if (ent->driver_data == pbn_default) {
3168                 /*
3169                  * Use a copy of the pci_board entry for this;
3170                  * avoid changing entries in the table.
3171                  */
3172                 memcpy(&tmp, board, sizeof(struct pciserial_board));
3173                 board = &tmp;
3174
3175                 /*
3176                  * We matched one of our class entries.  Try to
3177                  * determine the parameters of this board.
3178                  */
3179                 rc = serial_pci_guess_board(dev, &tmp);
3180                 if (rc)
3181                         goto disable;
3182         } else {
3183                 /*
3184                  * We matched an explicit entry.  If we are able to
3185                  * detect this boards settings with our heuristic,
3186                  * then we no longer need this entry.
3187                  */
3188                 memcpy(&tmp, &pci_boards[pbn_default],
3189                        sizeof(struct pciserial_board));
3190                 rc = serial_pci_guess_board(dev, &tmp);
3191                 if (rc == 0 && serial_pci_matches(board, &tmp))
3192                         moan_device("Redundant entry in serial pci_table.",
3193                                     dev);
3194         }
3195
3196         priv = pciserial_init_ports(dev, board);
3197         if (!IS_ERR(priv)) {
3198                 pci_set_drvdata(dev, priv);
3199                 return 0;
3200         }
3201
3202         rc = PTR_ERR(priv);
3203
3204  disable:
3205         pci_disable_device(dev);
3206         return rc;
3207 }
3208
3209 static void pciserial_remove_one(struct pci_dev *dev)
3210 {
3211         struct serial_private *priv = pci_get_drvdata(dev);
3212
3213         pci_set_drvdata(dev, NULL);
3214
3215         pciserial_remove_ports(priv);
3216
3217         pci_disable_device(dev);
3218 }
3219
3220 #ifdef CONFIG_PM
3221 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3222 {
3223         struct serial_private *priv = pci_get_drvdata(dev);
3224
3225         if (priv)
3226                 pciserial_suspend_ports(priv);
3227
3228         pci_save_state(dev);
3229         pci_set_power_state(dev, pci_choose_state(dev, state));
3230         return 0;
3231 }
3232
3233 static int pciserial_resume_one(struct pci_dev *dev)
3234 {
3235         int err;
3236         struct serial_private *priv = pci_get_drvdata(dev);
3237
3238         pci_set_power_state(dev, PCI_D0);
3239         pci_restore_state(dev);
3240
3241         if (priv) {
3242                 /*
3243                  * The device may have been disabled.  Re-enable it.
3244                  */
3245                 err = pci_enable_device(dev);
3246                 /* FIXME: We cannot simply error out here */
3247                 if (err)
3248                         printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
3249                 pciserial_resume_ports(priv);
3250         }
3251         return 0;
3252 }
3253 #endif
3254
3255 static struct pci_device_id serial_pci_tbl[] = {
3256         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3257         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3258                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3259                 pbn_b2_8_921600 },
3260         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3261                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3262                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3263                 pbn_b1_8_1382400 },
3264         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3265                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3266                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3267                 pbn_b1_4_1382400 },
3268         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3269                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3270                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3271                 pbn_b1_2_1382400 },
3272         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3273                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3274                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3275                 pbn_b1_8_1382400 },
3276         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3277                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3278                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3279                 pbn_b1_4_1382400 },
3280         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3281                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3282                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3283                 pbn_b1_2_1382400 },
3284         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3285                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3286                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3287                 pbn_b1_8_921600 },
3288         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3289                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3290                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3291                 pbn_b1_8_921600 },
3292         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3293                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3294                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3295                 pbn_b1_4_921600 },
3296         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3297                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3298                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3299                 pbn_b1_4_921600 },
3300         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3301                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3302                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3303                 pbn_b1_2_921600 },
3304         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3305                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3306                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3307                 pbn_b1_8_921600 },
3308         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3309                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3310                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3311                 pbn_b1_8_921600 },
3312         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3313                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3314                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3315                 pbn_b1_4_921600 },
3316         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3317                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3318                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3319                 pbn_b1_2_1250000 },
3320         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3321                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3322                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3323                 pbn_b0_2_1843200 },
3324         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3325                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3326                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3327                 pbn_b0_4_1843200 },
3328         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3329                 PCI_VENDOR_ID_AFAVLAB,
3330                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3331                 pbn_b0_4_1152000 },
3332         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3333                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3334                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3335                 pbn_b0_2_1843200_200 },
3336         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3337                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3338                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3339                 pbn_b0_4_1843200_200 },
3340         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3341                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3342                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3343                 pbn_b0_8_1843200_200 },
3344         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3345                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3346                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3347                 pbn_b0_2_1843200_200 },
3348         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3349                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3350                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3351                 pbn_b0_4_1843200_200 },
3352         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3353                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3354                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3355                 pbn_b0_8_1843200_200 },
3356         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3357                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3358                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3359                 pbn_b0_2_1843200_200 },
3360         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3361                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3362                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3363                 pbn_b0_4_1843200_200 },
3364         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3365                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3366                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3367                 pbn_b0_8_1843200_200 },
3368         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3369                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3370                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3371                 pbn_b0_2_1843200_200 },
3372         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3373                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3374                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3375                 pbn_b0_4_1843200_200 },
3376         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3377                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3378                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3379                 pbn_b0_8_1843200_200 },
3380         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3381                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3382                 0, 0, pbn_exar_ibm_saturn },
3383
3384         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3385                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3386                 pbn_b2_bt_1_115200 },
3387         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3388                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3389                 pbn_b2_bt_2_115200 },
3390         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3391                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3392                 pbn_b2_bt_4_115200 },
3393         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3394                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3395                 pbn_b2_bt_2_115200 },
3396         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3397                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3398                 pbn_b2_bt_4_115200 },
3399         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3400                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3401                 pbn_b2_8_115200 },
3402         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3403                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3404                 pbn_b2_8_460800 },
3405         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3406                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3407                 pbn_b2_8_115200 },
3408
3409         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3410                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3411                 pbn_b2_bt_2_115200 },
3412         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3413                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3414                 pbn_b2_bt_2_921600 },
3415         /*
3416          * VScom SPCOM800, from sl@s.pl
3417          */
3418         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3419                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3420                 pbn_b2_8_921600 },
3421         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3422                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3423                 pbn_b2_4_921600 },
3424         /* Unknown card - subdevice 0x1584 */
3425         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3426                 PCI_VENDOR_ID_PLX,
3427                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3428                 pbn_b0_4_115200 },
3429         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3430                 PCI_SUBVENDOR_ID_KEYSPAN,
3431                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3432                 pbn_panacom },
3433         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3434                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3435                 pbn_panacom4 },
3436         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3437                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3438                 pbn_panacom2 },
3439         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3440                 PCI_VENDOR_ID_ESDGMBH,
3441                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3442                 pbn_b2_4_115200 },
3443         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3444                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3445                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3446                 pbn_b2_4_460800 },
3447         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3448                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3449                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3450                 pbn_b2_8_460800 },
3451         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3452                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3453                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3454                 pbn_b2_16_460800 },
3455         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3456                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3457                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3458                 pbn_b2_16_460800 },
3459         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3460                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3461                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3462                 pbn_b2_4_460800 },
3463         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3464                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3465                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3466                 pbn_b2_8_460800 },
3467         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3468                 PCI_SUBVENDOR_ID_EXSYS,
3469                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3470                 pbn_b2_4_115200 },
3471         /*
3472          * Megawolf Romulus PCI Serial Card, from Mike Hudson
3473          * (Exoray@isys.ca)
3474          */
3475         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3476                 0x10b5, 0x106a, 0, 0,
3477                 pbn_plx_romulus },
3478         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3479                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3480                 pbn_b1_4_115200 },
3481         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3482                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3483                 pbn_b1_2_115200 },
3484         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3485                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3486                 pbn_b1_8_115200 },
3487         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3488                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3489                 pbn_b1_8_115200 },
3490         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3491                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3492                 0, 0,
3493                 pbn_b0_4_921600 },
3494         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3495                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3496                 0, 0,
3497                 pbn_b0_4_1152000 },
3498         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
3499                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3500                 pbn_b0_bt_2_921600 },
3501
3502                 /*
3503                  * The below card is a little controversial since it is the
3504                  * subject of a PCI vendor/device ID clash.  (See
3505                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3506                  * For now just used the hex ID 0x950a.
3507                  */
3508         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3509                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
3510                 0, 0, pbn_b0_2_115200 },
3511         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3512                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
3513                 0, 0, pbn_b0_2_115200 },
3514         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3515                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3516                 pbn_b0_2_1130000 },
3517         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3518                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3519                 pbn_b0_1_921600 },
3520         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3521                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3522                 pbn_b0_4_115200 },
3523         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3524                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3525                 pbn_b0_bt_2_921600 },
3526         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3527                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3528                 pbn_b2_8_1152000 },
3529
3530         /*
3531          * Oxford Semiconductor Inc. Tornado PCI express device range.
3532          */
3533         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
3534                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3535                 pbn_b0_1_4000000 },
3536         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
3537                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3538                 pbn_b0_1_4000000 },
3539         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
3540                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3541                 pbn_oxsemi_1_4000000 },
3542         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
3543                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3544                 pbn_oxsemi_1_4000000 },
3545         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
3546                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3547                 pbn_b0_1_4000000 },
3548         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
3549                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3550                 pbn_b0_1_4000000 },
3551         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
3552                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3553                 pbn_oxsemi_1_4000000 },
3554         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
3555                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3556                 pbn_oxsemi_1_4000000 },
3557         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
3558                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3559                 pbn_b0_1_4000000 },
3560         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
3561                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3562                 pbn_b0_1_4000000 },
3563         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
3564                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3565                 pbn_b0_1_4000000 },
3566         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
3567                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3568                 pbn_b0_1_4000000 },
3569         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
3570                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3571                 pbn_oxsemi_2_4000000 },
3572         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
3573                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3574                 pbn_oxsemi_2_4000000 },
3575         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
3576                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3577                 pbn_oxsemi_4_4000000 },
3578         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
3579                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3580                 pbn_oxsemi_4_4000000 },
3581         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
3582                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3583                 pbn_oxsemi_8_4000000 },
3584         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
3585                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3586                 pbn_oxsemi_8_4000000 },
3587         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
3588                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3589                 pbn_oxsemi_1_4000000 },
3590         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
3591                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3592                 pbn_oxsemi_1_4000000 },
3593         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
3594                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3595                 pbn_oxsemi_1_4000000 },
3596         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
3597                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3598                 pbn_oxsemi_1_4000000 },
3599         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
3600                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3601                 pbn_oxsemi_1_4000000 },
3602         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
3603                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3604                 pbn_oxsemi_1_4000000 },
3605         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
3606                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3607                 pbn_oxsemi_1_4000000 },
3608         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
3609                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3610                 pbn_oxsemi_1_4000000 },
3611         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
3612                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3613                 pbn_oxsemi_1_4000000 },
3614         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
3615                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3616                 pbn_oxsemi_1_4000000 },
3617         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
3618                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3619                 pbn_oxsemi_1_4000000 },
3620         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
3621                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3622                 pbn_oxsemi_1_4000000 },
3623         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
3624                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3625                 pbn_oxsemi_1_4000000 },
3626         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
3627                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3628                 pbn_oxsemi_1_4000000 },
3629         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
3630                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3631                 pbn_oxsemi_1_4000000 },
3632         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
3633                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3634                 pbn_oxsemi_1_4000000 },
3635         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
3636                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3637                 pbn_oxsemi_1_4000000 },
3638         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
3639                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3640                 pbn_oxsemi_1_4000000 },
3641         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
3642                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3643                 pbn_oxsemi_1_4000000 },
3644         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
3645                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3646                 pbn_oxsemi_1_4000000 },
3647         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
3648                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3649                 pbn_oxsemi_1_4000000 },
3650         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
3651                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3652                 pbn_oxsemi_1_4000000 },
3653         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
3654                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3655                 pbn_oxsemi_1_4000000 },
3656         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
3657                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3658                 pbn_oxsemi_1_4000000 },
3659         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
3660                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3661                 pbn_oxsemi_1_4000000 },
3662         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
3663                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3664                 pbn_oxsemi_1_4000000 },
3665         /*
3666          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3667          */
3668         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3669                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3670                 pbn_oxsemi_1_4000000 },
3671         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3672                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3673                 pbn_oxsemi_2_4000000 },
3674         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3675                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3676                 pbn_oxsemi_4_4000000 },
3677         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3678                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3679                 pbn_oxsemi_8_4000000 },
3680
3681         /*
3682          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3683          */
3684         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3685                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3686                 pbn_oxsemi_2_4000000 },
3687
3688         /*
3689          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3690          * from skokodyn@yahoo.com
3691          */
3692         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3693                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3694                 pbn_sbsxrsio },
3695         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3696                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3697                 pbn_sbsxrsio },
3698         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3699                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3700                 pbn_sbsxrsio },
3701         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3702                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3703                 pbn_sbsxrsio },
3704
3705         /*
3706          * Digitan DS560-558, from jimd@esoft.com
3707          */
3708         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3709                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3710                 pbn_b1_1_115200 },
3711
3712         /*
3713          * Titan Electronic cards
3714          *  The 400L and 800L have a custom setup quirk.
3715          */
3716         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3717                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3718                 pbn_b0_1_921600 },
3719         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3720                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3721                 pbn_b0_2_921600 },
3722         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3723                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3724                 pbn_b0_4_921600 },
3725         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3726                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3727                 pbn_b0_4_921600 },
3728         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3729                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3730                 pbn_b1_1_921600 },
3731         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3732                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3733                 pbn_b1_bt_2_921600 },
3734         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3735                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3736                 pbn_b0_bt_4_921600 },
3737         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3738                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3739                 pbn_b0_bt_8_921600 },
3740         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3741                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3742                 pbn_b4_bt_2_921600 },
3743         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3744                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3745                 pbn_b4_bt_4_921600 },
3746         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3747                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3748                 pbn_b4_bt_8_921600 },
3749         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3750                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3751                 pbn_b0_4_921600 },
3752         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3753                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3754                 pbn_b0_4_921600 },
3755         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3756                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3757                 pbn_b0_4_921600 },
3758         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3759                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3760                 pbn_oxsemi_1_4000000 },
3761         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3762                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3763                 pbn_oxsemi_2_4000000 },
3764         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3765                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3766                 pbn_oxsemi_4_4000000 },
3767         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3768                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3769                 pbn_oxsemi_8_4000000 },
3770         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3771                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3772                 pbn_oxsemi_2_4000000 },
3773         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3774                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3775                 pbn_oxsemi_2_4000000 },
3776         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
3777                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3778                 pbn_b0_4_921600 },
3779         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
3780                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3781                 pbn_b0_4_921600 },
3782         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
3783                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3784                 pbn_b0_4_921600 },
3785         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
3786                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3787                 pbn_b0_4_921600 },
3788
3789         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3790                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3791                 pbn_b2_1_460800 },
3792         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3793                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3794                 pbn_b2_1_460800 },
3795         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3796                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3797                 pbn_b2_1_460800 },
3798         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3799                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3800                 pbn_b2_bt_2_921600 },
3801         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3802                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3803                 pbn_b2_bt_2_921600 },
3804         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3805                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3806                 pbn_b2_bt_2_921600 },
3807         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3808                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3809                 pbn_b2_bt_4_921600 },
3810         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3811                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3812                 pbn_b2_bt_4_921600 },
3813         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3814                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3815                 pbn_b2_bt_4_921600 },
3816         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3817                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3818                 pbn_b0_1_921600 },
3819         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3820                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3821                 pbn_b0_1_921600 },
3822         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3823                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3824                 pbn_b0_1_921600 },
3825         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3826                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3827                 pbn_b0_bt_2_921600 },
3828         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3829                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3830                 pbn_b0_bt_2_921600 },
3831         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3832                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3833                 pbn_b0_bt_2_921600 },
3834         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3835                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3836                 pbn_b0_bt_4_921600 },
3837         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3838                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3839                 pbn_b0_bt_4_921600 },
3840         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3841                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3842                 pbn_b0_bt_4_921600 },
3843         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3844                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3845                 pbn_b0_bt_8_921600 },
3846         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3847                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3848                 pbn_b0_bt_8_921600 },
3849         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3850                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3851                 pbn_b0_bt_8_921600 },
3852
3853         /*
3854          * Computone devices submitted by Doug McNash dmcnash@computone.com
3855          */
3856         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3857                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3858                 0, 0, pbn_computone_4 },
3859         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3860                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3861                 0, 0, pbn_computone_8 },
3862         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3863                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3864                 0, 0, pbn_computone_6 },
3865
3866         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3867                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3868                 pbn_oxsemi },
3869         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3870                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3871                 pbn_b0_bt_1_921600 },
3872
3873         /*
3874          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3875          */
3876         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3877                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3878                 pbn_b0_bt_8_115200 },
3879         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3880                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3881                 pbn_b0_bt_8_115200 },
3882
3883         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3884                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3885                 pbn_b0_bt_2_115200 },
3886         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3887                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3888                 pbn_b0_bt_2_115200 },
3889         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3890                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3891                 pbn_b0_bt_2_115200 },
3892         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3893                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3894                 pbn_b0_bt_2_115200 },
3895         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3896                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3897                 pbn_b0_bt_2_115200 },
3898         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3899                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3900                 pbn_b0_bt_4_460800 },
3901         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3902                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3903                 pbn_b0_bt_4_460800 },
3904         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3905                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3906                 pbn_b0_bt_2_460800 },
3907         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3908                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3909                 pbn_b0_bt_2_460800 },
3910         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3911                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3912                 pbn_b0_bt_2_460800 },
3913         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3914                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3915                 pbn_b0_bt_1_115200 },
3916         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3917                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3918                 pbn_b0_bt_1_460800 },
3919
3920         /*
3921          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3922          * Cards are identified by their subsystem vendor IDs, which
3923          * (in hex) match the model number.
3924          *
3925          * Note that JC140x are RS422/485 cards which require ox950
3926          * ACR = 0x10, and as such are not currently fully supported.
3927          */
3928         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3929                 0x1204, 0x0004, 0, 0,
3930                 pbn_b0_4_921600 },
3931         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3932                 0x1208, 0x0004, 0, 0,
3933                 pbn_b0_4_921600 },
3934 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3935                 0x1402, 0x0002, 0, 0,
3936                 pbn_b0_2_921600 }, */
3937 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3938                 0x1404, 0x0004, 0, 0,
3939                 pbn_b0_4_921600 }, */
3940         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3941                 0x1208, 0x0004, 0, 0,
3942                 pbn_b0_4_921600 },
3943
3944         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3945                 0x1204, 0x0004, 0, 0,
3946                 pbn_b0_4_921600 },
3947         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3948                 0x1208, 0x0004, 0, 0,
3949                 pbn_b0_4_921600 },
3950         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3951                 0x1208, 0x0004, 0, 0,
3952                 pbn_b0_4_921600 },
3953         /*
3954          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3955          */
3956         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3957                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3958                 pbn_b1_1_1382400 },
3959
3960         /*
3961          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3962          */
3963         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3964                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3965                 pbn_b1_1_1382400 },
3966
3967         /*
3968          * RAStel 2 port modem, gerg@moreton.com.au
3969          */
3970         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3971                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3972                 pbn_b2_bt_2_115200 },
3973
3974         /*
3975          * EKF addition for i960 Boards form EKF with serial port
3976          */
3977         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3978                 0xE4BF, PCI_ANY_ID, 0, 0,
3979                 pbn_intel_i960 },
3980
3981         /*
3982          * Xircom Cardbus/Ethernet combos
3983          */
3984         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3985                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3986                 pbn_b0_1_115200 },
3987         /*
3988          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3989          */
3990         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3991                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3992                 pbn_b0_1_115200 },
3993
3994         /*
3995          * Untested PCI modems, sent in from various folks...
3996          */
3997
3998         /*
3999          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4000          */
4001         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
4002                 0x1048, 0x1500, 0, 0,
4003                 pbn_b1_1_115200 },
4004
4005         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4006                 0xFF00, 0, 0, 0,
4007                 pbn_sgi_ioc3 },
4008
4009         /*
4010          * HP Diva card
4011          */
4012         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4013                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4014                 pbn_b1_1_115200 },
4015         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4016                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4017                 pbn_b0_5_115200 },
4018         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4019                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4020                 pbn_b2_1_115200 },
4021
4022         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4023                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4024                 pbn_b3_2_115200 },
4025         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4026                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4027                 pbn_b3_4_115200 },
4028         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4029                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4030                 pbn_b3_8_115200 },
4031
4032         /*
4033          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4034          */
4035         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4036                 PCI_ANY_ID, PCI_ANY_ID,
4037                 0,
4038                 0, pbn_exar_XR17C152 },
4039         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4040                 PCI_ANY_ID, PCI_ANY_ID,
4041                 0,
4042                 0, pbn_exar_XR17C154 },
4043         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4044                 PCI_ANY_ID, PCI_ANY_ID,
4045                 0,
4046                 0, pbn_exar_XR17C158 },
4047         /*
4048          * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
4049          */
4050         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4051                 PCI_ANY_ID, PCI_ANY_ID,
4052                 0,
4053                 0, pbn_exar_XR17V352 },
4054         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4055                 PCI_ANY_ID, PCI_ANY_ID,
4056                 0,
4057                 0, pbn_exar_XR17V354 },
4058         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4059                 PCI_ANY_ID, PCI_ANY_ID,
4060                 0,
4061                 0, pbn_exar_XR17V358 },
4062
4063         /*
4064          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4065          */
4066         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4067                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4068                 pbn_b0_1_115200 },
4069         /*
4070          * ITE
4071          */
4072         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4073                 PCI_ANY_ID, PCI_ANY_ID,
4074                 0, 0,
4075                 pbn_b1_bt_1_115200 },
4076
4077         /*
4078          * IntaShield IS-200
4079          */
4080         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4081                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
4082                 pbn_b2_2_115200 },
4083         /*
4084          * IntaShield IS-400
4085          */
4086         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4087                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
4088                 pbn_b2_4_115200 },
4089         /*
4090          * Perle PCI-RAS cards
4091          */
4092         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4093                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4094                 0, 0, pbn_b2_4_921600 },
4095         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4096                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4097                 0, 0, pbn_b2_8_921600 },
4098
4099         /*
4100          * Mainpine series cards: Fairly standard layout but fools
4101          * parts of the autodetect in some cases and uses otherwise
4102          * unmatched communications subclasses in the PCI Express case
4103          */
4104
4105         {       /* RockForceDUO */
4106                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4107                 PCI_VENDOR_ID_MAINPINE, 0x0200,
4108                 0, 0, pbn_b0_2_115200 },
4109         {       /* RockForceQUATRO */
4110                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4111                 PCI_VENDOR_ID_MAINPINE, 0x0300,
4112                 0, 0, pbn_b0_4_115200 },
4113         {       /* RockForceDUO+ */
4114                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4115                 PCI_VENDOR_ID_MAINPINE, 0x0400,
4116                 0, 0, pbn_b0_2_115200 },
4117         {       /* RockForceQUATRO+ */
4118                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4119                 PCI_VENDOR_ID_MAINPINE, 0x0500,
4120                 0, 0, pbn_b0_4_115200 },
4121         {       /* RockForce+ */
4122                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4123                 PCI_VENDOR_ID_MAINPINE, 0x0600,
4124                 0, 0, pbn_b0_2_115200 },
4125         {       /* RockForce+ */
4126                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4127                 PCI_VENDOR_ID_MAINPINE, 0x0700,
4128                 0, 0, pbn_b0_4_115200 },
4129         {       /* RockForceOCTO+ */
4130                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4131                 PCI_VENDOR_ID_MAINPINE, 0x0800,
4132                 0, 0, pbn_b0_8_115200 },
4133         {       /* RockForceDUO+ */
4134                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4135                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4136                 0, 0, pbn_b0_2_115200 },
4137         {       /* RockForceQUARTRO+ */
4138                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4139                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4140                 0, 0, pbn_b0_4_115200 },
4141         {       /* RockForceOCTO+ */
4142                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4143                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4144                 0, 0, pbn_b0_8_115200 },
4145         {       /* RockForceD1 */
4146                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4147                 PCI_VENDOR_ID_MAINPINE, 0x2000,
4148                 0, 0, pbn_b0_1_115200 },
4149         {       /* RockForceF1 */
4150                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4151                 PCI_VENDOR_ID_MAINPINE, 0x2100,
4152                 0, 0, pbn_b0_1_115200 },
4153         {       /* RockForceD2 */
4154                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4155                 PCI_VENDOR_ID_MAINPINE, 0x2200,
4156                 0, 0, pbn_b0_2_115200 },
4157         {       /* RockForceF2 */
4158                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4159                 PCI_VENDOR_ID_MAINPINE, 0x2300,
4160                 0, 0, pbn_b0_2_115200 },
4161         {       /* RockForceD4 */
4162                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4163                 PCI_VENDOR_ID_MAINPINE, 0x2400,
4164                 0, 0, pbn_b0_4_115200 },
4165         {       /* RockForceF4 */
4166                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4167                 PCI_VENDOR_ID_MAINPINE, 0x2500,
4168                 0, 0, pbn_b0_4_115200 },
4169         {       /* RockForceD8 */
4170                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4171                 PCI_VENDOR_ID_MAINPINE, 0x2600,
4172                 0, 0, pbn_b0_8_115200 },
4173         {       /* RockForceF8 */
4174                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4175                 PCI_VENDOR_ID_MAINPINE, 0x2700,
4176                 0, 0, pbn_b0_8_115200 },
4177         {       /* IQ Express D1 */
4178                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4179                 PCI_VENDOR_ID_MAINPINE, 0x3000,
4180                 0, 0, pbn_b0_1_115200 },
4181         {       /* IQ Express F1 */
4182                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4183                 PCI_VENDOR_ID_MAINPINE, 0x3100,
4184                 0, 0, pbn_b0_1_115200 },
4185         {       /* IQ Express D2 */
4186                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4187                 PCI_VENDOR_ID_MAINPINE, 0x3200,
4188                 0, 0, pbn_b0_2_115200 },
4189         {       /* IQ Express F2 */
4190                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4191                 PCI_VENDOR_ID_MAINPINE, 0x3300,
4192                 0, 0, pbn_b0_2_115200 },
4193         {       /* IQ Express D4 */
4194                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4195                 PCI_VENDOR_ID_MAINPINE, 0x3400,
4196                 0, 0, pbn_b0_4_115200 },
4197         {       /* IQ Express F4 */
4198                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4199                 PCI_VENDOR_ID_MAINPINE, 0x3500,
4200                 0, 0, pbn_b0_4_115200 },
4201         {       /* IQ Express D8 */
4202                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4203                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4204                 0, 0, pbn_b0_8_115200 },
4205         {       /* IQ Express F8 */
4206                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4207                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4208                 0, 0, pbn_b0_8_115200 },
4209
4210
4211         /*
4212          * PA Semi PA6T-1682M on-chip UART
4213          */
4214         {       PCI_VENDOR_ID_PASEMI, 0xa004,
4215                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4216                 pbn_pasemi_1682M },
4217
4218         /*
4219          * National Instruments
4220          */
4221         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4222                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4223                 pbn_b1_16_115200 },
4224         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4225                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4226                 pbn_b1_8_115200 },
4227         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4228                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4229                 pbn_b1_bt_4_115200 },
4230         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4231                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4232                 pbn_b1_bt_2_115200 },
4233         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4234                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4235                 pbn_b1_bt_4_115200 },
4236         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4237                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4238                 pbn_b1_bt_2_115200 },
4239         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4240                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4241                 pbn_b1_16_115200 },
4242         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4243                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4244                 pbn_b1_8_115200 },
4245         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4246                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4247                 pbn_b1_bt_4_115200 },
4248         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4249                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4250                 pbn_b1_bt_2_115200 },
4251         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4252                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4253                 pbn_b1_bt_4_115200 },
4254         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4255                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4256                 pbn_b1_bt_2_115200 },
4257         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4258                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4259                 pbn_ni8430_2 },
4260         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4261                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4262                 pbn_ni8430_2 },
4263         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4264                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4265                 pbn_ni8430_4 },
4266         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4267                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4268                 pbn_ni8430_4 },
4269         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4270                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4271                 pbn_ni8430_8 },
4272         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4273                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4274                 pbn_ni8430_8 },
4275         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4276                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4277                 pbn_ni8430_16 },
4278         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4279                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4280                 pbn_ni8430_16 },
4281         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4282                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4283                 pbn_ni8430_2 },
4284         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
4285                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4286                 pbn_ni8430_2 },
4287         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4288                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4289                 pbn_ni8430_4 },
4290         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4291                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4292                 pbn_ni8430_4 },
4293
4294         /*
4295         * ADDI-DATA GmbH communication cards <info@addi-data.com>
4296         */
4297         {       PCI_VENDOR_ID_ADDIDATA,
4298                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
4299                 PCI_ANY_ID,
4300                 PCI_ANY_ID,
4301                 0,
4302                 0,
4303                 pbn_b0_4_115200 },
4304
4305         {       PCI_VENDOR_ID_ADDIDATA,
4306                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4307                 PCI_ANY_ID,
4308                 PCI_ANY_ID,
4309                 0,
4310                 0,
4311                 pbn_b0_2_115200 },
4312
4313         {       PCI_VENDOR_ID_ADDIDATA,
4314                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4315                 PCI_ANY_ID,
4316                 PCI_ANY_ID,
4317                 0,
4318                 0,
4319                 pbn_b0_1_115200 },
4320
4321         {       PCI_VENDOR_ID_ADDIDATA_OLD,
4322                 PCI_DEVICE_ID_ADDIDATA_APCI7800,
4323                 PCI_ANY_ID,
4324                 PCI_ANY_ID,
4325                 0,
4326                 0,
4327                 pbn_b1_8_115200 },
4328
4329         {       PCI_VENDOR_ID_ADDIDATA,
4330                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4331                 PCI_ANY_ID,
4332                 PCI_ANY_ID,
4333                 0,
4334                 0,
4335                 pbn_b0_4_115200 },
4336
4337         {       PCI_VENDOR_ID_ADDIDATA,
4338                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4339                 PCI_ANY_ID,
4340                 PCI_ANY_ID,
4341                 0,
4342                 0,
4343                 pbn_b0_2_115200 },
4344
4345         {       PCI_VENDOR_ID_ADDIDATA,
4346                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4347                 PCI_ANY_ID,
4348                 PCI_ANY_ID,
4349                 0,
4350                 0,
4351                 pbn_b0_1_115200 },
4352
4353         {       PCI_VENDOR_ID_ADDIDATA,
4354                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4355                 PCI_ANY_ID,
4356                 PCI_ANY_ID,
4357                 0,
4358                 0,
4359                 pbn_b0_4_115200 },
4360
4361         {       PCI_VENDOR_ID_ADDIDATA,
4362                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4363                 PCI_ANY_ID,
4364                 PCI_ANY_ID,
4365                 0,
4366                 0,
4367                 pbn_b0_2_115200 },
4368
4369         {       PCI_VENDOR_ID_ADDIDATA,
4370                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4371                 PCI_ANY_ID,
4372                 PCI_ANY_ID,
4373                 0,
4374                 0,
4375                 pbn_b0_1_115200 },
4376
4377         {       PCI_VENDOR_ID_ADDIDATA,
4378                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4379                 PCI_ANY_ID,
4380                 PCI_ANY_ID,
4381                 0,
4382                 0,
4383                 pbn_b0_8_115200 },
4384
4385         {       PCI_VENDOR_ID_ADDIDATA,
4386                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4387                 PCI_ANY_ID,
4388                 PCI_ANY_ID,
4389                 0,
4390                 0,
4391                 pbn_ADDIDATA_PCIe_4_3906250 },
4392
4393         {       PCI_VENDOR_ID_ADDIDATA,
4394                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4395                 PCI_ANY_ID,
4396                 PCI_ANY_ID,
4397                 0,
4398                 0,
4399                 pbn_ADDIDATA_PCIe_2_3906250 },
4400
4401         {       PCI_VENDOR_ID_ADDIDATA,
4402                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4403                 PCI_ANY_ID,
4404                 PCI_ANY_ID,
4405                 0,
4406                 0,
4407                 pbn_ADDIDATA_PCIe_1_3906250 },
4408
4409         {       PCI_VENDOR_ID_ADDIDATA,
4410                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4411                 PCI_ANY_ID,
4412                 PCI_ANY_ID,
4413                 0,
4414                 0,
4415                 pbn_ADDIDATA_PCIe_8_3906250 },
4416
4417         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4418                 PCI_VENDOR_ID_IBM, 0x0299,
4419                 0, 0, pbn_b0_bt_2_115200 },
4420
4421         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4422                 0xA000, 0x1000,
4423                 0, 0, pbn_b0_1_115200 },
4424
4425         /* the 9901 is a rebranded 9912 */
4426         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4427                 0xA000, 0x1000,
4428                 0, 0, pbn_b0_1_115200 },
4429
4430         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4431                 0xA000, 0x1000,
4432                 0, 0, pbn_b0_1_115200 },
4433
4434         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4435                 0xA000, 0x1000,
4436                 0, 0, pbn_b0_1_115200 },
4437
4438         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4439                 0xA000, 0x1000,
4440                 0, 0, pbn_b0_1_115200 },
4441
4442         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4443                 0xA000, 0x3002,
4444                 0, 0, pbn_NETMOS9900_2s_115200 },
4445
4446         /*
4447          * Best Connectivity and Rosewill PCI Multi I/O cards
4448          */
4449
4450         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4451                 0xA000, 0x1000,
4452                 0, 0, pbn_b0_1_115200 },
4453
4454         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4455                 0xA000, 0x3002,
4456                 0, 0, pbn_b0_bt_2_115200 },
4457
4458         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4459                 0xA000, 0x3004,
4460                 0, 0, pbn_b0_bt_4_115200 },
4461         /* Intel CE4100 */
4462         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4463                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
4464                 pbn_ce4100_1_115200 },
4465
4466         /*
4467          * Cronyx Omega PCI
4468          */
4469         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4470                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4471                 pbn_omegapci },
4472
4473         /*
4474          * AgeStar as-prs2-009
4475          */
4476         {       PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
4477                 PCI_ANY_ID, PCI_ANY_ID,
4478                 0, 0, pbn_b0_bt_2_115200 },
4479
4480         /*
4481          * WCH CH353 series devices: The 2S1P is handled by parport_serial
4482          * so not listed here.
4483          */
4484         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
4485                 PCI_ANY_ID, PCI_ANY_ID,
4486                 0, 0, pbn_b0_bt_4_115200 },
4487
4488         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
4489                 PCI_ANY_ID, PCI_ANY_ID,
4490                 0, 0, pbn_b0_bt_2_115200 },
4491
4492         /*
4493          * Commtech, Inc. Fastcom adapters
4494          */
4495         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
4496                 PCI_ANY_ID, PCI_ANY_ID,
4497                 0,
4498                 0, pbn_b0_2_1152000_200 },
4499         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
4500                 PCI_ANY_ID, PCI_ANY_ID,
4501                 0,
4502                 0, pbn_b0_4_1152000_200 },
4503         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
4504                 PCI_ANY_ID, PCI_ANY_ID,
4505                 0,
4506                 0, pbn_b0_4_1152000_200 },
4507         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
4508                 PCI_ANY_ID, PCI_ANY_ID,
4509                 0,
4510                 0, pbn_b0_8_1152000_200 },
4511         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
4512                 PCI_ANY_ID, PCI_ANY_ID,
4513                 0,
4514                 0, pbn_exar_XR17V352 },
4515         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
4516                 PCI_ANY_ID, PCI_ANY_ID,
4517                 0,
4518                 0, pbn_exar_XR17V354 },
4519         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
4520                 PCI_ANY_ID, PCI_ANY_ID,
4521                 0,
4522                 0, pbn_exar_XR17V358 },
4523
4524         /*
4525          * These entries match devices with class COMMUNICATION_SERIAL,
4526          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4527          */
4528         {       PCI_ANY_ID, PCI_ANY_ID,
4529                 PCI_ANY_ID, PCI_ANY_ID,
4530                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4531                 0xffff00, pbn_default },
4532         {       PCI_ANY_ID, PCI_ANY_ID,
4533                 PCI_ANY_ID, PCI_ANY_ID,
4534                 PCI_CLASS_COMMUNICATION_MODEM << 8,
4535                 0xffff00, pbn_default },
4536         {       PCI_ANY_ID, PCI_ANY_ID,
4537                 PCI_ANY_ID, PCI_ANY_ID,
4538                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4539                 0xffff00, pbn_default },
4540         { 0, }
4541 };
4542
4543 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4544                                                 pci_channel_state_t state)
4545 {
4546         struct serial_private *priv = pci_get_drvdata(dev);
4547
4548         if (state == pci_channel_io_perm_failure)
4549                 return PCI_ERS_RESULT_DISCONNECT;
4550
4551         if (priv)
4552                 pciserial_suspend_ports(priv);
4553
4554         pci_disable_device(dev);
4555
4556         return PCI_ERS_RESULT_NEED_RESET;
4557 }
4558
4559 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4560 {
4561         int rc;
4562
4563         rc = pci_enable_device(dev);
4564
4565         if (rc)
4566                 return PCI_ERS_RESULT_DISCONNECT;
4567
4568         pci_restore_state(dev);
4569         pci_save_state(dev);
4570
4571         return PCI_ERS_RESULT_RECOVERED;
4572 }
4573
4574 static void serial8250_io_resume(struct pci_dev *dev)
4575 {
4576         struct serial_private *priv = pci_get_drvdata(dev);
4577
4578         if (priv)
4579                 pciserial_resume_ports(priv);
4580 }
4581
4582 static const struct pci_error_handlers serial8250_err_handler = {
4583         .error_detected = serial8250_io_error_detected,
4584         .slot_reset = serial8250_io_slot_reset,
4585         .resume = serial8250_io_resume,
4586 };
4587
4588 static struct pci_driver serial_pci_driver = {
4589         .name           = "serial",
4590         .probe          = pciserial_init_one,
4591         .remove         = pciserial_remove_one,
4592 #ifdef CONFIG_PM
4593         .suspend        = pciserial_suspend_one,
4594         .resume         = pciserial_resume_one,
4595 #endif
4596         .id_table       = serial_pci_tbl,
4597         .err_handler    = &serial8250_err_handler,
4598 };
4599
4600 module_pci_driver(serial_pci_driver);
4601
4602 MODULE_LICENSE("GPL");
4603 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4604 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);