2 * Base port operations for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * A note about mapbase / membase
14 * mapbase is the physical address of the IO port.
15 * membase is an 'ioremapped' cookie.
18 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/ioport.h>
25 #include <linux/init.h>
26 #include <linux/console.h>
27 #include <linux/sysrq.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/ratelimit.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/serial_8250.h>
35 #include <linux/nmi.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/timer.h>
48 * These are definitions for the Exar XR17V35X and XR17(C|D)15X
50 #define UART_EXAR_INT0 0x80
51 #define UART_EXAR_SLEEP 0x8b /* Sleep mode */
52 #define UART_EXAR_DVID 0x8d /* Device identification */
58 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
60 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
63 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
66 * Here we define the default xmit fifo size used for each type of UART.
68 static const struct serial8250_config uart_config[] = {
93 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
94 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
95 .rxtrig_bytes = {1, 4, 8, 14},
96 .flags = UART_CAP_FIFO,
107 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
113 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
115 .rxtrig_bytes = {8, 16, 24, 28},
116 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
122 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
124 .rxtrig_bytes = {1, 16, 32, 56},
125 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
133 .name = "16C950/954",
136 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
137 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
138 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
144 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
146 .rxtrig_bytes = {8, 16, 56, 60},
147 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
153 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
154 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
160 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
161 .flags = UART_CAP_FIFO,
167 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
168 .flags = UART_CAP_FIFO | UART_NATSEMI,
174 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
175 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
181 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
182 .flags = UART_CAP_FIFO,
188 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
189 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
195 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
196 .flags = UART_CAP_FIFO | UART_CAP_AFE,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
204 .rxtrig_bytes = {1, 4, 8, 14},
205 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
211 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
212 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
219 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
221 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
228 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
229 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
230 .flags = UART_CAP_FIFO,
232 [PORT_BRCM_TRUMANAGE] = {
236 .flags = UART_CAP_HFIFO,
241 [PORT_ALTR_16550_F32] = {
242 .name = "Altera 16550 FIFO32",
245 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
246 .flags = UART_CAP_FIFO | UART_CAP_AFE,
248 [PORT_ALTR_16550_F64] = {
249 .name = "Altera 16550 FIFO64",
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .flags = UART_CAP_FIFO | UART_CAP_AFE,
255 [PORT_ALTR_16550_F128] = {
256 .name = "Altera 16550 FIFO128",
259 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
260 .flags = UART_CAP_FIFO | UART_CAP_AFE,
263 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
264 * workaround of errata A-008006 which states that tx_loadsz should
265 * be configured less than Maximum supported fifo bytes.
267 [PORT_16550A_FSL64] = {
268 .name = "16550A_FSL64",
271 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
273 .flags = UART_CAP_FIFO,
276 .name = "Palmchip BK-3103",
279 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
280 .rxtrig_bytes = {1, 4, 8, 14},
281 .flags = UART_CAP_FIFO,
284 .name = "TI DA8xx/66AK2x",
287 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
289 .rxtrig_bytes = {1, 4, 8, 14},
290 .flags = UART_CAP_FIFO | UART_CAP_AFE,
294 /* Uart divisor latch read */
295 static int default_serial_dl_read(struct uart_8250_port *up)
297 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
300 /* Uart divisor latch write */
301 static void default_serial_dl_write(struct uart_8250_port *up, int value)
303 serial_out(up, UART_DLL, value & 0xff);
304 serial_out(up, UART_DLM, value >> 8 & 0xff);
307 #ifdef CONFIG_SERIAL_8250_RT288X
309 /* Au1x00/RT288x UART hardware has a weird register layout */
310 static const s8 au_io_in_map[8] = {
318 -1, /* UART_SCR (unmapped) */
321 static const s8 au_io_out_map[8] = {
327 -1, /* UART_LSR (unmapped) */
328 -1, /* UART_MSR (unmapped) */
329 -1, /* UART_SCR (unmapped) */
332 unsigned int au_serial_in(struct uart_port *p, int offset)
334 if (offset >= ARRAY_SIZE(au_io_in_map))
336 offset = au_io_in_map[offset];
339 return __raw_readl(p->membase + (offset << p->regshift));
342 void au_serial_out(struct uart_port *p, int offset, int value)
344 if (offset >= ARRAY_SIZE(au_io_out_map))
346 offset = au_io_out_map[offset];
349 __raw_writel(value, p->membase + (offset << p->regshift));
352 /* Au1x00 haven't got a standard divisor latch */
353 static int au_serial_dl_read(struct uart_8250_port *up)
355 return __raw_readl(up->port.membase + 0x28);
358 static void au_serial_dl_write(struct uart_8250_port *up, int value)
360 __raw_writel(value, up->port.membase + 0x28);
365 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
367 offset = offset << p->regshift;
368 outb(p->hub6 - 1 + offset, p->iobase);
369 return inb(p->iobase + 1);
372 static void hub6_serial_out(struct uart_port *p, int offset, int value)
374 offset = offset << p->regshift;
375 outb(p->hub6 - 1 + offset, p->iobase);
376 outb(value, p->iobase + 1);
379 static unsigned int mem_serial_in(struct uart_port *p, int offset)
381 offset = offset << p->regshift;
382 return readb(p->membase + offset);
385 static void mem_serial_out(struct uart_port *p, int offset, int value)
387 offset = offset << p->regshift;
388 writeb(value, p->membase + offset);
391 static void mem16_serial_out(struct uart_port *p, int offset, int value)
393 offset = offset << p->regshift;
394 writew(value, p->membase + offset);
397 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
399 offset = offset << p->regshift;
400 return readw(p->membase + offset);
403 static void mem32_serial_out(struct uart_port *p, int offset, int value)
405 offset = offset << p->regshift;
406 writel(value, p->membase + offset);
409 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
411 offset = offset << p->regshift;
412 return readl(p->membase + offset);
415 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
417 offset = offset << p->regshift;
418 iowrite32be(value, p->membase + offset);
421 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
423 offset = offset << p->regshift;
424 return ioread32be(p->membase + offset);
427 static unsigned int io_serial_in(struct uart_port *p, int offset)
429 offset = offset << p->regshift;
430 return inb(p->iobase + offset);
433 static void io_serial_out(struct uart_port *p, int offset, int value)
435 offset = offset << p->regshift;
436 outb(value, p->iobase + offset);
439 static int serial8250_default_handle_irq(struct uart_port *port);
440 static int exar_handle_irq(struct uart_port *port);
442 static void set_io_from_upio(struct uart_port *p)
444 struct uart_8250_port *up = up_to_u8250p(p);
446 up->dl_read = default_serial_dl_read;
447 up->dl_write = default_serial_dl_write;
451 p->serial_in = hub6_serial_in;
452 p->serial_out = hub6_serial_out;
456 p->serial_in = mem_serial_in;
457 p->serial_out = mem_serial_out;
461 p->serial_in = mem16_serial_in;
462 p->serial_out = mem16_serial_out;
466 p->serial_in = mem32_serial_in;
467 p->serial_out = mem32_serial_out;
471 p->serial_in = mem32be_serial_in;
472 p->serial_out = mem32be_serial_out;
475 #ifdef CONFIG_SERIAL_8250_RT288X
477 p->serial_in = au_serial_in;
478 p->serial_out = au_serial_out;
479 up->dl_read = au_serial_dl_read;
480 up->dl_write = au_serial_dl_write;
485 p->serial_in = io_serial_in;
486 p->serial_out = io_serial_out;
489 /* Remember loaded iotype */
490 up->cur_iotype = p->iotype;
491 p->handle_irq = serial8250_default_handle_irq;
495 serial_port_out_sync(struct uart_port *p, int offset, int value)
503 p->serial_out(p, offset, value);
504 p->serial_in(p, UART_LCR); /* safe, no side-effects */
507 p->serial_out(p, offset, value);
514 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
516 serial_out(up, UART_SCR, offset);
517 serial_out(up, UART_ICR, value);
520 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
524 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
525 serial_out(up, UART_SCR, offset);
526 value = serial_in(up, UART_ICR);
527 serial_icr_write(up, UART_ACR, up->acr);
535 static void serial8250_clear_fifos(struct uart_8250_port *p)
537 if (p->capabilities & UART_CAP_FIFO) {
538 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
539 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
540 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
541 serial_out(p, UART_FCR, 0);
545 static inline void serial8250_em485_rts_after_send(struct uart_8250_port *p)
547 unsigned char mcr = serial8250_in_MCR(p);
549 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
552 mcr &= ~UART_MCR_RTS;
553 serial8250_out_MCR(p, mcr);
556 static void serial8250_em485_handle_start_tx(unsigned long arg);
557 static void serial8250_em485_handle_stop_tx(unsigned long arg);
559 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
561 serial8250_clear_fifos(p);
562 serial_out(p, UART_FCR, p->fcr);
564 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
566 void serial8250_rpm_get(struct uart_8250_port *p)
568 if (!(p->capabilities & UART_CAP_RPM))
570 pm_runtime_get_sync(p->port.dev);
572 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
574 void serial8250_rpm_put(struct uart_8250_port *p)
576 if (!(p->capabilities & UART_CAP_RPM))
578 pm_runtime_mark_last_busy(p->port.dev);
579 pm_runtime_put_autosuspend(p->port.dev);
581 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
584 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
585 * @p: uart_8250_port port instance
587 * The function is used to start rs485 software emulating on the
588 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
589 * transmission. The function is idempotent, so it is safe to call it
592 * The caller MUST enable interrupt on empty shift register before
593 * calling serial8250_em485_init(). This interrupt is not a part of
594 * 8250 standard, but implementation defined.
596 * The function is supposed to be called from .rs485_config callback
597 * or from any other callback protected with p->port.lock spinlock.
599 * See also serial8250_em485_destroy()
601 * Return 0 - success, -errno - otherwise
603 int serial8250_em485_init(struct uart_8250_port *p)
608 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
612 setup_timer(&p->em485->stop_tx_timer,
613 serial8250_em485_handle_stop_tx, (unsigned long)p);
614 setup_timer(&p->em485->start_tx_timer,
615 serial8250_em485_handle_start_tx, (unsigned long)p);
616 p->em485->active_timer = NULL;
618 serial8250_em485_rts_after_send(p);
622 EXPORT_SYMBOL_GPL(serial8250_em485_init);
625 * serial8250_em485_destroy() - put uart_8250_port into normal state
626 * @p: uart_8250_port port instance
628 * The function is used to stop rs485 software emulating on the
629 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
630 * call it multiple times.
632 * The function is supposed to be called from .rs485_config callback
633 * or from any other callback protected with p->port.lock spinlock.
635 * See also serial8250_em485_init()
637 void serial8250_em485_destroy(struct uart_8250_port *p)
642 del_timer(&p->em485->start_tx_timer);
643 del_timer(&p->em485->stop_tx_timer);
648 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
651 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
652 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
653 * empty and the HW can idle again.
655 void serial8250_rpm_get_tx(struct uart_8250_port *p)
657 unsigned char rpm_active;
659 if (!(p->capabilities & UART_CAP_RPM))
662 rpm_active = xchg(&p->rpm_tx_active, 1);
665 pm_runtime_get_sync(p->port.dev);
667 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
669 void serial8250_rpm_put_tx(struct uart_8250_port *p)
671 unsigned char rpm_active;
673 if (!(p->capabilities & UART_CAP_RPM))
676 rpm_active = xchg(&p->rpm_tx_active, 0);
679 pm_runtime_mark_last_busy(p->port.dev);
680 pm_runtime_put_autosuspend(p->port.dev);
682 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
685 * IER sleep support. UARTs which have EFRs need the "extended
686 * capability" bit enabled. Note that on XR16C850s, we need to
687 * reset LCR to write to IER.
689 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
691 unsigned char lcr = 0, efr = 0;
693 * Exar UARTs have a SLEEP register that enables or disables
694 * each UART to enter sleep mode separately. On the XR17V35x the
695 * register is accessible to each UART at the UART_EXAR_SLEEP
696 * offset but the UART channel may only write to the corresponding
699 serial8250_rpm_get(p);
700 if ((p->port.type == PORT_XR17V35X) ||
701 (p->port.type == PORT_XR17D15X)) {
702 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
706 if (p->capabilities & UART_CAP_SLEEP) {
707 if (p->capabilities & UART_CAP_EFR) {
708 lcr = serial_in(p, UART_LCR);
709 efr = serial_in(p, UART_EFR);
710 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
711 serial_out(p, UART_EFR, UART_EFR_ECB);
712 serial_out(p, UART_LCR, 0);
714 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
715 if (p->capabilities & UART_CAP_EFR) {
716 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
717 serial_out(p, UART_EFR, efr);
718 serial_out(p, UART_LCR, lcr);
722 serial8250_rpm_put(p);
725 #ifdef CONFIG_SERIAL_8250_RSA
727 * Attempts to turn on the RSA FIFO. Returns zero on failure.
728 * We set the port uart clock rate if we succeed.
730 static int __enable_rsa(struct uart_8250_port *up)
735 mode = serial_in(up, UART_RSA_MSR);
736 result = mode & UART_RSA_MSR_FIFO;
739 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
740 mode = serial_in(up, UART_RSA_MSR);
741 result = mode & UART_RSA_MSR_FIFO;
745 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
750 static void enable_rsa(struct uart_8250_port *up)
752 if (up->port.type == PORT_RSA) {
753 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
754 spin_lock_irq(&up->port.lock);
756 spin_unlock_irq(&up->port.lock);
758 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
759 serial_out(up, UART_RSA_FRR, 0);
764 * Attempts to turn off the RSA FIFO. Returns zero on failure.
765 * It is unknown why interrupts were disabled in here. However,
766 * the caller is expected to preserve this behaviour by grabbing
767 * the spinlock before calling this function.
769 static void disable_rsa(struct uart_8250_port *up)
774 if (up->port.type == PORT_RSA &&
775 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
776 spin_lock_irq(&up->port.lock);
778 mode = serial_in(up, UART_RSA_MSR);
779 result = !(mode & UART_RSA_MSR_FIFO);
782 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
783 mode = serial_in(up, UART_RSA_MSR);
784 result = !(mode & UART_RSA_MSR_FIFO);
788 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
789 spin_unlock_irq(&up->port.lock);
792 #endif /* CONFIG_SERIAL_8250_RSA */
795 * This is a quickie test to see how big the FIFO is.
796 * It doesn't work at all the time, more's the pity.
798 static int size_fifo(struct uart_8250_port *up)
800 unsigned char old_fcr, old_mcr, old_lcr;
801 unsigned short old_dl;
804 old_lcr = serial_in(up, UART_LCR);
805 serial_out(up, UART_LCR, 0);
806 old_fcr = serial_in(up, UART_FCR);
807 old_mcr = serial8250_in_MCR(up);
808 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
809 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
810 serial8250_out_MCR(up, UART_MCR_LOOP);
811 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
812 old_dl = serial_dl_read(up);
813 serial_dl_write(up, 0x0001);
814 serial_out(up, UART_LCR, 0x03);
815 for (count = 0; count < 256; count++)
816 serial_out(up, UART_TX, count);
817 mdelay(20);/* FIXME - schedule_timeout */
818 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
819 (count < 256); count++)
820 serial_in(up, UART_RX);
821 serial_out(up, UART_FCR, old_fcr);
822 serial8250_out_MCR(up, old_mcr);
823 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
824 serial_dl_write(up, old_dl);
825 serial_out(up, UART_LCR, old_lcr);
831 * Read UART ID using the divisor method - set DLL and DLM to zero
832 * and the revision will be in DLL and device type in DLM. We
833 * preserve the device state across this.
835 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
837 unsigned char old_lcr;
838 unsigned int id, old_dl;
840 old_lcr = serial_in(p, UART_LCR);
841 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
842 old_dl = serial_dl_read(p);
843 serial_dl_write(p, 0);
844 id = serial_dl_read(p);
845 serial_dl_write(p, old_dl);
847 serial_out(p, UART_LCR, old_lcr);
853 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
854 * When this function is called we know it is at least a StarTech
855 * 16650 V2, but it might be one of several StarTech UARTs, or one of
856 * its clones. (We treat the broken original StarTech 16650 V1 as a
857 * 16550, and why not? Startech doesn't seem to even acknowledge its
860 * What evil have men's minds wrought...
862 static void autoconfig_has_efr(struct uart_8250_port *up)
864 unsigned int id1, id2, id3, rev;
867 * Everything with an EFR has SLEEP
869 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
872 * First we check to see if it's an Oxford Semiconductor UART.
874 * If we have to do this here because some non-National
875 * Semiconductor clone chips lock up if you try writing to the
876 * LSR register (which serial_icr_read does)
880 * Check for Oxford Semiconductor 16C950.
882 * EFR [4] must be set else this test fails.
884 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
885 * claims that it's needed for 952 dual UART's (which are not
886 * recommended for new designs).
889 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
890 serial_out(up, UART_EFR, UART_EFR_ECB);
891 serial_out(up, UART_LCR, 0x00);
892 id1 = serial_icr_read(up, UART_ID1);
893 id2 = serial_icr_read(up, UART_ID2);
894 id3 = serial_icr_read(up, UART_ID3);
895 rev = serial_icr_read(up, UART_REV);
897 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
899 if (id1 == 0x16 && id2 == 0xC9 &&
900 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
901 up->port.type = PORT_16C950;
904 * Enable work around for the Oxford Semiconductor 952 rev B
905 * chip which causes it to seriously miscalculate baud rates
908 if (id3 == 0x52 && rev == 0x01)
909 up->bugs |= UART_BUG_QUOT;
914 * We check for a XR16C850 by setting DLL and DLM to 0, and then
915 * reading back DLL and DLM. The chip type depends on the DLM
917 * 0x10 - XR16C850 and the DLL contains the chip revision.
921 id1 = autoconfig_read_divisor_id(up);
922 DEBUG_AUTOCONF("850id=%04x ", id1);
925 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
926 up->port.type = PORT_16850;
931 * It wasn't an XR16C850.
933 * We distinguish between the '654 and the '650 by counting
934 * how many bytes are in the FIFO. I'm using this for now,
935 * since that's the technique that was sent to me in the
936 * serial driver update, but I'm not convinced this works.
937 * I've had problems doing this in the past. -TYT
939 if (size_fifo(up) == 64)
940 up->port.type = PORT_16654;
942 up->port.type = PORT_16650V2;
946 * We detected a chip without a FIFO. Only two fall into
947 * this category - the original 8250 and the 16450. The
948 * 16450 has a scratch register (accessible with LCR=0)
950 static void autoconfig_8250(struct uart_8250_port *up)
952 unsigned char scratch, status1, status2;
954 up->port.type = PORT_8250;
956 scratch = serial_in(up, UART_SCR);
957 serial_out(up, UART_SCR, 0xa5);
958 status1 = serial_in(up, UART_SCR);
959 serial_out(up, UART_SCR, 0x5a);
960 status2 = serial_in(up, UART_SCR);
961 serial_out(up, UART_SCR, scratch);
963 if (status1 == 0xa5 && status2 == 0x5a)
964 up->port.type = PORT_16450;
967 static int broken_efr(struct uart_8250_port *up)
970 * Exar ST16C2550 "A2" devices incorrectly detect as
971 * having an EFR, and report an ID of 0x0201. See
972 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
974 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
981 * We know that the chip has FIFOs. Does it have an EFR? The
982 * EFR is located in the same register position as the IIR and
983 * we know the top two bits of the IIR are currently set. The
984 * EFR should contain zero. Try to read the EFR.
986 static void autoconfig_16550a(struct uart_8250_port *up)
988 unsigned char status1, status2;
989 unsigned int iersave;
991 up->port.type = PORT_16550A;
992 up->capabilities |= UART_CAP_FIFO;
995 * XR17V35x UARTs have an extra divisor register, DLD
996 * that gets enabled with when DLAB is set which will
997 * cause the device to incorrectly match and assign
998 * port type to PORT_16650. The EFR for this UART is
999 * found at offset 0x09. Instead check the Deice ID (DVID)
1000 * register for a 2, 4 or 8 port UART.
1002 if (up->port.flags & UPF_EXAR_EFR) {
1003 status1 = serial_in(up, UART_EXAR_DVID);
1004 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
1005 DEBUG_AUTOCONF("Exar XR17V35x ");
1006 up->port.type = PORT_XR17V35X;
1007 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1016 * Check for presence of the EFR when DLAB is set.
1017 * Only ST16C650V1 UARTs pass this test.
1019 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1020 if (serial_in(up, UART_EFR) == 0) {
1021 serial_out(up, UART_EFR, 0xA8);
1022 if (serial_in(up, UART_EFR) != 0) {
1023 DEBUG_AUTOCONF("EFRv1 ");
1024 up->port.type = PORT_16650;
1025 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1027 serial_out(up, UART_LCR, 0);
1028 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1030 status1 = serial_in(up, UART_IIR) >> 5;
1031 serial_out(up, UART_FCR, 0);
1032 serial_out(up, UART_LCR, 0);
1035 up->port.type = PORT_16550A_FSL64;
1037 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1039 serial_out(up, UART_EFR, 0);
1044 * Maybe it requires 0xbf to be written to the LCR.
1045 * (other ST16C650V2 UARTs, TI16C752A, etc)
1047 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1048 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1049 DEBUG_AUTOCONF("EFRv2 ");
1050 autoconfig_has_efr(up);
1055 * Check for a National Semiconductor SuperIO chip.
1056 * Attempt to switch to bank 2, read the value of the LOOP bit
1057 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1058 * switch back to bank 2, read it from EXCR1 again and check
1059 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1061 serial_out(up, UART_LCR, 0);
1062 status1 = serial8250_in_MCR(up);
1063 serial_out(up, UART_LCR, 0xE0);
1064 status2 = serial_in(up, 0x02); /* EXCR1 */
1066 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1067 serial_out(up, UART_LCR, 0);
1068 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1069 serial_out(up, UART_LCR, 0xE0);
1070 status2 = serial_in(up, 0x02); /* EXCR1 */
1071 serial_out(up, UART_LCR, 0);
1072 serial8250_out_MCR(up, status1);
1074 if ((status2 ^ status1) & UART_MCR_LOOP) {
1075 unsigned short quot;
1077 serial_out(up, UART_LCR, 0xE0);
1079 quot = serial_dl_read(up);
1082 if (ns16550a_goto_highspeed(up))
1083 serial_dl_write(up, quot);
1085 serial_out(up, UART_LCR, 0);
1087 up->port.uartclk = 921600*16;
1088 up->port.type = PORT_NS16550A;
1089 up->capabilities |= UART_NATSEMI;
1095 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1096 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1097 * Try setting it with and without DLAB set. Cheap clones
1098 * set bit 5 without DLAB set.
1100 serial_out(up, UART_LCR, 0);
1101 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1102 status1 = serial_in(up, UART_IIR) >> 5;
1103 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1104 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1105 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1106 status2 = serial_in(up, UART_IIR) >> 5;
1107 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1108 serial_out(up, UART_LCR, 0);
1110 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1112 if (status1 == 6 && status2 == 7) {
1113 up->port.type = PORT_16750;
1114 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1119 * Try writing and reading the UART_IER_UUE bit (b6).
1120 * If it works, this is probably one of the Xscale platform's
1122 * We're going to explicitly set the UUE bit to 0 before
1123 * trying to write and read a 1 just to make sure it's not
1124 * already a 1 and maybe locked there before we even start start.
1126 iersave = serial_in(up, UART_IER);
1127 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1128 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1130 * OK it's in a known zero state, try writing and reading
1131 * without disturbing the current state of the other bits.
1133 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1134 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1137 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1139 DEBUG_AUTOCONF("Xscale ");
1140 up->port.type = PORT_XSCALE;
1141 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1146 * If we got here we couldn't force the IER_UUE bit to 0.
1147 * Log it and continue.
1149 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1151 serial_out(up, UART_IER, iersave);
1154 * Exar uarts have EFR in a weird location
1156 if (up->port.flags & UPF_EXAR_EFR) {
1157 DEBUG_AUTOCONF("Exar XR17D15x ");
1158 up->port.type = PORT_XR17D15X;
1159 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1166 * We distinguish between 16550A and U6 16550A by counting
1167 * how many bytes are in the FIFO.
1169 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1170 up->port.type = PORT_U6_16550A;
1171 up->capabilities |= UART_CAP_AFE;
1176 * This routine is called by rs_init() to initialize a specific serial
1177 * port. It determines what type of UART chip this serial port is
1178 * using: 8250, 16450, 16550, 16550A. The important question is
1179 * whether or not this UART is a 16550A or not, since this will
1180 * determine whether or not we can use its FIFO features or not.
1182 static void autoconfig(struct uart_8250_port *up)
1184 unsigned char status1, scratch, scratch2, scratch3;
1185 unsigned char save_lcr, save_mcr;
1186 struct uart_port *port = &up->port;
1187 unsigned long flags;
1188 unsigned int old_capabilities;
1190 if (!port->iobase && !port->mapbase && !port->membase)
1193 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1194 serial_index(port), port->iobase, port->membase);
1197 * We really do need global IRQs disabled here - we're going to
1198 * be frobbing the chips IRQ enable register to see if it exists.
1200 spin_lock_irqsave(&port->lock, flags);
1202 up->capabilities = 0;
1205 if (!(port->flags & UPF_BUGGY_UART)) {
1207 * Do a simple existence test first; if we fail this,
1208 * there's no point trying anything else.
1210 * 0x80 is used as a nonsense port to prevent against
1211 * false positives due to ISA bus float. The
1212 * assumption is that 0x80 is a non-existent port;
1213 * which should be safe since include/asm/io.h also
1214 * makes this assumption.
1216 * Note: this is safe as long as MCR bit 4 is clear
1217 * and the device is in "PC" mode.
1219 scratch = serial_in(up, UART_IER);
1220 serial_out(up, UART_IER, 0);
1225 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1226 * 16C754B) allow only to modify them if an EFR bit is set.
1228 scratch2 = serial_in(up, UART_IER) & 0x0f;
1229 serial_out(up, UART_IER, 0x0F);
1233 scratch3 = serial_in(up, UART_IER) & 0x0f;
1234 serial_out(up, UART_IER, scratch);
1235 if (scratch2 != 0 || scratch3 != 0x0F) {
1237 * We failed; there's nothing here
1239 spin_unlock_irqrestore(&port->lock, flags);
1240 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1241 scratch2, scratch3);
1246 save_mcr = serial8250_in_MCR(up);
1247 save_lcr = serial_in(up, UART_LCR);
1250 * Check to see if a UART is really there. Certain broken
1251 * internal modems based on the Rockwell chipset fail this
1252 * test, because they apparently don't implement the loopback
1253 * test mode. So this test is skipped on the COM 1 through
1254 * COM 4 ports. This *should* be safe, since no board
1255 * manufacturer would be stupid enough to design a board
1256 * that conflicts with COM 1-4 --- we hope!
1258 if (!(port->flags & UPF_SKIP_TEST)) {
1259 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1260 status1 = serial_in(up, UART_MSR) & 0xF0;
1261 serial8250_out_MCR(up, save_mcr);
1262 if (status1 != 0x90) {
1263 spin_unlock_irqrestore(&port->lock, flags);
1264 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1271 * We're pretty sure there's a port here. Lets find out what
1272 * type of port it is. The IIR top two bits allows us to find
1273 * out if it's 8250 or 16450, 16550, 16550A or later. This
1274 * determines what we test for next.
1276 * We also initialise the EFR (if any) to zero for later. The
1277 * EFR occupies the same register location as the FCR and IIR.
1279 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1280 serial_out(up, UART_EFR, 0);
1281 serial_out(up, UART_LCR, 0);
1283 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1284 scratch = serial_in(up, UART_IIR) >> 6;
1288 autoconfig_8250(up);
1291 port->type = PORT_UNKNOWN;
1294 port->type = PORT_16550;
1297 autoconfig_16550a(up);
1301 #ifdef CONFIG_SERIAL_8250_RSA
1303 * Only probe for RSA ports if we got the region.
1305 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1307 port->type = PORT_RSA;
1310 serial_out(up, UART_LCR, save_lcr);
1312 port->fifosize = uart_config[up->port.type].fifo_size;
1313 old_capabilities = up->capabilities;
1314 up->capabilities = uart_config[port->type].flags;
1315 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1317 if (port->type == PORT_UNKNOWN)
1323 #ifdef CONFIG_SERIAL_8250_RSA
1324 if (port->type == PORT_RSA)
1325 serial_out(up, UART_RSA_FRR, 0);
1327 serial8250_out_MCR(up, save_mcr);
1328 serial8250_clear_fifos(up);
1329 serial_in(up, UART_RX);
1330 if (up->capabilities & UART_CAP_UUE)
1331 serial_out(up, UART_IER, UART_IER_UUE);
1333 serial_out(up, UART_IER, 0);
1336 spin_unlock_irqrestore(&port->lock, flags);
1339 * Check if the device is a Fintek F81216A
1341 if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1342 fintek_8250_probe(up);
1344 if (up->capabilities != old_capabilities) {
1345 pr_warn("ttyS%d: detected caps %08x should be %08x\n",
1346 serial_index(port), old_capabilities,
1350 DEBUG_AUTOCONF("iir=%d ", scratch);
1351 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1354 static void autoconfig_irq(struct uart_8250_port *up)
1356 struct uart_port *port = &up->port;
1357 unsigned char save_mcr, save_ier;
1358 unsigned char save_ICP = 0;
1359 unsigned int ICP = 0;
1363 if (port->flags & UPF_FOURPORT) {
1364 ICP = (port->iobase & 0xfe0) | 0x1f;
1365 save_ICP = inb_p(ICP);
1370 if (uart_console(port))
1373 /* forget possible initially masked and pending IRQ */
1374 probe_irq_off(probe_irq_on());
1375 save_mcr = serial8250_in_MCR(up);
1376 save_ier = serial_in(up, UART_IER);
1377 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1379 irqs = probe_irq_on();
1380 serial8250_out_MCR(up, 0);
1382 if (port->flags & UPF_FOURPORT) {
1383 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1385 serial8250_out_MCR(up,
1386 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1388 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1389 serial_in(up, UART_LSR);
1390 serial_in(up, UART_RX);
1391 serial_in(up, UART_IIR);
1392 serial_in(up, UART_MSR);
1393 serial_out(up, UART_TX, 0xFF);
1395 irq = probe_irq_off(irqs);
1397 serial8250_out_MCR(up, save_mcr);
1398 serial_out(up, UART_IER, save_ier);
1400 if (port->flags & UPF_FOURPORT)
1401 outb_p(save_ICP, ICP);
1403 if (uart_console(port))
1406 port->irq = (irq > 0) ? irq : 0;
1409 static void serial8250_stop_rx(struct uart_port *port)
1411 struct uart_8250_port *up = up_to_u8250p(port);
1413 serial8250_rpm_get(up);
1415 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1416 up->port.read_status_mask &= ~UART_LSR_DR;
1417 serial_port_out(port, UART_IER, up->ier);
1419 serial8250_rpm_put(up);
1422 static void __do_stop_tx_rs485(struct uart_8250_port *p)
1424 serial8250_em485_rts_after_send(p);
1427 * Empty the RX FIFO, we are not interested in anything
1428 * received during the half-duplex transmission.
1429 * Enable previously disabled RX interrupts.
1431 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1432 serial8250_clear_and_reinit_fifos(p);
1434 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1435 serial_port_out(&p->port, UART_IER, p->ier);
1439 static void serial8250_em485_handle_stop_tx(unsigned long arg)
1441 struct uart_8250_port *p = (struct uart_8250_port *)arg;
1442 struct uart_8250_em485 *em485 = p->em485;
1443 unsigned long flags;
1445 serial8250_rpm_get(p);
1446 spin_lock_irqsave(&p->port.lock, flags);
1448 em485->active_timer == &em485->stop_tx_timer) {
1449 __do_stop_tx_rs485(p);
1450 em485->active_timer = NULL;
1452 spin_unlock_irqrestore(&p->port.lock, flags);
1453 serial8250_rpm_put(p);
1456 static void __stop_tx_rs485(struct uart_8250_port *p)
1458 struct uart_8250_em485 *em485 = p->em485;
1461 * __do_stop_tx_rs485 is going to set RTS according to config
1462 * AND flush RX FIFO if required.
1464 if (p->port.rs485.delay_rts_after_send > 0) {
1465 em485->active_timer = &em485->stop_tx_timer;
1466 mod_timer(&em485->stop_tx_timer, jiffies +
1467 p->port.rs485.delay_rts_after_send * HZ / 1000);
1469 __do_stop_tx_rs485(p);
1473 static inline void __do_stop_tx(struct uart_8250_port *p)
1475 if (p->ier & UART_IER_THRI) {
1476 p->ier &= ~UART_IER_THRI;
1477 serial_out(p, UART_IER, p->ier);
1478 serial8250_rpm_put_tx(p);
1482 static inline void __stop_tx(struct uart_8250_port *p)
1484 struct uart_8250_em485 *em485 = p->em485;
1487 unsigned char lsr = serial_in(p, UART_LSR);
1489 * To provide required timeing and allow FIFO transfer,
1490 * __stop_tx_rs485() must be called only when both FIFO and
1491 * shift register are empty. It is for device driver to enable
1492 * interrupt on TEMT.
1494 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1497 del_timer(&em485->start_tx_timer);
1498 em485->active_timer = NULL;
1505 static void serial8250_stop_tx(struct uart_port *port)
1507 struct uart_8250_port *up = up_to_u8250p(port);
1509 serial8250_rpm_get(up);
1513 * We really want to stop the transmitter from sending.
1515 if (port->type == PORT_16C950) {
1516 up->acr |= UART_ACR_TXDIS;
1517 serial_icr_write(up, UART_ACR, up->acr);
1519 serial8250_rpm_put(up);
1522 static inline void __start_tx(struct uart_port *port)
1524 struct uart_8250_port *up = up_to_u8250p(port);
1526 if (up->dma && !up->dma->tx_dma(up))
1529 if (!(up->ier & UART_IER_THRI)) {
1530 up->ier |= UART_IER_THRI;
1531 serial_port_out(port, UART_IER, up->ier);
1533 if (up->bugs & UART_BUG_TXEN) {
1536 lsr = serial_in(up, UART_LSR);
1537 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1538 if (lsr & UART_LSR_THRE)
1539 serial8250_tx_chars(up);
1544 * Re-enable the transmitter if we disabled it.
1546 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1547 up->acr &= ~UART_ACR_TXDIS;
1548 serial_icr_write(up, UART_ACR, up->acr);
1552 static inline void start_tx_rs485(struct uart_port *port)
1554 struct uart_8250_port *up = up_to_u8250p(port);
1555 struct uart_8250_em485 *em485 = up->em485;
1558 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1559 serial8250_stop_rx(&up->port);
1561 del_timer(&em485->stop_tx_timer);
1562 em485->active_timer = NULL;
1564 mcr = serial8250_in_MCR(up);
1565 if (!!(up->port.rs485.flags & SER_RS485_RTS_ON_SEND) !=
1566 !!(mcr & UART_MCR_RTS)) {
1567 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1568 mcr |= UART_MCR_RTS;
1570 mcr &= ~UART_MCR_RTS;
1571 serial8250_out_MCR(up, mcr);
1573 if (up->port.rs485.delay_rts_before_send > 0) {
1574 em485->active_timer = &em485->start_tx_timer;
1575 mod_timer(&em485->start_tx_timer, jiffies +
1576 up->port.rs485.delay_rts_before_send * HZ / 1000);
1584 static void serial8250_em485_handle_start_tx(unsigned long arg)
1586 struct uart_8250_port *p = (struct uart_8250_port *)arg;
1587 struct uart_8250_em485 *em485 = p->em485;
1588 unsigned long flags;
1590 spin_lock_irqsave(&p->port.lock, flags);
1592 em485->active_timer == &em485->start_tx_timer) {
1593 __start_tx(&p->port);
1594 em485->active_timer = NULL;
1596 spin_unlock_irqrestore(&p->port.lock, flags);
1599 static void serial8250_start_tx(struct uart_port *port)
1601 struct uart_8250_port *up = up_to_u8250p(port);
1602 struct uart_8250_em485 *em485 = up->em485;
1604 serial8250_rpm_get_tx(up);
1607 em485->active_timer == &em485->start_tx_timer)
1611 start_tx_rs485(port);
1616 static void serial8250_throttle(struct uart_port *port)
1618 port->throttle(port);
1621 static void serial8250_unthrottle(struct uart_port *port)
1623 port->unthrottle(port);
1626 static void serial8250_disable_ms(struct uart_port *port)
1628 struct uart_8250_port *up = up_to_u8250p(port);
1630 /* no MSR capabilities */
1631 if (up->bugs & UART_BUG_NOMSR)
1634 up->ier &= ~UART_IER_MSI;
1635 serial_port_out(port, UART_IER, up->ier);
1638 static void serial8250_enable_ms(struct uart_port *port)
1640 struct uart_8250_port *up = up_to_u8250p(port);
1642 /* no MSR capabilities */
1643 if (up->bugs & UART_BUG_NOMSR)
1646 up->ier |= UART_IER_MSI;
1648 serial8250_rpm_get(up);
1649 serial_port_out(port, UART_IER, up->ier);
1650 serial8250_rpm_put(up);
1653 static void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1655 struct uart_port *port = &up->port;
1657 char flag = TTY_NORMAL;
1659 if (likely(lsr & UART_LSR_DR))
1660 ch = serial_in(up, UART_RX);
1663 * Intel 82571 has a Serial Over Lan device that will
1664 * set UART_LSR_BI without setting UART_LSR_DR when
1665 * it receives a break. To avoid reading from the
1666 * receive buffer without UART_LSR_DR bit set, we
1667 * just force the read character to be 0
1673 lsr |= up->lsr_saved_flags;
1674 up->lsr_saved_flags = 0;
1676 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1677 if (lsr & UART_LSR_BI) {
1678 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1681 * We do the SysRQ and SAK checking
1682 * here because otherwise the break
1683 * may get masked by ignore_status_mask
1684 * or read_status_mask.
1686 if (uart_handle_break(port))
1688 } else if (lsr & UART_LSR_PE)
1689 port->icount.parity++;
1690 else if (lsr & UART_LSR_FE)
1691 port->icount.frame++;
1692 if (lsr & UART_LSR_OE)
1693 port->icount.overrun++;
1696 * Mask off conditions which should be ignored.
1698 lsr &= port->read_status_mask;
1700 if (lsr & UART_LSR_BI) {
1701 pr_debug("%s: handling break\n", __func__);
1703 } else if (lsr & UART_LSR_PE)
1705 else if (lsr & UART_LSR_FE)
1708 if (uart_handle_sysrq_char(port, ch))
1711 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1715 * serial8250_rx_chars: processes according to the passed in LSR
1716 * value, and returns the remaining LSR bits not handled
1717 * by this Rx routine.
1719 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1721 struct uart_port *port = &up->port;
1722 int max_count = 256;
1725 serial8250_read_char(up, lsr);
1726 if (--max_count == 0)
1728 lsr = serial_in(up, UART_LSR);
1729 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1731 tty_flip_buffer_push(&port->state->port);
1734 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1736 void serial8250_tx_chars(struct uart_8250_port *up)
1738 struct uart_port *port = &up->port;
1739 struct circ_buf *xmit = &port->state->xmit;
1743 serial_out(up, UART_TX, port->x_char);
1748 if (uart_tx_stopped(port)) {
1749 serial8250_stop_tx(port);
1752 if (uart_circ_empty(xmit)) {
1757 count = up->tx_loadsz;
1759 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1760 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1762 if (uart_circ_empty(xmit))
1764 if ((up->capabilities & UART_CAP_HFIFO) &&
1765 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1767 /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1768 if ((up->capabilities & UART_CAP_MINI) &&
1769 !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1771 } while (--count > 0);
1773 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1774 uart_write_wakeup(port);
1777 * With RPM enabled, we have to wait until the FIFO is empty before the
1778 * HW can go idle. So we get here once again with empty FIFO and disable
1779 * the interrupt and RPM in __stop_tx()
1781 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1784 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1786 /* Caller holds uart port lock */
1787 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1789 struct uart_port *port = &up->port;
1790 unsigned int status = serial_in(up, UART_MSR);
1792 status |= up->msr_saved_flags;
1793 up->msr_saved_flags = 0;
1794 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1795 port->state != NULL) {
1796 if (status & UART_MSR_TERI)
1798 if (status & UART_MSR_DDSR)
1800 if (status & UART_MSR_DDCD)
1801 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1802 if (status & UART_MSR_DCTS)
1803 uart_handle_cts_change(port, status & UART_MSR_CTS);
1805 wake_up_interruptible(&port->state->port.delta_msr_wait);
1810 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1812 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1814 switch (iir & 0x3f) {
1815 case UART_IIR_RX_TIMEOUT:
1816 serial8250_rx_dma_flush(up);
1821 return up->dma->rx_dma(up);
1825 * This handles the interrupt from one port.
1827 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1829 unsigned char status;
1830 unsigned long flags;
1831 struct uart_8250_port *up = up_to_u8250p(port);
1833 if (iir & UART_IIR_NO_INT)
1836 spin_lock_irqsave(&port->lock, flags);
1838 status = serial_port_in(port, UART_LSR);
1840 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1841 if (!up->dma || handle_rx_dma(up, iir))
1842 status = serial8250_rx_chars(up, status);
1844 serial8250_modem_status(up);
1845 if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE))
1846 serial8250_tx_chars(up);
1848 spin_unlock_irqrestore(&port->lock, flags);
1851 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1853 static int serial8250_default_handle_irq(struct uart_port *port)
1855 struct uart_8250_port *up = up_to_u8250p(port);
1859 serial8250_rpm_get(up);
1861 iir = serial_port_in(port, UART_IIR);
1862 ret = serial8250_handle_irq(port, iir);
1864 serial8250_rpm_put(up);
1869 * These Exar UARTs have an extra interrupt indicator that could
1870 * fire for a few unimplemented interrupts. One of which is a
1871 * wakeup event when coming out of sleep. Put this here just
1872 * to be on the safe side that these interrupts don't go unhandled.
1874 static int exar_handle_irq(struct uart_port *port)
1876 unsigned int iir = serial_port_in(port, UART_IIR);
1879 if (((port->type == PORT_XR17V35X) || (port->type == PORT_XR17D15X)) &&
1880 serial_port_in(port, UART_EXAR_INT0) != 0)
1883 ret |= serial8250_handle_irq(port, iir);
1889 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1890 * have a programmable TX threshold that triggers the THRE interrupt in
1891 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1892 * has space available. Load it up with tx_loadsz bytes.
1894 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1896 unsigned long flags;
1897 unsigned int iir = serial_port_in(port, UART_IIR);
1899 /* TX Threshold IRQ triggered so load up FIFO */
1900 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1901 struct uart_8250_port *up = up_to_u8250p(port);
1903 spin_lock_irqsave(&port->lock, flags);
1904 serial8250_tx_chars(up);
1905 spin_unlock_irqrestore(&port->lock, flags);
1908 iir = serial_port_in(port, UART_IIR);
1909 return serial8250_handle_irq(port, iir);
1912 static unsigned int serial8250_tx_empty(struct uart_port *port)
1914 struct uart_8250_port *up = up_to_u8250p(port);
1915 unsigned long flags;
1918 serial8250_rpm_get(up);
1920 spin_lock_irqsave(&port->lock, flags);
1921 lsr = serial_port_in(port, UART_LSR);
1922 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1923 spin_unlock_irqrestore(&port->lock, flags);
1925 serial8250_rpm_put(up);
1927 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1930 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1932 struct uart_8250_port *up = up_to_u8250p(port);
1933 unsigned int status;
1936 serial8250_rpm_get(up);
1937 status = serial8250_modem_status(up);
1938 serial8250_rpm_put(up);
1941 if (status & UART_MSR_DCD)
1943 if (status & UART_MSR_RI)
1945 if (status & UART_MSR_DSR)
1947 if (status & UART_MSR_CTS)
1951 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
1953 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1955 if (port->get_mctrl)
1956 return port->get_mctrl(port);
1957 return serial8250_do_get_mctrl(port);
1960 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1962 struct uart_8250_port *up = up_to_u8250p(port);
1963 unsigned char mcr = 0;
1965 if (mctrl & TIOCM_RTS)
1966 mcr |= UART_MCR_RTS;
1967 if (mctrl & TIOCM_DTR)
1968 mcr |= UART_MCR_DTR;
1969 if (mctrl & TIOCM_OUT1)
1970 mcr |= UART_MCR_OUT1;
1971 if (mctrl & TIOCM_OUT2)
1972 mcr |= UART_MCR_OUT2;
1973 if (mctrl & TIOCM_LOOP)
1974 mcr |= UART_MCR_LOOP;
1976 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1978 serial8250_out_MCR(up, mcr);
1980 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1982 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1984 if (port->set_mctrl)
1985 port->set_mctrl(port, mctrl);
1987 serial8250_do_set_mctrl(port, mctrl);
1990 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1992 struct uart_8250_port *up = up_to_u8250p(port);
1993 unsigned long flags;
1995 serial8250_rpm_get(up);
1996 spin_lock_irqsave(&port->lock, flags);
1997 if (break_state == -1)
1998 up->lcr |= UART_LCR_SBC;
2000 up->lcr &= ~UART_LCR_SBC;
2001 serial_port_out(port, UART_LCR, up->lcr);
2002 spin_unlock_irqrestore(&port->lock, flags);
2003 serial8250_rpm_put(up);
2007 * Wait for transmitter & holding register to empty
2009 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2011 unsigned int status, tmout = 10000;
2013 /* Wait up to 10ms for the character(s) to be sent. */
2015 status = serial_in(up, UART_LSR);
2017 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2019 if ((status & bits) == bits)
2024 touch_nmi_watchdog();
2027 /* Wait up to 1s for flow control if necessary */
2028 if (up->port.flags & UPF_CONS_FLOW) {
2029 for (tmout = 1000000; tmout; tmout--) {
2030 unsigned int msr = serial_in(up, UART_MSR);
2031 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2032 if (msr & UART_MSR_CTS)
2035 touch_nmi_watchdog();
2040 #ifdef CONFIG_CONSOLE_POLL
2042 * Console polling routines for writing and reading from the uart while
2043 * in an interrupt or debug context.
2046 static int serial8250_get_poll_char(struct uart_port *port)
2048 struct uart_8250_port *up = up_to_u8250p(port);
2052 serial8250_rpm_get(up);
2054 lsr = serial_port_in(port, UART_LSR);
2056 if (!(lsr & UART_LSR_DR)) {
2057 status = NO_POLL_CHAR;
2061 status = serial_port_in(port, UART_RX);
2063 serial8250_rpm_put(up);
2068 static void serial8250_put_poll_char(struct uart_port *port,
2072 struct uart_8250_port *up = up_to_u8250p(port);
2074 serial8250_rpm_get(up);
2076 * First save the IER then disable the interrupts
2078 ier = serial_port_in(port, UART_IER);
2079 if (up->capabilities & UART_CAP_UUE)
2080 serial_port_out(port, UART_IER, UART_IER_UUE);
2082 serial_port_out(port, UART_IER, 0);
2084 wait_for_xmitr(up, BOTH_EMPTY);
2086 * Send the character out.
2088 serial_port_out(port, UART_TX, c);
2091 * Finally, wait for transmitter to become empty
2092 * and restore the IER
2094 wait_for_xmitr(up, BOTH_EMPTY);
2095 serial_port_out(port, UART_IER, ier);
2096 serial8250_rpm_put(up);
2099 #endif /* CONFIG_CONSOLE_POLL */
2101 int serial8250_do_startup(struct uart_port *port)
2103 struct uart_8250_port *up = up_to_u8250p(port);
2104 unsigned long flags;
2105 unsigned char lsr, iir;
2108 if (!port->fifosize)
2109 port->fifosize = uart_config[port->type].fifo_size;
2111 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2112 if (!up->capabilities)
2113 up->capabilities = uart_config[port->type].flags;
2116 if (port->iotype != up->cur_iotype)
2117 set_io_from_upio(port);
2119 serial8250_rpm_get(up);
2120 if (port->type == PORT_16C950) {
2121 /* Wake up and initialize UART */
2123 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2124 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2125 serial_port_out(port, UART_IER, 0);
2126 serial_port_out(port, UART_LCR, 0);
2127 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2128 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2129 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2130 serial_port_out(port, UART_LCR, 0);
2133 if (port->type == PORT_DA830) {
2134 /* Reset the port */
2135 serial_port_out(port, UART_IER, 0);
2136 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2139 /* Enable Tx, Rx and free run mode */
2140 serial_port_out(port, UART_DA830_PWREMU_MGMT,
2141 UART_DA830_PWREMU_MGMT_UTRST |
2142 UART_DA830_PWREMU_MGMT_URRST |
2143 UART_DA830_PWREMU_MGMT_FREE);
2146 #ifdef CONFIG_SERIAL_8250_RSA
2148 * If this is an RSA port, see if we can kick it up to the
2149 * higher speed clock.
2154 if (port->type == PORT_XR17V35X) {
2156 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
2157 * MCR [7:5] and MSR [7:0]
2159 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
2162 * Make sure all interrups are masked until initialization is
2163 * complete and the FIFOs are cleared
2165 serial_port_out(port, UART_IER, 0);
2169 * Clear the FIFO buffers and disable them.
2170 * (they will be reenabled in set_termios())
2172 serial8250_clear_fifos(up);
2175 * Clear the interrupt registers.
2177 serial_port_in(port, UART_LSR);
2178 serial_port_in(port, UART_RX);
2179 serial_port_in(port, UART_IIR);
2180 serial_port_in(port, UART_MSR);
2181 if ((port->type == PORT_XR17V35X) || (port->type == PORT_XR17D15X))
2182 serial_port_in(port, UART_EXAR_INT0);
2185 * At this point, there's no way the LSR could still be 0xff;
2186 * if it is, then bail out, because there's likely no UART
2189 if (!(port->flags & UPF_BUGGY_UART) &&
2190 (serial_port_in(port, UART_LSR) == 0xff)) {
2191 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2192 serial_index(port));
2198 * For a XR16C850, we need to set the trigger levels
2200 if (port->type == PORT_16850) {
2203 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2205 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2206 serial_port_out(port, UART_FCTR,
2207 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2208 serial_port_out(port, UART_TRG, UART_TRG_96);
2209 serial_port_out(port, UART_FCTR,
2210 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2211 serial_port_out(port, UART_TRG, UART_TRG_96);
2213 serial_port_out(port, UART_LCR, 0);
2217 * For the Altera 16550 variants, set TX threshold trigger level.
2219 if (((port->type == PORT_ALTR_16550_F32) ||
2220 (port->type == PORT_ALTR_16550_F64) ||
2221 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2222 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2223 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2224 pr_err("ttyS%d TX FIFO Threshold errors, skipping\n",
2225 serial_index(port));
2227 serial_port_out(port, UART_ALTR_AFR,
2228 UART_ALTR_EN_TXFIFO_LW);
2229 serial_port_out(port, UART_ALTR_TX_LOW,
2230 port->fifosize - up->tx_loadsz);
2231 port->handle_irq = serial8250_tx_threshold_handle_irq;
2235 if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2238 * Test for UARTs that do not reassert THRE when the
2239 * transmitter is idle and the interrupt has already
2240 * been cleared. Real 16550s should always reassert
2241 * this interrupt whenever the transmitter is idle and
2242 * the interrupt is enabled. Delays are necessary to
2243 * allow register changes to become visible.
2245 spin_lock_irqsave(&port->lock, flags);
2246 if (up->port.irqflags & IRQF_SHARED)
2247 disable_irq_nosync(port->irq);
2249 wait_for_xmitr(up, UART_LSR_THRE);
2250 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2251 udelay(1); /* allow THRE to set */
2252 iir1 = serial_port_in(port, UART_IIR);
2253 serial_port_out(port, UART_IER, 0);
2254 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2255 udelay(1); /* allow a working UART time to re-assert THRE */
2256 iir = serial_port_in(port, UART_IIR);
2257 serial_port_out(port, UART_IER, 0);
2259 if (port->irqflags & IRQF_SHARED)
2260 enable_irq(port->irq);
2261 spin_unlock_irqrestore(&port->lock, flags);
2264 * If the interrupt is not reasserted, or we otherwise
2265 * don't trust the iir, setup a timer to kick the UART
2266 * on a regular basis.
2268 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2269 up->port.flags & UPF_BUG_THRE) {
2270 up->bugs |= UART_BUG_THRE;
2274 retval = up->ops->setup_irq(up);
2279 * Now, initialize the UART
2281 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2283 spin_lock_irqsave(&port->lock, flags);
2284 if (up->port.flags & UPF_FOURPORT) {
2286 up->port.mctrl |= TIOCM_OUT1;
2289 * Most PC uarts need OUT2 raised to enable interrupts.
2292 up->port.mctrl |= TIOCM_OUT2;
2294 serial8250_set_mctrl(port, port->mctrl);
2297 * Serial over Lan (SoL) hack:
2298 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2299 * used for Serial Over Lan. Those chips take a longer time than a
2300 * normal serial device to signalize that a transmission data was
2301 * queued. Due to that, the above test generally fails. One solution
2302 * would be to delay the reading of iir. However, this is not
2303 * reliable, since the timeout is variable. So, let's just don't
2304 * test if we receive TX irq. This way, we'll never enable
2307 if (up->port.flags & UPF_NO_TXEN_TEST)
2308 goto dont_test_tx_en;
2311 * Do a quick test to see if we receive an interrupt when we enable
2314 serial_port_out(port, UART_IER, UART_IER_THRI);
2315 lsr = serial_port_in(port, UART_LSR);
2316 iir = serial_port_in(port, UART_IIR);
2317 serial_port_out(port, UART_IER, 0);
2319 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2320 if (!(up->bugs & UART_BUG_TXEN)) {
2321 up->bugs |= UART_BUG_TXEN;
2322 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2323 serial_index(port));
2326 up->bugs &= ~UART_BUG_TXEN;
2330 spin_unlock_irqrestore(&port->lock, flags);
2333 * Clear the interrupt registers again for luck, and clear the
2334 * saved flags to avoid getting false values from polling
2335 * routines or the previous session.
2337 serial_port_in(port, UART_LSR);
2338 serial_port_in(port, UART_RX);
2339 serial_port_in(port, UART_IIR);
2340 serial_port_in(port, UART_MSR);
2341 if ((port->type == PORT_XR17V35X) || (port->type == PORT_XR17D15X))
2342 serial_port_in(port, UART_EXAR_INT0);
2343 up->lsr_saved_flags = 0;
2344 up->msr_saved_flags = 0;
2347 * Request DMA channels for both RX and TX.
2350 retval = serial8250_request_dma(up);
2352 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2353 serial_index(port));
2359 * Set the IER shadow for rx interrupts but defer actual interrupt
2360 * enable until after the FIFOs are enabled; otherwise, an already-
2361 * active sender can swamp the interrupt handler with "too much work".
2363 up->ier = UART_IER_RLSI | UART_IER_RDI;
2365 if (port->flags & UPF_FOURPORT) {
2368 * Enable interrupts on the AST Fourport board
2370 icp = (port->iobase & 0xfe0) | 0x01f;
2376 serial8250_rpm_put(up);
2379 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2381 static int serial8250_startup(struct uart_port *port)
2384 return port->startup(port);
2385 return serial8250_do_startup(port);
2388 void serial8250_do_shutdown(struct uart_port *port)
2390 struct uart_8250_port *up = up_to_u8250p(port);
2391 unsigned long flags;
2393 serial8250_rpm_get(up);
2395 * Disable interrupts from this port
2397 spin_lock_irqsave(&port->lock, flags);
2399 serial_port_out(port, UART_IER, 0);
2400 spin_unlock_irqrestore(&port->lock, flags);
2402 synchronize_irq(port->irq);
2405 serial8250_release_dma(up);
2407 spin_lock_irqsave(&port->lock, flags);
2408 if (port->flags & UPF_FOURPORT) {
2409 /* reset interrupts on the AST Fourport board */
2410 inb((port->iobase & 0xfe0) | 0x1f);
2411 port->mctrl |= TIOCM_OUT1;
2413 port->mctrl &= ~TIOCM_OUT2;
2415 serial8250_set_mctrl(port, port->mctrl);
2416 spin_unlock_irqrestore(&port->lock, flags);
2419 * Disable break condition and FIFOs
2421 serial_port_out(port, UART_LCR,
2422 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2423 serial8250_clear_fifos(up);
2425 #ifdef CONFIG_SERIAL_8250_RSA
2427 * Reset the RSA board back to 115kbps compat mode.
2433 * Read data port to reset things, and then unlink from
2436 serial_port_in(port, UART_RX);
2437 serial8250_rpm_put(up);
2439 up->ops->release_irq(up);
2441 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2443 static void serial8250_shutdown(struct uart_port *port)
2446 port->shutdown(port);
2448 serial8250_do_shutdown(port);
2452 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2453 * Calculate divisor with extra 4-bit fractional portion
2455 static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2459 struct uart_port *port = &up->port;
2460 unsigned int quot_16;
2462 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2463 *frac = quot_16 & 0x0f;
2465 return quot_16 >> 4;
2468 static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2472 struct uart_port *port = &up->port;
2476 * Handle magic divisors for baud rates above baud_base on
2477 * SMSC SuperIO chips.
2480 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2481 baud == (port->uartclk/4))
2483 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2484 baud == (port->uartclk/8))
2486 else if (up->port.type == PORT_XR17V35X)
2487 quot = xr17v35x_get_divisor(up, baud, frac);
2489 quot = uart_get_divisor(port, baud);
2492 * Oxford Semi 952 rev B workaround
2494 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2500 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2505 switch (c_cflag & CSIZE) {
2507 cval = UART_LCR_WLEN5;
2510 cval = UART_LCR_WLEN6;
2513 cval = UART_LCR_WLEN7;
2517 cval = UART_LCR_WLEN8;
2521 if (c_cflag & CSTOPB)
2522 cval |= UART_LCR_STOP;
2523 if (c_cflag & PARENB) {
2524 cval |= UART_LCR_PARITY;
2525 if (up->bugs & UART_BUG_PARITY)
2526 up->fifo_bug = true;
2528 if (!(c_cflag & PARODD))
2529 cval |= UART_LCR_EPAR;
2531 if (c_cflag & CMSPAR)
2532 cval |= UART_LCR_SPAR;
2538 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2539 unsigned int quot, unsigned int quot_frac)
2541 struct uart_8250_port *up = up_to_u8250p(port);
2543 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2544 if (is_omap1510_8250(up)) {
2545 if (baud == 115200) {
2547 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2549 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2553 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2554 * otherwise just set DLAB
2556 if (up->capabilities & UART_NATSEMI)
2557 serial_port_out(port, UART_LCR, 0xe0);
2559 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2561 serial_dl_write(up, quot);
2563 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2564 if (up->port.type == PORT_XR17V35X)
2565 serial_port_out(port, 0x2, quot_frac);
2568 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2569 struct ktermios *termios,
2570 struct ktermios *old)
2573 * Ask the core to calculate the divisor for us.
2574 * Allow 1% tolerance at the upper limit so uart clks marginally
2575 * slower than nominal still match standard baud rates without
2576 * causing transmission errors.
2578 return uart_get_baud_rate(port, termios, old,
2579 port->uartclk / 16 / 0xffff,
2584 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2585 struct ktermios *old)
2587 struct uart_8250_port *up = up_to_u8250p(port);
2589 unsigned long flags;
2590 unsigned int baud, quot, frac = 0;
2592 if (up->capabilities & UART_CAP_MINI) {
2593 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2594 if ((termios->c_cflag & CSIZE) == CS5 ||
2595 (termios->c_cflag & CSIZE) == CS6)
2596 termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2598 cval = serial8250_compute_lcr(up, termios->c_cflag);
2600 baud = serial8250_get_baud_rate(port, termios, old);
2601 quot = serial8250_get_divisor(up, baud, &frac);
2604 * Ok, we're now changing the port state. Do it with
2605 * interrupts disabled.
2607 serial8250_rpm_get(up);
2608 spin_lock_irqsave(&port->lock, flags);
2610 up->lcr = cval; /* Save computed LCR */
2612 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2613 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2614 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2615 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2616 up->fcr |= UART_FCR_TRIGGER_1;
2621 * MCR-based auto flow control. When AFE is enabled, RTS will be
2622 * deasserted when the receive FIFO contains more characters than
2623 * the trigger, or the MCR RTS bit is cleared.
2625 if (up->capabilities & UART_CAP_AFE) {
2626 up->mcr &= ~UART_MCR_AFE;
2627 if (termios->c_cflag & CRTSCTS)
2628 up->mcr |= UART_MCR_AFE;
2632 * Update the per-port timeout.
2634 uart_update_timeout(port, termios->c_cflag, baud);
2636 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2637 if (termios->c_iflag & INPCK)
2638 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2639 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2640 port->read_status_mask |= UART_LSR_BI;
2643 * Characteres to ignore
2645 port->ignore_status_mask = 0;
2646 if (termios->c_iflag & IGNPAR)
2647 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2648 if (termios->c_iflag & IGNBRK) {
2649 port->ignore_status_mask |= UART_LSR_BI;
2651 * If we're ignoring parity and break indicators,
2652 * ignore overruns too (for real raw support).
2654 if (termios->c_iflag & IGNPAR)
2655 port->ignore_status_mask |= UART_LSR_OE;
2659 * ignore all characters if CREAD is not set
2661 if ((termios->c_cflag & CREAD) == 0)
2662 port->ignore_status_mask |= UART_LSR_DR;
2665 * CTS flow control flag and modem status interrupts
2667 up->ier &= ~UART_IER_MSI;
2668 if (!(up->bugs & UART_BUG_NOMSR) &&
2669 UART_ENABLE_MS(&up->port, termios->c_cflag))
2670 up->ier |= UART_IER_MSI;
2671 if (up->capabilities & UART_CAP_UUE)
2672 up->ier |= UART_IER_UUE;
2673 if (up->capabilities & UART_CAP_RTOIE)
2674 up->ier |= UART_IER_RTOIE;
2676 serial_port_out(port, UART_IER, up->ier);
2678 if (up->capabilities & UART_CAP_EFR) {
2679 unsigned char efr = 0;
2681 * TI16C752/Startech hardware flow control. FIXME:
2682 * - TI16C752 requires control thresholds to be set.
2683 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2685 if (termios->c_cflag & CRTSCTS)
2686 efr |= UART_EFR_CTS;
2688 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2689 if (port->flags & UPF_EXAR_EFR)
2690 serial_port_out(port, UART_XR_EFR, efr);
2692 serial_port_out(port, UART_EFR, efr);
2695 serial8250_set_divisor(port, baud, quot, frac);
2698 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2699 * is written without DLAB set, this mode will be disabled.
2701 if (port->type == PORT_16750)
2702 serial_port_out(port, UART_FCR, up->fcr);
2704 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2705 if (port->type != PORT_16750) {
2706 /* emulated UARTs (Lucent Venus 167x) need two steps */
2707 if (up->fcr & UART_FCR_ENABLE_FIFO)
2708 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2709 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2711 serial8250_set_mctrl(port, port->mctrl);
2712 spin_unlock_irqrestore(&port->lock, flags);
2713 serial8250_rpm_put(up);
2715 /* Don't rewrite B0 */
2716 if (tty_termios_baud_rate(termios))
2717 tty_termios_encode_baud_rate(termios, baud, baud);
2719 EXPORT_SYMBOL(serial8250_do_set_termios);
2722 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2723 struct ktermios *old)
2725 if (port->set_termios)
2726 port->set_termios(port, termios, old);
2728 serial8250_do_set_termios(port, termios, old);
2731 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2733 if (termios->c_line == N_PPS) {
2734 port->flags |= UPF_HARDPPS_CD;
2735 spin_lock_irq(&port->lock);
2736 serial8250_enable_ms(port);
2737 spin_unlock_irq(&port->lock);
2739 port->flags &= ~UPF_HARDPPS_CD;
2740 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2741 spin_lock_irq(&port->lock);
2742 serial8250_disable_ms(port);
2743 spin_unlock_irq(&port->lock);
2747 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2750 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2752 if (port->set_ldisc)
2753 port->set_ldisc(port, termios);
2755 serial8250_do_set_ldisc(port, termios);
2758 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2759 unsigned int oldstate)
2761 struct uart_8250_port *p = up_to_u8250p(port);
2763 serial8250_set_sleep(p, state != 0);
2765 EXPORT_SYMBOL(serial8250_do_pm);
2768 serial8250_pm(struct uart_port *port, unsigned int state,
2769 unsigned int oldstate)
2772 port->pm(port, state, oldstate);
2774 serial8250_do_pm(port, state, oldstate);
2777 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2779 if (pt->port.mapsize)
2780 return pt->port.mapsize;
2781 if (pt->port.iotype == UPIO_AU) {
2782 if (pt->port.type == PORT_RT2880)
2786 if (is_omap1_8250(pt))
2787 return 0x16 << pt->port.regshift;
2789 return 8 << pt->port.regshift;
2793 * Resource handling.
2795 static int serial8250_request_std_resource(struct uart_8250_port *up)
2797 unsigned int size = serial8250_port_size(up);
2798 struct uart_port *port = &up->port;
2801 switch (port->iotype) {
2811 if (!request_mem_region(port->mapbase, size, "serial")) {
2816 if (port->flags & UPF_IOREMAP) {
2817 port->membase = ioremap_nocache(port->mapbase, size);
2818 if (!port->membase) {
2819 release_mem_region(port->mapbase, size);
2827 if (!request_region(port->iobase, size, "serial"))
2834 static void serial8250_release_std_resource(struct uart_8250_port *up)
2836 unsigned int size = serial8250_port_size(up);
2837 struct uart_port *port = &up->port;
2839 switch (port->iotype) {
2849 if (port->flags & UPF_IOREMAP) {
2850 iounmap(port->membase);
2851 port->membase = NULL;
2854 release_mem_region(port->mapbase, size);
2859 release_region(port->iobase, size);
2864 static void serial8250_release_port(struct uart_port *port)
2866 struct uart_8250_port *up = up_to_u8250p(port);
2868 serial8250_release_std_resource(up);
2871 static int serial8250_request_port(struct uart_port *port)
2873 struct uart_8250_port *up = up_to_u8250p(port);
2875 return serial8250_request_std_resource(up);
2878 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2880 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2881 unsigned char bytes;
2883 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2885 return bytes ? bytes : -EOPNOTSUPP;
2888 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2890 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2893 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2896 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2897 if (bytes < conf_type->rxtrig_bytes[i])
2898 /* Use the nearest lower value */
2899 return (--i) << UART_FCR_R_TRIG_SHIFT;
2902 return UART_FCR_R_TRIG_11;
2905 static int do_get_rxtrig(struct tty_port *port)
2907 struct uart_state *state = container_of(port, struct uart_state, port);
2908 struct uart_port *uport = state->uart_port;
2909 struct uart_8250_port *up = up_to_u8250p(uport);
2911 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2914 return fcr_get_rxtrig_bytes(up);
2917 static int do_serial8250_get_rxtrig(struct tty_port *port)
2921 mutex_lock(&port->mutex);
2922 rxtrig_bytes = do_get_rxtrig(port);
2923 mutex_unlock(&port->mutex);
2925 return rxtrig_bytes;
2928 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2929 struct device_attribute *attr, char *buf)
2931 struct tty_port *port = dev_get_drvdata(dev);
2934 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2935 if (rxtrig_bytes < 0)
2936 return rxtrig_bytes;
2938 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2941 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2943 struct uart_state *state = container_of(port, struct uart_state, port);
2944 struct uart_port *uport = state->uart_port;
2945 struct uart_8250_port *up = up_to_u8250p(uport);
2948 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2952 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2956 serial8250_clear_fifos(up);
2957 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2958 up->fcr |= (unsigned char)rxtrig;
2959 serial_out(up, UART_FCR, up->fcr);
2963 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2967 mutex_lock(&port->mutex);
2968 ret = do_set_rxtrig(port, bytes);
2969 mutex_unlock(&port->mutex);
2974 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2975 struct device_attribute *attr, const char *buf, size_t count)
2977 struct tty_port *port = dev_get_drvdata(dev);
2978 unsigned char bytes;
2984 ret = kstrtou8(buf, 10, &bytes);
2988 ret = do_serial8250_set_rxtrig(port, bytes);
2995 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2996 serial8250_get_attr_rx_trig_bytes,
2997 serial8250_set_attr_rx_trig_bytes);
2999 static struct attribute *serial8250_dev_attrs[] = {
3000 &dev_attr_rx_trig_bytes.attr,
3004 static struct attribute_group serial8250_dev_attr_group = {
3005 .attrs = serial8250_dev_attrs,
3008 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3010 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3012 if (conf_type->rxtrig_bytes[0])
3013 up->port.attr_group = &serial8250_dev_attr_group;
3016 static void serial8250_config_port(struct uart_port *port, int flags)
3018 struct uart_8250_port *up = up_to_u8250p(port);
3022 * Find the region that we can probe for. This in turn
3023 * tells us whether we can probe for the type of port.
3025 ret = serial8250_request_std_resource(up);
3029 if (port->iotype != up->cur_iotype)
3030 set_io_from_upio(port);
3032 if (flags & UART_CONFIG_TYPE)
3035 /* if access method is AU, it is a 16550 with a quirk */
3036 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3037 up->bugs |= UART_BUG_NOMSR;
3039 /* HW bugs may trigger IRQ while IIR == NO_INT */
3040 if (port->type == PORT_TEGRA)
3041 up->bugs |= UART_BUG_NOMSR;
3043 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3046 if (port->type == PORT_UNKNOWN)
3047 serial8250_release_std_resource(up);
3049 /* Fixme: probably not the best place for this */
3050 if ((port->type == PORT_XR17V35X) ||
3051 (port->type == PORT_XR17D15X))
3052 port->handle_irq = exar_handle_irq;
3054 register_dev_spec_attr_grp(up);
3055 up->fcr = uart_config[up->port.type].fcr;
3059 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3061 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3062 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3063 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3064 ser->type == PORT_STARTECH)
3069 static const char *serial8250_type(struct uart_port *port)
3071 int type = port->type;
3073 if (type >= ARRAY_SIZE(uart_config))
3075 return uart_config[type].name;
3078 static const struct uart_ops serial8250_pops = {
3079 .tx_empty = serial8250_tx_empty,
3080 .set_mctrl = serial8250_set_mctrl,
3081 .get_mctrl = serial8250_get_mctrl,
3082 .stop_tx = serial8250_stop_tx,
3083 .start_tx = serial8250_start_tx,
3084 .throttle = serial8250_throttle,
3085 .unthrottle = serial8250_unthrottle,
3086 .stop_rx = serial8250_stop_rx,
3087 .enable_ms = serial8250_enable_ms,
3088 .break_ctl = serial8250_break_ctl,
3089 .startup = serial8250_startup,
3090 .shutdown = serial8250_shutdown,
3091 .set_termios = serial8250_set_termios,
3092 .set_ldisc = serial8250_set_ldisc,
3093 .pm = serial8250_pm,
3094 .type = serial8250_type,
3095 .release_port = serial8250_release_port,
3096 .request_port = serial8250_request_port,
3097 .config_port = serial8250_config_port,
3098 .verify_port = serial8250_verify_port,
3099 #ifdef CONFIG_CONSOLE_POLL
3100 .poll_get_char = serial8250_get_poll_char,
3101 .poll_put_char = serial8250_put_poll_char,
3105 void serial8250_init_port(struct uart_8250_port *up)
3107 struct uart_port *port = &up->port;
3109 spin_lock_init(&port->lock);
3110 port->ops = &serial8250_pops;
3112 up->cur_iotype = 0xFF;
3114 EXPORT_SYMBOL_GPL(serial8250_init_port);
3116 void serial8250_set_defaults(struct uart_8250_port *up)
3118 struct uart_port *port = &up->port;
3120 if (up->port.flags & UPF_FIXED_TYPE) {
3121 unsigned int type = up->port.type;
3123 if (!up->port.fifosize)
3124 up->port.fifosize = uart_config[type].fifo_size;
3126 up->tx_loadsz = uart_config[type].tx_loadsz;
3127 if (!up->capabilities)
3128 up->capabilities = uart_config[type].flags;
3131 set_io_from_upio(port);
3133 /* default dma handlers */
3135 if (!up->dma->tx_dma)
3136 up->dma->tx_dma = serial8250_tx_dma;
3137 if (!up->dma->rx_dma)
3138 up->dma->rx_dma = serial8250_rx_dma;
3141 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3143 #ifdef CONFIG_SERIAL_8250_CONSOLE
3145 static void serial8250_console_putchar(struct uart_port *port, int ch)
3147 struct uart_8250_port *up = up_to_u8250p(port);
3149 wait_for_xmitr(up, UART_LSR_THRE);
3150 serial_port_out(port, UART_TX, ch);
3154 * Restore serial console when h/w power-off detected
3156 static void serial8250_console_restore(struct uart_8250_port *up)
3158 struct uart_port *port = &up->port;
3159 struct ktermios termios;
3160 unsigned int baud, quot, frac = 0;
3162 termios.c_cflag = port->cons->cflag;
3163 if (port->state->port.tty && termios.c_cflag == 0)
3164 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3166 baud = serial8250_get_baud_rate(port, &termios, NULL);
3167 quot = serial8250_get_divisor(up, baud, &frac);
3169 serial8250_set_divisor(port, baud, quot, frac);
3170 serial_port_out(port, UART_LCR, up->lcr);
3171 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
3175 * Print a string to the serial port trying not to disturb
3176 * any possible real use of the port...
3178 * The console_lock must be held when we get here.
3180 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3183 struct uart_port *port = &up->port;
3184 unsigned long flags;
3188 touch_nmi_watchdog();
3190 serial8250_rpm_get(up);
3194 else if (oops_in_progress)
3195 locked = spin_trylock_irqsave(&port->lock, flags);
3197 spin_lock_irqsave(&port->lock, flags);
3200 * First save the IER then disable the interrupts
3202 ier = serial_port_in(port, UART_IER);
3204 if (up->capabilities & UART_CAP_UUE)
3205 serial_port_out(port, UART_IER, UART_IER_UUE);
3207 serial_port_out(port, UART_IER, 0);
3209 /* check scratch reg to see if port powered off during system sleep */
3210 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3211 serial8250_console_restore(up);
3215 uart_console_write(port, s, count, serial8250_console_putchar);
3218 * Finally, wait for transmitter to become empty
3219 * and restore the IER
3221 wait_for_xmitr(up, BOTH_EMPTY);
3222 serial_port_out(port, UART_IER, ier);
3225 * The receive handling will happen properly because the
3226 * receive ready bit will still be set; it is not cleared
3227 * on read. However, modem control will not, we must
3228 * call it if we have saved something in the saved flags
3229 * while processing with interrupts off.
3231 if (up->msr_saved_flags)
3232 serial8250_modem_status(up);
3235 spin_unlock_irqrestore(&port->lock, flags);
3236 serial8250_rpm_put(up);
3239 static unsigned int probe_baud(struct uart_port *port)
3241 unsigned char lcr, dll, dlm;
3244 lcr = serial_port_in(port, UART_LCR);
3245 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3246 dll = serial_port_in(port, UART_DLL);
3247 dlm = serial_port_in(port, UART_DLM);
3248 serial_port_out(port, UART_LCR, lcr);
3250 quot = (dlm << 8) | dll;
3251 return (port->uartclk / 16) / quot;
3254 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3261 if (!port->iobase && !port->membase)
3265 uart_parse_options(options, &baud, &parity, &bits, &flow);
3267 baud = probe_baud(port);
3269 return uart_set_options(port, port->cons, baud, parity, bits, flow);
3272 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3274 MODULE_LICENSE("GPL");