drivers/tty/serial/omap-serial.c

   1 /*
   2  * Driver for OMAP-UART controller.
   3  * Based on drivers/serial/8250.c
   4  *
   5  * Copyright (C) 2010 Texas Instruments.
   6  *
   7  * Authors:
   8  *      Govindraj R     <govindraj.raja@ti.com>
   9  *      Thara Gopinath  <thara@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * Note: This driver is made separate from 8250 driver as we cannot
  17  * over load 8250 driver with omap platform specific configuration for
  18  * features like DMA, it makes easier to implement features like DMA and
  19  * hardware flow control and software flow control configuration with
  20  * this driver as required for the omap-platform.
  21  */
  22
  23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  24 #define SUPPORT_SYSRQ
  25 #endif
  26
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/console.h>
  30 #include <linux/serial_reg.h>
  31 #include <linux/delay.h>
  32 #include <linux/slab.h>
  33 #include <linux/tty.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/io.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/clk.h>
  38 #include <linux/serial_core.h>
  39 #include <linux/irq.h>
  40 #include <linux/pm_runtime.h>
  41 #include <linux/of.h>
  42
  43 #include <plat/dma.h>
  44 #include <plat/dmtimer.h>
  45 #include <plat/omap-serial.h>
  46
  47 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
  48
  49 /* SCR register bitmasks */
  50 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK               (1 << 7)
  51
  52 /* FCR register bitmasks */
  53 #define OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT                6
  54 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK                 (0x3 << 6)
  55
  56 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
  57
  58 /* Forward declaration of functions */
  59 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
  60 static void serial_omap_rxdma_poll(unsigned long uart_no);
  61 static int serial_omap_start_rxdma(struct uart_omap_port *up);
  62 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
  63
  64 static struct workqueue_struct *serial_omap_uart_wq;
  65
  66 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
  67 {
  68         offset <<= up->port.regshift;
  69         return readw(up->port.membase + offset);
  70 }
  71
  72 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
  73 {
  74         offset <<= up->port.regshift;
  75         writew(value, up->port.membase + offset);
  76 }
  77
  78 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
  79 {
  80         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
  81         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
  82                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
  83         serial_out(up, UART_FCR, 0);
  84 }
  85
  86 /*
  87  * serial_omap_get_divisor - calculate divisor value
  88  * @port: uart port info
  89  * @baud: baudrate for which divisor needs to be calculated.
  90  *
  91  * We have written our own function to get the divisor so as to support
  92  * 13x mode. 3Mbps Baudrate as an different divisor.
  93  * Reference OMAP TRM Chapter 17:
  94  * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
  95  * referring to oversampling - divisor value
  96  * baudrate 460,800 to 3,686,400 all have divisor 13
  97  * except 3,000,000 which has divisor value 16
  98  */
  99 static unsigned int
 100 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
 101 {
 102         unsigned int divisor;
 103
 104         if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
 105                 divisor = 13;
 106         else
 107                 divisor = 16;
 108         return port->uartclk/(baud * divisor);
 109 }
 110
 111 static void serial_omap_stop_rxdma(struct uart_omap_port *up)
 112 {
 113         if (up->uart_dma.rx_dma_used) {
 114                 del_timer(&up->uart_dma.rx_timer);
 115                 omap_stop_dma(up->uart_dma.rx_dma_channel);
 116                 omap_free_dma(up->uart_dma.rx_dma_channel);
 117                 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
 118                 up->uart_dma.rx_dma_used = false;
 119                 pm_runtime_mark_last_busy(&up->pdev->dev);
 120                 pm_runtime_put_autosuspend(&up->pdev->dev);
 121         }
 122 }
 123
 124 static void serial_omap_enable_ms(struct uart_port *port)
 125 {
 126         struct uart_omap_port *up = (struct uart_omap_port *)port;
 127
 128         dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 129
 130         pm_runtime_get_sync(&up->pdev->dev);
 131         up->ier |= UART_IER_MSI;
 132         serial_out(up, UART_IER, up->ier);
 133         pm_runtime_put(&up->pdev->dev);
 134 }
 135
 136 static void serial_omap_stop_tx(struct uart_port *port)
 137 {
 138         struct uart_omap_port *up = (struct uart_omap_port *)port;
 139
 140         if (up->use_dma &&
 141                 up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) {
 142                 /*
 143                  * Check if dma is still active. If yes do nothing,
 144                  * return. Else stop dma
 145                  */
 146                 if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel))
 147                         return;
 148                 omap_stop_dma(up->uart_dma.tx_dma_channel);
 149                 omap_free_dma(up->uart_dma.tx_dma_channel);
 150                 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
 151                 pm_runtime_mark_last_busy(&up->pdev->dev);
 152                 pm_runtime_put_autosuspend(&up->pdev->dev);
 153         }
 154
 155         pm_runtime_get_sync(&up->pdev->dev);
 156         if (up->ier & UART_IER_THRI) {
 157                 up->ier &= ~UART_IER_THRI;
 158                 serial_out(up, UART_IER, up->ier);
 159         }
 160
 161         pm_runtime_mark_last_busy(&up->pdev->dev);
 162         pm_runtime_put_autosuspend(&up->pdev->dev);
 163 }
 164
 165 static void serial_omap_stop_rx(struct uart_port *port)
 166 {
 167         struct uart_omap_port *up = (struct uart_omap_port *)port;
 168
 169         pm_runtime_get_sync(&up->pdev->dev);
 170         if (up->use_dma)
 171                 serial_omap_stop_rxdma(up);
 172         up->ier &= ~UART_IER_RLSI;
 173         up->port.read_status_mask &= ~UART_LSR_DR;
 174         serial_out(up, UART_IER, up->ier);
 175         pm_runtime_mark_last_busy(&up->pdev->dev);
 176         pm_runtime_put_autosuspend(&up->pdev->dev);
 177 }
 178
 179 static inline void receive_chars(struct uart_omap_port *up,
 180                 unsigned int *status)
 181 {
 182         struct tty_struct *tty = up->port.state->port.tty;
 183         unsigned int flag, lsr = *status;
 184         unsigned char ch = 0;
 185         int max_count = 256;
 186
 187         do {
 188                 if (likely(lsr & UART_LSR_DR))
 189                         ch = serial_in(up, UART_RX);
 190                 flag = TTY_NORMAL;
 191                 up->port.icount.rx++;
 192
 193                 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
 194                         /*
 195                          * For statistics only
 196                          */
 197                         if (lsr & UART_LSR_BI) {
 198                                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
 199                                 up->port.icount.brk++;
 200                                 /*
 201                                  * We do the SysRQ and SAK checking
 202                                  * here because otherwise the break
 203                                  * may get masked by ignore_status_mask
 204                                  * or read_status_mask.
 205                                  */
 206                                 if (uart_handle_break(&up->port))
 207                                         goto ignore_char;
 208                         } else if (lsr & UART_LSR_PE) {
 209                                 up->port.icount.parity++;
 210                         } else if (lsr & UART_LSR_FE) {
 211                                 up->port.icount.frame++;
 212                         }
 213
 214                         if (lsr & UART_LSR_OE)
 215                                 up->port.icount.overrun++;
 216
 217                         /*
 218                          * Mask off conditions which should be ignored.
 219                          */
 220                         lsr &= up->port.read_status_mask;
 221
 222 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
 223                         if (up->port.line == up->port.cons->index) {
 224                                 /* Recover the break flag from console xmit */
 225                                 lsr |= up->lsr_break_flag;
 226                         }
 227 #endif
 228                         if (lsr & UART_LSR_BI)
 229                                 flag = TTY_BREAK;
 230                         else if (lsr & UART_LSR_PE)
 231                                 flag = TTY_PARITY;
 232                         else if (lsr & UART_LSR_FE)
 233                                 flag = TTY_FRAME;
 234                 }
 235
 236                 if (uart_handle_sysrq_char(&up->port, ch))
 237                         goto ignore_char;
 238                 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
 239 ignore_char:
 240                 lsr = serial_in(up, UART_LSR);
 241         } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
 242         spin_unlock(&up->port.lock);
 243         tty_flip_buffer_push(tty);
 244         spin_lock(&up->port.lock);
 245 }
 246
 247 static void transmit_chars(struct uart_omap_port *up)
 248 {
 249         struct circ_buf *xmit = &up->port.state->xmit;
 250         int count;
 251
 252         if (up->port.x_char) {
 253                 serial_out(up, UART_TX, up->port.x_char);
 254                 up->port.icount.tx++;
 255                 up->port.x_char = 0;
 256                 return;
 257         }
 258         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 259                 serial_omap_stop_tx(&up->port);
 260                 return;
 261         }
 262         count = up->port.fifosize / 4;
 263         do {
 264                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 265                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 266                 up->port.icount.tx++;
 267                 if (uart_circ_empty(xmit))
 268                         break;
 269         } while (--count > 0);
 270
 271         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 272                 uart_write_wakeup(&up->port);
 273
 274         if (uart_circ_empty(xmit))
 275                 serial_omap_stop_tx(&up->port);
 276 }
 277
 278 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 279 {
 280         if (!(up->ier & UART_IER_THRI)) {
 281                 up->ier |= UART_IER_THRI;
 282                 serial_out(up, UART_IER, up->ier);
 283         }
 284 }
 285
 286 static void serial_omap_start_tx(struct uart_port *port)
 287 {
 288         struct uart_omap_port *up = (struct uart_omap_port *)port;
 289         struct circ_buf *xmit;
 290         unsigned int start;
 291         int ret = 0;
 292
 293         if (!up->use_dma) {
 294                 pm_runtime_get_sync(&up->pdev->dev);
 295                 serial_omap_enable_ier_thri(up);
 296                 pm_runtime_mark_last_busy(&up->pdev->dev);
 297                 pm_runtime_put_autosuspend(&up->pdev->dev);
 298                 return;
 299         }
 300
 301         if (up->uart_dma.tx_dma_used)
 302                 return;
 303
 304         xmit = &up->port.state->xmit;
 305
 306         if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
 307                 pm_runtime_get_sync(&up->pdev->dev);
 308                 ret = omap_request_dma(up->uart_dma.uart_dma_tx,
 309                                 "UART Tx DMA",
 310                                 (void *)uart_tx_dma_callback, up,
 311                                 &(up->uart_dma.tx_dma_channel));
 312
 313                 if (ret < 0) {
 314                         serial_omap_enable_ier_thri(up);
 315                         return;
 316                 }
 317         }
 318         spin_lock(&(up->uart_dma.tx_lock));
 319         up->uart_dma.tx_dma_used = true;
 320         spin_unlock(&(up->uart_dma.tx_lock));
 321
 322         start = up->uart_dma.tx_buf_dma_phys +
 323                                 (xmit->tail & (UART_XMIT_SIZE - 1));
 324
 325         up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
 326         /*
 327          * It is a circular buffer. See if the buffer has wounded back.
 328          * If yes it will have to be transferred in two separate dma
 329          * transfers
 330          */
 331         if (start + up->uart_dma.tx_buf_size >=
 332                         up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
 333                 up->uart_dma.tx_buf_size =
 334                         (up->uart_dma.tx_buf_dma_phys +
 335                         UART_XMIT_SIZE) - start;
 336
 337         omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
 338                                 OMAP_DMA_AMODE_CONSTANT,
 339                                 up->uart_dma.uart_base, 0, 0);
 340         omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
 341                                 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
 342         omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
 343                                 OMAP_DMA_DATA_TYPE_S8,
 344                                 up->uart_dma.tx_buf_size, 1,
 345                                 OMAP_DMA_SYNC_ELEMENT,
 346                                 up->uart_dma.uart_dma_tx, 0);
 347         /* FIXME: Cache maintenance needed here? */
 348         omap_start_dma(up->uart_dma.tx_dma_channel);
 349 }
 350
 351 static unsigned int check_modem_status(struct uart_omap_port *up)
 352 {
 353         unsigned int status;
 354
 355         status = serial_in(up, UART_MSR);
 356         status |= up->msr_saved_flags;
 357         up->msr_saved_flags = 0;
 358         if ((status & UART_MSR_ANY_DELTA) == 0)
 359                 return status;
 360
 361         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
 362             up->port.state != NULL) {
 363                 if (status & UART_MSR_TERI)
 364                         up->port.icount.rng++;
 365                 if (status & UART_MSR_DDSR)
 366                         up->port.icount.dsr++;
 367                 if (status & UART_MSR_DDCD)
 368                         uart_handle_dcd_change
 369                                 (&up->port, status & UART_MSR_DCD);
 370                 if (status & UART_MSR_DCTS)
 371                         uart_handle_cts_change
 372                                 (&up->port, status & UART_MSR_CTS);
 373                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 374         }
 375
 376         return status;
 377 }
 378
 379 /**
 380  * serial_omap_irq() - This handles the interrupt from one port
 381  * @irq: uart port irq number
 382  * @dev_id: uart port info
 383  */
 384 static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 385 {
 386         struct uart_omap_port *up = dev_id;
 387         unsigned int iir, lsr;
 388         unsigned long flags;
 389
 390         pm_runtime_get_sync(&up->pdev->dev);
 391         iir = serial_in(up, UART_IIR);
 392         if (iir & UART_IIR_NO_INT) {
 393                 pm_runtime_mark_last_busy(&up->pdev->dev);
 394                 pm_runtime_put_autosuspend(&up->pdev->dev);
 395                 return IRQ_NONE;
 396         }
 397
 398         spin_lock_irqsave(&up->port.lock, flags);
 399         lsr = serial_in(up, UART_LSR);
 400         if (iir & UART_IIR_RLSI) {
 401                 if (!up->use_dma) {
 402                         if (lsr & UART_LSR_DR)
 403                                 receive_chars(up, &lsr);
 404                 } else {
 405                         up->ier &= ~(UART_IER_RDI | UART_IER_RLSI);
 406                         serial_out(up, UART_IER, up->ier);
 407                         if ((serial_omap_start_rxdma(up) != 0) &&
 408                                         (lsr & UART_LSR_DR))
 409                                 receive_chars(up, &lsr);
 410                 }
 411         }
 412
 413         check_modem_status(up);
 414         if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI))
 415                 transmit_chars(up);
 416
 417         spin_unlock_irqrestore(&up->port.lock, flags);
 418         pm_runtime_mark_last_busy(&up->pdev->dev);
 419         pm_runtime_put_autosuspend(&up->pdev->dev);
 420
 421         up->port_activity = jiffies;
 422         return IRQ_HANDLED;
 423 }
 424
 425 static unsigned int serial_omap_tx_empty(struct uart_port *port)
 426 {
 427         struct uart_omap_port *up = (struct uart_omap_port *)port;
 428         unsigned long flags = 0;
 429         unsigned int ret = 0;
 430
 431         pm_runtime_get_sync(&up->pdev->dev);
 432         dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
 433         spin_lock_irqsave(&up->port.lock, flags);
 434         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 435         spin_unlock_irqrestore(&up->port.lock, flags);
 436         pm_runtime_put(&up->pdev->dev);
 437         return ret;
 438 }
 439
 440 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 441 {
 442         struct uart_omap_port *up = (struct uart_omap_port *)port;
 443         unsigned int status;
 444         unsigned int ret = 0;
 445
 446         pm_runtime_get_sync(&up->pdev->dev);
 447         status = check_modem_status(up);
 448         pm_runtime_put(&up->pdev->dev);
 449
 450         dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 451
 452         if (status & UART_MSR_DCD)
 453                 ret |= TIOCM_CAR;
 454         if (status & UART_MSR_RI)
 455                 ret |= TIOCM_RNG;
 456         if (status & UART_MSR_DSR)
 457                 ret |= TIOCM_DSR;
 458         if (status & UART_MSR_CTS)
 459                 ret |= TIOCM_CTS;
 460         return ret;
 461 }
 462
 463 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 464 {
 465         struct uart_omap_port *up = (struct uart_omap_port *)port;
 466         unsigned char mcr = 0;
 467
 468         dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
 469         if (mctrl & TIOCM_RTS)
 470                 mcr |= UART_MCR_RTS;
 471         if (mctrl & TIOCM_DTR)
 472                 mcr |= UART_MCR_DTR;
 473         if (mctrl & TIOCM_OUT1)
 474                 mcr |= UART_MCR_OUT1;
 475         if (mctrl & TIOCM_OUT2)
 476                 mcr |= UART_MCR_OUT2;
 477         if (mctrl & TIOCM_LOOP)
 478                 mcr |= UART_MCR_LOOP;
 479
 480         pm_runtime_get_sync(&up->pdev->dev);
 481         up->mcr = serial_in(up, UART_MCR);
 482         up->mcr |= mcr;
 483         serial_out(up, UART_MCR, up->mcr);
 484         pm_runtime_put(&up->pdev->dev);
 485 }
 486
 487 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 488 {
 489         struct uart_omap_port *up = (struct uart_omap_port *)port;
 490         unsigned long flags = 0;
 491
 492         dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
 493         pm_runtime_get_sync(&up->pdev->dev);
 494         spin_lock_irqsave(&up->port.lock, flags);
 495         if (break_state == -1)
 496                 up->lcr |= UART_LCR_SBC;
 497         else
 498                 up->lcr &= ~UART_LCR_SBC;
 499         serial_out(up, UART_LCR, up->lcr);
 500         spin_unlock_irqrestore(&up->port.lock, flags);
 501         pm_runtime_put(&up->pdev->dev);
 502 }
 503
 504 static int serial_omap_startup(struct uart_port *port)
 505 {
 506         struct uart_omap_port *up = (struct uart_omap_port *)port;
 507         unsigned long flags = 0;
 508         int retval;
 509
 510         /*
 511          * Allocate the IRQ
 512          */
 513         retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
 514                                 up->name, up);
 515         if (retval)
 516                 return retval;
 517
 518         dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
 519
 520         pm_runtime_get_sync(&up->pdev->dev);
 521         /*
 522          * Clear the FIFO buffers and disable them.
 523          * (they will be reenabled in set_termios())
 524          */
 525         serial_omap_clear_fifos(up);
 526         /* For Hardware flow control */
 527         serial_out(up, UART_MCR, UART_MCR_RTS);
 528
 529         /*
 530          * Clear the interrupt registers.
 531          */
 532         (void) serial_in(up, UART_LSR);
 533         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 534                 (void) serial_in(up, UART_RX);
 535         (void) serial_in(up, UART_IIR);
 536         (void) serial_in(up, UART_MSR);
 537
 538         /*
 539          * Now, initialize the UART
 540          */
 541         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 542         spin_lock_irqsave(&up->port.lock, flags);
 543         /*
 544          * Most PC uarts need OUT2 raised to enable interrupts.
 545          */
 546         up->port.mctrl |= TIOCM_OUT2;
 547         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 548         spin_unlock_irqrestore(&up->port.lock, flags);
 549
 550         up->msr_saved_flags = 0;
 551         if (up->use_dma) {
 552                 free_page((unsigned long)up->port.state->xmit.buf);
 553                 up->port.state->xmit.buf = dma_alloc_coherent(NULL,
 554                         UART_XMIT_SIZE,
 555                         (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
 556                         0);
 557                 init_timer(&(up->uart_dma.rx_timer));
 558                 up->uart_dma.rx_timer.function = serial_omap_rxdma_poll;
 559                 up->uart_dma.rx_timer.data = up->port.line;
 560                 /* Currently the buffer size is 4KB. Can increase it */
 561                 up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
 562                         up->uart_dma.rx_buf_size,
 563                         (dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0);
 564         }
 565         /*
 566          * Finally, enable interrupts. Note: Modem status interrupts
 567          * are set via set_termios(), which will be occurring imminently
 568          * anyway, so we don't enable them here.
 569          */
 570         up->ier = UART_IER_RLSI | UART_IER_RDI;
 571         serial_out(up, UART_IER, up->ier);
 572
 573         /* Enable module level wake up */
 574         serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
 575
 576         pm_runtime_mark_last_busy(&up->pdev->dev);
 577         pm_runtime_put_autosuspend(&up->pdev->dev);
 578         up->port_activity = jiffies;
 579         return 0;
 580 }
 581
 582 static void serial_omap_shutdown(struct uart_port *port)
 583 {
 584         struct uart_omap_port *up = (struct uart_omap_port *)port;
 585         unsigned long flags = 0;
 586
 587         dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
 588
 589         pm_runtime_get_sync(&up->pdev->dev);
 590         /*
 591          * Disable interrupts from this port
 592          */
 593         up->ier = 0;
 594         serial_out(up, UART_IER, 0);
 595
 596         spin_lock_irqsave(&up->port.lock, flags);
 597         up->port.mctrl &= ~TIOCM_OUT2;
 598         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 599         spin_unlock_irqrestore(&up->port.lock, flags);
 600
 601         /*
 602          * Disable break condition and FIFOs
 603          */
 604         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 605         serial_omap_clear_fifos(up);
 606
 607         /*
 608          * Read data port to reset things, and then free the irq
 609          */
 610         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 611                 (void) serial_in(up, UART_RX);
 612         if (up->use_dma) {
 613                 dma_free_coherent(up->port.dev,
 614                         UART_XMIT_SIZE, up->port.state->xmit.buf,
 615                         up->uart_dma.tx_buf_dma_phys);
 616                 up->port.state->xmit.buf = NULL;
 617                 serial_omap_stop_rx(port);
 618                 dma_free_coherent(up->port.dev,
 619                         up->uart_dma.rx_buf_size, up->uart_dma.rx_buf,
 620                         up->uart_dma.rx_buf_dma_phys);
 621                 up->uart_dma.rx_buf = NULL;
 622         }
 623
 624         pm_runtime_put(&up->pdev->dev);
 625         free_irq(up->port.irq, up);
 626 }
 627
 628 static inline void
 629 serial_omap_configure_xonxoff
 630                 (struct uart_omap_port *up, struct ktermios *termios)
 631 {
 632         up->lcr = serial_in(up, UART_LCR);
 633         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 634         up->efr = serial_in(up, UART_EFR);
 635         serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
 636
 637         serial_out(up, UART_XON1, termios->c_cc[VSTART]);
 638         serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
 639
 640         /* clear SW control mode bits */
 641         up->efr &= OMAP_UART_SW_CLR;
 642
 643         /*
 644          * IXON Flag:
 645          * Enable XON/XOFF flow control on output.
 646          * Transmit XON1, XOFF1
 647          */
 648         if (termios->c_iflag & IXON)
 649                 up->efr |= OMAP_UART_SW_TX;
 650
 651         /*
 652          * IXOFF Flag:
 653          * Enable XON/XOFF flow control on input.
 654          * Receiver compares XON1, XOFF1.
 655          */
 656         if (termios->c_iflag & IXOFF)
 657                 up->efr |= OMAP_UART_SW_RX;
 658
 659         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 660         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 661
 662         up->mcr = serial_in(up, UART_MCR);
 663
 664         /*
 665          * IXANY Flag:
 666          * Enable any character to restart output.
 667          * Operation resumes after receiving any
 668          * character after recognition of the XOFF character
 669          */
 670         if (termios->c_iflag & IXANY)
 671                 up->mcr |= UART_MCR_XONANY;
 672
 673         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 674         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 675         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
 676         /* Enable special char function UARTi.EFR_REG[5] and
 677          * load the new software flow control mode IXON or IXOFF
 678          * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
 679          */
 680         serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
 681         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 682
 683         serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
 684         serial_out(up, UART_LCR, up->lcr);
 685 }
 686
 687 static void serial_omap_uart_qos_work(struct work_struct *work)
 688 {
 689         struct uart_omap_port *up = container_of(work, struct uart_omap_port,
 690                                                 qos_work);
 691
 692         pm_qos_update_request(&up->pm_qos_request, up->latency);
 693 }
 694
 695 static void
 696 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 697                         struct ktermios *old)
 698 {
 699         struct uart_omap_port *up = (struct uart_omap_port *)port;
 700         unsigned char cval = 0;
 701         unsigned char efr = 0;
 702         unsigned long flags = 0;
 703         unsigned int baud, quot;
 704
 705         switch (termios->c_cflag & CSIZE) {
 706         case CS5:
 707                 cval = UART_LCR_WLEN5;
 708                 break;
 709         case CS6:
 710                 cval = UART_LCR_WLEN6;
 711                 break;
 712         case CS7:
 713                 cval = UART_LCR_WLEN7;
 714                 break;
 715         default:
 716         case CS8:
 717                 cval = UART_LCR_WLEN8;
 718                 break;
 719         }
 720
 721         if (termios->c_cflag & CSTOPB)
 722                 cval |= UART_LCR_STOP;
 723         if (termios->c_cflag & PARENB)
 724                 cval |= UART_LCR_PARITY;
 725         if (!(termios->c_cflag & PARODD))
 726                 cval |= UART_LCR_EPAR;
 727
 728         /*
 729          * Ask the core to calculate the divisor for us.
 730          */
 731
 732         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
 733         quot = serial_omap_get_divisor(port, baud);
 734
 735         /* calculate wakeup latency constraint */
 736         up->calc_latency = (1000000 * up->port.fifosize) /
 737                                 (1000 * baud / 8);
 738         up->latency = up->calc_latency;
 739         schedule_work(&up->qos_work);
 740
 741         up->dll = quot & 0xff;
 742         up->dlh = quot >> 8;
 743         up->mdr1 = UART_OMAP_MDR1_DISABLE;
 744
 745         up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
 746                         UART_FCR_ENABLE_FIFO;
 747         if (up->use_dma)
 748                 up->fcr |= UART_FCR_DMA_SELECT;
 749
 750         /*
 751          * Ok, we're now changing the port state. Do it with
 752          * interrupts disabled.
 753          */
 754         pm_runtime_get_sync(&up->pdev->dev);
 755         spin_lock_irqsave(&up->port.lock, flags);
 756
 757         /*
 758          * Update the per-port timeout.
 759          */
 760         uart_update_timeout(port, termios->c_cflag, baud);
 761
 762         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 763         if (termios->c_iflag & INPCK)
 764                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 765         if (termios->c_iflag & (BRKINT | PARMRK))
 766                 up->port.read_status_mask |= UART_LSR_BI;
 767
 768         /*
 769          * Characters to ignore
 770          */
 771         up->port.ignore_status_mask = 0;
 772         if (termios->c_iflag & IGNPAR)
 773                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 774         if (termios->c_iflag & IGNBRK) {
 775                 up->port.ignore_status_mask |= UART_LSR_BI;
 776                 /*
 777                  * If we're ignoring parity and break indicators,
 778                  * ignore overruns too (for real raw support).
 779                  */
 780                 if (termios->c_iflag & IGNPAR)
 781                         up->port.ignore_status_mask |= UART_LSR_OE;
 782         }
 783
 784         /*
 785          * ignore all characters if CREAD is not set
 786          */
 787         if ((termios->c_cflag & CREAD) == 0)
 788                 up->port.ignore_status_mask |= UART_LSR_DR;
 789
 790         /*
 791          * Modem status interrupts
 792          */
 793         up->ier &= ~UART_IER_MSI;
 794         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 795                 up->ier |= UART_IER_MSI;
 796         serial_out(up, UART_IER, up->ier);
 797         serial_out(up, UART_LCR, cval);         /* reset DLAB */
 798         up->lcr = cval;
 799         up->scr = OMAP_UART_SCR_TX_EMPTY;
 800
 801         /* FIFOs and DMA Settings */
 802
 803         /* FCR can be changed only when the
 804          * baud clock is not running
 805          * DLL_REG and DLH_REG set to 0.
 806          */
 807         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 808         serial_out(up, UART_DLL, 0);
 809         serial_out(up, UART_DLM, 0);
 810         serial_out(up, UART_LCR, 0);
 811
 812         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 813
 814         up->efr = serial_in(up, UART_EFR);
 815         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 816
 817         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 818         up->mcr = serial_in(up, UART_MCR);
 819         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 820         /* FIFO ENABLE, DMA MODE */
 821
 822         up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
 823
 824         if (up->use_dma) {
 825                 serial_out(up, UART_TI752_TLR, 0);
 826                 up->scr |= UART_FCR_TRIGGER_4;
 827         } else {
 828                 /* Set receive FIFO threshold to 1 byte */
 829                 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
 830                 up->fcr |= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT);
 831         }
 832
 833         serial_out(up, UART_FCR, up->fcr);
 834         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 835
 836         serial_out(up, UART_OMAP_SCR, up->scr);
 837
 838         serial_out(up, UART_EFR, up->efr);
 839         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 840         serial_out(up, UART_MCR, up->mcr);
 841
 842         /* Protocol, Baud Rate, and Interrupt Settings */
 843
 844         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 845                 serial_omap_mdr1_errataset(up, up->mdr1);
 846         else
 847                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 848
 849         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 850
 851         up->efr = serial_in(up, UART_EFR);
 852         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 853
 854         serial_out(up, UART_LCR, 0);
 855         serial_out(up, UART_IER, 0);
 856         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 857
 858         serial_out(up, UART_DLL, up->dll);      /* LS of divisor */
 859         serial_out(up, UART_DLM, up->dlh);      /* MS of divisor */
 860
 861         serial_out(up, UART_LCR, 0);
 862         serial_out(up, UART_IER, up->ier);
 863         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 864
 865         serial_out(up, UART_EFR, up->efr);
 866         serial_out(up, UART_LCR, cval);
 867
 868         if (baud > 230400 && baud != 3000000)
 869                 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
 870         else
 871                 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
 872
 873         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 874                 serial_omap_mdr1_errataset(up, up->mdr1);
 875         else
 876                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 877
 878         /* Hardware Flow Control Configuration */
 879
 880         if (termios->c_cflag & CRTSCTS) {
 881                 efr |= (UART_EFR_CTS | UART_EFR_RTS);
 882                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 883
 884                 up->mcr = serial_in(up, UART_MCR);
 885                 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 886
 887                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 888                 up->efr = serial_in(up, UART_EFR);
 889                 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 890
 891                 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
 892                 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
 893                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 894                 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
 895                 serial_out(up, UART_LCR, cval);
 896         }
 897
 898         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 899         /* Software Flow Control Configuration */
 900         serial_omap_configure_xonxoff(up, termios);
 901
 902         spin_unlock_irqrestore(&up->port.lock, flags);
 903         pm_runtime_put(&up->pdev->dev);
 904         dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
 905 }
 906
 907 static void
 908 serial_omap_pm(struct uart_port *port, unsigned int state,
 909                unsigned int oldstate)
 910 {
 911         struct uart_omap_port *up = (struct uart_omap_port *)port;
 912         unsigned char efr;
 913
 914         dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
 915
 916         pm_runtime_get_sync(&up->pdev->dev);
 917         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 918         efr = serial_in(up, UART_EFR);
 919         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
 920         serial_out(up, UART_LCR, 0);
 921
 922         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
 923         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 924         serial_out(up, UART_EFR, efr);
 925         serial_out(up, UART_LCR, 0);
 926
 927         if (!device_may_wakeup(&up->pdev->dev)) {
 928                 if (!state)
 929                         pm_runtime_forbid(&up->pdev->dev);
 930                 else
 931                         pm_runtime_allow(&up->pdev->dev);
 932         }
 933
 934         pm_runtime_put(&up->pdev->dev);
 935 }
 936
 937 static void serial_omap_release_port(struct uart_port *port)
 938 {
 939         dev_dbg(port->dev, "serial_omap_release_port+\n");
 940 }
 941
 942 static int serial_omap_request_port(struct uart_port *port)
 943 {
 944         dev_dbg(port->dev, "serial_omap_request_port+\n");
 945         return 0;
 946 }
 947
 948 static void serial_omap_config_port(struct uart_port *port, int flags)
 949 {
 950         struct uart_omap_port *up = (struct uart_omap_port *)port;
 951
 952         dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
 953                                                         up->port.line);
 954         up->port.type = PORT_OMAP;
 955 }
 956
 957 static int
 958 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
 959 {
 960         /* we don't want the core code to modify any port params */
 961         dev_dbg(port->dev, "serial_omap_verify_port+\n");
 962         return -EINVAL;
 963 }
 964
 965 static const char *
 966 serial_omap_type(struct uart_port *port)
 967 {
 968         struct uart_omap_port *up = (struct uart_omap_port *)port;
 969
 970         dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
 971         return up->name;
 972 }
 973
 974 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 975
 976 static inline void wait_for_xmitr(struct uart_omap_port *up)
 977 {
 978         unsigned int status, tmout = 10000;
 979
 980         /* Wait up to 10ms for the character(s) to be sent. */
 981         do {
 982                 status = serial_in(up, UART_LSR);
 983
 984                 if (status & UART_LSR_BI)
 985                         up->lsr_break_flag = UART_LSR_BI;
 986
 987                 if (--tmout == 0)
 988                         break;
 989                 udelay(1);
 990         } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
 991
 992         /* Wait up to 1s for flow control if necessary */
 993         if (up->port.flags & UPF_CONS_FLOW) {
 994                 tmout = 1000000;
 995                 for (tmout = 1000000; tmout; tmout--) {
 996                         unsigned int msr = serial_in(up, UART_MSR);
 997
 998                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
 999                         if (msr & UART_MSR_CTS)
1000                                 break;
1001
1002                         udelay(1);
1003                 }
1004         }
1005 }
1006
1007 #ifdef CONFIG_CONSOLE_POLL
1008
1009 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1010 {
1011         struct uart_omap_port *up = (struct uart_omap_port *)port;
1012
1013         pm_runtime_get_sync(&up->pdev->dev);
1014         wait_for_xmitr(up);
1015         serial_out(up, UART_TX, ch);
1016         pm_runtime_put(&up->pdev->dev);
1017 }
1018
1019 static int serial_omap_poll_get_char(struct uart_port *port)
1020 {
1021         struct uart_omap_port *up = (struct uart_omap_port *)port;
1022         unsigned int status;
1023
1024         pm_runtime_get_sync(&up->pdev->dev);
1025         status = serial_in(up, UART_LSR);
1026         if (!(status & UART_LSR_DR))
1027                 return NO_POLL_CHAR;
1028
1029         status = serial_in(up, UART_RX);
1030         pm_runtime_put(&up->pdev->dev);
1031         return status;
1032 }
1033
1034 #endif /* CONFIG_CONSOLE_POLL */
1035
1036 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1037
1038 static struct uart_omap_port *serial_omap_console_ports[4];
1039
1040 static struct uart_driver serial_omap_reg;
1041
1042 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1043 {
1044         struct uart_omap_port *up = (struct uart_omap_port *)port;
1045
1046         wait_for_xmitr(up);
1047         serial_out(up, UART_TX, ch);
1048 }
1049
1050 static void
1051 serial_omap_console_write(struct console *co, const char *s,
1052                 unsigned int count)
1053 {
1054         struct uart_omap_port *up = serial_omap_console_ports[co->index];
1055         unsigned long flags;
1056         unsigned int ier;
1057         int locked = 1;
1058
1059         pm_runtime_get_sync(&up->pdev->dev);
1060
1061         local_irq_save(flags);
1062         if (up->port.sysrq)
1063                 locked = 0;
1064         else if (oops_in_progress)
1065                 locked = spin_trylock(&up->port.lock);
1066         else
1067                 spin_lock(&up->port.lock);
1068
1069         /*
1070          * First save the IER then disable the interrupts
1071          */
1072         ier = serial_in(up, UART_IER);
1073         serial_out(up, UART_IER, 0);
1074
1075         uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1076
1077         /*
1078          * Finally, wait for transmitter to become empty
1079          * and restore the IER
1080          */
1081         wait_for_xmitr(up);
1082         serial_out(up, UART_IER, ier);
1083         /*
1084          * The receive handling will happen properly because the
1085          * receive ready bit will still be set; it is not cleared
1086          * on read.  However, modem control will not, we must
1087          * call it if we have saved something in the saved flags
1088          * while processing with interrupts off.
1089          */
1090         if (up->msr_saved_flags)
1091                 check_modem_status(up);
1092
1093         pm_runtime_mark_last_busy(&up->pdev->dev);
1094         pm_runtime_put_autosuspend(&up->pdev->dev);
1095         if (locked)
1096                 spin_unlock(&up->port.lock);
1097         local_irq_restore(flags);
1098 }
1099
1100 static int __init
1101 serial_omap_console_setup(struct console *co, char *options)
1102 {
1103         struct uart_omap_port *up;
1104         int baud = 115200;
1105         int bits = 8;
1106         int parity = 'n';
1107         int flow = 'n';
1108
1109         if (serial_omap_console_ports[co->index] == NULL)
1110                 return -ENODEV;
1111         up = serial_omap_console_ports[co->index];
1112
1113         if (options)
1114                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1115
1116         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1117 }
1118
1119 static struct console serial_omap_console = {
1120         .name           = OMAP_SERIAL_NAME,
1121         .write          = serial_omap_console_write,
1122         .device         = uart_console_device,
1123         .setup          = serial_omap_console_setup,
1124         .flags          = CON_PRINTBUFFER,
1125         .index          = -1,
1126         .data           = &serial_omap_reg,
1127 };
1128
1129 static void serial_omap_add_console_port(struct uart_omap_port *up)
1130 {
1131         serial_omap_console_ports[up->port.line] = up;
1132 }
1133
1134 #define OMAP_CONSOLE    (&serial_omap_console)
1135
1136 #else
1137
1138 #define OMAP_CONSOLE    NULL
1139
1140 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1141 {}
1142
1143 #endif
1144
1145 static struct uart_ops serial_omap_pops = {
1146         .tx_empty       = serial_omap_tx_empty,
1147         .set_mctrl      = serial_omap_set_mctrl,
1148         .get_mctrl      = serial_omap_get_mctrl,
1149         .stop_tx        = serial_omap_stop_tx,
1150         .start_tx       = serial_omap_start_tx,
1151         .stop_rx        = serial_omap_stop_rx,
1152         .enable_ms      = serial_omap_enable_ms,
1153         .break_ctl      = serial_omap_break_ctl,
1154         .startup        = serial_omap_startup,
1155         .shutdown       = serial_omap_shutdown,
1156         .set_termios    = serial_omap_set_termios,
1157         .pm             = serial_omap_pm,
1158         .type           = serial_omap_type,
1159         .release_port   = serial_omap_release_port,
1160         .request_port   = serial_omap_request_port,
1161         .config_port    = serial_omap_config_port,
1162         .verify_port    = serial_omap_verify_port,
1163 #ifdef CONFIG_CONSOLE_POLL
1164         .poll_put_char  = serial_omap_poll_put_char,
1165         .poll_get_char  = serial_omap_poll_get_char,
1166 #endif
1167 };
1168
1169 static struct uart_driver serial_omap_reg = {
1170         .owner          = THIS_MODULE,
1171         .driver_name    = "OMAP-SERIAL",
1172         .dev_name       = OMAP_SERIAL_NAME,
1173         .nr             = OMAP_MAX_HSUART_PORTS,
1174         .cons           = OMAP_CONSOLE,
1175 };
1176
1177 #ifdef CONFIG_SUSPEND
1178 static int serial_omap_suspend(struct device *dev)
1179 {
1180         struct uart_omap_port *up = dev_get_drvdata(dev);
1181
1182         if (up) {
1183                 uart_suspend_port(&serial_omap_reg, &up->port);
1184                 flush_work_sync(&up->qos_work);
1185         }
1186
1187         return 0;
1188 }
1189
1190 static int serial_omap_resume(struct device *dev)
1191 {
1192         struct uart_omap_port *up = dev_get_drvdata(dev);
1193
1194         if (up)
1195                 uart_resume_port(&serial_omap_reg, &up->port);
1196         return 0;
1197 }
1198 #endif
1199
1200 static void serial_omap_rxdma_poll(unsigned long uart_no)
1201 {
1202         struct uart_omap_port *up = ui[uart_no];
1203         unsigned int curr_dma_pos, curr_transmitted_size;
1204         int ret = 0;
1205
1206         curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel);
1207         if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
1208                              (curr_dma_pos == 0)) {
1209                 if (jiffies_to_msecs(jiffies - up->port_activity) <
1210                                                 up->uart_dma.rx_timeout) {
1211                         mod_timer(&up->uart_dma.rx_timer, jiffies +
1212                                 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1213                 } else {
1214                         serial_omap_stop_rxdma(up);
1215                         up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1216                         serial_out(up, UART_IER, up->ier);
1217                 }
1218                 return;
1219         }
1220
1221         curr_transmitted_size = curr_dma_pos -
1222                                         up->uart_dma.prev_rx_dma_pos;
1223         up->port.icount.rx += curr_transmitted_size;
1224         tty_insert_flip_string(up->port.state->port.tty,
1225                         up->uart_dma.rx_buf +
1226                         (up->uart_dma.prev_rx_dma_pos -
1227                         up->uart_dma.rx_buf_dma_phys),
1228                         curr_transmitted_size);
1229         tty_flip_buffer_push(up->port.state->port.tty);
1230         up->uart_dma.prev_rx_dma_pos = curr_dma_pos;
1231         if (up->uart_dma.rx_buf_size +
1232                         up->uart_dma.rx_buf_dma_phys == curr_dma_pos) {
1233                 ret = serial_omap_start_rxdma(up);
1234                 if (ret < 0) {
1235                         serial_omap_stop_rxdma(up);
1236                         up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1237                         serial_out(up, UART_IER, up->ier);
1238                 }
1239         } else  {
1240                 mod_timer(&up->uart_dma.rx_timer, jiffies +
1241                         usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1242         }
1243         up->port_activity = jiffies;
1244 }
1245
1246 static void uart_rx_dma_callback(int lch, u16 ch_status, void *data)
1247 {
1248         return;
1249 }
1250
1251 static int serial_omap_start_rxdma(struct uart_omap_port *up)
1252 {
1253         int ret = 0;
1254
1255         if (up->uart_dma.rx_dma_channel == -1) {
1256                 pm_runtime_get_sync(&up->pdev->dev);
1257                 ret = omap_request_dma(up->uart_dma.uart_dma_rx,
1258                                 "UART Rx DMA",
1259                                 (void *)uart_rx_dma_callback, up,
1260                                 &(up->uart_dma.rx_dma_channel));
1261                 if (ret < 0)
1262                         return ret;
1263
1264                 omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0,
1265                                 OMAP_DMA_AMODE_CONSTANT,
1266                                 up->uart_dma.uart_base, 0, 0);
1267                 omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0,
1268                                 OMAP_DMA_AMODE_POST_INC,
1269                                 up->uart_dma.rx_buf_dma_phys, 0, 0);
1270                 omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel,
1271                                 OMAP_DMA_DATA_TYPE_S8,
1272                                 up->uart_dma.rx_buf_size, 1,
1273                                 OMAP_DMA_SYNC_ELEMENT,
1274                                 up->uart_dma.uart_dma_rx, 0);
1275         }
1276         up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys;
1277         /* FIXME: Cache maintenance needed here? */
1278         omap_start_dma(up->uart_dma.rx_dma_channel);
1279         mod_timer(&up->uart_dma.rx_timer, jiffies +
1280                                 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1281         up->uart_dma.rx_dma_used = true;
1282         return ret;
1283 }
1284
1285 static void serial_omap_continue_tx(struct uart_omap_port *up)
1286 {
1287         struct circ_buf *xmit = &up->port.state->xmit;
1288         unsigned int start = up->uart_dma.tx_buf_dma_phys
1289                         + (xmit->tail & (UART_XMIT_SIZE - 1));
1290
1291         if (uart_circ_empty(xmit))
1292                 return;
1293
1294         up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
1295         /*
1296          * It is a circular buffer. See if the buffer has wounded back.
1297          * If yes it will have to be transferred in two separate dma
1298          * transfers
1299          */
1300         if (start + up->uart_dma.tx_buf_size >=
1301                         up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
1302                 up->uart_dma.tx_buf_size =
1303                         (up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start;
1304         omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
1305                                 OMAP_DMA_AMODE_CONSTANT,
1306                                 up->uart_dma.uart_base, 0, 0);
1307         omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
1308                                 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
1309         omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
1310                                 OMAP_DMA_DATA_TYPE_S8,
1311                                 up->uart_dma.tx_buf_size, 1,
1312                                 OMAP_DMA_SYNC_ELEMENT,
1313                                 up->uart_dma.uart_dma_tx, 0);
1314         /* FIXME: Cache maintenance needed here? */
1315         omap_start_dma(up->uart_dma.tx_dma_channel);
1316 }
1317
1318 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
1319 {
1320         struct uart_omap_port *up = (struct uart_omap_port *)data;
1321         struct circ_buf *xmit = &up->port.state->xmit;
1322
1323         xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \
1324                         (UART_XMIT_SIZE - 1);
1325         up->port.icount.tx += up->uart_dma.tx_buf_size;
1326
1327         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1328                 uart_write_wakeup(&up->port);
1329
1330         if (uart_circ_empty(xmit)) {
1331                 spin_lock(&(up->uart_dma.tx_lock));
1332                 serial_omap_stop_tx(&up->port);
1333                 up->uart_dma.tx_dma_used = false;
1334                 spin_unlock(&(up->uart_dma.tx_lock));
1335         } else {
1336                 omap_stop_dma(up->uart_dma.tx_dma_channel);
1337                 serial_omap_continue_tx(up);
1338         }
1339         up->port_activity = jiffies;
1340         return;
1341 }
1342
1343 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1344 {
1345         struct omap_uart_port_info *omap_up_info;
1346
1347         omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1348         if (!omap_up_info)
1349                 return NULL; /* out of memory */
1350
1351         of_property_read_u32(dev->of_node, "clock-frequency",
1352                                          &omap_up_info->uartclk);
1353         return omap_up_info;
1354 }
1355
1356 static int serial_omap_probe(struct platform_device *pdev)
1357 {
1358         struct uart_omap_port   *up;
1359         struct resource         *mem, *irq, *dma_tx, *dma_rx;
1360         struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1361         int ret = -ENOSPC;
1362
1363         if (pdev->dev.of_node)
1364                 omap_up_info = of_get_uart_port_info(&pdev->dev);
1365
1366         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1367         if (!mem) {
1368                 dev_err(&pdev->dev, "no mem resource?\n");
1369                 return -ENODEV;
1370         }
1371
1372         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1373         if (!irq) {
1374                 dev_err(&pdev->dev, "no irq resource?\n");
1375                 return -ENODEV;
1376         }
1377
1378         if (!request_mem_region(mem->start, resource_size(mem),
1379                                 pdev->dev.driver->name)) {
1380                 dev_err(&pdev->dev, "memory region already claimed\n");
1381                 return -EBUSY;
1382         }
1383
1384         dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1385         if (!dma_rx) {
1386                 ret = -EINVAL;
1387                 goto err;
1388         }
1389
1390         dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1391         if (!dma_tx) {
1392                 ret = -EINVAL;
1393                 goto err;
1394         }
1395
1396         up = kzalloc(sizeof(*up), GFP_KERNEL);
1397         if (up == NULL) {
1398                 ret = -ENOMEM;
1399                 goto do_release_region;
1400         }
1401         up->pdev = pdev;
1402         up->port.dev = &pdev->dev;
1403         up->port.type = PORT_OMAP;
1404         up->port.iotype = UPIO_MEM;
1405         up->port.irq = irq->start;
1406
1407         up->port.regshift = 2;
1408         up->port.fifosize = 64;
1409         up->port.ops = &serial_omap_pops;
1410
1411         if (pdev->dev.of_node)
1412                 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1413         else
1414                 up->port.line = pdev->id;
1415
1416         if (up->port.line < 0) {
1417                 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1418                                                                 up->port.line);
1419                 ret = -ENODEV;
1420                 goto err;
1421         }
1422
1423         sprintf(up->name, "OMAP UART%d", up->port.line);
1424         up->port.mapbase = mem->start;
1425         up->port.membase = ioremap(mem->start, resource_size(mem));
1426         if (!up->port.membase) {
1427                 dev_err(&pdev->dev, "can't ioremap UART\n");
1428                 ret = -ENOMEM;
1429                 goto err;
1430         }
1431
1432         up->port.flags = omap_up_info->flags;
1433         up->port.uartclk = omap_up_info->uartclk;
1434         if (!up->port.uartclk) {
1435                 up->port.uartclk = DEFAULT_CLK_SPEED;
1436                 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1437                                                 "%d\n", DEFAULT_CLK_SPEED);
1438         }
1439         up->uart_dma.uart_base = mem->start;
1440         up->errata = omap_up_info->errata;
1441
1442         if (omap_up_info->dma_enabled) {
1443                 up->uart_dma.uart_dma_tx = dma_tx->start;
1444                 up->uart_dma.uart_dma_rx = dma_rx->start;
1445                 up->use_dma = 1;
1446                 up->uart_dma.rx_buf_size = omap_up_info->dma_rx_buf_size;
1447                 up->uart_dma.rx_timeout = omap_up_info->dma_rx_timeout;
1448                 up->uart_dma.rx_poll_rate = omap_up_info->dma_rx_poll_rate;
1449                 spin_lock_init(&(up->uart_dma.tx_lock));
1450                 spin_lock_init(&(up->uart_dma.rx_lock));
1451                 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
1452                 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
1453         }
1454
1455         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1456         up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1457         pm_qos_add_request(&up->pm_qos_request,
1458                 PM_QOS_CPU_DMA_LATENCY, up->latency);
1459         serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1460         INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1461
1462         pm_runtime_use_autosuspend(&pdev->dev);
1463         pm_runtime_set_autosuspend_delay(&pdev->dev,
1464                         omap_up_info->autosuspend_timeout);
1465
1466         pm_runtime_irq_safe(&pdev->dev);
1467         pm_runtime_enable(&pdev->dev);
1468         pm_runtime_get_sync(&pdev->dev);
1469
1470         ui[up->port.line] = up;
1471         serial_omap_add_console_port(up);
1472
1473         ret = uart_add_one_port(&serial_omap_reg, &up->port);
1474         if (ret != 0)
1475                 goto do_release_region;
1476
1477         pm_runtime_put(&pdev->dev);
1478         platform_set_drvdata(pdev, up);
1479         return 0;
1480 err:
1481         dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1482                                 pdev->id, __func__, ret);
1483 do_release_region:
1484         release_mem_region(mem->start, resource_size(mem));
1485         return ret;
1486 }
1487
1488 static int serial_omap_remove(struct platform_device *dev)
1489 {
1490         struct uart_omap_port *up = platform_get_drvdata(dev);
1491
1492         if (up) {
1493                 pm_runtime_disable(&up->pdev->dev);
1494                 uart_remove_one_port(&serial_omap_reg, &up->port);
1495                 pm_qos_remove_request(&up->pm_qos_request);
1496
1497                 kfree(up);
1498         }
1499
1500         platform_set_drvdata(dev, NULL);
1501         return 0;
1502 }
1503
1504 /*
1505  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1506  * The access to uart register after MDR1 Access
1507  * causes UART to corrupt data.
1508  *
1509  * Need a delay =
1510  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1511  * give 10 times as much
1512  */
1513 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1514 {
1515         u8 timeout = 255;
1516
1517         serial_out(up, UART_OMAP_MDR1, mdr1);
1518         udelay(2);
1519         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1520                         UART_FCR_CLEAR_RCVR);
1521         /*
1522          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1523          * TX_FIFO_E bit is 1.
1524          */
1525         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1526                                 (UART_LSR_THRE | UART_LSR_DR))) {
1527                 timeout--;
1528                 if (!timeout) {
1529                         /* Should *never* happen. we warn and carry on */
1530                         dev_crit(&up->pdev->dev, "Errata i202: timedout %x\n",
1531                                                 serial_in(up, UART_LSR));
1532                         break;
1533                 }
1534                 udelay(1);
1535         }
1536 }
1537
1538 static void serial_omap_restore_context(struct uart_omap_port *up)
1539 {
1540         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1541                 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1542         else
1543                 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1544
1545         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1546         serial_out(up, UART_EFR, UART_EFR_ECB);
1547         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1548         serial_out(up, UART_IER, 0x0);
1549         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1550         serial_out(up, UART_DLL, up->dll);
1551         serial_out(up, UART_DLM, up->dlh);
1552         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1553         serial_out(up, UART_IER, up->ier);
1554         serial_out(up, UART_FCR, up->fcr);
1555         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1556         serial_out(up, UART_MCR, up->mcr);
1557         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1558         serial_out(up, UART_OMAP_SCR, up->scr);
1559         serial_out(up, UART_EFR, up->efr);
1560         serial_out(up, UART_LCR, up->lcr);
1561         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1562                 serial_omap_mdr1_errataset(up, up->mdr1);
1563         else
1564                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1565 }
1566
1567 #ifdef CONFIG_PM_RUNTIME
1568 static int serial_omap_runtime_suspend(struct device *dev)
1569 {
1570         struct uart_omap_port *up = dev_get_drvdata(dev);
1571         struct omap_uart_port_info *pdata = dev->platform_data;
1572
1573         if (!up)
1574                 return -EINVAL;
1575
1576         if (!pdata || !pdata->enable_wakeup)
1577                 return 0;
1578
1579         if (pdata->get_context_loss_count)
1580                 up->context_loss_cnt = pdata->get_context_loss_count(dev);
1581
1582         if (device_may_wakeup(dev)) {
1583                 if (!up->wakeups_enabled) {
1584                         pdata->enable_wakeup(up->pdev, true);
1585                         up->wakeups_enabled = true;
1586                 }
1587         } else {
1588                 if (up->wakeups_enabled) {
1589                         pdata->enable_wakeup(up->pdev, false);
1590                         up->wakeups_enabled = false;
1591                 }
1592         }
1593
1594         /* Errata i291 */
1595         if (up->use_dma && pdata->set_forceidle &&
1596                         (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
1597                 pdata->set_forceidle(up->pdev);
1598
1599         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1600         schedule_work(&up->qos_work);
1601
1602         return 0;
1603 }
1604
1605 static int serial_omap_runtime_resume(struct device *dev)
1606 {
1607         struct uart_omap_port *up = dev_get_drvdata(dev);
1608         struct omap_uart_port_info *pdata = dev->platform_data;
1609
1610         if (up) {
1611                 if (pdata->get_context_loss_count) {
1612                         u32 loss_cnt = pdata->get_context_loss_count(dev);
1613
1614                         if (up->context_loss_cnt != loss_cnt)
1615                                 serial_omap_restore_context(up);
1616                 }
1617
1618                 /* Errata i291 */
1619                 if (up->use_dma && pdata->set_noidle &&
1620                                 (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
1621                         pdata->set_noidle(up->pdev);
1622
1623                 up->latency = up->calc_latency;
1624                 schedule_work(&up->qos_work);
1625         }
1626
1627         return 0;
1628 }
1629 #endif
1630
1631 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1632         SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1633         SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1634                                 serial_omap_runtime_resume, NULL)
1635 };
1636
1637 #if defined(CONFIG_OF)
1638 static const struct of_device_id omap_serial_of_match[] = {
1639         { .compatible = "ti,omap2-uart" },
1640         { .compatible = "ti,omap3-uart" },
1641         { .compatible = "ti,omap4-uart" },
1642         {},
1643 };
1644 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1645 #endif
1646
1647 static struct platform_driver serial_omap_driver = {
1648         .probe          = serial_omap_probe,
1649         .remove         = serial_omap_remove,
1650         .driver         = {
1651                 .name   = DRIVER_NAME,
1652                 .pm     = &serial_omap_dev_pm_ops,
1653                 .of_match_table = of_match_ptr(omap_serial_of_match),
1654         },
1655 };
1656
1657 static int __init serial_omap_init(void)
1658 {
1659         int ret;
1660
1661         ret = uart_register_driver(&serial_omap_reg);
1662         if (ret != 0)
1663                 return ret;
1664         ret = platform_driver_register(&serial_omap_driver);
1665         if (ret != 0)
1666                 uart_unregister_driver(&serial_omap_reg);
1667         return ret;
1668 }
1669
1670 static void __exit serial_omap_exit(void)
1671 {
1672         platform_driver_unregister(&serial_omap_driver);
1673         uart_unregister_driver(&serial_omap_reg);
1674 }
1675
1676 module_init(serial_omap_init);
1677 module_exit(serial_omap_exit);
1678
1679 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1680 MODULE_LICENSE("GPL");
1681 MODULE_AUTHOR("Texas Instruments Inc");