drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include <linux/kernel.h>
  40 #include <linux/delay.h>
  41 #include <linux/slab.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/pm_runtime.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/io.h>
  47 #include <linux/list.h>
  48 #include <linux/dma-mapping.h>
  49
  50 #include <linux/usb/ch9.h>
  51 #include <linux/usb/gadget.h>
  52
  53 #include "core.h"
  54 #include "gadget.h"
  55 #include "io.h"
  56
  57 /**
  58  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  59  * @dwc: pointer to our context structure
  60  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  61  *
  62  * Caller should take care of locking. This function will
  63  * return 0 on success or -EINVAL if wrong Test Selector
  64  * is passed
  65  */
  66 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  67 {
  68         u32             reg;
  69
  70         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  71         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  72
  73         switch (mode) {
  74         case TEST_J:
  75         case TEST_K:
  76         case TEST_SE0_NAK:
  77         case TEST_PACKET:
  78         case TEST_FORCE_EN:
  79                 reg |= mode << 1;
  80                 break;
  81         default:
  82                 return -EINVAL;
  83         }
  84
  85         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  86
  87         return 0;
  88 }
  89
  90 /**
  91  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  92  * @dwc: pointer to our context structure
  93  * @state: the state to put link into
  94  *
  95  * Caller should take care of locking. This function will
  96  * return 0 on success or -ETIMEDOUT.
  97  */
  98 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  99 {
 100         int             retries = 10000;
 101         u32             reg;
 102
 103         /*
 104          * Wait until device controller is ready. Only applies to 1.94a and
 105          * later RTL.
 106          */
 107         if (dwc->revision >= DWC3_REVISION_194A) {
 108                 while (--retries) {
 109                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 110                         if (reg & DWC3_DSTS_DCNRD)
 111                                 udelay(5);
 112                         else
 113                                 break;
 114                 }
 115
 116                 if (retries <= 0)
 117                         return -ETIMEDOUT;
 118         }
 119
 120         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 121         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 122
 123         /* set requested state */
 124         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 125         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 126
 127         /*
 128          * The following code is racy when called from dwc3_gadget_wakeup,
 129          * and is not needed, at least on newer versions
 130          */
 131         if (dwc->revision >= DWC3_REVISION_194A)
 132                 return 0;
 133
 134         /* wait for a change in DSTS */
 135         retries = 10000;
 136         while (--retries) {
 137                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 138
 139                 if (DWC3_DSTS_USBLNKST(reg) == state)
 140                         return 0;
 141
 142                 udelay(5);
 143         }
 144
 145         dev_vdbg(dwc->dev, "link state change request timed out\n");
 146
 147         return -ETIMEDOUT;
 148 }
 149
 150 /**
 151  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 152  * @dwc: pointer to our context structure
 153  *
 154  * This function will a best effort FIFO allocation in order
 155  * to improve FIFO usage and throughput, while still allowing
 156  * us to enable as many endpoints as possible.
 157  *
 158  * Keep in mind that this operation will be highly dependent
 159  * on the configured size for RAM1 - which contains TxFifo -,
 160  * the amount of endpoints enabled on coreConsultant tool, and
 161  * the width of the Master Bus.
 162  *
 163  * In the ideal world, we would always be able to satisfy the
 164  * following equation:
 165  *
 166  * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
 167  * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
 168  *
 169  * Unfortunately, due to many variables that's not always the case.
 170  */
 171 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
 172 {
 173         int             last_fifo_depth = 0;
 174         int             ram1_depth;
 175         int             fifo_size;
 176         int             mdwidth;
 177         int             num;
 178
 179         if (!dwc->needs_fifo_resize)
 180                 return 0;
 181
 182         ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
 183         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
 184
 185         /* MDWIDTH is represented in bits, we need it in bytes */
 186         mdwidth >>= 3;
 187
 188         /*
 189          * FIXME For now we will only allocate 1 wMaxPacketSize space
 190          * for each enabled endpoint, later patches will come to
 191          * improve this algorithm so that we better use the internal
 192          * FIFO space
 193          */
 194         for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
 195                 struct dwc3_ep  *dep = dwc->eps[num];
 196                 int             fifo_number = dep->number >> 1;
 197                 int             mult = 1;
 198                 int             tmp;
 199
 200                 if (!(dep->number & 1))
 201                         continue;
 202
 203                 if (!(dep->flags & DWC3_EP_ENABLED))
 204                         continue;
 205
 206                 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
 207                                 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
 208                         mult = 3;
 209
 210                 /*
 211                  * REVISIT: the following assumes we will always have enough
 212                  * space available on the FIFO RAM for all possible use cases.
 213                  * Make sure that's true somehow and change FIFO allocation
 214                  * accordingly.
 215                  *
 216                  * If we have Bulk or Isochronous endpoints, we want
 217                  * them to be able to be very, very fast. So we're giving
 218                  * those endpoints a fifo_size which is enough for 3 full
 219                  * packets
 220                  */
 221                 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
 222                 tmp += mdwidth;
 223
 224                 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
 225
 226                 fifo_size |= (last_fifo_depth << 16);
 227
 228                 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
 229                                 dep->name, last_fifo_depth, fifo_size & 0xffff);
 230
 231                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
 232                                 fifo_size);
 233
 234                 last_fifo_depth += (fifo_size & 0xffff);
 235         }
 236
 237         return 0;
 238 }
 239
 240 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 241                 int status)
 242 {
 243         struct dwc3                     *dwc = dep->dwc;
 244
 245         if (req->queued) {
 246                 if (req->request.num_mapped_sgs)
 247                         dep->busy_slot += req->request.num_mapped_sgs;
 248                 else
 249                         dep->busy_slot++;
 250
 251                 /*
 252                  * Skip LINK TRB. We can't use req->trb and check for
 253                  * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
 254                  * completed (not the LINK TRB).
 255                  */
 256                 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 257                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
 258                         dep->busy_slot++;
 259         }
 260         list_del(&req->list);
 261         req->trb = NULL;
 262
 263         if (req->request.status == -EINPROGRESS)
 264                 req->request.status = status;
 265
 266         if (dwc->ep0_bounced && dep->number == 0)
 267                 dwc->ep0_bounced = false;
 268         else
 269                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 270                                 req->direction);
 271
 272         dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
 273                         req, dep->name, req->request.actual,
 274                         req->request.length, status);
 275
 276         spin_unlock(&dwc->lock);
 277         req->request.complete(&dep->endpoint, &req->request);
 278         spin_lock(&dwc->lock);
 279 }
 280
 281 static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
 282 {
 283         switch (cmd) {
 284         case DWC3_DEPCMD_DEPSTARTCFG:
 285                 return "Start New Configuration";
 286         case DWC3_DEPCMD_ENDTRANSFER:
 287                 return "End Transfer";
 288         case DWC3_DEPCMD_UPDATETRANSFER:
 289                 return "Update Transfer";
 290         case DWC3_DEPCMD_STARTTRANSFER:
 291                 return "Start Transfer";
 292         case DWC3_DEPCMD_CLEARSTALL:
 293                 return "Clear Stall";
 294         case DWC3_DEPCMD_SETSTALL:
 295                 return "Set Stall";
 296         case DWC3_DEPCMD_GETEPSTATE:
 297                 return "Get Endpoint State";
 298         case DWC3_DEPCMD_SETTRANSFRESOURCE:
 299                 return "Set Endpoint Transfer Resource";
 300         case DWC3_DEPCMD_SETEPCONFIG:
 301                 return "Set Endpoint Configuration";
 302         default:
 303                 return "UNKNOWN command";
 304         }
 305 }
 306
 307 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
 308 {
 309         u32             timeout = 500;
 310         u32             reg;
 311
 312         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 313         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 314
 315         do {
 316                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 317                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 318                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 319                                         DWC3_DGCMD_STATUS(reg));
 320                         return 0;
 321                 }
 322
 323                 /*
 324                  * We can't sleep here, because it's also called from
 325                  * interrupt context.
 326                  */
 327                 timeout--;
 328                 if (!timeout)
 329                         return -ETIMEDOUT;
 330                 udelay(1);
 331         } while (1);
 332 }
 333
 334 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 335                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 336 {
 337         struct dwc3_ep          *dep = dwc->eps[ep];
 338         u32                     timeout = 500;
 339         u32                     reg;
 340
 341         dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
 342                         dep->name,
 343                         dwc3_gadget_ep_cmd_string(cmd), params->param0,
 344                         params->param1, params->param2);
 345
 346         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 347         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 348         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 349
 350         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 351         do {
 352                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 353                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 354                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 355                                         DWC3_DEPCMD_STATUS(reg));
 356                         return 0;
 357                 }
 358
 359                 /*
 360                  * We can't sleep here, because it is also called from
 361                  * interrupt context.
 362                  */
 363                 timeout--;
 364                 if (!timeout)
 365                         return -ETIMEDOUT;
 366
 367                 udelay(1);
 368         } while (1);
 369 }
 370
 371 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 372                 struct dwc3_trb *trb)
 373 {
 374         u32             offset = (char *) trb - (char *) dep->trb_pool;
 375
 376         return dep->trb_pool_dma + offset;
 377 }
 378
 379 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 380 {
 381         struct dwc3             *dwc = dep->dwc;
 382
 383         if (dep->trb_pool)
 384                 return 0;
 385
 386         if (dep->number == 0 || dep->number == 1)
 387                 return 0;
 388
 389         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 390                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 391                         &dep->trb_pool_dma, GFP_KERNEL);
 392         if (!dep->trb_pool) {
 393                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 394                                 dep->name);
 395                 return -ENOMEM;
 396         }
 397
 398         return 0;
 399 }
 400
 401 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 402 {
 403         struct dwc3             *dwc = dep->dwc;
 404
 405         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 406                         dep->trb_pool, dep->trb_pool_dma);
 407
 408         dep->trb_pool = NULL;
 409         dep->trb_pool_dma = 0;
 410 }
 411
 412 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 413 {
 414         struct dwc3_gadget_ep_cmd_params params;
 415         u32                     cmd;
 416
 417         memset(&params, 0x00, sizeof(params));
 418
 419         if (dep->number != 1) {
 420                 cmd = DWC3_DEPCMD_DEPSTARTCFG;
 421                 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
 422                 if (dep->number > 1) {
 423                         if (dwc->start_config_issued)
 424                                 return 0;
 425                         dwc->start_config_issued = true;
 426                         cmd |= DWC3_DEPCMD_PARAM(2);
 427                 }
 428
 429                 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 430         }
 431
 432         return 0;
 433 }
 434
 435 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 436                 const struct usb_endpoint_descriptor *desc,
 437                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 438                 bool ignore)
 439 {
 440         struct dwc3_gadget_ep_cmd_params params;
 441
 442         memset(&params, 0x00, sizeof(params));
 443
 444         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 445                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 446
 447         /* Burst size is only needed in SuperSpeed mode */
 448         if (dwc->gadget.speed == USB_SPEED_SUPER) {
 449                 u32 burst = dep->endpoint.maxburst - 1;
 450
 451                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 452         }
 453
 454         if (ignore)
 455                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 456
 457         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 458                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 459
 460         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 461                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 462                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 463                 dep->stream_capable = true;
 464         }
 465
 466         if (usb_endpoint_xfer_isoc(desc))
 467                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 468
 469         /*
 470          * We are doing 1:1 mapping for endpoints, meaning
 471          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 472          * so on. We consider the direction bit as part of the physical
 473          * endpoint number. So USB endpoint 0x81 is 0x03.
 474          */
 475         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 476
 477         /*
 478          * We must use the lower 16 TX FIFOs even though
 479          * HW might have more
 480          */
 481         if (dep->direction)
 482                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 483
 484         if (desc->bInterval) {
 485                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 486                 dep->interval = 1 << (desc->bInterval - 1);
 487         }
 488
 489         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 490                         DWC3_DEPCMD_SETEPCONFIG, &params);
 491 }
 492
 493 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 494 {
 495         struct dwc3_gadget_ep_cmd_params params;
 496
 497         memset(&params, 0x00, sizeof(params));
 498
 499         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 500
 501         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 502                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 503 }
 504
 505 /**
 506  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 507  * @dep: endpoint to be initialized
 508  * @desc: USB Endpoint Descriptor
 509  *
 510  * Caller should take care of locking
 511  */
 512 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 513                 const struct usb_endpoint_descriptor *desc,
 514                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 515                 bool ignore)
 516 {
 517         struct dwc3             *dwc = dep->dwc;
 518         u32                     reg;
 519         int                     ret = -ENOMEM;
 520
 521         if (!(dep->flags & DWC3_EP_ENABLED)) {
 522                 ret = dwc3_gadget_start_config(dwc, dep);
 523                 if (ret)
 524                         return ret;
 525         }
 526
 527         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore);
 528         if (ret)
 529                 return ret;
 530
 531         if (!(dep->flags & DWC3_EP_ENABLED)) {
 532                 struct dwc3_trb *trb_st_hw;
 533                 struct dwc3_trb *trb_link;
 534
 535                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 536                 if (ret)
 537                         return ret;
 538
 539                 dep->endpoint.desc = desc;
 540                 dep->comp_desc = comp_desc;
 541                 dep->type = usb_endpoint_type(desc);
 542                 dep->flags |= DWC3_EP_ENABLED;
 543
 544                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 545                 reg |= DWC3_DALEPENA_EP(dep->number);
 546                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 547
 548                 if (!usb_endpoint_xfer_isoc(desc))
 549                         return 0;
 550
 551                 memset(&trb_link, 0, sizeof(trb_link));
 552
 553                 /* Link TRB for ISOC. The HWO bit is never reset */
 554                 trb_st_hw = &dep->trb_pool[0];
 555
 556                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 557
 558                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 559                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 560                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 561                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 562         }
 563
 564         return 0;
 565 }
 566
 567 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
 568 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 569 {
 570         struct dwc3_request             *req;
 571
 572         if (!list_empty(&dep->req_queued)) {
 573                 dwc3_stop_active_transfer(dwc, dep->number);
 574
 575                 /* - giveback all requests to gadget driver */
 576                 while (!list_empty(&dep->req_queued)) {
 577                         req = next_request(&dep->req_queued);
 578
 579                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 580                 }
 581         }
 582
 583         while (!list_empty(&dep->request_list)) {
 584                 req = next_request(&dep->request_list);
 585
 586                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 587         }
 588 }
 589
 590 /**
 591  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 592  * @dep: the endpoint to disable
 593  *
 594  * This function also removes requests which are currently processed ny the
 595  * hardware and those which are not yet scheduled.
 596  * Caller should take care of locking.
 597  */
 598 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 599 {
 600         struct dwc3             *dwc = dep->dwc;
 601         u32                     reg;
 602
 603         dwc3_remove_requests(dwc, dep);
 604
 605         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 606         reg &= ~DWC3_DALEPENA_EP(dep->number);
 607         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 608
 609         dep->stream_capable = false;
 610         dep->endpoint.desc = NULL;
 611         dep->comp_desc = NULL;
 612         dep->type = 0;
 613         dep->flags = 0;
 614
 615         return 0;
 616 }
 617
 618 /* -------------------------------------------------------------------------- */
 619
 620 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 621                 const struct usb_endpoint_descriptor *desc)
 622 {
 623         return -EINVAL;
 624 }
 625
 626 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 627 {
 628         return -EINVAL;
 629 }
 630
 631 /* -------------------------------------------------------------------------- */
 632
 633 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 634                 const struct usb_endpoint_descriptor *desc)
 635 {
 636         struct dwc3_ep                  *dep;
 637         struct dwc3                     *dwc;
 638         unsigned long                   flags;
 639         int                             ret;
 640
 641         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 642                 pr_debug("dwc3: invalid parameters\n");
 643                 return -EINVAL;
 644         }
 645
 646         if (!desc->wMaxPacketSize) {
 647                 pr_debug("dwc3: missing wMaxPacketSize\n");
 648                 return -EINVAL;
 649         }
 650
 651         dep = to_dwc3_ep(ep);
 652         dwc = dep->dwc;
 653
 654         if (dep->flags & DWC3_EP_ENABLED) {
 655                 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
 656                                 dep->name);
 657                 return 0;
 658         }
 659
 660         switch (usb_endpoint_type(desc)) {
 661         case USB_ENDPOINT_XFER_CONTROL:
 662                 strlcat(dep->name, "-control", sizeof(dep->name));
 663                 break;
 664         case USB_ENDPOINT_XFER_ISOC:
 665                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 666                 break;
 667         case USB_ENDPOINT_XFER_BULK:
 668                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 669                 break;
 670         case USB_ENDPOINT_XFER_INT:
 671                 strlcat(dep->name, "-int", sizeof(dep->name));
 672                 break;
 673         default:
 674                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 675         }
 676
 677         dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
 678
 679         spin_lock_irqsave(&dwc->lock, flags);
 680         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false);
 681         spin_unlock_irqrestore(&dwc->lock, flags);
 682
 683         return ret;
 684 }
 685
 686 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 687 {
 688         struct dwc3_ep                  *dep;
 689         struct dwc3                     *dwc;
 690         unsigned long                   flags;
 691         int                             ret;
 692
 693         if (!ep) {
 694                 pr_debug("dwc3: invalid parameters\n");
 695                 return -EINVAL;
 696         }
 697
 698         dep = to_dwc3_ep(ep);
 699         dwc = dep->dwc;
 700
 701         if (!(dep->flags & DWC3_EP_ENABLED)) {
 702                 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
 703                                 dep->name);
 704                 return 0;
 705         }
 706
 707         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 708                         dep->number >> 1,
 709                         (dep->number & 1) ? "in" : "out");
 710
 711         spin_lock_irqsave(&dwc->lock, flags);
 712         ret = __dwc3_gadget_ep_disable(dep);
 713         spin_unlock_irqrestore(&dwc->lock, flags);
 714
 715         return ret;
 716 }
 717
 718 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 719         gfp_t gfp_flags)
 720 {
 721         struct dwc3_request             *req;
 722         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 723         struct dwc3                     *dwc = dep->dwc;
 724
 725         req = kzalloc(sizeof(*req), gfp_flags);
 726         if (!req) {
 727                 dev_err(dwc->dev, "not enough memory\n");
 728                 return NULL;
 729         }
 730
 731         req->epnum      = dep->number;
 732         req->dep        = dep;
 733
 734         return &req->request;
 735 }
 736
 737 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 738                 struct usb_request *request)
 739 {
 740         struct dwc3_request             *req = to_dwc3_request(request);
 741
 742         kfree(req);
 743 }
 744
 745 /**
 746  * dwc3_prepare_one_trb - setup one TRB from one request
 747  * @dep: endpoint for which this request is prepared
 748  * @req: dwc3_request pointer
 749  */
 750 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 751                 struct dwc3_request *req, dma_addr_t dma,
 752                 unsigned length, unsigned last, unsigned chain)
 753 {
 754         struct dwc3             *dwc = dep->dwc;
 755         struct dwc3_trb         *trb;
 756
 757         unsigned int            cur_slot;
 758
 759         dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
 760                         dep->name, req, (unsigned long long) dma,
 761                         length, last ? " last" : "",
 762                         chain ? " chain" : "");
 763
 764         trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 765         cur_slot = dep->free_slot;
 766         dep->free_slot++;
 767
 768         /* Skip the LINK-TRB on ISOC */
 769         if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 770                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 771                 return;
 772
 773         if (!req->trb) {
 774                 dwc3_gadget_move_request_queued(req);
 775                 req->trb = trb;
 776                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 777         }
 778
 779         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 780         trb->bpl = lower_32_bits(dma);
 781         trb->bph = upper_32_bits(dma);
 782
 783         switch (usb_endpoint_type(dep->endpoint.desc)) {
 784         case USB_ENDPOINT_XFER_CONTROL:
 785                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 786                 break;
 787
 788         case USB_ENDPOINT_XFER_ISOC:
 789                 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 790
 791                 if (!req->request.no_interrupt)
 792                         trb->ctrl |= DWC3_TRB_CTRL_IOC;
 793                 break;
 794
 795         case USB_ENDPOINT_XFER_BULK:
 796         case USB_ENDPOINT_XFER_INT:
 797                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 798                 break;
 799         default:
 800                 /*
 801                  * This is only possible with faulty memory because we
 802                  * checked it already :)
 803                  */
 804                 BUG();
 805         }
 806
 807         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 808                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 809                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 810         } else {
 811                 if (chain)
 812                         trb->ctrl |= DWC3_TRB_CTRL_CHN;
 813
 814                 if (last)
 815                         trb->ctrl |= DWC3_TRB_CTRL_LST;
 816         }
 817
 818         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 819                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 820
 821         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 822 }
 823
 824 /*
 825  * dwc3_prepare_trbs - setup TRBs from requests
 826  * @dep: endpoint for which requests are being prepared
 827  * @starting: true if the endpoint is idle and no requests are queued.
 828  *
 829  * The function goes through the requests list and sets up TRBs for the
 830  * transfers. The function returns once there are no more TRBs available or
 831  * it runs out of requests.
 832  */
 833 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 834 {
 835         struct dwc3_request     *req, *n;
 836         u32                     trbs_left;
 837         u32                     max;
 838         unsigned int            last_one = 0;
 839
 840         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 841
 842         /* the first request must not be queued */
 843         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 844
 845         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 846         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 847                 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
 848                 if (trbs_left > max)
 849                         trbs_left = max;
 850         }
 851
 852         /*
 853          * If busy & slot are equal than it is either full or empty. If we are
 854          * starting to process requests then we are empty. Otherwise we are
 855          * full and don't do anything
 856          */
 857         if (!trbs_left) {
 858                 if (!starting)
 859                         return;
 860                 trbs_left = DWC3_TRB_NUM;
 861                 /*
 862                  * In case we start from scratch, we queue the ISOC requests
 863                  * starting from slot 1. This is done because we use ring
 864                  * buffer and have no LST bit to stop us. Instead, we place
 865                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 866                  * after the first request so we start at slot 1 and have
 867                  * 7 requests proceed before we hit the first IOC.
 868                  * Other transfer types don't use the ring buffer and are
 869                  * processed from the first TRB until the last one. Since we
 870                  * don't wrap around we have to start at the beginning.
 871                  */
 872                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 873                         dep->busy_slot = 1;
 874                         dep->free_slot = 1;
 875                 } else {
 876                         dep->busy_slot = 0;
 877                         dep->free_slot = 0;
 878                 }
 879         }
 880
 881         /* The last TRB is a link TRB, not used for xfer */
 882         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 883                 return;
 884
 885         list_for_each_entry_safe(req, n, &dep->request_list, list) {
 886                 unsigned        length;
 887                 dma_addr_t      dma;
 888
 889                 if (req->request.num_mapped_sgs > 0) {
 890                         struct usb_request *request = &req->request;
 891                         struct scatterlist *sg = request->sg;
 892                         struct scatterlist *s;
 893                         int             i;
 894
 895                         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 896                                 unsigned chain = true;
 897
 898                                 length = sg_dma_len(s);
 899                                 dma = sg_dma_address(s);
 900
 901                                 if (i == (request->num_mapped_sgs - 1) ||
 902                                                 sg_is_last(s)) {
 903                                         last_one = true;
 904                                         chain = false;
 905                                 }
 906
 907                                 trbs_left--;
 908                                 if (!trbs_left)
 909                                         last_one = true;
 910
 911                                 if (last_one)
 912                                         chain = false;
 913
 914                                 dwc3_prepare_one_trb(dep, req, dma, length,
 915                                                 last_one, chain);
 916
 917                                 if (last_one)
 918                                         break;
 919                         }
 920                 } else {
 921                         dma = req->request.dma;
 922                         length = req->request.length;
 923                         trbs_left--;
 924
 925                         if (!trbs_left)
 926                                 last_one = 1;
 927
 928                         /* Is this the last request? */
 929                         if (list_is_last(&req->list, &dep->request_list))
 930                                 last_one = 1;
 931
 932                         dwc3_prepare_one_trb(dep, req, dma, length,
 933                                         last_one, false);
 934
 935                         if (last_one)
 936                                 break;
 937                 }
 938         }
 939 }
 940
 941 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 942                 int start_new)
 943 {
 944         struct dwc3_gadget_ep_cmd_params params;
 945         struct dwc3_request             *req;
 946         struct dwc3                     *dwc = dep->dwc;
 947         int                             ret;
 948         u32                             cmd;
 949
 950         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 951                 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
 952                 return -EBUSY;
 953         }
 954         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
 955
 956         /*
 957          * If we are getting here after a short-out-packet we don't enqueue any
 958          * new requests as we try to set the IOC bit only on the last request.
 959          */
 960         if (start_new) {
 961                 if (list_empty(&dep->req_queued))
 962                         dwc3_prepare_trbs(dep, start_new);
 963
 964                 /* req points to the first request which will be sent */
 965                 req = next_request(&dep->req_queued);
 966         } else {
 967                 dwc3_prepare_trbs(dep, start_new);
 968
 969                 /*
 970                  * req points to the first request where HWO changed from 0 to 1
 971                  */
 972                 req = next_request(&dep->req_queued);
 973         }
 974         if (!req) {
 975                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 976                 return 0;
 977         }
 978
 979         memset(&params, 0, sizeof(params));
 980         params.param0 = upper_32_bits(req->trb_dma);
 981         params.param1 = lower_32_bits(req->trb_dma);
 982
 983         if (start_new)
 984                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 985         else
 986                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
 987
 988         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
 989         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 990         if (ret < 0) {
 991                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 992
 993                 /*
 994                  * FIXME we need to iterate over the list of requests
 995                  * here and stop, unmap, free and del each of the linked
 996                  * requests instead of what we do now.
 997                  */
 998                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 999                                 req->direction);
1000                 list_del(&req->list);
1001                 return ret;
1002         }
1003
1004         dep->flags |= DWC3_EP_BUSY;
1005
1006         if (start_new) {
1007                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1008                                 dep->number);
1009                 WARN_ON_ONCE(!dep->resource_index);
1010         }
1011
1012         return 0;
1013 }
1014
1015 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1016                 struct dwc3_ep *dep, u32 cur_uf)
1017 {
1018         u32 uf;
1019
1020         if (list_empty(&dep->request_list)) {
1021                 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1022                         dep->name);
1023                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1024                 return;
1025         }
1026
1027         /* 4 micro frames in the future */
1028         uf = cur_uf + dep->interval * 4;
1029
1030         __dwc3_gadget_kick_transfer(dep, uf, 1);
1031 }
1032
1033 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1034                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1035 {
1036         u32 cur_uf, mask;
1037
1038         mask = ~(dep->interval - 1);
1039         cur_uf = event->parameters & mask;
1040
1041         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1042 }
1043
1044 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1045 {
1046         struct dwc3             *dwc = dep->dwc;
1047         int                     ret;
1048
1049         req->request.actual     = 0;
1050         req->request.status     = -EINPROGRESS;
1051         req->direction          = dep->direction;
1052         req->epnum              = dep->number;
1053
1054         /*
1055          * We only add to our list of requests now and
1056          * start consuming the list once we get XferNotReady
1057          * IRQ.
1058          *
1059          * That way, we avoid doing anything that we don't need
1060          * to do now and defer it until the point we receive a
1061          * particular token from the Host side.
1062          *
1063          * This will also avoid Host cancelling URBs due to too
1064          * many NAKs.
1065          */
1066         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1067                         dep->direction);
1068         if (ret)
1069                 return ret;
1070
1071         list_add_tail(&req->list, &dep->request_list);
1072
1073         /*
1074          * There are a few special cases:
1075          *
1076          * 1. XferNotReady with empty list of requests. We need to kick the
1077          *    transfer here in that situation, otherwise we will be NAKing
1078          *    forever. If we get XferNotReady before gadget driver has a
1079          *    chance to queue a request, we will ACK the IRQ but won't be
1080          *    able to receive the data until the next request is queued.
1081          *    The following code is handling exactly that.
1082          *
1083          */
1084         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1085                 /*
1086                  * If xfernotready is already elapsed and it is a case
1087                  * of isoc transfer, then issue END TRANSFER, so that
1088                  * you can receive xfernotready again and can have
1089                  * notion of current microframe.
1090                  */
1091                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1092                         dwc3_stop_active_transfer(dwc, dep->number);
1093                         return 0;
1094                 }
1095
1096                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1097                 if (ret && ret != -EBUSY)
1098                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1099                                         dep->name);
1100         }
1101
1102         /*
1103          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1104          *    kick the transfer here after queuing a request, otherwise the
1105          *    core may not see the modified TRB(s).
1106          */
1107         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1108                         (dep->flags & DWC3_EP_BUSY) &&
1109                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1110                 WARN_ON_ONCE(!dep->resource_index);
1111                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1112                                 false);
1113                 if (ret && ret != -EBUSY)
1114                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1115                                         dep->name);
1116         }
1117
1118         /*
1119          * 3. Missed ISOC Handling. We need to start isoc transfer on the saved
1120          * uframe number.
1121          */
1122         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1123                 (dep->flags & DWC3_EP_MISSED_ISOC)) {
1124                         __dwc3_gadget_start_isoc(dwc, dep, dep->current_uf);
1125                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1126         }
1127
1128         return 0;
1129 }
1130
1131 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1132         gfp_t gfp_flags)
1133 {
1134         struct dwc3_request             *req = to_dwc3_request(request);
1135         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1136         struct dwc3                     *dwc = dep->dwc;
1137
1138         unsigned long                   flags;
1139
1140         int                             ret;
1141
1142         if (!dep->endpoint.desc) {
1143                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1144                                 request, ep->name);
1145                 return -ESHUTDOWN;
1146         }
1147
1148         dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1149                         request, ep->name, request->length);
1150
1151         spin_lock_irqsave(&dwc->lock, flags);
1152         ret = __dwc3_gadget_ep_queue(dep, req);
1153         spin_unlock_irqrestore(&dwc->lock, flags);
1154
1155         return ret;
1156 }
1157
1158 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1159                 struct usb_request *request)
1160 {
1161         struct dwc3_request             *req = to_dwc3_request(request);
1162         struct dwc3_request             *r = NULL;
1163
1164         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1165         struct dwc3                     *dwc = dep->dwc;
1166
1167         unsigned long                   flags;
1168         int                             ret = 0;
1169
1170         spin_lock_irqsave(&dwc->lock, flags);
1171
1172         list_for_each_entry(r, &dep->request_list, list) {
1173                 if (r == req)
1174                         break;
1175         }
1176
1177         if (r != req) {
1178                 list_for_each_entry(r, &dep->req_queued, list) {
1179                         if (r == req)
1180                                 break;
1181                 }
1182                 if (r == req) {
1183                         /* wait until it is processed */
1184                         dwc3_stop_active_transfer(dwc, dep->number);
1185                         goto out1;
1186                 }
1187                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1188                                 request, ep->name);
1189                 ret = -EINVAL;
1190                 goto out0;
1191         }
1192
1193 out1:
1194         /* giveback the request */
1195         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1196
1197 out0:
1198         spin_unlock_irqrestore(&dwc->lock, flags);
1199
1200         return ret;
1201 }
1202
1203 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1204 {
1205         struct dwc3_gadget_ep_cmd_params        params;
1206         struct dwc3                             *dwc = dep->dwc;
1207         int                                     ret;
1208
1209         memset(&params, 0x00, sizeof(params));
1210
1211         if (value) {
1212                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1213                         DWC3_DEPCMD_SETSTALL, &params);
1214                 if (ret)
1215                         dev_err(dwc->dev, "failed to %s STALL on %s\n",
1216                                         value ? "set" : "clear",
1217                                         dep->name);
1218                 else
1219                         dep->flags |= DWC3_EP_STALL;
1220         } else {
1221                 if (dep->flags & DWC3_EP_WEDGE)
1222                         return 0;
1223
1224                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1225                         DWC3_DEPCMD_CLEARSTALL, &params);
1226                 if (ret)
1227                         dev_err(dwc->dev, "failed to %s STALL on %s\n",
1228                                         value ? "set" : "clear",
1229                                         dep->name);
1230                 else
1231                         dep->flags &= ~DWC3_EP_STALL;
1232         }
1233
1234         return ret;
1235 }
1236
1237 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1238 {
1239         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1240         struct dwc3                     *dwc = dep->dwc;
1241
1242         unsigned long                   flags;
1243
1244         int                             ret;
1245
1246         spin_lock_irqsave(&dwc->lock, flags);
1247
1248         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1249                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1250                 ret = -EINVAL;
1251                 goto out;
1252         }
1253
1254         ret = __dwc3_gadget_ep_set_halt(dep, value);
1255 out:
1256         spin_unlock_irqrestore(&dwc->lock, flags);
1257
1258         return ret;
1259 }
1260
1261 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1262 {
1263         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1264         struct dwc3                     *dwc = dep->dwc;
1265         unsigned long                   flags;
1266
1267         spin_lock_irqsave(&dwc->lock, flags);
1268         dep->flags |= DWC3_EP_WEDGE;
1269         spin_unlock_irqrestore(&dwc->lock, flags);
1270
1271         if (dep->number == 0 || dep->number == 1)
1272                 return dwc3_gadget_ep0_set_halt(ep, 1);
1273         else
1274                 return dwc3_gadget_ep_set_halt(ep, 1);
1275 }
1276
1277 /* -------------------------------------------------------------------------- */
1278
1279 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1280         .bLength        = USB_DT_ENDPOINT_SIZE,
1281         .bDescriptorType = USB_DT_ENDPOINT,
1282         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1283 };
1284
1285 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1286         .enable         = dwc3_gadget_ep0_enable,
1287         .disable        = dwc3_gadget_ep0_disable,
1288         .alloc_request  = dwc3_gadget_ep_alloc_request,
1289         .free_request   = dwc3_gadget_ep_free_request,
1290         .queue          = dwc3_gadget_ep0_queue,
1291         .dequeue        = dwc3_gadget_ep_dequeue,
1292         .set_halt       = dwc3_gadget_ep0_set_halt,
1293         .set_wedge      = dwc3_gadget_ep_set_wedge,
1294 };
1295
1296 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1297         .enable         = dwc3_gadget_ep_enable,
1298         .disable        = dwc3_gadget_ep_disable,
1299         .alloc_request  = dwc3_gadget_ep_alloc_request,
1300         .free_request   = dwc3_gadget_ep_free_request,
1301         .queue          = dwc3_gadget_ep_queue,
1302         .dequeue        = dwc3_gadget_ep_dequeue,
1303         .set_halt       = dwc3_gadget_ep_set_halt,
1304         .set_wedge      = dwc3_gadget_ep_set_wedge,
1305 };
1306
1307 /* -------------------------------------------------------------------------- */
1308
1309 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1310 {
1311         struct dwc3             *dwc = gadget_to_dwc(g);
1312         u32                     reg;
1313
1314         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1315         return DWC3_DSTS_SOFFN(reg);
1316 }
1317
1318 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1319 {
1320         struct dwc3             *dwc = gadget_to_dwc(g);
1321
1322         unsigned long           timeout;
1323         unsigned long           flags;
1324
1325         u32                     reg;
1326
1327         int                     ret = 0;
1328
1329         u8                      link_state;
1330         u8                      speed;
1331
1332         spin_lock_irqsave(&dwc->lock, flags);
1333
1334         /*
1335          * According to the Databook Remote wakeup request should
1336          * be issued only when the device is in early suspend state.
1337          *
1338          * We can check that via USB Link State bits in DSTS register.
1339          */
1340         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1341
1342         speed = reg & DWC3_DSTS_CONNECTSPD;
1343         if (speed == DWC3_DSTS_SUPERSPEED) {
1344                 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1345                 ret = -EINVAL;
1346                 goto out;
1347         }
1348
1349         link_state = DWC3_DSTS_USBLNKST(reg);
1350
1351         switch (link_state) {
1352         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1353         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1354                 break;
1355         default:
1356                 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1357                                 link_state);
1358                 ret = -EINVAL;
1359                 goto out;
1360         }
1361
1362         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1363         if (ret < 0) {
1364                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1365                 goto out;
1366         }
1367
1368         /* Recent versions do this automatically */
1369         if (dwc->revision < DWC3_REVISION_194A) {
1370                 /* write zeroes to Link Change Request */
1371                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1372                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1373                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1374         }
1375
1376         /* poll until Link State changes to ON */
1377         timeout = jiffies + msecs_to_jiffies(100);
1378
1379         while (!time_after(jiffies, timeout)) {
1380                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1381
1382                 /* in HS, means ON */
1383                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1384                         break;
1385         }
1386
1387         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1388                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1389                 ret = -EINVAL;
1390         }
1391
1392 out:
1393         spin_unlock_irqrestore(&dwc->lock, flags);
1394
1395         return ret;
1396 }
1397
1398 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1399                 int is_selfpowered)
1400 {
1401         struct dwc3             *dwc = gadget_to_dwc(g);
1402         unsigned long           flags;
1403
1404         spin_lock_irqsave(&dwc->lock, flags);
1405         dwc->is_selfpowered = !!is_selfpowered;
1406         spin_unlock_irqrestore(&dwc->lock, flags);
1407
1408         return 0;
1409 }
1410
1411 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1412 {
1413         u32                     reg;
1414         u32                     timeout = 500;
1415
1416         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1417         if (is_on) {
1418                 if (dwc->revision <= DWC3_REVISION_187A) {
1419                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1420                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1421                 }
1422
1423                 if (dwc->revision >= DWC3_REVISION_194A)
1424                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1425                 reg |= DWC3_DCTL_RUN_STOP;
1426         } else {
1427                 reg &= ~DWC3_DCTL_RUN_STOP;
1428         }
1429
1430         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1431
1432         do {
1433                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1434                 if (is_on) {
1435                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1436                                 break;
1437                 } else {
1438                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1439                                 break;
1440                 }
1441                 timeout--;
1442                 if (!timeout)
1443                         return -ETIMEDOUT;
1444                 udelay(1);
1445         } while (1);
1446
1447         dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1448                         dwc->gadget_driver
1449                         ? dwc->gadget_driver->function : "no-function",
1450                         is_on ? "connect" : "disconnect");
1451
1452         return 0;
1453 }
1454
1455 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1456 {
1457         struct dwc3             *dwc = gadget_to_dwc(g);
1458         unsigned long           flags;
1459         int                     ret;
1460
1461         is_on = !!is_on;
1462
1463         spin_lock_irqsave(&dwc->lock, flags);
1464         ret = dwc3_gadget_run_stop(dwc, is_on);
1465         spin_unlock_irqrestore(&dwc->lock, flags);
1466
1467         return ret;
1468 }
1469
1470 static int dwc3_gadget_start(struct usb_gadget *g,
1471                 struct usb_gadget_driver *driver)
1472 {
1473         struct dwc3             *dwc = gadget_to_dwc(g);
1474         struct dwc3_ep          *dep;
1475         unsigned long           flags;
1476         int                     ret = 0;
1477         u32                     reg;
1478
1479         spin_lock_irqsave(&dwc->lock, flags);
1480
1481         if (dwc->gadget_driver) {
1482                 dev_err(dwc->dev, "%s is already bound to %s\n",
1483                                 dwc->gadget.name,
1484                                 dwc->gadget_driver->driver.name);
1485                 ret = -EBUSY;
1486                 goto err0;
1487         }
1488
1489         dwc->gadget_driver      = driver;
1490         dwc->gadget.dev.driver  = &driver->driver;
1491
1492         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1493         reg &= ~(DWC3_DCFG_SPEED_MASK);
1494
1495         /**
1496          * WORKAROUND: DWC3 revision < 2.20a have an issue
1497          * which would cause metastability state on Run/Stop
1498          * bit if we try to force the IP to USB2-only mode.
1499          *
1500          * Because of that, we cannot configure the IP to any
1501          * speed other than the SuperSpeed
1502          *
1503          * Refers to:
1504          *
1505          * STAR#9000525659: Clock Domain Crossing on DCTL in
1506          * USB 2.0 Mode
1507          */
1508         if (dwc->revision < DWC3_REVISION_220A)
1509                 reg |= DWC3_DCFG_SUPERSPEED;
1510         else
1511                 reg |= dwc->maximum_speed;
1512         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1513
1514         dwc->start_config_issued = false;
1515
1516         /* Start with SuperSpeed Default */
1517         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1518
1519         dep = dwc->eps[0];
1520         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
1521         if (ret) {
1522                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1523                 goto err0;
1524         }
1525
1526         dep = dwc->eps[1];
1527         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
1528         if (ret) {
1529                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1530                 goto err1;
1531         }
1532
1533         /* begin to receive SETUP packets */
1534         dwc->ep0state = EP0_SETUP_PHASE;
1535         dwc3_ep0_out_start(dwc);
1536
1537         spin_unlock_irqrestore(&dwc->lock, flags);
1538
1539         return 0;
1540
1541 err1:
1542         __dwc3_gadget_ep_disable(dwc->eps[0]);
1543
1544 err0:
1545         spin_unlock_irqrestore(&dwc->lock, flags);
1546
1547         return ret;
1548 }
1549
1550 static int dwc3_gadget_stop(struct usb_gadget *g,
1551                 struct usb_gadget_driver *driver)
1552 {
1553         struct dwc3             *dwc = gadget_to_dwc(g);
1554         unsigned long           flags;
1555
1556         spin_lock_irqsave(&dwc->lock, flags);
1557
1558         __dwc3_gadget_ep_disable(dwc->eps[0]);
1559         __dwc3_gadget_ep_disable(dwc->eps[1]);
1560
1561         dwc->gadget_driver      = NULL;
1562         dwc->gadget.dev.driver  = NULL;
1563
1564         spin_unlock_irqrestore(&dwc->lock, flags);
1565
1566         return 0;
1567 }
1568
1569 static const struct usb_gadget_ops dwc3_gadget_ops = {
1570         .get_frame              = dwc3_gadget_get_frame,
1571         .wakeup                 = dwc3_gadget_wakeup,
1572         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1573         .pullup                 = dwc3_gadget_pullup,
1574         .udc_start              = dwc3_gadget_start,
1575         .udc_stop               = dwc3_gadget_stop,
1576 };
1577
1578 /* -------------------------------------------------------------------------- */
1579
1580 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1581 {
1582         struct dwc3_ep                  *dep;
1583         u8                              epnum;
1584
1585         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1586
1587         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1588                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1589                 if (!dep) {
1590                         dev_err(dwc->dev, "can't allocate endpoint %d\n",
1591                                         epnum);
1592                         return -ENOMEM;
1593                 }
1594
1595                 dep->dwc = dwc;
1596                 dep->number = epnum;
1597                 dwc->eps[epnum] = dep;
1598
1599                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1600                                 (epnum & 1) ? "in" : "out");
1601                 dep->endpoint.name = dep->name;
1602                 dep->direction = (epnum & 1);
1603
1604                 if (epnum == 0 || epnum == 1) {
1605                         dep->endpoint.maxpacket = 512;
1606                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1607                         if (!epnum)
1608                                 dwc->gadget.ep0 = &dep->endpoint;
1609                 } else {
1610                         int             ret;
1611
1612                         dep->endpoint.maxpacket = 1024;
1613                         dep->endpoint.max_streams = 15;
1614                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1615                         list_add_tail(&dep->endpoint.ep_list,
1616                                         &dwc->gadget.ep_list);
1617
1618                         ret = dwc3_alloc_trb_pool(dep);
1619                         if (ret)
1620                                 return ret;
1621                 }
1622
1623                 INIT_LIST_HEAD(&dep->request_list);
1624                 INIT_LIST_HEAD(&dep->req_queued);
1625         }
1626
1627         return 0;
1628 }
1629
1630 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1631 {
1632         struct dwc3_ep                  *dep;
1633         u8                              epnum;
1634
1635         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1636                 dep = dwc->eps[epnum];
1637                 dwc3_free_trb_pool(dep);
1638
1639                 if (epnum != 0 && epnum != 1)
1640                         list_del(&dep->endpoint.ep_list);
1641
1642                 kfree(dep);
1643         }
1644 }
1645
1646 static void dwc3_gadget_release(struct device *dev)
1647 {
1648         dev_dbg(dev, "%s\n", __func__);
1649 }
1650
1651 /* -------------------------------------------------------------------------- */
1652 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1653                 const struct dwc3_event_depevt *event, int status)
1654 {
1655         struct dwc3_request     *req;
1656         struct dwc3_trb         *trb;
1657         unsigned int            count;
1658         unsigned int            s_pkt = 0;
1659         unsigned int            trb_status;
1660
1661         do {
1662                 req = next_request(&dep->req_queued);
1663                 if (!req) {
1664                         WARN_ON_ONCE(1);
1665                         return 1;
1666                 }
1667
1668                 trb = req->trb;
1669
1670                 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1671                         /*
1672                          * We continue despite the error. There is not much we
1673                          * can do. If we don't clean it up we loop forever. If
1674                          * we skip the TRB then it gets overwritten after a
1675                          * while since we use them in a ring buffer. A BUG()
1676                          * would help. Lets hope that if this occurs, someone
1677                          * fixes the root cause instead of looking away :)
1678                          */
1679                         dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1680                                         dep->name, req->trb);
1681                 count = trb->size & DWC3_TRB_SIZE_MASK;
1682
1683                 if (dep->direction) {
1684                         if (count) {
1685                                 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1686                                 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1687                                         dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1688                                                         dep->name);
1689                                         dep->current_uf = event->parameters &
1690                                                 ~(dep->interval - 1);
1691                                         dep->flags |= DWC3_EP_MISSED_ISOC;
1692                                 } else {
1693                                         dev_err(dwc->dev, "incomplete IN transfer %s\n",
1694                                                         dep->name);
1695                                         status = -ECONNRESET;
1696                                 }
1697                         }
1698                 } else {
1699                         if (count && (event->status & DEPEVT_STATUS_SHORT))
1700                                 s_pkt = 1;
1701                 }
1702
1703                 /*
1704                  * We assume here we will always receive the entire data block
1705                  * which we should receive. Meaning, if we program RX to
1706                  * receive 4K but we receive only 2K, we assume that's all we
1707                  * should receive and we simply bounce the request back to the
1708                  * gadget driver for further processing.
1709                  */
1710                 req->request.actual += req->request.length - count;
1711                 dwc3_gadget_giveback(dep, req, status);
1712                 if (s_pkt)
1713                         break;
1714                 if ((event->status & DEPEVT_STATUS_LST) &&
1715                                 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1716                                                 DWC3_TRB_CTRL_HWO)))
1717                         break;
1718                 if ((event->status & DEPEVT_STATUS_IOC) &&
1719                                 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1720                         break;
1721         } while (1);
1722
1723         if ((event->status & DEPEVT_STATUS_IOC) &&
1724                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1725                 return 0;
1726         return 1;
1727 }
1728
1729 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1730                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1731                 int start_new)
1732 {
1733         unsigned                status = 0;
1734         int                     clean_busy;
1735
1736         if (event->status & DEPEVT_STATUS_BUSERR)
1737                 status = -ECONNRESET;
1738
1739         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1740         if (clean_busy)
1741                 dep->flags &= ~DWC3_EP_BUSY;
1742
1743         /*
1744          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1745          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1746          */
1747         if (dwc->revision < DWC3_REVISION_183A) {
1748                 u32             reg;
1749                 int             i;
1750
1751                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1752                         dep = dwc->eps[i];
1753
1754                         if (!(dep->flags & DWC3_EP_ENABLED))
1755                                 continue;
1756
1757                         if (!list_empty(&dep->req_queued))
1758                                 return;
1759                 }
1760
1761                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1762                 reg |= dwc->u1u2;
1763                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1764
1765                 dwc->u1u2 = 0;
1766         }
1767 }
1768
1769 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1770                 const struct dwc3_event_depevt *event)
1771 {
1772         struct dwc3_ep          *dep;
1773         u8                      epnum = event->endpoint_number;
1774
1775         dep = dwc->eps[epnum];
1776
1777         if (!(dep->flags & DWC3_EP_ENABLED))
1778                 return;
1779
1780         dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1781                         dwc3_ep_event_string(event->endpoint_event));
1782
1783         if (epnum == 0 || epnum == 1) {
1784                 dwc3_ep0_interrupt(dwc, event);
1785                 return;
1786         }
1787
1788         switch (event->endpoint_event) {
1789         case DWC3_DEPEVT_XFERCOMPLETE:
1790                 dep->resource_index = 0;
1791
1792                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1793                         dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1794                                         dep->name);
1795                         return;
1796                 }
1797
1798                 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1799                 break;
1800         case DWC3_DEPEVT_XFERINPROGRESS:
1801                 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1802                         dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1803                                         dep->name);
1804                         return;
1805                 }
1806
1807                 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1808                 break;
1809         case DWC3_DEPEVT_XFERNOTREADY:
1810                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1811                         dwc3_gadget_start_isoc(dwc, dep, event);
1812                 } else {
1813                         int ret;
1814
1815                         dev_vdbg(dwc->dev, "%s: reason %s\n",
1816                                         dep->name, event->status &
1817                                         DEPEVT_STATUS_TRANSFER_ACTIVE
1818                                         ? "Transfer Active"
1819                                         : "Transfer Not Active");
1820
1821                         ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1822                         if (!ret || ret == -EBUSY)
1823                                 return;
1824
1825                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1826                                         dep->name);
1827                 }
1828
1829                 break;
1830         case DWC3_DEPEVT_STREAMEVT:
1831                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1832                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1833                                         dep->name);
1834                         return;
1835                 }
1836
1837                 switch (event->status) {
1838                 case DEPEVT_STREAMEVT_FOUND:
1839                         dev_vdbg(dwc->dev, "Stream %d found and started\n",
1840                                         event->parameters);
1841
1842                         break;
1843                 case DEPEVT_STREAMEVT_NOTFOUND:
1844                         /* FALLTHROUGH */
1845                 default:
1846                         dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1847                 }
1848                 break;
1849         case DWC3_DEPEVT_RXTXFIFOEVT:
1850                 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1851                 break;
1852         case DWC3_DEPEVT_EPCMDCMPLT:
1853                 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
1854                 break;
1855         }
1856 }
1857
1858 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1859 {
1860         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1861                 spin_unlock(&dwc->lock);
1862                 dwc->gadget_driver->disconnect(&dwc->gadget);
1863                 spin_lock(&dwc->lock);
1864         }
1865 }
1866
1867 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1868 {
1869         struct dwc3_ep *dep;
1870         struct dwc3_gadget_ep_cmd_params params;
1871         u32 cmd;
1872         int ret;
1873
1874         dep = dwc->eps[epnum];
1875
1876         if (!dep->resource_index)
1877                 return;
1878
1879         /*
1880          * NOTICE: We are violating what the Databook says about the
1881          * EndTransfer command. Ideally we would _always_ wait for the
1882          * EndTransfer Command Completion IRQ, but that's causing too
1883          * much trouble synchronizing between us and gadget driver.
1884          *
1885          * We have discussed this with the IP Provider and it was
1886          * suggested to giveback all requests here, but give HW some
1887          * extra time to synchronize with the interconnect. We're using
1888          * an arbitraty 100us delay for that.
1889          *
1890          * Note also that a similar handling was tested by Synopsys
1891          * (thanks a lot Paul) and nothing bad has come out of it.
1892          * In short, what we're doing is:
1893          *
1894          * - Issue EndTransfer WITH CMDIOC bit set
1895          * - Wait 100us
1896          */
1897
1898         cmd = DWC3_DEPCMD_ENDTRANSFER;
1899         cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1900         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1901         memset(&params, 0, sizeof(params));
1902         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1903         WARN_ON_ONCE(ret);
1904         dep->resource_index = 0;
1905         dep->flags &= ~DWC3_EP_BUSY;
1906         udelay(100);
1907 }
1908
1909 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1910 {
1911         u32 epnum;
1912
1913         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1914                 struct dwc3_ep *dep;
1915
1916                 dep = dwc->eps[epnum];
1917                 if (!(dep->flags & DWC3_EP_ENABLED))
1918                         continue;
1919
1920                 dwc3_remove_requests(dwc, dep);
1921         }
1922 }
1923
1924 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1925 {
1926         u32 epnum;
1927
1928         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1929                 struct dwc3_ep *dep;
1930                 struct dwc3_gadget_ep_cmd_params params;
1931                 int ret;
1932
1933                 dep = dwc->eps[epnum];
1934
1935                 if (!(dep->flags & DWC3_EP_STALL))
1936                         continue;
1937
1938                 dep->flags &= ~DWC3_EP_STALL;
1939
1940                 memset(&params, 0, sizeof(params));
1941                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1942                                 DWC3_DEPCMD_CLEARSTALL, &params);
1943                 WARN_ON_ONCE(ret);
1944         }
1945 }
1946
1947 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1948 {
1949         int                     reg;
1950
1951         dev_vdbg(dwc->dev, "%s\n", __func__);
1952
1953         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1954         reg &= ~DWC3_DCTL_INITU1ENA;
1955         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1956
1957         reg &= ~DWC3_DCTL_INITU2ENA;
1958         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1959
1960         dwc3_disconnect_gadget(dwc);
1961         dwc->start_config_issued = false;
1962
1963         dwc->gadget.speed = USB_SPEED_UNKNOWN;
1964         dwc->setup_packet_pending = false;
1965 }
1966
1967 static void dwc3_gadget_usb3_phy_suspend(struct dwc3 *dwc, int suspend)
1968 {
1969         u32                     reg;
1970
1971         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1972
1973         if (suspend)
1974                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1975         else
1976                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
1977
1978         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1979 }
1980
1981 static void dwc3_gadget_usb2_phy_suspend(struct dwc3 *dwc, int suspend)
1982 {
1983         u32                     reg;
1984
1985         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1986
1987         if (suspend)
1988                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1989         else
1990                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1991
1992         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1993 }
1994
1995 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1996 {
1997         u32                     reg;
1998
1999         dev_vdbg(dwc->dev, "%s\n", __func__);
2000
2001         /*
2002          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2003          * would cause a missing Disconnect Event if there's a
2004          * pending Setup Packet in the FIFO.
2005          *
2006          * There's no suggested workaround on the official Bug
2007          * report, which states that "unless the driver/application
2008          * is doing any special handling of a disconnect event,
2009          * there is no functional issue".
2010          *
2011          * Unfortunately, it turns out that we _do_ some special
2012          * handling of a disconnect event, namely complete all
2013          * pending transfers, notify gadget driver of the
2014          * disconnection, and so on.
2015          *
2016          * Our suggested workaround is to follow the Disconnect
2017          * Event steps here, instead, based on a setup_packet_pending
2018          * flag. Such flag gets set whenever we have a XferNotReady
2019          * event on EP0 and gets cleared on XferComplete for the
2020          * same endpoint.
2021          *
2022          * Refers to:
2023          *
2024          * STAR#9000466709: RTL: Device : Disconnect event not
2025          * generated if setup packet pending in FIFO
2026          */
2027         if (dwc->revision < DWC3_REVISION_188A) {
2028                 if (dwc->setup_packet_pending)
2029                         dwc3_gadget_disconnect_interrupt(dwc);
2030         }
2031
2032         /* after reset -> Default State */
2033         dwc->dev_state = DWC3_DEFAULT_STATE;
2034
2035         /* Recent versions support automatic phy suspend and don't need this */
2036         if (dwc->revision < DWC3_REVISION_194A) {
2037                 /* Resume PHYs */
2038                 dwc3_gadget_usb2_phy_suspend(dwc, false);
2039                 dwc3_gadget_usb3_phy_suspend(dwc, false);
2040         }
2041
2042         if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
2043                 dwc3_disconnect_gadget(dwc);
2044
2045         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2046         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2047         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2048         dwc->test_mode = false;
2049
2050         dwc3_stop_active_transfers(dwc);
2051         dwc3_clear_stall_all_ep(dwc);
2052         dwc->start_config_issued = false;
2053
2054         /* Reset device address to zero */
2055         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2056         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2057         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2058 }
2059
2060 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2061 {
2062         u32 reg;
2063         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2064
2065         /*
2066          * We change the clock only at SS but I dunno why I would want to do
2067          * this. Maybe it becomes part of the power saving plan.
2068          */
2069
2070         if (speed != DWC3_DSTS_SUPERSPEED)
2071                 return;
2072
2073         /*
2074          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2075          * each time on Connect Done.
2076          */
2077         if (!usb30_clock)
2078                 return;
2079
2080         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2081         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2082         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2083 }
2084
2085 static void dwc3_gadget_phy_suspend(struct dwc3 *dwc, u8 speed)
2086 {
2087         switch (speed) {
2088         case USB_SPEED_SUPER:
2089                 dwc3_gadget_usb2_phy_suspend(dwc, true);
2090                 break;
2091         case USB_SPEED_HIGH:
2092         case USB_SPEED_FULL:
2093         case USB_SPEED_LOW:
2094                 dwc3_gadget_usb3_phy_suspend(dwc, true);
2095                 break;
2096         }
2097 }
2098
2099 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2100 {
2101         struct dwc3_gadget_ep_cmd_params params;
2102         struct dwc3_ep          *dep;
2103         int                     ret;
2104         u32                     reg;
2105         u8                      speed;
2106
2107         dev_vdbg(dwc->dev, "%s\n", __func__);
2108
2109         memset(&params, 0x00, sizeof(params));
2110
2111         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2112         speed = reg & DWC3_DSTS_CONNECTSPD;
2113         dwc->speed = speed;
2114
2115         dwc3_update_ram_clk_sel(dwc, speed);
2116
2117         switch (speed) {
2118         case DWC3_DCFG_SUPERSPEED:
2119                 /*
2120                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2121                  * would cause a missing USB3 Reset event.
2122                  *
2123                  * In such situations, we should force a USB3 Reset
2124                  * event by calling our dwc3_gadget_reset_interrupt()
2125                  * routine.
2126                  *
2127                  * Refers to:
2128                  *
2129                  * STAR#9000483510: RTL: SS : USB3 reset event may
2130                  * not be generated always when the link enters poll
2131                  */
2132                 if (dwc->revision < DWC3_REVISION_190A)
2133                         dwc3_gadget_reset_interrupt(dwc);
2134
2135                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2136                 dwc->gadget.ep0->maxpacket = 512;
2137                 dwc->gadget.speed = USB_SPEED_SUPER;
2138                 break;
2139         case DWC3_DCFG_HIGHSPEED:
2140                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2141                 dwc->gadget.ep0->maxpacket = 64;
2142                 dwc->gadget.speed = USB_SPEED_HIGH;
2143                 break;
2144         case DWC3_DCFG_FULLSPEED2:
2145         case DWC3_DCFG_FULLSPEED1:
2146                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2147                 dwc->gadget.ep0->maxpacket = 64;
2148                 dwc->gadget.speed = USB_SPEED_FULL;
2149                 break;
2150         case DWC3_DCFG_LOWSPEED:
2151                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2152                 dwc->gadget.ep0->maxpacket = 8;
2153                 dwc->gadget.speed = USB_SPEED_LOW;
2154                 break;
2155         }
2156
2157         /* Enable USB2 LPM Capability */
2158
2159         if ((dwc->revision > DWC3_REVISION_194A)
2160                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2161                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2162                 reg |= DWC3_DCFG_LPM_CAP;
2163                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2164
2165                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2166                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2167
2168                 /* TODO: This should be configurable */
2169                 reg |= DWC3_DCTL_HIRD_THRES(28);
2170
2171                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2172         }
2173
2174         /* Recent versions support automatic phy suspend and don't need this */
2175         if (dwc->revision < DWC3_REVISION_194A) {
2176                 /* Suspend unneeded PHY */
2177                 dwc3_gadget_phy_suspend(dwc, dwc->gadget.speed);
2178         }
2179
2180         dep = dwc->eps[0];
2181         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
2182         if (ret) {
2183                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2184                 return;
2185         }
2186
2187         dep = dwc->eps[1];
2188         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
2189         if (ret) {
2190                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2191                 return;
2192         }
2193
2194         /*
2195          * Configure PHY via GUSB3PIPECTLn if required.
2196          *
2197          * Update GTXFIFOSIZn
2198          *
2199          * In both cases reset values should be sufficient.
2200          */
2201 }
2202
2203 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2204 {
2205         dev_vdbg(dwc->dev, "%s\n", __func__);
2206
2207         /*
2208          * TODO take core out of low power mode when that's
2209          * implemented.
2210          */
2211
2212         dwc->gadget_driver->resume(&dwc->gadget);
2213 }
2214
2215 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2216                 unsigned int evtinfo)
2217 {
2218         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2219
2220         /*
2221          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2222          * on the link partner, the USB session might do multiple entry/exit
2223          * of low power states before a transfer takes place.
2224          *
2225          * Due to this problem, we might experience lower throughput. The
2226          * suggested workaround is to disable DCTL[12:9] bits if we're
2227          * transitioning from U1/U2 to U0 and enable those bits again
2228          * after a transfer completes and there are no pending transfers
2229          * on any of the enabled endpoints.
2230          *
2231          * This is the first half of that workaround.
2232          *
2233          * Refers to:
2234          *
2235          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2236          * core send LGO_Ux entering U0
2237          */
2238         if (dwc->revision < DWC3_REVISION_183A) {
2239                 if (next == DWC3_LINK_STATE_U0) {
2240                         u32     u1u2;
2241                         u32     reg;
2242
2243                         switch (dwc->link_state) {
2244                         case DWC3_LINK_STATE_U1:
2245                         case DWC3_LINK_STATE_U2:
2246                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2247                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2248                                                 | DWC3_DCTL_ACCEPTU2ENA
2249                                                 | DWC3_DCTL_INITU1ENA
2250                                                 | DWC3_DCTL_ACCEPTU1ENA);
2251
2252                                 if (!dwc->u1u2)
2253                                         dwc->u1u2 = reg & u1u2;
2254
2255                                 reg &= ~u1u2;
2256
2257                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2258                                 break;
2259                         default:
2260                                 /* do nothing */
2261                                 break;
2262                         }
2263                 }
2264         }
2265
2266         dwc->link_state = next;
2267
2268         dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
2269 }
2270
2271 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2272                 const struct dwc3_event_devt *event)
2273 {
2274         switch (event->type) {
2275         case DWC3_DEVICE_EVENT_DISCONNECT:
2276                 dwc3_gadget_disconnect_interrupt(dwc);
2277                 break;
2278         case DWC3_DEVICE_EVENT_RESET:
2279                 dwc3_gadget_reset_interrupt(dwc);
2280                 break;
2281         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2282                 dwc3_gadget_conndone_interrupt(dwc);
2283                 break;
2284         case DWC3_DEVICE_EVENT_WAKEUP:
2285                 dwc3_gadget_wakeup_interrupt(dwc);
2286                 break;
2287         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2288                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2289                 break;
2290         case DWC3_DEVICE_EVENT_EOPF:
2291                 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2292                 break;
2293         case DWC3_DEVICE_EVENT_SOF:
2294                 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2295                 break;
2296         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2297                 dev_vdbg(dwc->dev, "Erratic Error\n");
2298                 break;
2299         case DWC3_DEVICE_EVENT_CMD_CMPL:
2300                 dev_vdbg(dwc->dev, "Command Complete\n");
2301                 break;
2302         case DWC3_DEVICE_EVENT_OVERFLOW:
2303                 dev_vdbg(dwc->dev, "Overflow\n");
2304                 break;
2305         default:
2306                 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2307         }
2308 }
2309
2310 static void dwc3_process_event_entry(struct dwc3 *dwc,
2311                 const union dwc3_event *event)
2312 {
2313         /* Endpoint IRQ, handle it and return early */
2314         if (event->type.is_devspec == 0) {
2315                 /* depevt */
2316                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2317         }
2318
2319         switch (event->type.type) {
2320         case DWC3_EVENT_TYPE_DEV:
2321                 dwc3_gadget_interrupt(dwc, &event->devt);
2322                 break;
2323         /* REVISIT what to do with Carkit and I2C events ? */
2324         default:
2325                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2326         }
2327 }
2328
2329 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2330 {
2331         struct dwc3_event_buffer *evt;
2332         int left;
2333         u32 count;
2334
2335         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2336         count &= DWC3_GEVNTCOUNT_MASK;
2337         if (!count)
2338                 return IRQ_NONE;
2339
2340         evt = dwc->ev_buffs[buf];
2341         left = count;
2342
2343         while (left > 0) {
2344                 union dwc3_event event;
2345
2346                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2347
2348                 dwc3_process_event_entry(dwc, &event);
2349                 /*
2350                  * XXX we wrap around correctly to the next entry as almost all
2351                  * entries are 4 bytes in size. There is one entry which has 12
2352                  * bytes which is a regular entry followed by 8 bytes data. ATM
2353                  * I don't know how things are organized if were get next to the
2354                  * a boundary so I worry about that once we try to handle that.
2355                  */
2356                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2357                 left -= 4;
2358
2359                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2360         }
2361
2362         return IRQ_HANDLED;
2363 }
2364
2365 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2366 {
2367         struct dwc3                     *dwc = _dwc;
2368         int                             i;
2369         irqreturn_t                     ret = IRQ_NONE;
2370
2371         spin_lock(&dwc->lock);
2372
2373         for (i = 0; i < dwc->num_event_buffers; i++) {
2374                 irqreturn_t status;
2375
2376                 status = dwc3_process_event_buf(dwc, i);
2377                 if (status == IRQ_HANDLED)
2378                         ret = status;
2379         }
2380
2381         spin_unlock(&dwc->lock);
2382
2383         return ret;
2384 }
2385
2386 /**
2387  * dwc3_gadget_init - Initializes gadget related registers
2388  * @dwc: pointer to our controller context structure
2389  *
2390  * Returns 0 on success otherwise negative errno.
2391  */
2392 int dwc3_gadget_init(struct dwc3 *dwc)
2393 {
2394         u32                                     reg;
2395         int                                     ret;
2396         int                                     irq;
2397
2398         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2399                         &dwc->ctrl_req_addr, GFP_KERNEL);
2400         if (!dwc->ctrl_req) {
2401                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2402                 ret = -ENOMEM;
2403                 goto err0;
2404         }
2405
2406         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2407                         &dwc->ep0_trb_addr, GFP_KERNEL);
2408         if (!dwc->ep0_trb) {
2409                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2410                 ret = -ENOMEM;
2411                 goto err1;
2412         }
2413
2414         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2415         if (!dwc->setup_buf) {
2416                 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2417                 ret = -ENOMEM;
2418                 goto err2;
2419         }
2420
2421         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2422                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2423                         GFP_KERNEL);
2424         if (!dwc->ep0_bounce) {
2425                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2426                 ret = -ENOMEM;
2427                 goto err3;
2428         }
2429
2430         dev_set_name(&dwc->gadget.dev, "gadget");
2431
2432         dwc->gadget.ops                 = &dwc3_gadget_ops;
2433         dwc->gadget.max_speed           = USB_SPEED_SUPER;
2434         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2435         dwc->gadget.dev.parent          = dwc->dev;
2436         dwc->gadget.sg_supported        = true;
2437
2438         dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
2439
2440         dwc->gadget.dev.dma_parms       = dwc->dev->dma_parms;
2441         dwc->gadget.dev.dma_mask        = dwc->dev->dma_mask;
2442         dwc->gadget.dev.release         = dwc3_gadget_release;
2443         dwc->gadget.name                = "dwc3-gadget";
2444
2445         /*
2446          * REVISIT: Here we should clear all pending IRQs to be
2447          * sure we're starting from a well known location.
2448          */
2449
2450         ret = dwc3_gadget_init_endpoints(dwc);
2451         if (ret)
2452                 goto err4;
2453
2454         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2455
2456         ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
2457                         "dwc3", dwc);
2458         if (ret) {
2459                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2460                                 irq, ret);
2461                 goto err5;
2462         }
2463
2464         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2465         reg |= DWC3_DCFG_LPM_CAP;
2466         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2467
2468         /* Enable all but Start and End of Frame IRQs */
2469         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2470                         DWC3_DEVTEN_EVNTOVERFLOWEN |
2471                         DWC3_DEVTEN_CMDCMPLTEN |
2472                         DWC3_DEVTEN_ERRTICERREN |
2473                         DWC3_DEVTEN_WKUPEVTEN |
2474                         DWC3_DEVTEN_ULSTCNGEN |
2475                         DWC3_DEVTEN_CONNECTDONEEN |
2476                         DWC3_DEVTEN_USBRSTEN |
2477                         DWC3_DEVTEN_DISCONNEVTEN);
2478         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2479
2480         /* automatic phy suspend only on recent versions */
2481         if (dwc->revision >= DWC3_REVISION_194A) {
2482                 dwc3_gadget_usb2_phy_suspend(dwc, false);
2483                 dwc3_gadget_usb3_phy_suspend(dwc, false);
2484         }
2485
2486         ret = device_register(&dwc->gadget.dev);
2487         if (ret) {
2488                 dev_err(dwc->dev, "failed to register gadget device\n");
2489                 put_device(&dwc->gadget.dev);
2490                 goto err6;
2491         }
2492
2493         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2494         if (ret) {
2495                 dev_err(dwc->dev, "failed to register udc\n");
2496                 goto err7;
2497         }
2498
2499         return 0;
2500
2501 err7:
2502         device_unregister(&dwc->gadget.dev);
2503
2504 err6:
2505         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2506         free_irq(irq, dwc);
2507
2508 err5:
2509         dwc3_gadget_free_endpoints(dwc);
2510
2511 err4:
2512         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2513                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2514
2515 err3:
2516         kfree(dwc->setup_buf);
2517
2518 err2:
2519         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2520                         dwc->ep0_trb, dwc->ep0_trb_addr);
2521
2522 err1:
2523         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2524                         dwc->ctrl_req, dwc->ctrl_req_addr);
2525
2526 err0:
2527         return ret;
2528 }
2529
2530 void dwc3_gadget_exit(struct dwc3 *dwc)
2531 {
2532         int                     irq;
2533
2534         usb_del_gadget_udc(&dwc->gadget);
2535         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2536
2537         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2538         free_irq(irq, dwc);
2539
2540         dwc3_gadget_free_endpoints(dwc);
2541
2542         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2543                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2544
2545         kfree(dwc->setup_buf);
2546
2547         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2548                         dwc->ep0_trb, dwc->ep0_trb_addr);
2549
2550         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2551                         dwc->ctrl_req, dwc->ctrl_req_addr);
2552
2553         device_unregister(&dwc->gadget.dev);
2554 }