drivers/usb/gadget/s3c-hsudc.c

   1 /* linux/drivers/usb/gadget/s3c-hsudc.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S3C24XX USB 2.0 High-speed USB controller gadget driver
   7  *
   8  * The S3C24XX USB 2.0 high-speed USB controller supports upto 9 endpoints.
   9  * Each endpoint can be configured as either in or out endpoint. Endpoints
  10  * can be configured for Bulk or Interrupt transfer mode.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15 */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/delay.h>
  24 #include <linux/io.h>
  25 #include <linux/slab.h>
  26 #include <linux/clk.h>
  27 #include <linux/err.h>
  28 #include <linux/usb/ch9.h>
  29 #include <linux/usb/gadget.h>
  30 #include <linux/usb/otg.h>
  31 #include <linux/prefetch.h>
  32 #include <linux/platform_data/s3c-hsudc.h>
  33 #include <linux/regulator/consumer.h>
  34 #include <linux/pm_runtime.h>
  35
  36 #include <mach/regs-s3c2443-clock.h>
  37
  38 #define S3C_HSUDC_REG(x)        (x)
  39
  40 /* Non-Indexed Registers */
  41 #define S3C_IR                          S3C_HSUDC_REG(0x00) /* Index Register */
  42 #define S3C_EIR                         S3C_HSUDC_REG(0x04) /* EP Intr Status */
  43 #define S3C_EIR_EP0                     (1<<0)
  44 #define S3C_EIER                        S3C_HSUDC_REG(0x08) /* EP Intr Enable */
  45 #define S3C_FAR                         S3C_HSUDC_REG(0x0c) /* Gadget Address */
  46 #define S3C_FNR                         S3C_HSUDC_REG(0x10) /* Frame Number */
  47 #define S3C_EDR                         S3C_HSUDC_REG(0x14) /* EP Direction */
  48 #define S3C_TR                          S3C_HSUDC_REG(0x18) /* Test Register */
  49 #define S3C_SSR                         S3C_HSUDC_REG(0x1c) /* System Status */
  50 #define S3C_SSR_DTZIEN_EN               (0xff8f)
  51 #define S3C_SSR_ERR                     (0xff80)
  52 #define S3C_SSR_VBUSON                  (1 << 8)
  53 #define S3C_SSR_HSP                     (1 << 4)
  54 #define S3C_SSR_SDE                     (1 << 3)
  55 #define S3C_SSR_RESUME                  (1 << 2)
  56 #define S3C_SSR_SUSPEND                 (1 << 1)
  57 #define S3C_SSR_RESET                   (1 << 0)
  58 #define S3C_SCR                         S3C_HSUDC_REG(0x20) /* System Control */
  59 #define S3C_SCR_DTZIEN_EN               (1 << 14)
  60 #define S3C_SCR_RRD_EN                  (1 << 5)
  61 #define S3C_SCR_SUS_EN                  (1 << 1)
  62 #define S3C_SCR_RST_EN                  (1 << 0)
  63 #define S3C_EP0SR                       S3C_HSUDC_REG(0x24) /* EP0 Status */
  64 #define S3C_EP0SR_EP0_LWO               (1 << 6)
  65 #define S3C_EP0SR_STALL                 (1 << 4)
  66 #define S3C_EP0SR_TX_SUCCESS            (1 << 1)
  67 #define S3C_EP0SR_RX_SUCCESS            (1 << 0)
  68 #define S3C_EP0CR                       S3C_HSUDC_REG(0x28) /* EP0 Control */
  69 #define S3C_BR(_x)                      S3C_HSUDC_REG(0x60 + (_x * 4))
  70
  71 /* Indexed Registers */
  72 #define S3C_ESR                         S3C_HSUDC_REG(0x2c) /* EPn Status */
  73 #define S3C_ESR_FLUSH                   (1 << 6)
  74 #define S3C_ESR_STALL                   (1 << 5)
  75 #define S3C_ESR_LWO                     (1 << 4)
  76 #define S3C_ESR_PSIF_ONE                (1 << 2)
  77 #define S3C_ESR_PSIF_TWO                (2 << 2)
  78 #define S3C_ESR_TX_SUCCESS              (1 << 1)
  79 #define S3C_ESR_RX_SUCCESS              (1 << 0)
  80 #define S3C_ECR                         S3C_HSUDC_REG(0x30) /* EPn Control */
  81 #define S3C_ECR_DUEN                    (1 << 7)
  82 #define S3C_ECR_FLUSH                   (1 << 6)
  83 #define S3C_ECR_STALL                   (1 << 1)
  84 #define S3C_ECR_IEMS                    (1 << 0)
  85 #define S3C_BRCR                        S3C_HSUDC_REG(0x34) /* Read Count */
  86 #define S3C_BWCR                        S3C_HSUDC_REG(0x38) /* Write Count */
  87 #define S3C_MPR                         S3C_HSUDC_REG(0x3c) /* Max Pkt Size */
  88
  89 #define WAIT_FOR_SETUP                  (0)
  90 #define DATA_STATE_XMIT                 (1)
  91 #define DATA_STATE_RECV                 (2)
  92
  93 static const char * const s3c_hsudc_supply_names[] = {
  94         "vdda",         /* analog phy supply, 3.3V */
  95         "vddi",         /* digital phy supply, 1.2V */
  96         "vddosc",       /* oscillator supply, 1.8V - 3.3V */
  97 };
  98
  99 /**
 100  * struct s3c_hsudc_ep - Endpoint representation used by driver.
 101  * @ep: USB gadget layer representation of device endpoint.
 102  * @name: Endpoint name (as required by ep autoconfiguration).
 103  * @dev: Reference to the device controller to which this EP belongs.
 104  * @desc: Endpoint descriptor obtained from the gadget driver.
 105  * @queue: Transfer request queue for the endpoint.
 106  * @stopped: Maintains state of endpoint, set if EP is halted.
 107  * @bEndpointAddress: EP address (including direction bit).
 108  * @fifo: Base address of EP FIFO.
 109  */
 110 struct s3c_hsudc_ep {
 111         struct usb_ep ep;
 112         char name[20];
 113         struct s3c_hsudc *dev;
 114         struct list_head queue;
 115         u8 stopped;
 116         u8 wedge;
 117         u8 bEndpointAddress;
 118         void __iomem *fifo;
 119 };
 120
 121 /**
 122  * struct s3c_hsudc_req - Driver encapsulation of USB gadget transfer request.
 123  * @req: Reference to USB gadget transfer request.
 124  * @queue: Used for inserting this request to the endpoint request queue.
 125  */
 126 struct s3c_hsudc_req {
 127         struct usb_request req;
 128         struct list_head queue;
 129 };
 130
 131 /**
 132  * struct s3c_hsudc - Driver's abstraction of the device controller.
 133  * @gadget: Instance of usb_gadget which is referenced by gadget driver.
 134  * @driver: Reference to currenty active gadget driver.
 135  * @dev: The device reference used by probe function.
 136  * @lock: Lock to synchronize the usage of Endpoints (EP's are indexed).
 137  * @regs: Remapped base address of controller's register space.
 138  * irq: IRQ number used by the controller.
 139  * uclk: Reference to the controller clock.
 140  * ep0state: Current state of EP0.
 141  * ep: List of endpoints supported by the controller.
 142  */
 143 struct s3c_hsudc {
 144         struct usb_gadget gadget;
 145         struct usb_gadget_driver *driver;
 146         struct device *dev;
 147         struct s3c24xx_hsudc_platdata *pd;
 148         struct usb_phy *transceiver;
 149         struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsudc_supply_names)];
 150         spinlock_t lock;
 151         void __iomem *regs;
 152         int irq;
 153         struct clk *uclk;
 154         int ep0state;
 155         struct s3c_hsudc_ep ep[];
 156 };
 157
 158 #define ep_maxpacket(_ep)       ((_ep)->ep.maxpacket)
 159 #define ep_is_in(_ep)           ((_ep)->bEndpointAddress & USB_DIR_IN)
 160 #define ep_index(_ep)           ((_ep)->bEndpointAddress & \
 161                                         USB_ENDPOINT_NUMBER_MASK)
 162
 163 static const char driver_name[] = "s3c-udc";
 164 static const char ep0name[] = "ep0-control";
 165
 166 static inline struct s3c_hsudc_req *our_req(struct usb_request *req)
 167 {
 168         return container_of(req, struct s3c_hsudc_req, req);
 169 }
 170
 171 static inline struct s3c_hsudc_ep *our_ep(struct usb_ep *ep)
 172 {
 173         return container_of(ep, struct s3c_hsudc_ep, ep);
 174 }
 175
 176 static inline struct s3c_hsudc *to_hsudc(struct usb_gadget *gadget)
 177 {
 178         return container_of(gadget, struct s3c_hsudc, gadget);
 179 }
 180
 181 static inline void set_index(struct s3c_hsudc *hsudc, int ep_addr)
 182 {
 183         ep_addr &= USB_ENDPOINT_NUMBER_MASK;
 184         writel(ep_addr, hsudc->regs + S3C_IR);
 185 }
 186
 187 static inline void __orr32(void __iomem *ptr, u32 val)
 188 {
 189         writel(readl(ptr) | val, ptr);
 190 }
 191
 192 static void s3c_hsudc_init_phy(void)
 193 {
 194         u32 cfg;
 195
 196         cfg = readl(S3C2443_PWRCFG) | S3C2443_PWRCFG_USBPHY;
 197         writel(cfg, S3C2443_PWRCFG);
 198
 199         cfg = readl(S3C2443_URSTCON);
 200         cfg |= (S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
 201         writel(cfg, S3C2443_URSTCON);
 202         mdelay(1);
 203
 204         cfg = readl(S3C2443_URSTCON);
 205         cfg &= ~(S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
 206         writel(cfg, S3C2443_URSTCON);
 207
 208         cfg = readl(S3C2443_PHYCTRL);
 209         cfg &= ~(S3C2443_PHYCTRL_CLKSEL | S3C2443_PHYCTRL_DSPORT);
 210         cfg |= (S3C2443_PHYCTRL_EXTCLK | S3C2443_PHYCTRL_PLLSEL);
 211         writel(cfg, S3C2443_PHYCTRL);
 212
 213         cfg = readl(S3C2443_PHYPWR);
 214         cfg &= ~(S3C2443_PHYPWR_FSUSPEND | S3C2443_PHYPWR_PLL_PWRDN |
 215                 S3C2443_PHYPWR_XO_ON | S3C2443_PHYPWR_PLL_REFCLK |
 216                 S3C2443_PHYPWR_ANALOG_PD);
 217         cfg |= S3C2443_PHYPWR_COMMON_ON;
 218         writel(cfg, S3C2443_PHYPWR);
 219
 220         cfg = readl(S3C2443_UCLKCON);
 221         cfg |= (S3C2443_UCLKCON_DETECT_VBUS | S3C2443_UCLKCON_FUNC_CLKEN |
 222                 S3C2443_UCLKCON_TCLKEN);
 223         writel(cfg, S3C2443_UCLKCON);
 224 }
 225
 226 static void s3c_hsudc_uninit_phy(void)
 227 {
 228         u32 cfg;
 229
 230         cfg = readl(S3C2443_PWRCFG) & ~S3C2443_PWRCFG_USBPHY;
 231         writel(cfg, S3C2443_PWRCFG);
 232
 233         writel(S3C2443_PHYPWR_FSUSPEND, S3C2443_PHYPWR);
 234
 235         cfg = readl(S3C2443_UCLKCON) & ~S3C2443_UCLKCON_FUNC_CLKEN;
 236         writel(cfg, S3C2443_UCLKCON);
 237 }
 238
 239 /**
 240  * s3c_hsudc_complete_request - Complete a transfer request.
 241  * @hsep: Endpoint to which the request belongs.
 242  * @hsreq: Transfer request to be completed.
 243  * @status: Transfer completion status for the transfer request.
 244  */
 245 static void s3c_hsudc_complete_request(struct s3c_hsudc_ep *hsep,
 246                                 struct s3c_hsudc_req *hsreq, int status)
 247 {
 248         unsigned int stopped = hsep->stopped;
 249         struct s3c_hsudc *hsudc = hsep->dev;
 250
 251         list_del_init(&hsreq->queue);
 252         hsreq->req.status = status;
 253
 254         if (!ep_index(hsep)) {
 255                 hsudc->ep0state = WAIT_FOR_SETUP;
 256                 hsep->bEndpointAddress &= ~USB_DIR_IN;
 257         }
 258
 259         hsep->stopped = 1;
 260         spin_unlock(&hsudc->lock);
 261         if (hsreq->req.complete != NULL)
 262                 hsreq->req.complete(&hsep->ep, &hsreq->req);
 263         spin_lock(&hsudc->lock);
 264         hsep->stopped = stopped;
 265 }
 266
 267 /**
 268  * s3c_hsudc_nuke_ep - Terminate all requests queued for a endpoint.
 269  * @hsep: Endpoint for which queued requests have to be terminated.
 270  * @status: Transfer completion status for the transfer request.
 271  */
 272 static void s3c_hsudc_nuke_ep(struct s3c_hsudc_ep *hsep, int status)
 273 {
 274         struct s3c_hsudc_req *hsreq;
 275
 276         while (!list_empty(&hsep->queue)) {
 277                 hsreq = list_entry(hsep->queue.next,
 278                                 struct s3c_hsudc_req, queue);
 279                 s3c_hsudc_complete_request(hsep, hsreq, status);
 280         }
 281 }
 282
 283 /**
 284  * s3c_hsudc_stop_activity - Stop activity on all endpoints.
 285  * @hsudc: Device controller for which EP activity is to be stopped.
 286  *
 287  * All the endpoints are stopped and any pending transfer requests if any on
 288  * the endpoint are terminated.
 289  */
 290 static void s3c_hsudc_stop_activity(struct s3c_hsudc *hsudc)
 291 {
 292         struct s3c_hsudc_ep *hsep;
 293         int epnum;
 294
 295         hsudc->gadget.speed = USB_SPEED_UNKNOWN;
 296
 297         for (epnum = 0; epnum < hsudc->pd->epnum; epnum++) {
 298                 hsep = &hsudc->ep[epnum];
 299                 hsep->stopped = 1;
 300                 s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
 301         }
 302 }
 303
 304 /**
 305  * s3c_hsudc_read_setup_pkt - Read the received setup packet from EP0 fifo.
 306  * @hsudc: Device controller from which setup packet is to be read.
 307  * @buf: The buffer into which the setup packet is read.
 308  *
 309  * The setup packet received in the EP0 fifo is read and stored into a
 310  * given buffer address.
 311  */
 312
 313 static void s3c_hsudc_read_setup_pkt(struct s3c_hsudc *hsudc, u16 *buf)
 314 {
 315         int count;
 316
 317         count = readl(hsudc->regs + S3C_BRCR);
 318         while (count--)
 319                 *buf++ = (u16)readl(hsudc->regs + S3C_BR(0));
 320
 321         writel(S3C_EP0SR_RX_SUCCESS, hsudc->regs + S3C_EP0SR);
 322 }
 323
 324 /**
 325  * s3c_hsudc_write_fifo - Write next chunk of transfer data to EP fifo.
 326  * @hsep: Endpoint to which the data is to be written.
 327  * @hsreq: Transfer request from which the next chunk of data is written.
 328  *
 329  * Write the next chunk of data from a transfer request to the endpoint FIFO.
 330  * If the transfer request completes, 1 is returned, otherwise 0 is returned.
 331  */
 332 static int s3c_hsudc_write_fifo(struct s3c_hsudc_ep *hsep,
 333                                 struct s3c_hsudc_req *hsreq)
 334 {
 335         u16 *buf;
 336         u32 max = ep_maxpacket(hsep);
 337         u32 count, length;
 338         bool is_last;
 339         void __iomem *fifo = hsep->fifo;
 340
 341         buf = hsreq->req.buf + hsreq->req.actual;
 342         prefetch(buf);
 343
 344         length = hsreq->req.length - hsreq->req.actual;
 345         length = min(length, max);
 346         hsreq->req.actual += length;
 347
 348         writel(length, hsep->dev->regs + S3C_BWCR);
 349         for (count = 0; count < length; count += 2)
 350                 writel(*buf++, fifo);
 351
 352         if (count != max) {
 353                 is_last = true;
 354         } else {
 355                 if (hsreq->req.length != hsreq->req.actual || hsreq->req.zero)
 356                         is_last = false;
 357                 else
 358                         is_last = true;
 359         }
 360
 361         if (is_last) {
 362                 s3c_hsudc_complete_request(hsep, hsreq, 0);
 363                 return 1;
 364         }
 365
 366         return 0;
 367 }
 368
 369 /**
 370  * s3c_hsudc_read_fifo - Read the next chunk of data from EP fifo.
 371  * @hsep: Endpoint from which the data is to be read.
 372  * @hsreq: Transfer request to which the next chunk of data read is written.
 373  *
 374  * Read the next chunk of data from the endpoint FIFO and a write it to the
 375  * transfer request buffer. If the transfer request completes, 1 is returned,
 376  * otherwise 0 is returned.
 377  */
 378 static int s3c_hsudc_read_fifo(struct s3c_hsudc_ep *hsep,
 379                                 struct s3c_hsudc_req *hsreq)
 380 {
 381         struct s3c_hsudc *hsudc = hsep->dev;
 382         u32 csr, offset;
 383         u16 *buf, word;
 384         u32 buflen, rcnt, rlen;
 385         void __iomem *fifo = hsep->fifo;
 386         u32 is_short = 0;
 387
 388         offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
 389         csr = readl(hsudc->regs + offset);
 390         if (!(csr & S3C_ESR_RX_SUCCESS))
 391                 return -EINVAL;
 392
 393         buf = hsreq->req.buf + hsreq->req.actual;
 394         prefetchw(buf);
 395         buflen = hsreq->req.length - hsreq->req.actual;
 396
 397         rcnt = readl(hsudc->regs + S3C_BRCR);
 398         rlen = (csr & S3C_ESR_LWO) ? (rcnt * 2 - 1) : (rcnt * 2);
 399
 400         hsreq->req.actual += min(rlen, buflen);
 401         is_short = (rlen < hsep->ep.maxpacket);
 402
 403         while (rcnt-- != 0) {
 404                 word = (u16)readl(fifo);
 405                 if (buflen) {
 406                         *buf++ = word;
 407                         buflen--;
 408                 } else {
 409                         hsreq->req.status = -EOVERFLOW;
 410                 }
 411         }
 412
 413         writel(S3C_ESR_RX_SUCCESS, hsudc->regs + offset);
 414
 415         if (is_short || hsreq->req.actual == hsreq->req.length) {
 416                 s3c_hsudc_complete_request(hsep, hsreq, 0);
 417                 return 1;
 418         }
 419
 420         return 0;
 421 }
 422
 423 /**
 424  * s3c_hsudc_epin_intr - Handle in-endpoint interrupt.
 425  * @hsudc - Device controller for which the interrupt is to be handled.
 426  * @ep_idx - Endpoint number on which an interrupt is pending.
 427  *
 428  * Handles interrupt for a in-endpoint. The interrupts that are handled are
 429  * stall and data transmit complete interrupt.
 430  */
 431 static void s3c_hsudc_epin_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
 432 {
 433         struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
 434         struct s3c_hsudc_req *hsreq;
 435         u32 csr;
 436
 437         csr = readl(hsudc->regs + S3C_ESR);
 438         if (csr & S3C_ESR_STALL) {
 439                 writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
 440                 return;
 441         }
 442
 443         if (csr & S3C_ESR_TX_SUCCESS) {
 444                 writel(S3C_ESR_TX_SUCCESS, hsudc->regs + S3C_ESR);
 445                 if (list_empty(&hsep->queue))
 446                         return;
 447
 448                 hsreq = list_entry(hsep->queue.next,
 449                                 struct s3c_hsudc_req, queue);
 450                 if ((s3c_hsudc_write_fifo(hsep, hsreq) == 0) &&
 451                                 (csr & S3C_ESR_PSIF_TWO))
 452                         s3c_hsudc_write_fifo(hsep, hsreq);
 453         }
 454 }
 455
 456 /**
 457  * s3c_hsudc_epout_intr - Handle out-endpoint interrupt.
 458  * @hsudc - Device controller for which the interrupt is to be handled.
 459  * @ep_idx - Endpoint number on which an interrupt is pending.
 460  *
 461  * Handles interrupt for a out-endpoint. The interrupts that are handled are
 462  * stall, flush and data ready interrupt.
 463  */
 464 static void s3c_hsudc_epout_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
 465 {
 466         struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
 467         struct s3c_hsudc_req *hsreq;
 468         u32 csr;
 469
 470         csr = readl(hsudc->regs + S3C_ESR);
 471         if (csr & S3C_ESR_STALL) {
 472                 writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
 473                 return;
 474         }
 475
 476         if (csr & S3C_ESR_FLUSH) {
 477                 __orr32(hsudc->regs + S3C_ECR, S3C_ECR_FLUSH);
 478                 return;
 479         }
 480
 481         if (csr & S3C_ESR_RX_SUCCESS) {
 482                 if (list_empty(&hsep->queue))
 483                         return;
 484
 485                 hsreq = list_entry(hsep->queue.next,
 486                                 struct s3c_hsudc_req, queue);
 487                 if (((s3c_hsudc_read_fifo(hsep, hsreq)) == 0) &&
 488                                 (csr & S3C_ESR_PSIF_TWO))
 489                         s3c_hsudc_read_fifo(hsep, hsreq);
 490         }
 491 }
 492
 493 /** s3c_hsudc_set_halt - Set or clear a endpoint halt.
 494  * @_ep: Endpoint on which halt has to be set or cleared.
 495  * @value: 1 for setting halt on endpoint, 0 to clear halt.
 496  *
 497  * Set or clear endpoint halt. If halt is set, the endpoint is stopped.
 498  * If halt is cleared, for in-endpoints, if there are any pending
 499  * transfer requests, transfers are started.
 500  */
 501 static int s3c_hsudc_set_halt(struct usb_ep *_ep, int value)
 502 {
 503         struct s3c_hsudc_ep *hsep = our_ep(_ep);
 504         struct s3c_hsudc *hsudc = hsep->dev;
 505         struct s3c_hsudc_req *hsreq;
 506         unsigned long irqflags;
 507         u32 ecr;
 508         u32 offset;
 509
 510         if (value && ep_is_in(hsep) && !list_empty(&hsep->queue))
 511                 return -EAGAIN;
 512
 513         spin_lock_irqsave(&hsudc->lock, irqflags);
 514         set_index(hsudc, ep_index(hsep));
 515         offset = (ep_index(hsep)) ? S3C_ECR : S3C_EP0CR;
 516         ecr = readl(hsudc->regs + offset);
 517
 518         if (value) {
 519                 ecr |= S3C_ECR_STALL;
 520                 if (ep_index(hsep))
 521                         ecr |= S3C_ECR_FLUSH;
 522                 hsep->stopped = 1;
 523         } else {
 524                 ecr &= ~S3C_ECR_STALL;
 525                 hsep->stopped = hsep->wedge = 0;
 526         }
 527         writel(ecr, hsudc->regs + offset);
 528
 529         if (ep_is_in(hsep) && !list_empty(&hsep->queue) && !value) {
 530                 hsreq = list_entry(hsep->queue.next,
 531                         struct s3c_hsudc_req, queue);
 532                 if (hsreq)
 533                         s3c_hsudc_write_fifo(hsep, hsreq);
 534         }
 535
 536         spin_unlock_irqrestore(&hsudc->lock, irqflags);
 537         return 0;
 538 }
 539
 540 /** s3c_hsudc_set_wedge - Sets the halt feature with the clear requests ignored
 541  * @_ep: Endpoint on which wedge has to be set.
 542  *
 543  * Sets the halt feature with the clear requests ignored.
 544  */
 545 static int s3c_hsudc_set_wedge(struct usb_ep *_ep)
 546 {
 547         struct s3c_hsudc_ep *hsep = our_ep(_ep);
 548
 549         if (!hsep)
 550                 return -EINVAL;
 551
 552         hsep->wedge = 1;
 553         return usb_ep_set_halt(_ep);
 554 }
 555
 556 /** s3c_hsudc_handle_reqfeat - Handle set feature or clear feature requests.
 557  * @_ep: Device controller on which the set/clear feature needs to be handled.
 558  * @ctrl: Control request as received on the endpoint 0.
 559  *
 560  * Handle set feature or clear feature control requests on the control endpoint.
 561  */
 562 static int s3c_hsudc_handle_reqfeat(struct s3c_hsudc *hsudc,
 563                                         struct usb_ctrlrequest *ctrl)
 564 {
 565         struct s3c_hsudc_ep *hsep;
 566         bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
 567         u8 ep_num = ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK;
 568
 569         if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
 570                 hsep = &hsudc->ep[ep_num];
 571                 switch (le16_to_cpu(ctrl->wValue)) {
 572                 case USB_ENDPOINT_HALT:
 573                         if (set || (!set && !hsep->wedge))
 574                                 s3c_hsudc_set_halt(&hsep->ep, set);
 575                         return 0;
 576                 }
 577         }
 578
 579         return -ENOENT;
 580 }
 581
 582 /**
 583  * s3c_hsudc_process_req_status - Handle get status control request.
 584  * @hsudc: Device controller on which get status request has be handled.
 585  * @ctrl: Control request as received on the endpoint 0.
 586  *
 587  * Handle get status control request received on control endpoint.
 588  */
 589 static void s3c_hsudc_process_req_status(struct s3c_hsudc *hsudc,
 590                                         struct usb_ctrlrequest *ctrl)
 591 {
 592         struct s3c_hsudc_ep *hsep0 = &hsudc->ep[0];
 593         struct s3c_hsudc_req hsreq;
 594         struct s3c_hsudc_ep *hsep;
 595         __le16 reply;
 596         u8 epnum;
 597
 598         switch (ctrl->bRequestType & USB_RECIP_MASK) {
 599         case USB_RECIP_DEVICE:
 600                 reply = cpu_to_le16(0);
 601                 break;
 602
 603         case USB_RECIP_INTERFACE:
 604                 reply = cpu_to_le16(0);
 605                 break;
 606
 607         case USB_RECIP_ENDPOINT:
 608                 epnum = le16_to_cpu(ctrl->wIndex) & USB_ENDPOINT_NUMBER_MASK;
 609                 hsep = &hsudc->ep[epnum];
 610                 reply = cpu_to_le16(hsep->stopped ? 1 : 0);
 611                 break;
 612         }
 613
 614         INIT_LIST_HEAD(&hsreq.queue);
 615         hsreq.req.length = 2;
 616         hsreq.req.buf = &reply;
 617         hsreq.req.actual = 0;
 618         hsreq.req.complete = NULL;
 619         s3c_hsudc_write_fifo(hsep0, &hsreq);
 620 }
 621
 622 /**
 623  * s3c_hsudc_process_setup - Process control request received on endpoint 0.
 624  * @hsudc: Device controller on which control request has been received.
 625  *
 626  * Read the control request received on endpoint 0, decode it and handle
 627  * the request.
 628  */
 629 static void s3c_hsudc_process_setup(struct s3c_hsudc *hsudc)
 630 {
 631         struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
 632         struct usb_ctrlrequest ctrl = {0};
 633         int ret;
 634
 635         s3c_hsudc_nuke_ep(hsep, -EPROTO);
 636         s3c_hsudc_read_setup_pkt(hsudc, (u16 *)&ctrl);
 637
 638         if (ctrl.bRequestType & USB_DIR_IN) {
 639                 hsep->bEndpointAddress |= USB_DIR_IN;
 640                 hsudc->ep0state = DATA_STATE_XMIT;
 641         } else {
 642                 hsep->bEndpointAddress &= ~USB_DIR_IN;
 643                 hsudc->ep0state = DATA_STATE_RECV;
 644         }
 645
 646         switch (ctrl.bRequest) {
 647         case USB_REQ_SET_ADDRESS:
 648                 if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
 649                         break;
 650                 hsudc->ep0state = WAIT_FOR_SETUP;
 651                 return;
 652
 653         case USB_REQ_GET_STATUS:
 654                 if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
 655                         break;
 656                 s3c_hsudc_process_req_status(hsudc, &ctrl);
 657                 return;
 658
 659         case USB_REQ_SET_FEATURE:
 660         case USB_REQ_CLEAR_FEATURE:
 661                 if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
 662                         break;
 663                 s3c_hsudc_handle_reqfeat(hsudc, &ctrl);
 664                 hsudc->ep0state = WAIT_FOR_SETUP;
 665                 return;
 666         }
 667
 668         if (hsudc->driver) {
 669                 spin_unlock(&hsudc->lock);
 670                 ret = hsudc->driver->setup(&hsudc->gadget, &ctrl);
 671                 spin_lock(&hsudc->lock);
 672
 673                 if (ctrl.bRequest == USB_REQ_SET_CONFIGURATION) {
 674                         hsep->bEndpointAddress &= ~USB_DIR_IN;
 675                         hsudc->ep0state = WAIT_FOR_SETUP;
 676                 }
 677
 678                 if (ret < 0) {
 679                         dev_err(hsudc->dev, "setup failed, returned %d\n",
 680                                                 ret);
 681                         s3c_hsudc_set_halt(&hsep->ep, 1);
 682                         hsudc->ep0state = WAIT_FOR_SETUP;
 683                         hsep->bEndpointAddress &= ~USB_DIR_IN;
 684                 }
 685         }
 686 }
 687
 688 /** s3c_hsudc_handle_ep0_intr - Handle endpoint 0 interrupt.
 689  * @hsudc: Device controller on which endpoint 0 interrupt has occured.
 690  *
 691  * Handle endpoint 0 interrupt when it occurs. EP0 interrupt could occur
 692  * when a stall handshake is sent to host or data is sent/received on
 693  * endpoint 0.
 694  */
 695 static void s3c_hsudc_handle_ep0_intr(struct s3c_hsudc *hsudc)
 696 {
 697         struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
 698         struct s3c_hsudc_req *hsreq;
 699         u32 csr = readl(hsudc->regs + S3C_EP0SR);
 700         u32 ecr;
 701
 702         if (csr & S3C_EP0SR_STALL) {
 703                 ecr = readl(hsudc->regs + S3C_EP0CR);
 704                 ecr &= ~(S3C_ECR_STALL | S3C_ECR_FLUSH);
 705                 writel(ecr, hsudc->regs + S3C_EP0CR);
 706
 707                 writel(S3C_EP0SR_STALL, hsudc->regs + S3C_EP0SR);
 708                 hsep->stopped = 0;
 709
 710                 s3c_hsudc_nuke_ep(hsep, -ECONNABORTED);
 711                 hsudc->ep0state = WAIT_FOR_SETUP;
 712                 hsep->bEndpointAddress &= ~USB_DIR_IN;
 713                 return;
 714         }
 715
 716         if (csr & S3C_EP0SR_TX_SUCCESS) {
 717                 writel(S3C_EP0SR_TX_SUCCESS, hsudc->regs + S3C_EP0SR);
 718                 if (ep_is_in(hsep)) {
 719                         if (list_empty(&hsep->queue))
 720                                 return;
 721
 722                         hsreq = list_entry(hsep->queue.next,
 723                                         struct s3c_hsudc_req, queue);
 724                         s3c_hsudc_write_fifo(hsep, hsreq);
 725                 }
 726         }
 727
 728         if (csr & S3C_EP0SR_RX_SUCCESS) {
 729                 if (hsudc->ep0state == WAIT_FOR_SETUP)
 730                         s3c_hsudc_process_setup(hsudc);
 731                 else {
 732                         if (!ep_is_in(hsep)) {
 733                                 if (list_empty(&hsep->queue))
 734                                         return;
 735                                 hsreq = list_entry(hsep->queue.next,
 736                                         struct s3c_hsudc_req, queue);
 737                                 s3c_hsudc_read_fifo(hsep, hsreq);
 738                         }
 739                 }
 740         }
 741 }
 742
 743 /**
 744  * s3c_hsudc_ep_enable - Enable a endpoint.
 745  * @_ep: The endpoint to be enabled.
 746  * @desc: Endpoint descriptor.
 747  *
 748  * Enables a endpoint when called from the gadget driver. Endpoint stall if
 749  * any is cleared, transfer type is configured and endpoint interrupt is
 750  * enabled.
 751  */
 752 static int s3c_hsudc_ep_enable(struct usb_ep *_ep,
 753                                 const struct usb_endpoint_descriptor *desc)
 754 {
 755         struct s3c_hsudc_ep *hsep;
 756         struct s3c_hsudc *hsudc;
 757         unsigned long flags;
 758         u32 ecr = 0;
 759
 760         hsep = our_ep(_ep);
 761         if (!_ep || !desc || _ep->name == ep0name
 762                 || desc->bDescriptorType != USB_DT_ENDPOINT
 763                 || hsep->bEndpointAddress != desc->bEndpointAddress
 764                 || ep_maxpacket(hsep) < usb_endpoint_maxp(desc))
 765                 return -EINVAL;
 766
 767         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 768                 && usb_endpoint_maxp(desc) != ep_maxpacket(hsep))
 769                 || !desc->wMaxPacketSize)
 770                 return -ERANGE;
 771
 772         hsudc = hsep->dev;
 773         if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
 774                 return -ESHUTDOWN;
 775
 776         spin_lock_irqsave(&hsudc->lock, flags);
 777
 778         set_index(hsudc, hsep->bEndpointAddress);
 779         ecr |= ((usb_endpoint_xfer_int(desc)) ? S3C_ECR_IEMS : S3C_ECR_DUEN);
 780         writel(ecr, hsudc->regs + S3C_ECR);
 781
 782         hsep->stopped = hsep->wedge = 0;
 783         hsep->ep.desc = desc;
 784         hsep->ep.maxpacket = usb_endpoint_maxp(desc);
 785
 786         s3c_hsudc_set_halt(_ep, 0);
 787         __set_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
 788
 789         spin_unlock_irqrestore(&hsudc->lock, flags);
 790         return 0;
 791 }
 792
 793 /**
 794  * s3c_hsudc_ep_disable - Disable a endpoint.
 795  * @_ep: The endpoint to be disabled.
 796  * @desc: Endpoint descriptor.
 797  *
 798  * Disables a endpoint when called from the gadget driver.
 799  */
 800 static int s3c_hsudc_ep_disable(struct usb_ep *_ep)
 801 {
 802         struct s3c_hsudc_ep *hsep = our_ep(_ep);
 803         struct s3c_hsudc *hsudc = hsep->dev;
 804         unsigned long flags;
 805
 806         if (!_ep || !hsep->ep.desc)
 807                 return -EINVAL;
 808
 809         spin_lock_irqsave(&hsudc->lock, flags);
 810
 811         set_index(hsudc, hsep->bEndpointAddress);
 812         __clear_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
 813
 814         s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
 815
 816         hsep->ep.desc = NULL;
 817         hsep->stopped = 1;
 818
 819         spin_unlock_irqrestore(&hsudc->lock, flags);
 820         return 0;
 821 }
 822
 823 /**
 824  * s3c_hsudc_alloc_request - Allocate a new request.
 825  * @_ep: Endpoint for which request is allocated (not used).
 826  * @gfp_flags: Flags used for the allocation.
 827  *
 828  * Allocates a single transfer request structure when called from gadget driver.
 829  */
 830 static struct usb_request *s3c_hsudc_alloc_request(struct usb_ep *_ep,
 831                                                 gfp_t gfp_flags)
 832 {
 833         struct s3c_hsudc_req *hsreq;
 834
 835         hsreq = kzalloc(sizeof(*hsreq), gfp_flags);
 836         if (!hsreq)
 837                 return NULL;
 838
 839         INIT_LIST_HEAD(&hsreq->queue);
 840         return &hsreq->req;
 841 }
 842
 843 /**
 844  * s3c_hsudc_free_request - Deallocate a request.
 845  * @ep: Endpoint for which request is deallocated (not used).
 846  * @_req: Request to be deallocated.
 847  *
 848  * Allocates a single transfer request structure when called from gadget driver.
 849  */
 850 static void s3c_hsudc_free_request(struct usb_ep *ep, struct usb_request *_req)
 851 {
 852         struct s3c_hsudc_req *hsreq;
 853
 854         hsreq = our_req(_req);
 855         WARN_ON(!list_empty(&hsreq->queue));
 856         kfree(hsreq);
 857 }
 858
 859 /**
 860  * s3c_hsudc_queue - Queue a transfer request for the endpoint.
 861  * @_ep: Endpoint for which the request is queued.
 862  * @_req: Request to be queued.
 863  * @gfp_flags: Not used.
 864  *
 865  * Start or enqueue a request for a endpoint when called from gadget driver.
 866  */
 867 static int s3c_hsudc_queue(struct usb_ep *_ep, struct usb_request *_req,
 868                         gfp_t gfp_flags)
 869 {
 870         struct s3c_hsudc_req *hsreq;
 871         struct s3c_hsudc_ep *hsep;
 872         struct s3c_hsudc *hsudc;
 873         unsigned long flags;
 874         u32 offset;
 875         u32 csr;
 876
 877         hsreq = our_req(_req);
 878         if ((!_req || !_req->complete || !_req->buf ||
 879                 !list_empty(&hsreq->queue)))
 880                 return -EINVAL;
 881
 882         hsep = our_ep(_ep);
 883         hsudc = hsep->dev;
 884         if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
 885                 return -ESHUTDOWN;
 886
 887         spin_lock_irqsave(&hsudc->lock, flags);
 888         set_index(hsudc, hsep->bEndpointAddress);
 889
 890         _req->status = -EINPROGRESS;
 891         _req->actual = 0;
 892
 893         if (!ep_index(hsep) && _req->length == 0) {
 894                 hsudc->ep0state = WAIT_FOR_SETUP;
 895                 s3c_hsudc_complete_request(hsep, hsreq, 0);
 896                 spin_unlock_irqrestore(&hsudc->lock, flags);
 897                 return 0;
 898         }
 899
 900         if (list_empty(&hsep->queue) && !hsep->stopped) {
 901                 offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
 902                 if (ep_is_in(hsep)) {
 903                         csr = readl(hsudc->regs + offset);
 904                         if (!(csr & S3C_ESR_TX_SUCCESS) &&
 905                                 (s3c_hsudc_write_fifo(hsep, hsreq) == 1))
 906                                 hsreq = NULL;
 907                 } else {
 908                         csr = readl(hsudc->regs + offset);
 909                         if ((csr & S3C_ESR_RX_SUCCESS)
 910                                    && (s3c_hsudc_read_fifo(hsep, hsreq) == 1))
 911                                 hsreq = NULL;
 912                 }
 913         }
 914
 915         if (hsreq)
 916                 list_add_tail(&hsreq->queue, &hsep->queue);
 917
 918         spin_unlock_irqrestore(&hsudc->lock, flags);
 919         return 0;
 920 }
 921
 922 /**
 923  * s3c_hsudc_dequeue - Dequeue a transfer request from an endpoint.
 924  * @_ep: Endpoint from which the request is dequeued.
 925  * @_req: Request to be dequeued.
 926  *
 927  * Dequeue a request from a endpoint when called from gadget driver.
 928  */
 929 static int s3c_hsudc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 930 {
 931         struct s3c_hsudc_ep *hsep = our_ep(_ep);
 932         struct s3c_hsudc *hsudc = hsep->dev;
 933         struct s3c_hsudc_req *hsreq;
 934         unsigned long flags;
 935
 936         hsep = our_ep(_ep);
 937         if (!_ep || hsep->ep.name == ep0name)
 938                 return -EINVAL;
 939
 940         spin_lock_irqsave(&hsudc->lock, flags);
 941
 942         list_for_each_entry(hsreq, &hsep->queue, queue) {
 943                 if (&hsreq->req == _req)
 944                         break;
 945         }
 946         if (&hsreq->req != _req) {
 947                 spin_unlock_irqrestore(&hsudc->lock, flags);
 948                 return -EINVAL;
 949         }
 950
 951         set_index(hsudc, hsep->bEndpointAddress);
 952         s3c_hsudc_complete_request(hsep, hsreq, -ECONNRESET);
 953
 954         spin_unlock_irqrestore(&hsudc->lock, flags);
 955         return 0;
 956 }
 957
 958 static struct usb_ep_ops s3c_hsudc_ep_ops = {
 959         .enable = s3c_hsudc_ep_enable,
 960         .disable = s3c_hsudc_ep_disable,
 961         .alloc_request = s3c_hsudc_alloc_request,
 962         .free_request = s3c_hsudc_free_request,
 963         .queue = s3c_hsudc_queue,
 964         .dequeue = s3c_hsudc_dequeue,
 965         .set_halt = s3c_hsudc_set_halt,
 966         .set_wedge = s3c_hsudc_set_wedge,
 967 };
 968
 969 /**
 970  * s3c_hsudc_initep - Initialize a endpoint to default state.
 971  * @hsudc - Reference to the device controller.
 972  * @hsep - Endpoint to be initialized.
 973  * @epnum - Address to be assigned to the endpoint.
 974  *
 975  * Initialize a endpoint with default configuration.
 976  */
 977 static void s3c_hsudc_initep(struct s3c_hsudc *hsudc,
 978                                 struct s3c_hsudc_ep *hsep, int epnum)
 979 {
 980         char *dir;
 981
 982         if ((epnum % 2) == 0) {
 983                 dir = "out";
 984         } else {
 985                 dir = "in";
 986                 hsep->bEndpointAddress = USB_DIR_IN;
 987         }
 988
 989         hsep->bEndpointAddress |= epnum;
 990         if (epnum)
 991                 snprintf(hsep->name, sizeof(hsep->name), "ep%d%s", epnum, dir);
 992         else
 993                 snprintf(hsep->name, sizeof(hsep->name), "%s", ep0name);
 994
 995         INIT_LIST_HEAD(&hsep->queue);
 996         INIT_LIST_HEAD(&hsep->ep.ep_list);
 997         if (epnum)
 998                 list_add_tail(&hsep->ep.ep_list, &hsudc->gadget.ep_list);
 999
1000         hsep->dev = hsudc;
1001         hsep->ep.name = hsep->name;
1002         hsep->ep.maxpacket = epnum ? 512 : 64;
1003         hsep->ep.ops = &s3c_hsudc_ep_ops;
1004         hsep->fifo = hsudc->regs + S3C_BR(epnum);
1005         hsep->ep.desc = NULL;
1006         hsep->stopped = 0;
1007         hsep->wedge = 0;
1008
1009         set_index(hsudc, epnum);
1010         writel(hsep->ep.maxpacket, hsudc->regs + S3C_MPR);
1011 }
1012
1013 /**
1014  * s3c_hsudc_setup_ep - Configure all endpoints to default state.
1015  * @hsudc: Reference to device controller.
1016  *
1017  * Configures all endpoints to default state.
1018  */
1019 static void s3c_hsudc_setup_ep(struct s3c_hsudc *hsudc)
1020 {
1021         int epnum;
1022
1023         hsudc->ep0state = WAIT_FOR_SETUP;
1024         INIT_LIST_HEAD(&hsudc->gadget.ep_list);
1025         for (epnum = 0; epnum < hsudc->pd->epnum; epnum++)
1026                 s3c_hsudc_initep(hsudc, &hsudc->ep[epnum], epnum);
1027 }
1028
1029 /**
1030  * s3c_hsudc_reconfig - Reconfigure the device controller to default state.
1031  * @hsudc: Reference to device controller.
1032  *
1033  * Reconfigures the device controller registers to a default state.
1034  */
1035 static void s3c_hsudc_reconfig(struct s3c_hsudc *hsudc)
1036 {
1037         writel(0xAA, hsudc->regs + S3C_EDR);
1038         writel(1, hsudc->regs + S3C_EIER);
1039         writel(0, hsudc->regs + S3C_TR);
1040         writel(S3C_SCR_DTZIEN_EN | S3C_SCR_RRD_EN | S3C_SCR_SUS_EN |
1041                         S3C_SCR_RST_EN, hsudc->regs + S3C_SCR);
1042         writel(0, hsudc->regs + S3C_EP0CR);
1043
1044         s3c_hsudc_setup_ep(hsudc);
1045 }
1046
1047 /**
1048  * s3c_hsudc_irq - Interrupt handler for device controller.
1049  * @irq: Not used.
1050  * @_dev: Reference to the device controller.
1051  *
1052  * Interrupt handler for the device controller. This handler handles controller
1053  * interrupts and endpoint interrupts.
1054  */
1055 static irqreturn_t s3c_hsudc_irq(int irq, void *_dev)
1056 {
1057         struct s3c_hsudc *hsudc = _dev;
1058         struct s3c_hsudc_ep *hsep;
1059         u32 ep_intr;
1060         u32 sys_status;
1061         u32 ep_idx;
1062
1063         spin_lock(&hsudc->lock);
1064
1065         sys_status = readl(hsudc->regs + S3C_SSR);
1066         ep_intr = readl(hsudc->regs + S3C_EIR) & 0x3FF;
1067
1068         if (!ep_intr && !(sys_status & S3C_SSR_DTZIEN_EN)) {
1069                 spin_unlock(&hsudc->lock);
1070                 return IRQ_HANDLED;
1071         }
1072
1073         if (sys_status) {
1074                 if (sys_status & S3C_SSR_VBUSON)
1075                         writel(S3C_SSR_VBUSON, hsudc->regs + S3C_SSR);
1076
1077                 if (sys_status & S3C_SSR_ERR)
1078                         writel(S3C_SSR_ERR, hsudc->regs + S3C_SSR);
1079
1080                 if (sys_status & S3C_SSR_SDE) {
1081                         writel(S3C_SSR_SDE, hsudc->regs + S3C_SSR);
1082                         hsudc->gadget.speed = (sys_status & S3C_SSR_HSP) ?
1083                                 USB_SPEED_HIGH : USB_SPEED_FULL;
1084                 }
1085
1086                 if (sys_status & S3C_SSR_SUSPEND) {
1087                         writel(S3C_SSR_SUSPEND, hsudc->regs + S3C_SSR);
1088                         if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
1089                                 && hsudc->driver && hsudc->driver->suspend)
1090                                 hsudc->driver->suspend(&hsudc->gadget);
1091                 }
1092
1093                 if (sys_status & S3C_SSR_RESUME) {
1094                         writel(S3C_SSR_RESUME, hsudc->regs + S3C_SSR);
1095                         if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
1096                                 && hsudc->driver && hsudc->driver->resume)
1097                                 hsudc->driver->resume(&hsudc->gadget);
1098                 }
1099
1100                 if (sys_status & S3C_SSR_RESET) {
1101                         writel(S3C_SSR_RESET, hsudc->regs + S3C_SSR);
1102                         for (ep_idx = 0; ep_idx < hsudc->pd->epnum; ep_idx++) {
1103                                 hsep = &hsudc->ep[ep_idx];
1104                                 hsep->stopped = 1;
1105                                 s3c_hsudc_nuke_ep(hsep, -ECONNRESET);
1106                         }
1107                         s3c_hsudc_reconfig(hsudc);
1108                         hsudc->ep0state = WAIT_FOR_SETUP;
1109                 }
1110         }
1111
1112         if (ep_intr & S3C_EIR_EP0) {
1113                 writel(S3C_EIR_EP0, hsudc->regs + S3C_EIR);
1114                 set_index(hsudc, 0);
1115                 s3c_hsudc_handle_ep0_intr(hsudc);
1116         }
1117
1118         ep_intr >>= 1;
1119         ep_idx = 1;
1120         while (ep_intr) {
1121                 if (ep_intr & 1)  {
1122                         hsep = &hsudc->ep[ep_idx];
1123                         set_index(hsudc, ep_idx);
1124                         writel(1 << ep_idx, hsudc->regs + S3C_EIR);
1125                         if (ep_is_in(hsep))
1126                                 s3c_hsudc_epin_intr(hsudc, ep_idx);
1127                         else
1128                                 s3c_hsudc_epout_intr(hsudc, ep_idx);
1129                 }
1130                 ep_intr >>= 1;
1131                 ep_idx++;
1132         }
1133
1134         spin_unlock(&hsudc->lock);
1135         return IRQ_HANDLED;
1136 }
1137
1138 static int s3c_hsudc_start(struct usb_gadget *gadget,
1139                 struct usb_gadget_driver *driver)
1140 {
1141         struct s3c_hsudc *hsudc = to_hsudc(gadget);
1142         int ret;
1143
1144         if (!driver
1145                 || driver->max_speed < USB_SPEED_FULL
1146                 || !driver->setup)
1147                 return -EINVAL;
1148
1149         if (!hsudc)
1150                 return -ENODEV;
1151
1152         if (hsudc->driver)
1153                 return -EBUSY;
1154
1155         hsudc->driver = driver;
1156
1157         ret = regulator_bulk_enable(ARRAY_SIZE(hsudc->supplies),
1158                                     hsudc->supplies);
1159         if (ret != 0) {
1160                 dev_err(hsudc->dev, "failed to enable supplies: %d\n", ret);
1161                 goto err_supplies;
1162         }
1163
1164         /* connect to bus through transceiver */
1165         if (!IS_ERR_OR_NULL(hsudc->transceiver)) {
1166                 ret = otg_set_peripheral(hsudc->transceiver->otg,
1167                                         &hsudc->gadget);
1168                 if (ret) {
1169                         dev_err(hsudc->dev, "%s: can't bind to transceiver\n",
1170                                         hsudc->gadget.name);
1171                         goto err_otg;
1172                 }
1173         }
1174
1175         enable_irq(hsudc->irq);
1176         dev_info(hsudc->dev, "bound driver %s\n", driver->driver.name);
1177
1178         s3c_hsudc_reconfig(hsudc);
1179
1180         pm_runtime_get_sync(hsudc->dev);
1181
1182         s3c_hsudc_init_phy();
1183         if (hsudc->pd->gpio_init)
1184                 hsudc->pd->gpio_init();
1185
1186         return 0;
1187 err_otg:
1188         regulator_bulk_disable(ARRAY_SIZE(hsudc->supplies), hsudc->supplies);
1189 err_supplies:
1190         hsudc->driver = NULL;
1191         return ret;
1192 }
1193
1194 static int s3c_hsudc_stop(struct usb_gadget *gadget,
1195                 struct usb_gadget_driver *driver)
1196 {
1197         struct s3c_hsudc *hsudc = to_hsudc(gadget);
1198         unsigned long flags;
1199
1200         if (!hsudc)
1201                 return -ENODEV;
1202
1203         if (!driver || driver != hsudc->driver)
1204                 return -EINVAL;
1205
1206         spin_lock_irqsave(&hsudc->lock, flags);
1207         hsudc->driver = NULL;
1208         hsudc->gadget.speed = USB_SPEED_UNKNOWN;
1209         s3c_hsudc_uninit_phy();
1210
1211         pm_runtime_put(hsudc->dev);
1212
1213         if (hsudc->pd->gpio_uninit)
1214                 hsudc->pd->gpio_uninit();
1215         s3c_hsudc_stop_activity(hsudc);
1216         spin_unlock_irqrestore(&hsudc->lock, flags);
1217
1218         if (!IS_ERR_OR_NULL(hsudc->transceiver))
1219                 (void) otg_set_peripheral(hsudc->transceiver->otg, NULL);
1220
1221         disable_irq(hsudc->irq);
1222
1223         regulator_bulk_disable(ARRAY_SIZE(hsudc->supplies), hsudc->supplies);
1224
1225         dev_info(hsudc->dev, "unregistered gadget driver '%s'\n",
1226                         driver->driver.name);
1227         return 0;
1228 }
1229
1230 static inline u32 s3c_hsudc_read_frameno(struct s3c_hsudc *hsudc)
1231 {
1232         return readl(hsudc->regs + S3C_FNR) & 0x3FF;
1233 }
1234
1235 static int s3c_hsudc_gadget_getframe(struct usb_gadget *gadget)
1236 {
1237         return s3c_hsudc_read_frameno(to_hsudc(gadget));
1238 }
1239
1240 static int s3c_hsudc_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1241 {
1242         struct s3c_hsudc *hsudc = to_hsudc(gadget);
1243
1244         if (!hsudc)
1245                 return -ENODEV;
1246
1247         if (!IS_ERR_OR_NULL(hsudc->transceiver))
1248                 return usb_phy_set_power(hsudc->transceiver, mA);
1249
1250         return -EOPNOTSUPP;
1251 }
1252
1253 static const struct usb_gadget_ops s3c_hsudc_gadget_ops = {
1254         .get_frame      = s3c_hsudc_gadget_getframe,
1255         .udc_start      = s3c_hsudc_start,
1256         .udc_stop       = s3c_hsudc_stop,
1257         .vbus_draw      = s3c_hsudc_vbus_draw,
1258 };
1259
1260 static int s3c_hsudc_probe(struct platform_device *pdev)
1261 {
1262         struct device *dev = &pdev->dev;
1263         struct resource *res;
1264         struct s3c_hsudc *hsudc;
1265         struct s3c24xx_hsudc_platdata *pd = dev_get_platdata(&pdev->dev);
1266         int ret, i;
1267
1268         hsudc = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsudc) +
1269                         sizeof(struct s3c_hsudc_ep) * pd->epnum,
1270                         GFP_KERNEL);
1271         if (!hsudc) {
1272                 dev_err(dev, "cannot allocate memory\n");
1273                 return -ENOMEM;
1274         }
1275
1276         platform_set_drvdata(pdev, dev);
1277         hsudc->dev = dev;
1278         hsudc->pd = dev_get_platdata(&pdev->dev);
1279
1280         hsudc->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
1281
1282         for (i = 0; i < ARRAY_SIZE(hsudc->supplies); i++)
1283                 hsudc->supplies[i].supply = s3c_hsudc_supply_names[i];
1284
1285         ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsudc->supplies),
1286                                  hsudc->supplies);
1287         if (ret != 0) {
1288                 dev_err(dev, "failed to request supplies: %d\n", ret);
1289                 goto err_supplies;
1290         }
1291
1292         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1293
1294         hsudc->regs = devm_ioremap_resource(&pdev->dev, res);
1295         if (IS_ERR(hsudc->regs)) {
1296                 ret = PTR_ERR(hsudc->regs);
1297                 goto err_res;
1298         }
1299
1300         spin_lock_init(&hsudc->lock);
1301
1302         hsudc->gadget.max_speed = USB_SPEED_HIGH;
1303         hsudc->gadget.ops = &s3c_hsudc_gadget_ops;
1304         hsudc->gadget.name = dev_name(dev);
1305         hsudc->gadget.ep0 = &hsudc->ep[0].ep;
1306         hsudc->gadget.is_otg = 0;
1307         hsudc->gadget.is_a_peripheral = 0;
1308         hsudc->gadget.speed = USB_SPEED_UNKNOWN;
1309
1310         s3c_hsudc_setup_ep(hsudc);
1311
1312         ret = platform_get_irq(pdev, 0);
1313         if (ret < 0) {
1314                 dev_err(dev, "unable to obtain IRQ number\n");
1315                 goto err_res;
1316         }
1317         hsudc->irq = ret;
1318
1319         ret = devm_request_irq(&pdev->dev, hsudc->irq, s3c_hsudc_irq, 0,
1320                                 driver_name, hsudc);
1321         if (ret < 0) {
1322                 dev_err(dev, "irq request failed\n");
1323                 goto err_res;
1324         }
1325
1326         hsudc->uclk = devm_clk_get(&pdev->dev, "usb-device");
1327         if (IS_ERR(hsudc->uclk)) {
1328                 dev_err(dev, "failed to find usb-device clock source\n");
1329                 ret = PTR_ERR(hsudc->uclk);
1330                 goto err_res;
1331         }
1332         clk_enable(hsudc->uclk);
1333
1334         local_irq_disable();
1335
1336         disable_irq(hsudc->irq);
1337         local_irq_enable();
1338
1339         ret = usb_add_gadget_udc(&pdev->dev, &hsudc->gadget);
1340         if (ret)
1341                 goto err_add_udc;
1342
1343         pm_runtime_enable(dev);
1344
1345         return 0;
1346 err_add_udc:
1347 err_add_device:
1348         clk_disable(hsudc->uclk);
1349 err_res:
1350         if (!IS_ERR_OR_NULL(hsudc->transceiver))
1351                 usb_put_phy(hsudc->transceiver);
1352
1353 err_supplies:
1354         return ret;
1355 }
1356
1357 static struct platform_driver s3c_hsudc_driver = {
1358         .driver         = {
1359                 .owner  = THIS_MODULE,
1360                 .name   = "s3c-hsudc",
1361         },
1362         .probe          = s3c_hsudc_probe,
1363 };
1364
1365 module_platform_driver(s3c_hsudc_driver);
1366
1367 MODULE_DESCRIPTION("Samsung S3C24XX USB high-speed controller driver");
1368 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
1369 MODULE_LICENSE("GPL");
1370 MODULE_ALIAS("platform:s3c-hsudc");