drivers/video/atmel_lcdfb.c

   1 /*
   2  * Driver for AT91/AT32 LCD Controller
   3  *
   4  * Copyright (C) 2007 Atmel Corporation
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/gpio.h>
  12 #include <asm/arch/clk.h>
  13 #include <lcd.h>
  14 #include <atmel_lcdc.h>
  15
  16 /* configurable parameters */
  17 #define ATMEL_LCDC_CVAL_DEFAULT         0xc8
  18 #define ATMEL_LCDC_DMA_BURST_LEN        8
  19 #ifndef ATMEL_LCDC_GUARD_TIME
  20 #define ATMEL_LCDC_GUARD_TIME           1
  21 #endif
  22
  23 #if defined(CONFIG_AT91SAM9263)
  24 #define ATMEL_LCDC_FIFO_SIZE            2048
  25 #else
  26 #define ATMEL_LCDC_FIFO_SIZE            512
  27 #endif
  28
  29 #define lcdc_readl(mmio, reg)           __raw_readl((mmio)+(reg))
  30 #define lcdc_writel(mmio, reg, val)     __raw_writel((val), (mmio)+(reg))
  31
  32 ushort *configuration_get_cmap(void)
  33 {
  34         return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
  35 }
  36
  37 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
  38 {
  39 #if defined(CONFIG_ATMEL_LCD_BGR555)
  40         lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
  41                     (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7));
  42 #else
  43         lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
  44                     (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8));
  45 #endif
  46 }
  47
  48 void lcd_ctrl_init(void *lcdbase)
  49 {
  50         unsigned long value;
  51
  52         /* Turn off the LCD controller and the DMA controller */
  53         lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
  54                     ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
  55
  56         /* Wait for the LCDC core to become idle */
  57         while (lcdc_readl(panel_info.mmio, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
  58                 udelay(10);
  59
  60         lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, 0);
  61
  62         /* Reset LCDC DMA */
  63         lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
  64
  65         /* ...set frame size and burst length = 8 words (?) */
  66         value = (panel_info.vl_col * panel_info.vl_row *
  67                  NBITS(panel_info.vl_bpix)) / 32;
  68         value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
  69         lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMAFRMCFG, value);
  70
  71         /* Set pixel clock */
  72         value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
  73         if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
  74                 value++;
  75         value = (value / 2) - 1;
  76
  77         if (!value) {
  78                 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
  79         } else
  80                 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1,
  81                             value << ATMEL_LCDC_CLKVAL_OFFSET);
  82
  83         /* Initialize control register 2 */
  84 #ifdef CONFIG_AVR32
  85         value = ATMEL_LCDC_MEMOR_BIG | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
  86 #else
  87         value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
  88 #endif
  89         if (panel_info.vl_tft)
  90                 value |= ATMEL_LCDC_DISTYPE_TFT;
  91
  92         value |= panel_info.vl_sync;
  93         value |= (panel_info.vl_bpix << 5);
  94         lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON2, value);
  95
  96         /* Vertical timing */
  97         value = (panel_info.vl_vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
  98         value |= panel_info.vl_upper_margin << ATMEL_LCDC_VBP_OFFSET;
  99         value |= panel_info.vl_lower_margin;
 100         lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM1, value);
 101
 102         /* Horizontal timing */
 103         value = (panel_info.vl_right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
 104         value |= (panel_info.vl_hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
 105         value |= (panel_info.vl_left_margin - 1);
 106         lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM2, value);
 107
 108         /* Display size */
 109         value = (panel_info.vl_col - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
 110         value |= panel_info.vl_row - 1;
 111         lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDFRMCFG, value);
 112
 113         /* FIFO Threshold: Use formula from data sheet */
 114         value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
 115         lcdc_writel(panel_info.mmio, ATMEL_LCDC_FIFO, value);
 116
 117         /* Toggle LCD_MODE every frame */
 118         lcdc_writel(panel_info.mmio, ATMEL_LCDC_MVAL, 0);
 119
 120         /* Disable all interrupts */
 121         lcdc_writel(panel_info.mmio, ATMEL_LCDC_IDR, ~0UL);
 122
 123         /* Set contrast */
 124         value = ATMEL_LCDC_PS_DIV8 |
 125                 ATMEL_LCDC_ENA_PWMENABLE;
 126         if (!panel_info.vl_cont_pol_low)
 127                 value |= ATMEL_LCDC_POL_POSITIVE;
 128         lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_CTR, value);
 129         lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
 130
 131         /* Set framebuffer DMA base address and pixel offset */
 132         lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMABADDR1, (u_long)lcdbase);
 133
 134         lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
 135         lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
 136                     (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
 137 }
 138
 139 ulong calc_fbsize(void)
 140 {
 141         return ((panel_info.vl_col * panel_info.vl_row *
 142                 NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
 143 }