3 * DENX Software Engineering, Anatolij Gustschin, agust@denx.de
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * mb862xx.c - Graphic interface for Fujitsu CoralP/Lime
26 * PCI and video mode code was derived from smiLynxEM driver.
31 #if defined(CONFIG_VIDEO_MB862xx)
36 #include "videomodes.h"
42 GraphicDevice mb862xx;
45 * 32MB external RAM - 256K Chip MMIO = 0x1FC0000 ;
47 #define VIDEO_MEM_SIZE 0x01FC0000
49 #if defined(CONFIG_PCI)
50 #if defined(CONFIG_VIDEO_CORALP)
52 static struct pci_device_id supported[] = {
53 { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P },
54 { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA },
58 /* Internal clock frequency divider table, index is mode number */
59 unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 };
63 #if defined(CONFIG_VIDEO_CORALP)
67 #define rd_io(addr) in_be32((volatile unsigned*)(addr))
68 #define wr_io(addr,val) out_be32((volatile unsigned*)(addr), (val))
71 #define HOST_RD_REG(off) rd_io((pGD->frameAdrs + 0x01fc0000 + (off)))
72 #define HOST_WR_REG(off, val) wr_io((pGD->frameAdrs + 0x01fc0000 + (off)), (val))
73 #define DISP_RD_REG(off) rd_io((pGD->frameAdrs + 0x01fd0000 + (off)))
74 #define DISP_WR_REG(off, val) wr_io((pGD->frameAdrs + 0x01fd0000 + (off)), (val))
75 #define DE_RD_REG(off) rd_io((pGD->dprBase + (off)))
76 #define DE_WR_REG(off, val) wr_io((pGD->dprBase + (off)), (val))
78 #if defined(CONFIG_VIDEO_CORALP)
79 #define DE_WR_FIFO(val) wr_io((pGD->dprBase + (0x8400)), (val))
81 #define DE_WR_FIFO(val) wr_io((pGD->dprBase + (0x04a0)), (val))
84 #define L0PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd0400 + ((idx)<<2)))
85 #define L0PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd0400 + ((idx)<<2)), (val))
86 #define L1PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd0800 + ((idx)<<2)))
87 #define L1PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd0800 + ((idx)<<2)), (val))
88 #define L2PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd1000 + ((idx)<<2)))
89 #define L2PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd1000 + ((idx)<<2)), (val))
90 #define L3PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd1400 + ((idx)<<2)))
91 #define L3PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd1400 + ((idx)<<2)), (val))
93 static void gdc_sw_reset(void)
95 GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
96 HOST_WR_REG (0x002c, 0x00000001);
102 static void de_wait(void)
104 GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
107 /* Sync with software writes to framebuffer,
108 try to reset if engine locked */
109 while (DE_RD_REG (0x0400) & 0x00000131)
112 printf ("gdc reset done after drawing engine lock...\n");
117 static void de_wait_slots(int slots)
119 GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
122 /* Wait for free fifo slots */
123 while (DE_RD_REG (0x0408) < slots)
126 printf ("gdc reset done after drawing engine lock...\n");
131 #if !defined(CONFIG_VIDEO_CORALP)
132 static void board_disp_init(void)
134 GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
135 const gdc_regs *regs = board_get_regs ();
137 while (regs->index) {
138 DISP_WR_REG (regs->index, regs->value);
145 * Init drawing engine
147 static void de_init (void)
149 GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
150 int cf = (pGD->gdfBytesPP == 1) ? 0x0000 : 0x8000;
152 pGD->dprBase = pGD->frameAdrs + 0x01ff0000;
154 /* Setup mode and fbbase, xres, fg, bg */
156 DE_WR_FIFO (0xf1010108);
157 DE_WR_FIFO (cf | 0x0300);
158 DE_WR_REG (0x0440, 0x0000);
159 DE_WR_REG (0x0444, pGD->winSizeX);
160 DE_WR_REG (0x0480, 0x0000);
161 DE_WR_REG (0x0484, 0x0000);
163 DE_WR_REG (0x0454, 0x0000);
164 DE_WR_REG (0x0458, pGD->winSizeX);
165 DE_WR_REG (0x045c, 0x0000);
166 DE_WR_REG (0x0460, pGD->winSizeY);
168 /* Clear framebuffer using drawing engine */
170 DE_WR_FIFO (0x09410000);
171 DE_WR_FIFO (0x00000000);
172 DE_WR_FIFO (pGD->winSizeY<<16 | pGD->winSizeX);
175 #if defined(CONFIG_VIDEO_CORALP)
176 unsigned int pci_video_init(void)
178 GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
181 if ((devbusfn = pci_find_devices(supported, 0)) < 0)
183 printf ("PCI video controller not found!\n");
188 pci_write_config_dword (devbusfn, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
189 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pGD->frameAdrs);
190 pGD->frameAdrs = pci_mem_to_phys (devbusfn, pGD->frameAdrs);
192 if (pGD->frameAdrs == 0) {
193 printf ("PCI config: failed to get base address\n");
197 pGD->pciBase = pGD->frameAdrs;
199 /* Setup clocks and memory mode for Coral-P Eval. Board */
200 HOST_WR_REG (0x0038, 0x00090000);
202 HOST_WR_REG (0xfffc, 0x11d7fa13);
204 return pGD->frameAdrs;
207 unsigned int card_init (void)
209 GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
210 unsigned int cf, videomode, div = 0;
211 unsigned long t1, hsync, vsync;
214 struct ctfb_res_modes *res_mode;
215 struct ctfb_res_modes var_mode;
217 memset (pGD, 0, sizeof (GraphicDevice));
219 if (!pci_video_init ()) {
227 /* get video mode via environment */
228 if ((penv = getenv ("videomode")) != NULL) {
229 /* deceide if it is a string */
230 if (penv[0] <= '9') {
231 videomode = (int) simple_strtoul (penv, NULL, 16);
238 /* parameter are vesa modes */
240 for (i = 0; i < VESA_MODES_COUNT; i++) {
241 if (vesa_modes[i].vesanr == videomode)
244 if (i == VESA_MODES_COUNT) {
245 printf ("\tno VESA Mode found, switching to mode 0x%x \n", videomode);
249 (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex];
250 if (vesa_modes[i].resindex > 2) {
251 printf ("\tUnsupported resolution, switching to default\n");
252 bpp = vesa_modes[1].bits_per_pixel;
255 bpp = vesa_modes[i].bits_per_pixel;
256 div = fr_div[vesa_modes[i].resindex];
259 res_mode = (struct ctfb_res_modes *) &var_mode;
260 bpp = video_get_params (res_mode, penv);
263 /* calculate hsync and vsync freq (info only) */
264 t1 = (res_mode->left_margin + res_mode->xres +
265 res_mode->right_margin + res_mode->hsync_len) / 8;
267 t1 *= res_mode->pixclock;
269 hsync = 1000000000L / t1;
270 t1 *= (res_mode->upper_margin + res_mode->yres +
271 res_mode->lower_margin + res_mode->vsync_len);
273 vsync = 1000000000L / t1;
275 /* fill in Graphic device struct */
276 sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
277 res_mode->yres, bpp, (hsync / 1000), (vsync / 1000));
278 printf ("\t%s\n", pGD->modeIdent);
279 pGD->winSizeX = res_mode->xres;
280 pGD->winSizeY = res_mode->yres;
281 pGD->memSize = VIDEO_MEM_SIZE;
285 pGD->gdfIndex = GDF__8BIT_INDEX;
290 pGD->gdfIndex = GDF_15BIT_555RGB;
294 printf ("\t%d bpp configured, but only 8,15 and 16 supported.\n", bpp);
295 printf ("\tSwitching back to 15bpp\n");
296 pGD->gdfIndex = GDF_15BIT_555RGB;
300 /* Setup dot clock (internal pll, division rate) */
301 DISP_WR_REG (0x0100, div);
303 cf = (pGD->gdfBytesPP == 1) ? 0x00000000 : 0x80000000;
304 DISP_WR_REG (0x0020, ((pGD->winSizeX * pGD->gdfBytesPP)/64)<<16 |
307 DISP_WR_REG (0x0024, 0x00000000);
308 DISP_WR_REG (0x0028, 0x00000000);
309 DISP_WR_REG (0x002c, 0x00000000);
310 DISP_WR_REG (0x0110, 0x00000000);
311 DISP_WR_REG (0x0114, 0x00000000);
312 DISP_WR_REG (0x0118, (pGD->winSizeY-1)<<16 | pGD->winSizeX);
314 /* Display timing init */
315 DISP_WR_REG (0x0004, (pGD->winSizeX+res_mode->left_margin+res_mode->right_margin+res_mode->hsync_len-1)<<16);
316 DISP_WR_REG (0x0008, (pGD->winSizeX-1) << 16 | (pGD->winSizeX-1));
317 DISP_WR_REG (0x000c, (res_mode->vsync_len-1)<<24|(res_mode->hsync_len-1)<<16|(pGD->winSizeX+res_mode->right_margin-1));
318 DISP_WR_REG (0x0010, (pGD->winSizeY+res_mode->lower_margin+res_mode->upper_margin+res_mode->vsync_len-1)<<16);
319 DISP_WR_REG (0x0014, (pGD->winSizeY-1) << 16 | (pGD->winSizeY+res_mode->lower_margin-1));
320 DISP_WR_REG (0x0018, 0x00000000);
321 DISP_WR_REG (0x001c, pGD->winSizeY << 16 | pGD->winSizeX);
322 /* Display enable, L0 layer */
323 DISP_WR_REG (0x0100, 0x80010000 | div);
325 return pGD->frameAdrs;
329 void *video_hw_init (void)
331 GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
333 printf ("Video: Fujitsu ");
335 memset (pGD, 0, sizeof (GraphicDevice));
337 #if defined(CONFIG_VIDEO_CORALP)
338 if (card_init () == 0) {
342 /* Preliminary init of the onboard graphic controller,
343 retrieve base address */
344 if ((pGD->frameAdrs = board_video_init ()) == 0) {
345 printf ("Controller not found!\n");
353 #if !defined(CONFIG_VIDEO_CORALP)
357 #if defined(CONFIG_LWMON5)
359 board_backlight_switch (1);
366 * Set a RGB color in the LUT
368 void video_set_lut (unsigned int index, unsigned char r, unsigned char g, unsigned char b)
370 GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
372 L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b));
376 * Drawing engine Fill and BitBlt screen region
378 void video_hw_rectfill (unsigned int bpp, unsigned int dst_x, unsigned int dst_y,
379 unsigned int dim_x, unsigned int dim_y, unsigned int color)
381 GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
384 DE_WR_REG (0x0480, color);
385 DE_WR_FIFO (0x09410000);
386 DE_WR_FIFO ((dst_y << 16) | dst_x);
387 DE_WR_FIFO ((dim_y << 16) | dim_x);
391 void video_hw_bitblt (unsigned int bpp, unsigned int src_x, unsigned int src_y,
392 unsigned int dst_x, unsigned int dst_y, unsigned int width,
395 GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
396 unsigned int ctrl = 0x0d000000L;
398 if (src_x >= dst_x && src_y >= dst_y)
400 else if (src_x >= dst_x && src_y <= dst_y)
402 else if (src_x <= dst_x && src_y >= dst_y)
409 DE_WR_FIFO ((src_y << 16) | src_x);
410 DE_WR_FIFO ((dst_y << 16) | dst_x);
411 DE_WR_FIFO ((height << 16) | width);
412 de_wait (); /* sync */
414 #endif /* CONFIG_VIDEO_MB862xx */