3 * DENX Software Engineering, Anatolij Gustschin, agust@denx.de
5 * SPDX-License-Identifier: GPL-2.0+
9 * mb862xx.c - Graphic interface for Fujitsu CoralP/Lime
10 * PCI and video mode code was derived from smiLynxEM driver.
18 #include "videomodes.h"
21 #if defined(CONFIG_POST)
28 GraphicDevice mb862xx;
31 * 32MB external RAM - 256K Chip MMIO = 0x1FC0000 ;
33 #define VIDEO_MEM_SIZE 0x01FC0000
35 #if defined(CONFIG_PCI)
36 #if defined(CONFIG_VIDEO_CORALP)
38 static struct pci_device_id supported[] = {
39 { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P },
40 { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA },
44 /* Internal clock frequency divider table, index is mode number */
45 unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 };
49 #if defined(CONFIG_VIDEO_CORALP)
53 #define rd_io(addr) in_be32((volatile unsigned *)(addr))
54 #define wr_io(addr, val) out_be32((volatile unsigned *)(addr), (val))
57 #define HOST_RD_REG(off) rd_io((dev->frameAdrs + GC_HOST_BASE + (off)))
58 #define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + GC_HOST_BASE + (off)), \
60 #define DISP_RD_REG(off) rd_io((dev->frameAdrs + GC_DISP_BASE + (off)))
61 #define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + GC_DISP_BASE + (off)), \
63 #define DE_RD_REG(off) rd_io((dev->dprBase + (off)))
64 #define DE_WR_REG(off, val) wr_io((dev->dprBase + (off)), (val))
66 #if defined(CONFIG_VIDEO_CORALP)
67 #define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_GEO_FIFO)), (val))
69 #define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_FIFO)), (val))
72 #define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + \
73 (GC_DISP_BASE | GC_L0PAL0) + \
76 #if defined(CONFIG_VIDEO_MB862xx_ACCEL)
77 static void gdc_sw_reset (void)
79 GraphicDevice *dev = &mb862xx;
81 HOST_WR_REG (GC_SRST, 0x1);
87 static void de_wait (void)
89 GraphicDevice *dev = &mb862xx;
93 * Sync with software writes to framebuffer,
94 * try to reset if engine locked
96 while (DE_RD_REG (GC_CTR) & 0x00000131)
99 puts ("gdc reset done after drawing engine lock.\n");
104 static void de_wait_slots (int slots)
106 GraphicDevice *dev = &mb862xx;
109 /* Wait for free fifo slots */
110 while (DE_RD_REG (GC_IFCNT) < slots)
113 puts ("gdc reset done after drawing engine lock.\n");
119 #if !defined(CONFIG_VIDEO_CORALP)
120 static void board_disp_init (void)
122 GraphicDevice *dev = &mb862xx;
123 const gdc_regs *regs = board_get_regs ();
125 while (regs->index) {
126 DISP_WR_REG (regs->index, regs->value);
133 * Init drawing engine if accel enabled.
134 * Also clears visible framebuffer.
136 static void de_init (void)
138 GraphicDevice *dev = &mb862xx;
139 #if defined(CONFIG_VIDEO_MB862xx_ACCEL)
140 int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000;
142 dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
144 /* Setup mode and fbbase, xres, fg, bg */
146 DE_WR_FIFO (0xf1010108);
147 DE_WR_FIFO (cf | 0x0300);
148 DE_WR_REG (GC_FBR, 0x0);
149 DE_WR_REG (GC_XRES, dev->winSizeX);
150 DE_WR_REG (GC_FC, 0x0);
151 DE_WR_REG (GC_BC, 0x0);
153 DE_WR_REG (GC_CXMIN, 0x0);
154 DE_WR_REG (GC_CXMAX, dev->winSizeX);
155 DE_WR_REG (GC_CYMIN, 0x0);
156 DE_WR_REG (GC_CYMAX, dev->winSizeY);
158 /* Clear framebuffer using drawing engine */
160 DE_WR_FIFO (0x09410000);
161 DE_WR_FIFO (0x00000000);
162 DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX);
163 /* sync with SW access to framebuffer */
168 i = dev->winSizeX * dev->winSizeY;
169 p = (unsigned int *)dev->frameAdrs;
175 #if defined(CONFIG_VIDEO_CORALP)
176 /* use CCF and MMR parameters for Coral-P Eval. Board as default */
177 #ifndef CONFIG_SYS_MB862xx_CCF
178 #define CONFIG_SYS_MB862xx_CCF 0x00090000
180 #ifndef CONFIG_SYS_MB862xx_MMR
181 #define CONFIG_SYS_MB862xx_MMR 0x11d7fa13
184 unsigned int pci_video_init (void)
186 GraphicDevice *dev = &mb862xx;
190 if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
191 puts("controller not present\n");
196 pci_write_config_dword (devbusfn, PCI_COMMAND,
197 (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
198 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &dev->frameAdrs);
199 dev->frameAdrs = pci_mem_to_phys (devbusfn, dev->frameAdrs);
201 if (dev->frameAdrs == 0) {
202 puts ("PCI config: failed to get base address\n");
206 dev->pciBase = dev->frameAdrs;
210 pci_read_config_word(devbusfn, PCI_DEVICE_ID, &device);
212 case PCI_DEVICE_ID_CORAL_P:
215 case PCI_DEVICE_ID_CORAL_PA:
223 /* Setup clocks and memory mode for Coral-P(A) */
224 HOST_WR_REG(GC_CCF, CONFIG_SYS_MB862xx_CCF);
226 HOST_WR_REG(GC_MMR, CONFIG_SYS_MB862xx_MMR);
228 return dev->frameAdrs;
231 unsigned int card_init (void)
233 GraphicDevice *dev = &mb862xx;
234 unsigned int cf, videomode, div = 0;
235 unsigned long t1, hsync, vsync;
238 struct ctfb_res_modes *res_mode;
239 struct ctfb_res_modes var_mode;
241 memset (dev, 0, sizeof (GraphicDevice));
243 if (!pci_video_init ())
248 /* get video mode via environment */
249 if ((penv = getenv ("videomode")) != NULL) {
250 /* decide if it is a string */
251 if (penv[0] <= '9') {
252 videomode = (int) simple_strtoul (penv, NULL, 16);
260 /* parameter are vesa modes, search params */
261 for (i = 0; i < VESA_MODES_COUNT; i++) {
262 if (vesa_modes[i].vesanr == videomode)
265 if (i == VESA_MODES_COUNT) {
266 printf ("\tno VESA Mode found, fallback to mode 0x%x\n",
270 res_mode = (struct ctfb_res_modes *)
271 &res_mode_init[vesa_modes[i].resindex];
272 if (vesa_modes[i].resindex > 2) {
273 puts ("\tUnsupported resolution, using default\n");
274 bpp = vesa_modes[1].bits_per_pixel;
277 bpp = vesa_modes[i].bits_per_pixel;
278 div = fr_div[vesa_modes[i].resindex];
280 res_mode = (struct ctfb_res_modes *) &var_mode;
281 bpp = video_get_params (res_mode, penv);
284 /* calculate hsync and vsync freq (info only) */
285 t1 = (res_mode->left_margin + res_mode->xres +
286 res_mode->right_margin + res_mode->hsync_len) / 8;
288 t1 *= res_mode->pixclock;
290 hsync = 1000000000L / t1;
291 t1 *= (res_mode->upper_margin + res_mode->yres +
292 res_mode->lower_margin + res_mode->vsync_len);
294 vsync = 1000000000L / t1;
296 /* fill in Graphic device struct */
297 sprintf (dev->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
298 res_mode->yres, bpp, (hsync / 1000), (vsync / 1000));
299 printf ("\t%s\n", dev->modeIdent);
300 dev->winSizeX = res_mode->xres;
301 dev->winSizeY = res_mode->yres;
302 dev->memSize = VIDEO_MEM_SIZE;
306 dev->gdfIndex = GDF__8BIT_INDEX;
311 dev->gdfIndex = GDF_15BIT_555RGB;
315 printf ("\t%d bpp configured, but only 8,15 and 16 supported\n",
317 puts ("\tfallback to 15bpp\n");
318 dev->gdfIndex = GDF_15BIT_555RGB;
322 /* Setup dot clock (internal pll, division rate) */
323 DISP_WR_REG (GC_DCM1, div);
325 cf = (dev->gdfBytesPP == 1) ? 0x00000000 : 0x80000000;
326 DISP_WR_REG (GC_L0M, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 |
327 (dev->winSizeY - 1) | cf);
328 DISP_WR_REG (GC_L0OA0, 0x0);
329 DISP_WR_REG (GC_L0DA0, 0x0);
330 DISP_WR_REG (GC_L0DY_L0DX, 0x0);
331 DISP_WR_REG (GC_L0EM, 0x0);
332 DISP_WR_REG (GC_L0WY_L0WX, 0x0);
333 DISP_WR_REG (GC_L0WH_L0WW, (dev->winSizeY - 1) << 16 | dev->winSizeX);
335 /* Display timing init */
336 DISP_WR_REG (GC_HTP_A, (dev->winSizeX +
337 res_mode->left_margin +
338 res_mode->right_margin +
339 res_mode->hsync_len - 1) << 16);
340 DISP_WR_REG (GC_HDB_HDP_A, (dev->winSizeX - 1) << 16 |
341 (dev->winSizeX - 1));
342 DISP_WR_REG (GC_VSW_HSW_HSP_A, (res_mode->vsync_len - 1) << 24 |
343 (res_mode->hsync_len - 1) << 16 |
345 res_mode->right_margin - 1));
346 DISP_WR_REG (GC_VTR_A, (dev->winSizeY + res_mode->lower_margin +
347 res_mode->upper_margin +
348 res_mode->vsync_len - 1) << 16);
349 DISP_WR_REG (GC_VDP_VSP_A, (dev->winSizeY-1) << 16 |
351 res_mode->lower_margin - 1));
352 DISP_WR_REG (GC_WY_WX, 0x0);
353 DISP_WR_REG (GC_WH_WW, dev->winSizeY << 16 | dev->winSizeX);
354 /* Display enable, L0 layer */
355 DISP_WR_REG (GC_DCM1, 0x80010000 | div);
357 return dev->frameAdrs;
362 #if !defined(CONFIG_VIDEO_CORALP)
363 int mb862xx_probe(unsigned int addr)
365 GraphicDevice *dev = &mb862xx;
368 dev->frameAdrs = addr;
369 dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
371 /* Try to access GDC ID/Revision registers */
372 reg = HOST_RD_REG (GC_CID);
373 reg = HOST_RD_REG (GC_CID);
375 reg = DE_RD_REG(GC_REV);
376 reg = DE_RD_REG(GC_REV);
377 if ((reg & ~0xff) == 0x20050100)
378 return MB862XX_TYPE_LIME;
385 void *video_hw_init (void)
387 GraphicDevice *dev = &mb862xx;
389 puts ("Video: Fujitsu ");
391 memset (dev, 0, sizeof (GraphicDevice));
393 #if defined(CONFIG_VIDEO_CORALP)
394 if (card_init () == 0)
398 * Preliminary init of the onboard graphic controller,
399 * retrieve base address
401 if ((dev->frameAdrs = board_video_init ()) == 0) {
402 puts ("Controller not found!\n");
407 /* Set Change of Clock Frequency Register */
408 HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF);
411 /* Set Memory I/F Mode Register) */
412 HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR);
418 #if !defined(CONFIG_VIDEO_CORALP)
422 #if (defined(CONFIG_LWMON5) || \
423 defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON)
425 board_backlight_switch (1);
432 * Set a RGB color in the LUT
434 void video_set_lut (unsigned int index, unsigned char r,
435 unsigned char g, unsigned char b)
437 GraphicDevice *dev = &mb862xx;
439 L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b));
442 #if defined(CONFIG_VIDEO_MB862xx_ACCEL)
444 * Drawing engine Fill and BitBlt screen region
446 void video_hw_rectfill (unsigned int bpp, unsigned int dst_x,
447 unsigned int dst_y, unsigned int dim_x,
448 unsigned int dim_y, unsigned int color)
450 GraphicDevice *dev = &mb862xx;
453 DE_WR_REG (GC_FC, color);
454 DE_WR_FIFO (0x09410000);
455 DE_WR_FIFO ((dst_y << 16) | dst_x);
456 DE_WR_FIFO ((dim_y << 16) | dim_x);
460 void video_hw_bitblt (unsigned int bpp, unsigned int src_x,
461 unsigned int src_y, unsigned int dst_x,
462 unsigned int dst_y, unsigned int width,
465 GraphicDevice *dev = &mb862xx;
466 unsigned int ctrl = 0x0d000000L;
468 if (src_x >= dst_x && src_y >= dst_y)
470 else if (src_x >= dst_x && src_y <= dst_y)
472 else if (src_x <= dst_x && src_y >= dst_y)
479 DE_WR_FIFO ((src_y << 16) | src_x);
480 DE_WR_FIFO ((dst_y << 16) | dst_x);
481 DE_WR_FIFO ((height << 16) | width);
482 de_wait (); /* sync */