drivers/video/mxc/mxc_hdmi.c

   1 /*
   2  * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  17  *
  18  */
  19 /*
  20  * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
  21  * for SLISHDMI13T and SLIPHDMIT IP cores
  22  *
  23  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  24  *
  25  * This program is free software; you can redistribute it and/or modify
  26  * it under the terms of the GNU General Public License version 2 as
  27  * published by the Free Software Foundation.
  28  */
  29 #include <linux/module.h>
  30 #include <linux/kernel.h>
  31 #include <linux/device.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/input.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/irq.h>
  36 #include <linux/io.h>
  37 #include <linux/fb.h>
  38 #include <linux/init.h>
  39 #include <linux/list.h>
  40 #include <linux/delay.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/err.h>
  43 #include <linux/clk.h>
  44 #include <linux/uaccess.h>
  45 #include <linux/cpufreq.h>
  46 #include <linux/firmware.h>
  47 #include <linux/kthread.h>
  48 #include <linux/regulator/driver.h>
  49 #include <linux/fsl_devices.h>
  50 #include <linux/ipu.h>
  51 #include <linux/regmap.h>
  52 #include <linux/pinctrl/consumer.h>
  53 #include <linux/of_device.h>
  54
  55 #include <linux/console.h>
  56 #include <linux/types.h>
  57
  58 #include "../edid.h"
  59 #include <video/mxc_edid.h>
  60 #include <video/mxc_hdmi.h>
  61 #include "mxc_dispdrv.h"
  62
  63 #include <linux/mfd/mxc-hdmi-core.h>
  64
  65 #define DISPDRV_HDMI    "hdmi"
  66 #define HDMI_EDID_LEN           512
  67
  68 /* status codes for reading edid */
  69 #define HDMI_EDID_SUCCESS       0
  70 #define HDMI_EDID_FAIL          -1
  71 #define HDMI_EDID_SAME          -2
  72 #define HDMI_EDID_NO_MODES      -3
  73
  74 #define NUM_CEA_VIDEO_MODES     64
  75 #define DEFAULT_VIDEO_MODE      16 /* 1080P */
  76
  77 #define RGB                     0
  78 #define YCBCR444                1
  79 #define YCBCR422_16BITS         2
  80 #define YCBCR422_8BITS          3
  81 #define XVYCC444            4
  82
  83 /*
  84  * We follow a flowchart which is in the "Synopsys DesignWare Courses
  85  * HDMI Transmitter Controller User Guide, 1.30a", section 3.1
  86  * (dwc_hdmi_tx_user.pdf)
  87  *
  88  * Below are notes that say "HDMI Initialization Step X"
  89  * These correspond to the flowchart.
  90  */
  91
  92 /*
  93  * We are required to configure VGA mode before reading edid
  94  * in HDMI Initialization Step B
  95  */
  96 static const struct fb_videomode vga_mode = {
  97         /* 640x480 @ 60 Hz, 31.5 kHz hsync */
  98         NULL, 60, 640, 480, 39721, 48, 16, 33, 10, 96, 2, 0,
  99         FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, FB_MODE_IS_VESA,
 100 };
 101
 102 enum hdmi_datamap {
 103         RGB444_8B = 0x01,
 104         RGB444_10B = 0x03,
 105         RGB444_12B = 0x05,
 106         RGB444_16B = 0x07,
 107         YCbCr444_8B = 0x09,
 108         YCbCr444_10B = 0x0B,
 109         YCbCr444_12B = 0x0D,
 110         YCbCr444_16B = 0x0F,
 111         YCbCr422_8B = 0x16,
 112         YCbCr422_10B = 0x14,
 113         YCbCr422_12B = 0x12,
 114 };
 115
 116 enum hdmi_colorimetry {
 117         eITU601,
 118         eITU709,
 119 };
 120
 121 struct hdmi_vmode {
 122         bool mDVI;
 123         bool mHSyncPolarity;
 124         bool mVSyncPolarity;
 125         bool mInterlaced;
 126         bool mDataEnablePolarity;
 127
 128         unsigned int mPixelClock;
 129         unsigned int mPixelRepetitionInput;
 130         unsigned int mPixelRepetitionOutput;
 131 };
 132
 133 struct hdmi_data_info {
 134         unsigned int enc_in_format;
 135         unsigned int enc_out_format;
 136         unsigned int enc_color_depth;
 137         unsigned int colorimetry;
 138         unsigned int pix_repet_factor;
 139         unsigned int hdcp_enable;
 140         unsigned int rgb_out_enable;
 141         struct hdmi_vmode video_mode;
 142 };
 143
 144 struct hdmi_phy_reg_config {
 145         /* HDMI PHY register config for pass HCT */
 146         u16 reg_vlev;
 147         u16 reg_cksymtx;
 148 };
 149
 150 struct mxc_hdmi {
 151         struct platform_device *pdev;
 152         struct platform_device *core_pdev;
 153         struct mxc_dispdrv_handle *disp_mxc_hdmi;
 154         struct fb_info *fbi;
 155         struct clk *hdmi_isfr_clk;
 156         struct clk *hdmi_iahb_clk;
 157         struct delayed_work hotplug_work;
 158         struct delayed_work hdcp_hdp_work;
 159
 160         struct notifier_block nb;
 161
 162         struct hdmi_data_info hdmi_data;
 163         int vic;
 164         struct mxc_edid_cfg edid_cfg;
 165         u8 edid[HDMI_EDID_LEN];
 166         bool fb_reg;
 167         bool cable_plugin;
 168         u8  blank;
 169         bool dft_mode_set;
 170         char *dft_mode_str;
 171         int default_bpp;
 172         u8 latest_intr_stat;
 173         bool irq_enabled;
 174         spinlock_t irq_lock;
 175         bool phy_enabled;
 176         struct fb_videomode default_mode;
 177         struct fb_videomode previous_non_vga_mode;
 178         bool requesting_vga_for_initialization;
 179
 180         int *gpr_base;
 181         int *gpr_hdmi_base;
 182         int *gpr_sdma_base;
 183         int cpu_type;
 184         int cpu_version;
 185         struct hdmi_phy_reg_config phy_config;
 186
 187         struct pinctrl *pinctrl;
 188 };
 189
 190 static int hdmi_major;
 191 static struct class *hdmi_class;
 192
 193 struct i2c_client *hdmi_i2c;
 194 struct mxc_hdmi *g_hdmi;
 195
 196 static bool hdmi_inited;
 197 static bool hdcp_init;
 198
 199 extern const struct fb_videomode mxc_cea_mode[64];
 200 extern void mxc_hdmi_cec_handle(u16 cec_stat);
 201
 202 static void mxc_hdmi_setup(struct mxc_hdmi *hdmi, unsigned long event);
 203 static void hdmi_enable_overflow_interrupts(void);
 204 static void hdmi_disable_overflow_interrupts(void);
 205
 206 static struct platform_device_id imx_hdmi_devtype[] = {
 207         {
 208                 .name = "hdmi-imx6DL",
 209                 .driver_data = IMX6DL_HDMI,
 210         }, {
 211                 .name = "hdmi-imx6Q",
 212                 .driver_data = IMX6Q_HDMI,
 213         }, {
 214                 /* sentinel */
 215         }
 216 };
 217 MODULE_DEVICE_TABLE(platform, imx_hdmi_devtype);
 218
 219 static const struct of_device_id imx_hdmi_dt_ids[] = {
 220         { .compatible = "fsl,imx6dl-hdmi-video", .data = &imx_hdmi_devtype[IMX6DL_HDMI], },
 221         { .compatible = "fsl,imx6q-hdmi-video", .data = &imx_hdmi_devtype[IMX6Q_HDMI], },
 222         { /* sentinel */ }
 223 };
 224 MODULE_DEVICE_TABLE(of, imx_hdmi_dt_ids);
 225
 226 static inline int cpu_is_imx6dl(struct mxc_hdmi *hdmi)
 227 {
 228         return hdmi->cpu_type == IMX6DL_HDMI;
 229 }
 230 #ifdef DEBUG
 231 static void dump_fb_videomode(struct fb_videomode *m)
 232 {
 233         pr_debug("fb_videomode = %d %d %d %d %d %d %d %d %d %d %d %d %d\n",
 234                 m->refresh, m->xres, m->yres, m->pixclock, m->left_margin,
 235                 m->right_margin, m->upper_margin, m->lower_margin,
 236                 m->hsync_len, m->vsync_len, m->sync, m->vmode, m->flag);
 237 }
 238 #else
 239 static void dump_fb_videomode(struct fb_videomode *m)
 240 {}
 241 #endif
 242
 243 static ssize_t mxc_hdmi_show_name(struct device *dev,
 244                 struct device_attribute *attr, char *buf)
 245 {
 246         struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
 247
 248         strcpy(buf, hdmi->fbi->fix.id);
 249         sprintf(buf+strlen(buf), "\n");
 250
 251         return strlen(buf);
 252 }
 253
 254 static DEVICE_ATTR(fb_name, S_IRUGO, mxc_hdmi_show_name, NULL);
 255
 256 static ssize_t mxc_hdmi_show_state(struct device *dev,
 257                 struct device_attribute *attr, char *buf)
 258 {
 259         struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
 260
 261         if (hdmi->cable_plugin == false)
 262                 strcpy(buf, "plugout\n");
 263         else
 264                 strcpy(buf, "plugin\n");
 265
 266         return strlen(buf);
 267 }
 268
 269 static DEVICE_ATTR(cable_state, S_IRUGO, mxc_hdmi_show_state, NULL);
 270
 271 static ssize_t mxc_hdmi_show_edid(struct device *dev,
 272                 struct device_attribute *attr, char *buf)
 273 {
 274         struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
 275         int i, j, len = 0;
 276
 277         for (j = 0; j < HDMI_EDID_LEN/16; j++) {
 278                 for (i = 0; i < 16; i++)
 279                         len += sprintf(buf+len, "0x%02X ",
 280                                         hdmi->edid[j*16 + i]);
 281                 len += sprintf(buf+len, "\n");
 282         }
 283
 284         return len;
 285 }
 286
 287 static DEVICE_ATTR(edid, S_IRUGO, mxc_hdmi_show_edid, NULL);
 288
 289 static ssize_t mxc_hdmi_show_rgb_out_enable(struct device *dev,
 290                 struct device_attribute *attr, char *buf)
 291 {
 292         struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
 293
 294         if (hdmi->hdmi_data.rgb_out_enable == true)
 295                 strcpy(buf, "RGB out\n");
 296         else
 297                 strcpy(buf, "YCbCr out\n");
 298
 299         return strlen(buf);
 300 }
 301
 302 static ssize_t mxc_hdmi_store_rgb_out_enable(struct device *dev,
 303                 struct device_attribute *attr, const char *buf, size_t count)
 304 {
 305         struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
 306         unsigned long value;
 307         int ret;
 308
 309         ret = strict_strtoul(buf, 10, &value);
 310         if (ret)
 311                 return ret;
 312
 313         hdmi->hdmi_data.rgb_out_enable = value;
 314
 315         /* Reconfig HDMI for output color space change */
 316         mxc_hdmi_setup(hdmi, 0);
 317
 318         return count;
 319 }
 320
 321 static DEVICE_ATTR(rgb_out_enable, S_IRUGO | S_IWUSR,
 322                                 mxc_hdmi_show_rgb_out_enable,
 323                                 mxc_hdmi_store_rgb_out_enable);
 324
 325 static ssize_t mxc_hdmi_show_hdcp_enable(struct device *dev,
 326                 struct device_attribute *attr, char *buf)
 327 {
 328         struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
 329
 330         if (hdmi->hdmi_data.hdcp_enable == false)
 331                 strcpy(buf, "hdcp disable\n");
 332         else
 333                 strcpy(buf, "hdcp enable\n");
 334
 335         return strlen(buf);
 336
 337 }
 338
 339 static ssize_t mxc_hdmi_store_hdcp_enable(struct device *dev,
 340                 struct device_attribute *attr, const char *buf, size_t count)
 341 {
 342         struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
 343         char event_string[32];
 344         char *envp[] = { event_string, NULL };
 345         unsigned long value;
 346         int ret;
 347
 348         ret = strict_strtoul(buf, 10, &value);
 349         if (ret)
 350                 return ret;
 351
 352         hdmi->hdmi_data.hdcp_enable = value;
 353
 354         /* Reconfig HDMI for HDCP */
 355         mxc_hdmi_setup(hdmi, 0);
 356
 357         if (hdmi->hdmi_data.hdcp_enable == false) {
 358                 sprintf(event_string, "EVENT=hdcpdisable");
 359                 kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
 360         } else {
 361                 sprintf(event_string, "EVENT=hdcpenable");
 362                 kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
 363         }
 364
 365         return count;
 366
 367 }
 368
 369 static DEVICE_ATTR(hdcp_enable, S_IRUGO | S_IWUSR,
 370                         mxc_hdmi_show_hdcp_enable, mxc_hdmi_store_hdcp_enable);
 371
 372 /*!
 373  * this submodule is responsible for the video data synchronization.
 374  * for example, for RGB 4:4:4 input, the data map is defined as
 375  *                      pin{47~40} <==> R[7:0]
 376  *                      pin{31~24} <==> G[7:0]
 377  *                      pin{15~8}  <==> B[7:0]
 378  */
 379 static void hdmi_video_sample(struct mxc_hdmi *hdmi)
 380 {
 381         int color_format = 0;
 382         u8 val;
 383
 384         if (hdmi->hdmi_data.enc_in_format == RGB) {
 385                 if (hdmi->hdmi_data.enc_color_depth == 8)
 386                         color_format = 0x01;
 387                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 388                         color_format = 0x03;
 389                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 390                         color_format = 0x05;
 391                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 392                         color_format = 0x07;
 393                 else
 394                         return;
 395         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
 396                 if (hdmi->hdmi_data.enc_color_depth == 8)
 397                         color_format = 0x09;
 398                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 399                         color_format = 0x0B;
 400                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 401                         color_format = 0x0D;
 402                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 403                         color_format = 0x0F;
 404                 else
 405                         return;
 406         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
 407                 if (hdmi->hdmi_data.enc_color_depth == 8)
 408                         color_format = 0x16;
 409                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 410                         color_format = 0x14;
 411                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 412                         color_format = 0x12;
 413                 else
 414                         return;
 415         }
 416
 417         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 418                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 419                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 420         hdmi_writeb(val, HDMI_TX_INVID0);
 421
 422         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 423         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 424                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 425                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 426         hdmi_writeb(val, HDMI_TX_INSTUFFING);
 427         hdmi_writeb(0x0, HDMI_TX_GYDATA0);
 428         hdmi_writeb(0x0, HDMI_TX_GYDATA1);
 429         hdmi_writeb(0x0, HDMI_TX_RCRDATA0);
 430         hdmi_writeb(0x0, HDMI_TX_RCRDATA1);
 431         hdmi_writeb(0x0, HDMI_TX_BCBDATA0);
 432         hdmi_writeb(0x0, HDMI_TX_BCBDATA1);
 433 }
 434
 435 static int isColorSpaceConversion(struct mxc_hdmi *hdmi)
 436 {
 437         return (hdmi->hdmi_data.enc_in_format !=
 438                 hdmi->hdmi_data.enc_out_format);
 439 }
 440
 441 static int isColorSpaceDecimation(struct mxc_hdmi *hdmi)
 442 {
 443         return ((hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS) &&
 444                 (hdmi->hdmi_data.enc_in_format == RGB ||
 445                 hdmi->hdmi_data.enc_in_format == YCBCR444));
 446 }
 447
 448 static int isColorSpaceInterpolation(struct mxc_hdmi *hdmi)
 449 {
 450         return ((hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) &&
 451                 (hdmi->hdmi_data.enc_out_format == RGB
 452                 || hdmi->hdmi_data.enc_out_format == YCBCR444));
 453 }
 454
 455 /*!
 456  * update the color space conversion coefficients.
 457  */
 458 static void update_csc_coeffs(struct mxc_hdmi *hdmi)
 459 {
 460         unsigned short csc_coeff[3][4];
 461         unsigned int csc_scale = 1;
 462         u8 val;
 463         bool coeff_selected = false;
 464
 465         if (isColorSpaceConversion(hdmi)) { /* csc needed */
 466                 if (hdmi->hdmi_data.enc_out_format == RGB) {
 467                         if (hdmi->hdmi_data.colorimetry == eITU601) {
 468                                 csc_coeff[0][0] = 0x2000;
 469                                 csc_coeff[0][1] = 0x6926;
 470                                 csc_coeff[0][2] = 0x74fd;
 471                                 csc_coeff[0][3] = 0x010e;
 472
 473                                 csc_coeff[1][0] = 0x2000;
 474                                 csc_coeff[1][1] = 0x2cdd;
 475                                 csc_coeff[1][2] = 0x0000;
 476                                 csc_coeff[1][3] = 0x7e9a;
 477
 478                                 csc_coeff[2][0] = 0x2000;
 479                                 csc_coeff[2][1] = 0x0000;
 480                                 csc_coeff[2][2] = 0x38b4;
 481                                 csc_coeff[2][3] = 0x7e3b;
 482
 483                                 csc_scale = 1;
 484                                 coeff_selected = true;
 485                         } else if (hdmi->hdmi_data.colorimetry == eITU709) {
 486                                 csc_coeff[0][0] = 0x2000;
 487                                 csc_coeff[0][1] = 0x7106;
 488                                 csc_coeff[0][2] = 0x7a02;
 489                                 csc_coeff[0][3] = 0x00a7;
 490
 491                                 csc_coeff[1][0] = 0x2000;
 492                                 csc_coeff[1][1] = 0x3264;
 493                                 csc_coeff[1][2] = 0x0000;
 494                                 csc_coeff[1][3] = 0x7e6d;
 495
 496                                 csc_coeff[2][0] = 0x2000;
 497                                 csc_coeff[2][1] = 0x0000;
 498                                 csc_coeff[2][2] = 0x3b61;
 499                                 csc_coeff[2][3] = 0x7e25;
 500
 501                                 csc_scale = 1;
 502                                 coeff_selected = true;
 503                         }
 504                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
 505                         if (hdmi->hdmi_data.colorimetry == eITU601) {
 506                                 csc_coeff[0][0] = 0x2591;
 507                                 csc_coeff[0][1] = 0x1322;
 508                                 csc_coeff[0][2] = 0x074b;
 509                                 csc_coeff[0][3] = 0x0000;
 510
 511                                 csc_coeff[1][0] = 0x6535;
 512                                 csc_coeff[1][1] = 0x2000;
 513                                 csc_coeff[1][2] = 0x7acc;
 514                                 csc_coeff[1][3] = 0x0200;
 515
 516                                 csc_coeff[2][0] = 0x6acd;
 517                                 csc_coeff[2][1] = 0x7534;
 518                                 csc_coeff[2][2] = 0x2000;
 519                                 csc_coeff[2][3] = 0x0200;
 520
 521                                 csc_scale = 0;
 522                                 coeff_selected = true;
 523                         } else if (hdmi->hdmi_data.colorimetry == eITU709) {
 524                                 csc_coeff[0][0] = 0x2dc5;
 525                                 csc_coeff[0][1] = 0x0d9b;
 526                                 csc_coeff[0][2] = 0x049e;
 527                                 csc_coeff[0][3] = 0x0000;
 528
 529                                 csc_coeff[1][0] = 0x62f0;
 530                                 csc_coeff[1][1] = 0x2000;
 531                                 csc_coeff[1][2] = 0x7d11;
 532                                 csc_coeff[1][3] = 0x0200;
 533
 534                                 csc_coeff[2][0] = 0x6756;
 535                                 csc_coeff[2][1] = 0x78ab;
 536                                 csc_coeff[2][2] = 0x2000;
 537                                 csc_coeff[2][3] = 0x0200;
 538
 539                                 csc_scale = 0;
 540                                 coeff_selected = true;
 541                         }
 542                 }
 543         }
 544
 545         if (!coeff_selected) {
 546                 csc_coeff[0][0] = 0x2000;
 547                 csc_coeff[0][1] = 0x0000;
 548                 csc_coeff[0][2] = 0x0000;
 549                 csc_coeff[0][3] = 0x0000;
 550
 551                 csc_coeff[1][0] = 0x0000;
 552                 csc_coeff[1][1] = 0x2000;
 553                 csc_coeff[1][2] = 0x0000;
 554                 csc_coeff[1][3] = 0x0000;
 555
 556                 csc_coeff[2][0] = 0x0000;
 557                 csc_coeff[2][1] = 0x0000;
 558                 csc_coeff[2][2] = 0x2000;
 559                 csc_coeff[2][3] = 0x0000;
 560
 561                 csc_scale = 1;
 562         }
 563
 564         /* Update CSC parameters in HDMI CSC registers */
 565         hdmi_writeb((unsigned char)(csc_coeff[0][0] & 0xFF),
 566                 HDMI_CSC_COEF_A1_LSB);
 567         hdmi_writeb((unsigned char)(csc_coeff[0][0] >> 8),
 568                 HDMI_CSC_COEF_A1_MSB);
 569         hdmi_writeb((unsigned char)(csc_coeff[0][1] & 0xFF),
 570                 HDMI_CSC_COEF_A2_LSB);
 571         hdmi_writeb((unsigned char)(csc_coeff[0][1] >> 8),
 572                 HDMI_CSC_COEF_A2_MSB);
 573         hdmi_writeb((unsigned char)(csc_coeff[0][2] & 0xFF),
 574                 HDMI_CSC_COEF_A3_LSB);
 575         hdmi_writeb((unsigned char)(csc_coeff[0][2] >> 8),
 576                 HDMI_CSC_COEF_A3_MSB);
 577         hdmi_writeb((unsigned char)(csc_coeff[0][3] & 0xFF),
 578                 HDMI_CSC_COEF_A4_LSB);
 579         hdmi_writeb((unsigned char)(csc_coeff[0][3] >> 8),
 580                 HDMI_CSC_COEF_A4_MSB);
 581
 582         hdmi_writeb((unsigned char)(csc_coeff[1][0] & 0xFF),
 583                 HDMI_CSC_COEF_B1_LSB);
 584         hdmi_writeb((unsigned char)(csc_coeff[1][0] >> 8),
 585                 HDMI_CSC_COEF_B1_MSB);
 586         hdmi_writeb((unsigned char)(csc_coeff[1][1] & 0xFF),
 587                 HDMI_CSC_COEF_B2_LSB);
 588         hdmi_writeb((unsigned char)(csc_coeff[1][1] >> 8),
 589                 HDMI_CSC_COEF_B2_MSB);
 590         hdmi_writeb((unsigned char)(csc_coeff[1][2] & 0xFF),
 591                 HDMI_CSC_COEF_B3_LSB);
 592         hdmi_writeb((unsigned char)(csc_coeff[1][2] >> 8),
 593                 HDMI_CSC_COEF_B3_MSB);
 594         hdmi_writeb((unsigned char)(csc_coeff[1][3] & 0xFF),
 595                 HDMI_CSC_COEF_B4_LSB);
 596         hdmi_writeb((unsigned char)(csc_coeff[1][3] >> 8),
 597                 HDMI_CSC_COEF_B4_MSB);
 598
 599         hdmi_writeb((unsigned char)(csc_coeff[2][0] & 0xFF),
 600                 HDMI_CSC_COEF_C1_LSB);
 601         hdmi_writeb((unsigned char)(csc_coeff[2][0] >> 8),
 602                 HDMI_CSC_COEF_C1_MSB);
 603         hdmi_writeb((unsigned char)(csc_coeff[2][1] & 0xFF),
 604                 HDMI_CSC_COEF_C2_LSB);
 605         hdmi_writeb((unsigned char)(csc_coeff[2][1] >> 8),
 606                 HDMI_CSC_COEF_C2_MSB);
 607         hdmi_writeb((unsigned char)(csc_coeff[2][2] & 0xFF),
 608                 HDMI_CSC_COEF_C3_LSB);
 609         hdmi_writeb((unsigned char)(csc_coeff[2][2] >> 8),
 610                 HDMI_CSC_COEF_C3_MSB);
 611         hdmi_writeb((unsigned char)(csc_coeff[2][3] & 0xFF),
 612                 HDMI_CSC_COEF_C4_LSB);
 613         hdmi_writeb((unsigned char)(csc_coeff[2][3] >> 8),
 614                 HDMI_CSC_COEF_C4_MSB);
 615
 616         val = hdmi_readb(HDMI_CSC_SCALE);
 617         val &= ~HDMI_CSC_SCALE_CSCSCALE_MASK;
 618         val |= csc_scale & HDMI_CSC_SCALE_CSCSCALE_MASK;
 619         hdmi_writeb(val, HDMI_CSC_SCALE);
 620 }
 621
 622 static void hdmi_video_csc(struct mxc_hdmi *hdmi)
 623 {
 624         int color_depth = 0;
 625         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 626         int decimation = 0;
 627         u8 val;
 628
 629         /* YCC422 interpolation to 444 mode */
 630         if (isColorSpaceInterpolation(hdmi))
 631                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 632         else if (isColorSpaceDecimation(hdmi))
 633                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 634
 635         if (hdmi->hdmi_data.enc_color_depth == 8)
 636                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 637         else if (hdmi->hdmi_data.enc_color_depth == 10)
 638                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 639         else if (hdmi->hdmi_data.enc_color_depth == 12)
 640                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 641         else if (hdmi->hdmi_data.enc_color_depth == 16)
 642                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 643         else
 644                 return;
 645
 646         /*configure the CSC registers */
 647         hdmi_writeb(interpolation | decimation, HDMI_CSC_CFG);
 648         val = hdmi_readb(HDMI_CSC_SCALE);
 649         val &= ~HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK;
 650         val |= color_depth;
 651         hdmi_writeb(val, HDMI_CSC_SCALE);
 652
 653         update_csc_coeffs(hdmi);
 654 }
 655
 656 /*!
 657  * HDMI video packetizer is used to packetize the data.
 658  * for example, if input is YCC422 mode or repeater is used,
 659  * data should be repacked this module can be bypassed.
 660  */
 661 static void hdmi_video_packetize(struct mxc_hdmi *hdmi)
 662 {
 663         unsigned int color_depth = 0;
 664         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 665         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 666         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 667         u8 val;
 668
 669         if (hdmi_data->enc_out_format == RGB
 670                 || hdmi_data->enc_out_format == YCBCR444) {
 671                 if (hdmi_data->enc_color_depth == 0)
 672                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 673                 else if (hdmi_data->enc_color_depth == 8) {
 674                         color_depth = 4;
 675                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 676                 } else if (hdmi_data->enc_color_depth == 10)
 677                         color_depth = 5;
 678                 else if (hdmi_data->enc_color_depth == 12)
 679                         color_depth = 6;
 680                 else if (hdmi_data->enc_color_depth == 16)
 681                         color_depth = 7;
 682                 else
 683                         return;
 684         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
 685                 if (hdmi_data->enc_color_depth == 0 ||
 686                         hdmi_data->enc_color_depth == 8)
 687                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 688                 else if (hdmi_data->enc_color_depth == 10)
 689                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 690                 else if (hdmi_data->enc_color_depth == 12)
 691                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 692                 else
 693                         return;
 694                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 695         } else
 696                 return;
 697
 698         /* HDMI not support deep color,
 699          * because IPU MAX support color depth is 24bit */
 700         color_depth = 0;
 701
 702         /* set the packetizer registers */
 703         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 704                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 705                 ((hdmi_data->pix_repet_factor <<
 706                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 707                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 708         hdmi_writeb(val, HDMI_VP_PR_CD);
 709
 710         val = hdmi_readb(HDMI_VP_STUFF);
 711         val &= ~HDMI_VP_STUFF_PR_STUFFING_MASK;
 712         val |= HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE;
 713         hdmi_writeb(val, HDMI_VP_STUFF);
 714
 715         /* Data from pixel repeater block */
 716         if (hdmi_data->pix_repet_factor > 1) {
 717                 val = hdmi_readb(HDMI_VP_CONF);
 718                 val &= ~(HDMI_VP_CONF_PR_EN_MASK |
 719                         HDMI_VP_CONF_BYPASS_SELECT_MASK);
 720                 val |= HDMI_VP_CONF_PR_EN_ENABLE |
 721                         HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 722                 hdmi_writeb(val, HDMI_VP_CONF);
 723         } else { /* data from packetizer block */
 724                 val = hdmi_readb(HDMI_VP_CONF);
 725                 val &= ~(HDMI_VP_CONF_PR_EN_MASK |
 726                         HDMI_VP_CONF_BYPASS_SELECT_MASK);
 727                 val |= HDMI_VP_CONF_PR_EN_DISABLE |
 728                         HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 729                 hdmi_writeb(val, HDMI_VP_CONF);
 730         }
 731
 732         val = hdmi_readb(HDMI_VP_STUFF);
 733         val &= ~HDMI_VP_STUFF_IDEFAULT_PHASE_MASK;
 734         val |= 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET;
 735         hdmi_writeb(val, HDMI_VP_STUFF);
 736
 737         hdmi_writeb(remap_size, HDMI_VP_REMAP);
 738
 739         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 740                 val = hdmi_readb(HDMI_VP_CONF);
 741                 val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK |
 742                         HDMI_VP_CONF_PP_EN_ENMASK |
 743                         HDMI_VP_CONF_YCC422_EN_MASK);
 744                 val |= HDMI_VP_CONF_BYPASS_EN_DISABLE |
 745                         HDMI_VP_CONF_PP_EN_ENABLE |
 746                         HDMI_VP_CONF_YCC422_EN_DISABLE;
 747                 hdmi_writeb(val, HDMI_VP_CONF);
 748         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 749                 val = hdmi_readb(HDMI_VP_CONF);
 750                 val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK |
 751                         HDMI_VP_CONF_PP_EN_ENMASK |
 752                         HDMI_VP_CONF_YCC422_EN_MASK);
 753                 val |= HDMI_VP_CONF_BYPASS_EN_DISABLE |
 754                         HDMI_VP_CONF_PP_EN_DISABLE |
 755                         HDMI_VP_CONF_YCC422_EN_ENABLE;
 756                 hdmi_writeb(val, HDMI_VP_CONF);
 757         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 758                 val = hdmi_readb(HDMI_VP_CONF);
 759                 val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK |
 760                         HDMI_VP_CONF_PP_EN_ENMASK |
 761                         HDMI_VP_CONF_YCC422_EN_MASK);
 762                 val |= HDMI_VP_CONF_BYPASS_EN_ENABLE |
 763                         HDMI_VP_CONF_PP_EN_DISABLE |
 764                         HDMI_VP_CONF_YCC422_EN_DISABLE;
 765                 hdmi_writeb(val, HDMI_VP_CONF);
 766         } else {
 767                 return;
 768         }
 769
 770         val = hdmi_readb(HDMI_VP_STUFF);
 771         val &= ~(HDMI_VP_STUFF_PP_STUFFING_MASK |
 772                 HDMI_VP_STUFF_YCC422_STUFFING_MASK);
 773         val |= HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 774                 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE;
 775         hdmi_writeb(val, HDMI_VP_STUFF);
 776
 777         val = hdmi_readb(HDMI_VP_CONF);
 778         val &= ~HDMI_VP_CONF_OUTPUT_SELECTOR_MASK;
 779         val |= output_select;
 780         hdmi_writeb(val, HDMI_VP_CONF);
 781 }
 782
 783 #if 0
 784 /* Force a fixed color screen */
 785 static void hdmi_video_force_output(struct mxc_hdmi *hdmi, unsigned char force)
 786 {
 787         u8 val;
 788
 789         dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
 790
 791         if (force) {
 792                 hdmi_writeb(0x00, HDMI_FC_DBGTMDS2);   /* R */
 793                 hdmi_writeb(0x00, HDMI_FC_DBGTMDS1);   /* G */
 794                 hdmi_writeb(0xFF, HDMI_FC_DBGTMDS0);   /* B */
 795                 val = hdmi_readb(HDMI_FC_DBGFORCE);
 796                 val |= HDMI_FC_DBGFORCE_FORCEVIDEO;
 797                 hdmi_writeb(val, HDMI_FC_DBGFORCE);
 798         } else {
 799                 val = hdmi_readb(HDMI_FC_DBGFORCE);
 800                 val &= ~HDMI_FC_DBGFORCE_FORCEVIDEO;
 801                 hdmi_writeb(val, HDMI_FC_DBGFORCE);
 802                 hdmi_writeb(0x00, HDMI_FC_DBGTMDS2);   /* R */
 803                 hdmi_writeb(0x00, HDMI_FC_DBGTMDS1);   /* G */
 804                 hdmi_writeb(0x00, HDMI_FC_DBGTMDS0);   /* B */
 805         }
 806 }
 807 #endif
 808
 809 static inline void hdmi_phy_test_clear(struct mxc_hdmi *hdmi,
 810                                                 unsigned char bit)
 811 {
 812         u8 val = hdmi_readb(HDMI_PHY_TST0);
 813         val &= ~HDMI_PHY_TST0_TSTCLR_MASK;
 814         val |= (bit << HDMI_PHY_TST0_TSTCLR_OFFSET) &
 815                 HDMI_PHY_TST0_TSTCLR_MASK;
 816         hdmi_writeb(val, HDMI_PHY_TST0);
 817 }
 818
 819 static inline void hdmi_phy_test_enable(struct mxc_hdmi *hdmi,
 820                                                 unsigned char bit)
 821 {
 822         u8 val = hdmi_readb(HDMI_PHY_TST0);
 823         val &= ~HDMI_PHY_TST0_TSTEN_MASK;
 824         val |= (bit << HDMI_PHY_TST0_TSTEN_OFFSET) &
 825                 HDMI_PHY_TST0_TSTEN_MASK;
 826         hdmi_writeb(val, HDMI_PHY_TST0);
 827 }
 828
 829 static inline void hdmi_phy_test_clock(struct mxc_hdmi *hdmi,
 830                                                 unsigned char bit)
 831 {
 832         u8 val = hdmi_readb(HDMI_PHY_TST0);
 833         val &= ~HDMI_PHY_TST0_TSTCLK_MASK;
 834         val |= (bit << HDMI_PHY_TST0_TSTCLK_OFFSET) &
 835                 HDMI_PHY_TST0_TSTCLK_MASK;
 836         hdmi_writeb(val, HDMI_PHY_TST0);
 837 }
 838
 839 static inline void hdmi_phy_test_din(struct mxc_hdmi *hdmi,
 840                                                 unsigned char bit)
 841 {
 842         hdmi_writeb(bit, HDMI_PHY_TST1);
 843 }
 844
 845 static inline void hdmi_phy_test_dout(struct mxc_hdmi *hdmi,
 846                                                 unsigned char bit)
 847 {
 848         hdmi_writeb(bit, HDMI_PHY_TST2);
 849 }
 850
 851 static bool hdmi_phy_wait_i2c_done(struct mxc_hdmi *hdmi, int msec)
 852 {
 853         unsigned char val = 0;
 854         val = hdmi_readb(HDMI_IH_I2CMPHY_STAT0) & 0x3;
 855         while (val == 0) {
 856                 udelay(1000);
 857                 if (msec-- == 0)
 858                         return false;
 859                 val = hdmi_readb(HDMI_IH_I2CMPHY_STAT0) & 0x3;
 860         }
 861         return true;
 862 }
 863
 864 static void hdmi_phy_i2c_write(struct mxc_hdmi *hdmi, unsigned short data,
 865                               unsigned char addr)
 866 {
 867         hdmi_writeb(0xFF, HDMI_IH_I2CMPHY_STAT0);
 868         hdmi_writeb(addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
 869         hdmi_writeb((unsigned char)(data >> 8),
 870                 HDMI_PHY_I2CM_DATAO_1_ADDR);
 871         hdmi_writeb((unsigned char)(data >> 0),
 872                 HDMI_PHY_I2CM_DATAO_0_ADDR);
 873         hdmi_writeb(HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
 874                 HDMI_PHY_I2CM_OPERATION_ADDR);
 875         hdmi_phy_wait_i2c_done(hdmi, 1000);
 876 }
 877
 878 #if 0
 879 static unsigned short hdmi_phy_i2c_read(struct mxc_hdmi *hdmi,
 880                                         unsigned char addr)
 881 {
 882         unsigned short data;
 883         unsigned char msb = 0, lsb = 0;
 884         hdmi_writeb(0xFF, HDMI_IH_I2CMPHY_STAT0);
 885         hdmi_writeb(addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
 886         hdmi_writeb(HDMI_PHY_I2CM_OPERATION_ADDR_READ,
 887                 HDMI_PHY_I2CM_OPERATION_ADDR);
 888         hdmi_phy_wait_i2c_done(hdmi, 1000);
 889         msb = hdmi_readb(HDMI_PHY_I2CM_DATAI_1_ADDR);
 890         lsb = hdmi_readb(HDMI_PHY_I2CM_DATAI_0_ADDR);
 891         data = (msb << 8) | lsb;
 892         return data;
 893 }
 894
 895 static int hdmi_phy_i2c_write_verify(struct mxc_hdmi *hdmi, unsigned short data,
 896                                      unsigned char addr)
 897 {
 898         unsigned short val = 0;
 899         hdmi_phy_i2c_write(hdmi, data, addr);
 900         val = hdmi_phy_i2c_read(hdmi, addr);
 901         return (val == data);
 902 }
 903 #endif
 904
 905 static bool  hdmi_edid_wait_i2c_done(struct mxc_hdmi *hdmi, int msec)
 906 {
 907     unsigned char val = 0;
 908     val = hdmi_readb(HDMI_IH_I2CM_STAT0) & 0x2;
 909     while (val == 0) {
 910
 911                 udelay(1000);
 912                 if (msec-- == 0) {
 913                         dev_dbg(&hdmi->pdev->dev,
 914                                         "HDMI EDID i2c operation time out!!\n");
 915                         return false;
 916                 }
 917                 val = hdmi_readb(HDMI_IH_I2CM_STAT0) & 0x2;
 918         }
 919         return true;
 920 }
 921
 922 static u8 hdmi_edid_i2c_read(struct mxc_hdmi *hdmi,
 923                                         u8 addr, u8 blockno)
 924 {
 925         u8 spointer = blockno / 2;
 926         u8 edidaddress = ((blockno % 2) * 0x80) + addr;
 927         u8 data;
 928
 929         hdmi_writeb(0xFF, HDMI_IH_I2CM_STAT0);
 930         hdmi_writeb(edidaddress, HDMI_I2CM_ADDRESS);
 931         hdmi_writeb(spointer, HDMI_I2CM_SEGADDR);
 932         if (spointer == 0)
 933                 hdmi_writeb(HDMI_I2CM_OPERATION_READ,
 934                         HDMI_I2CM_OPERATION);
 935         else
 936                 hdmi_writeb(HDMI_I2CM_OPERATION_READ_EXT,
 937                         HDMI_I2CM_OPERATION);
 938
 939         hdmi_edid_wait_i2c_done(hdmi, 1000);
 940         data = hdmi_readb(HDMI_I2CM_DATAI);
 941         hdmi_writeb(0xFF, HDMI_IH_I2CM_STAT0);
 942         return data;
 943 }
 944
 945
 946 /* "Power-down enable (active low)"
 947  * That mean that power up == 1! */
 948 static void mxc_hdmi_phy_enable_power(u8 enable)
 949 {
 950         hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
 951                         HDMI_PHY_CONF0_PDZ_OFFSET,
 952                         HDMI_PHY_CONF0_PDZ_MASK);
 953 }
 954
 955 static void mxc_hdmi_phy_enable_tmds(u8 enable)
 956 {
 957         hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
 958                         HDMI_PHY_CONF0_ENTMDS_OFFSET,
 959                         HDMI_PHY_CONF0_ENTMDS_MASK);
 960 }
 961
 962 static void mxc_hdmi_phy_gen2_pddq(u8 enable)
 963 {
 964         hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
 965                         HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
 966                         HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
 967 }
 968
 969 static void mxc_hdmi_phy_gen2_txpwron(u8 enable)
 970 {
 971         hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
 972                         HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
 973                         HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
 974 }
 975
 976 #if 0
 977 static void mxc_hdmi_phy_gen2_enhpdrxsense(u8 enable)
 978 {
 979         hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
 980                         HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET,
 981                         HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK);
 982 }
 983 #endif
 984
 985 static void mxc_hdmi_phy_sel_data_en_pol(u8 enable)
 986 {
 987         hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
 988                         HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
 989                         HDMI_PHY_CONF0_SELDATAENPOL_MASK);
 990 }
 991
 992 static void mxc_hdmi_phy_sel_interface_control(u8 enable)
 993 {
 994         hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
 995                         HDMI_PHY_CONF0_SELDIPIF_OFFSET,
 996                         HDMI_PHY_CONF0_SELDIPIF_MASK);
 997 }
 998
 999 static int hdmi_phy_configure(struct mxc_hdmi *hdmi, unsigned char pRep,
1000                               unsigned char cRes, int cscOn)
1001 {
1002         u8 val;
1003         u8 msec;
1004
1005         dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1006
1007         /* color resolution 0 is 8 bit colour depth */
1008         if (cRes == 0)
1009                 cRes = 8;
1010
1011         if (pRep != 0)
1012                 return false;
1013         else if (cRes != 8 && cRes != 12)
1014                 return false;
1015
1016         /* Enable csc path */
1017         if (cscOn)
1018                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
1019         else
1020                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
1021
1022         hdmi_writeb(val, HDMI_MC_FLOWCTRL);
1023
1024         /* gen2 tx power off */
1025         mxc_hdmi_phy_gen2_txpwron(0);
1026
1027         /* gen2 pddq */
1028         mxc_hdmi_phy_gen2_pddq(1);
1029
1030         /* PHY reset */
1031         hdmi_writeb(HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
1032         hdmi_writeb(HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
1033
1034         hdmi_writeb(HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1035
1036         hdmi_phy_test_clear(hdmi, 1);
1037         hdmi_writeb(HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
1038                         HDMI_PHY_I2CM_SLAVE_ADDR);
1039         hdmi_phy_test_clear(hdmi, 0);
1040
1041         if (hdmi->hdmi_data.video_mode.mPixelClock < 0) {
1042                 dev_dbg(&hdmi->pdev->dev, "Pixel clock (%d) must be positive\n",
1043                         hdmi->hdmi_data.video_mode.mPixelClock);
1044                 return false;
1045         }
1046
1047         if (hdmi->hdmi_data.video_mode.mPixelClock <= 45250000) {
1048                 switch (cRes) {
1049                 case 8:
1050                         /* PLL/MPLL Cfg */
1051                         hdmi_phy_i2c_write(hdmi, 0x01e0, 0x06);
1052                         hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);  /* GMPCTRL */
1053                         break;
1054                 case 10:
1055                         hdmi_phy_i2c_write(hdmi, 0x21e1, 0x06);
1056                         hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);
1057                         break;
1058                 case 12:
1059                         hdmi_phy_i2c_write(hdmi, 0x41e2, 0x06);
1060                         hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);
1061                         break;
1062                 default:
1063                         return false;
1064                 }
1065         } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 92500000) {
1066                 switch (cRes) {
1067                 case 8:
1068                         hdmi_phy_i2c_write(hdmi, 0x0140, 0x06);
1069                         hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
1070                         break;
1071                 case 10:
1072                         hdmi_phy_i2c_write(hdmi, 0x2141, 0x06);
1073                         hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
1074                         break;
1075                 case 12:
1076                         hdmi_phy_i2c_write(hdmi, 0x4142, 0x06);
1077                         hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
1078                 default:
1079                         return false;
1080                 }
1081         } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 148500000) {
1082                 switch (cRes) {
1083                 case 8:
1084                         hdmi_phy_i2c_write(hdmi, 0x00a0, 0x06);
1085                         hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
1086                         break;
1087                 case 10:
1088                         hdmi_phy_i2c_write(hdmi, 0x20a1, 0x06);
1089                         hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
1090                         break;
1091                 case 12:
1092                         hdmi_phy_i2c_write(hdmi, 0x40a2, 0x06);
1093                         hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
1094                 default:
1095                         return false;
1096                 }
1097         } else {
1098                 switch (cRes) {
1099                 case 8:
1100                         hdmi_phy_i2c_write(hdmi, 0x00a0, 0x06);
1101                         hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
1102                         break;
1103                 case 10:
1104                         hdmi_phy_i2c_write(hdmi, 0x2001, 0x06);
1105                         hdmi_phy_i2c_write(hdmi, 0x000f, 0x15);
1106                         break;
1107                 case 12:
1108                         hdmi_phy_i2c_write(hdmi, 0x4002, 0x06);
1109                         hdmi_phy_i2c_write(hdmi, 0x000f, 0x15);
1110                 default:
1111                         return false;
1112                 }
1113         }
1114
1115         if (hdmi->hdmi_data.video_mode.mPixelClock <= 54000000) {
1116                 switch (cRes) {
1117                 case 8:
1118                         hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);  /* CURRCTRL */
1119                         break;
1120                 case 10:
1121                         hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
1122                         break;
1123                 case 12:
1124                         hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
1125                         break;
1126                 default:
1127                         return false;
1128                 }
1129         } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 58400000) {
1130                 switch (cRes) {
1131                 case 8:
1132                         hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
1133                         break;
1134                 case 10:
1135                         hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
1136                         break;
1137                 case 12:
1138                         hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
1139                         break;
1140                 default:
1141                         return false;
1142                 }
1143         } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 72000000) {
1144                 switch (cRes) {
1145                 case 8:
1146                         hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
1147                         break;
1148                 case 10:
1149                         hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
1150                         break;
1151                 case 12:
1152                         hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
1153                         break;
1154                 default:
1155                         return false;
1156                 }
1157         } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 74250000) {
1158                 switch (cRes) {
1159                 case 8:
1160                         hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
1161                         break;
1162                 case 10:
1163                         hdmi_phy_i2c_write(hdmi, 0x0b5c, 0x10);
1164                         break;
1165                 case 12:
1166                         hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
1167                         break;
1168                 default:
1169                         return false;
1170                 }
1171         } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 118800000) {
1172                 switch (cRes) {
1173                 case 8:
1174                         hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
1175                         break;
1176                 case 10:
1177                         hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
1178                         break;
1179                 case 12:
1180                         hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
1181                         break;
1182                 default:
1183                         return false;
1184                 }
1185         } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 216000000) {
1186                 switch (cRes) {
1187                 case 8:
1188                         hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
1189                         break;
1190                 case 10:
1191                         hdmi_phy_i2c_write(hdmi, 0x0b5c, 0x10);
1192                         break;
1193                 case 12:
1194                         hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
1195                         break;
1196                 default:
1197                         return false;
1198                 }
1199         } else {
1200                 dev_err(&hdmi->pdev->dev,
1201                                 "Pixel clock %d - unsupported by HDMI\n",
1202                                 hdmi->hdmi_data.video_mode.mPixelClock);
1203                 return false;
1204         }
1205
1206         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
1207         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
1208         /* RESISTANCE TERM 133Ohm Cfg */
1209         hdmi_phy_i2c_write(hdmi, 0x0005, 0x19);  /* TXTERM */
1210         /* PREEMP Cgf 0.00 */
1211         hdmi_phy_i2c_write(hdmi, 0x800d, 0x09);  /* CKSYMTXCTRL */
1212         /* TX/CK LVL 10 */
1213         hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E);  /* VLEVCTRL */
1214
1215         /* Board specific setting for PHY register 0x09, 0x0e to pass HCT */
1216         if (hdmi->phy_config.reg_cksymtx != 0)
1217                 hdmi_phy_i2c_write(hdmi, hdmi->phy_config.reg_cksymtx, 0x09);
1218
1219         if (hdmi->phy_config.reg_vlev != 0)
1220                 hdmi_phy_i2c_write(hdmi, hdmi->phy_config.reg_vlev, 0x0E);
1221
1222         /* REMOVE CLK TERM */
1223         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
1224
1225         if (hdmi->hdmi_data.video_mode.mPixelClock > 148500000) {
1226                         hdmi_phy_i2c_write(hdmi, 0x800b, 0x09);
1227                         hdmi_phy_i2c_write(hdmi, 0x0129, 0x0E);
1228         }
1229
1230         mxc_hdmi_phy_enable_power(1);
1231
1232         /* toggle TMDS enable */
1233         mxc_hdmi_phy_enable_tmds(0);
1234         mxc_hdmi_phy_enable_tmds(1);
1235
1236         /* gen2 tx power on */
1237         mxc_hdmi_phy_gen2_txpwron(1);
1238         mxc_hdmi_phy_gen2_pddq(0);
1239
1240         /*Wait for PHY PLL lock */
1241         msec = 4;
1242         val = hdmi_readb(HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1243         while (val == 0) {
1244                 udelay(1000);
1245                 if (msec-- == 0) {
1246                         dev_dbg(&hdmi->pdev->dev, "PHY PLL not locked\n");
1247                         return false;
1248                 }
1249                 val = hdmi_readb(HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1250         }
1251
1252         return true;
1253 }
1254
1255 static void mxc_hdmi_phy_init(struct mxc_hdmi *hdmi)
1256 {
1257         int i;
1258         bool cscon = false;
1259
1260         dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1261
1262         /* Never do phy init if pixel clock is gated.
1263          * Otherwise HDMI PHY will get messed up and generate an overflow
1264          * interrupt that can't be cleared or detected by accessing the
1265          * status register. */
1266         if (!hdmi->fb_reg || !hdmi->cable_plugin
1267                         || (hdmi->blank != FB_BLANK_UNBLANK))
1268                 return;
1269
1270         if (!hdmi->hdmi_data.video_mode.mDVI)
1271                 hdmi_enable_overflow_interrupts();
1272
1273         /*check csc whether needed activated in HDMI mode */
1274         cscon = (isColorSpaceConversion(hdmi) &&
1275                         !hdmi->hdmi_data.video_mode.mDVI);
1276
1277         /* HDMI Phy spec says to do the phy initialization sequence twice */
1278         for (i = 0 ; i < 2 ; i++) {
1279                 mxc_hdmi_phy_sel_data_en_pol(1);
1280                 mxc_hdmi_phy_sel_interface_control(0);
1281                 mxc_hdmi_phy_enable_tmds(0);
1282                 mxc_hdmi_phy_enable_power(0);
1283
1284                 /* Enable CSC */
1285                 hdmi_phy_configure(hdmi, 0, 8, cscon);
1286         }
1287
1288         hdmi->phy_enabled = true;
1289 }
1290
1291 static void hdmi_config_AVI(struct mxc_hdmi *hdmi)
1292 {
1293         u8 val;
1294         u8 pix_fmt;
1295         u8 under_scan;
1296         u8 act_ratio, coded_ratio, colorimetry, ext_colorimetry;
1297         struct fb_videomode mode;
1298         const struct fb_videomode *edid_mode;
1299         bool aspect_16_9;
1300
1301         dev_dbg(&hdmi->pdev->dev, "set up AVI frame\n");
1302
1303         fb_var_to_videomode(&mode, &hdmi->fbi->var);
1304         /* Use mode from list extracted from EDID to get aspect ratio */
1305         if (!list_empty(&hdmi->fbi->modelist)) {
1306                 edid_mode = fb_find_nearest_mode(&mode, &hdmi->fbi->modelist);
1307                 if (edid_mode->vmode & FB_VMODE_ASPECT_16_9)
1308                         aspect_16_9 = true;
1309                 else
1310                         aspect_16_9 = false;
1311         } else
1312                 aspect_16_9 = false;
1313
1314         /********************************************
1315          * AVI Data Byte 1
1316          ********************************************/
1317         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
1318                 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR444;
1319         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
1320                 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR422;
1321         else
1322                 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_RGB;
1323
1324         if (hdmi->edid_cfg.cea_underscan)
1325                 under_scan = HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN;
1326         else
1327                 under_scan =  HDMI_FC_AVICONF0_SCAN_INFO_NODATA;
1328
1329         /*
1330          * Active format identification data is present in the AVI InfoFrame.
1331          * Under scan info, no bar data
1332          */
1333         val = pix_fmt | under_scan |
1334                 HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT |
1335                 HDMI_FC_AVICONF0_BAR_DATA_NO_DATA;
1336
1337         hdmi_writeb(val, HDMI_FC_AVICONF0);
1338
1339         /********************************************
1340          * AVI Data Byte 2
1341          ********************************************/
1342
1343         /*  Set the Aspect Ratio */
1344         if (aspect_16_9) {
1345                 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9;
1346                 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9;
1347         } else {
1348                 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3;
1349                 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3;
1350         }
1351
1352         /* Set up colorimetry */
1353         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
1354                 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO;
1355                 if (hdmi->hdmi_data.colorimetry == eITU601)
1356                         ext_colorimetry =
1357                                 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
1358                 else /* hdmi->hdmi_data.colorimetry == eITU709 */
1359                         ext_colorimetry =
1360                                 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709;
1361         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
1362                 if (hdmi->hdmi_data.colorimetry == eITU601)
1363                         colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_SMPTE;
1364                 else /* hdmi->hdmi_data.colorimetry == eITU709 */
1365                         colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_ITUR;
1366                 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
1367         } else { /* Carries no data */
1368                 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA;
1369                 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
1370         }
1371
1372         val = colorimetry | coded_ratio | act_ratio;
1373         hdmi_writeb(val, HDMI_FC_AVICONF1);
1374
1375         /********************************************
1376          * AVI Data Byte 3
1377          ********************************************/
1378
1379         val = HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA | ext_colorimetry |
1380                 HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT |
1381                 HDMI_FC_AVICONF2_SCALING_NONE;
1382         hdmi_writeb(val, HDMI_FC_AVICONF2);
1383
1384         /********************************************
1385          * AVI Data Byte 4
1386          ********************************************/
1387         hdmi_writeb(hdmi->vic, HDMI_FC_AVIVID);
1388
1389         /********************************************
1390          * AVI Data Byte 5
1391          ********************************************/
1392
1393         /* Set up input and output pixel repetition */
1394         val = (((hdmi->hdmi_data.video_mode.mPixelRepetitionInput + 1) <<
1395                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1396                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1397                 ((hdmi->hdmi_data.video_mode.mPixelRepetitionOutput <<
1398                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1399                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1400         hdmi_writeb(val, HDMI_FC_PRCONF);
1401
1402         /* IT Content and quantization range = don't care */
1403         val = HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS |
1404                 HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED;
1405         hdmi_writeb(val, HDMI_FC_AVICONF3);
1406
1407         /********************************************
1408          * AVI Data Bytes 6-13
1409          ********************************************/
1410         hdmi_writeb(0, HDMI_FC_AVIETB0);
1411         hdmi_writeb(0, HDMI_FC_AVIETB1);
1412         hdmi_writeb(0, HDMI_FC_AVISBB0);
1413         hdmi_writeb(0, HDMI_FC_AVISBB1);
1414         hdmi_writeb(0, HDMI_FC_AVIELB0);
1415         hdmi_writeb(0, HDMI_FC_AVIELB1);
1416         hdmi_writeb(0, HDMI_FC_AVISRB0);
1417         hdmi_writeb(0, HDMI_FC_AVISRB1);
1418 }
1419
1420 /*!
1421  * this submodule is responsible for the video/audio data composition.
1422  */
1423 static void hdmi_av_composer(struct mxc_hdmi *hdmi)
1424 {
1425         u8 inv_val;
1426         struct fb_info *fbi = hdmi->fbi;
1427         struct fb_videomode fb_mode;
1428         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1429         int hblank, vblank;
1430
1431         dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1432
1433         fb_var_to_videomode(&fb_mode, &fbi->var);
1434
1435         vmode->mHSyncPolarity = ((fb_mode.sync & FB_SYNC_HOR_HIGH_ACT) != 0);
1436         vmode->mVSyncPolarity = ((fb_mode.sync & FB_SYNC_VERT_HIGH_ACT) != 0);
1437         vmode->mInterlaced = ((fb_mode.vmode & FB_VMODE_INTERLACED) != 0);
1438         vmode->mPixelClock = (fb_mode.xres + fb_mode.left_margin +
1439                 fb_mode.right_margin + fb_mode.hsync_len) * (fb_mode.yres +
1440                 fb_mode.upper_margin + fb_mode.lower_margin +
1441                 fb_mode.vsync_len) * fb_mode.refresh;
1442
1443         dev_dbg(&hdmi->pdev->dev, "final pixclk = %d\n", vmode->mPixelClock);
1444
1445         /* Set up HDMI_FC_INVIDCONF */
1446         inv_val = (vmode->mVSyncPolarity ?
1447                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1448                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
1449
1450         inv_val |= (vmode->mHSyncPolarity ?
1451                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1452                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
1453
1454         inv_val |= (vmode->mDataEnablePolarity ?
1455                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1456                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1457
1458         if (hdmi->vic == 39)
1459                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1460         else
1461                 inv_val |= (vmode->mInterlaced ?
1462                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1463                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW);
1464
1465         inv_val |= (vmode->mInterlaced ?
1466                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1467                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE);
1468
1469         inv_val |= (vmode->mDVI ?
1470                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE :
1471                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE);
1472
1473         hdmi_writeb(inv_val, HDMI_FC_INVIDCONF);
1474
1475         /* Set up horizontal active pixel region width */
1476         hdmi_writeb(fb_mode.xres >> 8, HDMI_FC_INHACTV1);
1477         hdmi_writeb(fb_mode.xres, HDMI_FC_INHACTV0);
1478
1479         /* Set up vertical blanking pixel region width */
1480         hdmi_writeb(fb_mode.yres >> 8, HDMI_FC_INVACTV1);
1481         hdmi_writeb(fb_mode.yres, HDMI_FC_INVACTV0);
1482
1483         /* Set up horizontal blanking pixel region width */
1484         hblank = fb_mode.left_margin + fb_mode.right_margin +
1485                 fb_mode.hsync_len;
1486         hdmi_writeb(hblank >> 8, HDMI_FC_INHBLANK1);
1487         hdmi_writeb(hblank, HDMI_FC_INHBLANK0);
1488
1489         /* Set up vertical blanking pixel region width */
1490         vblank = fb_mode.upper_margin + fb_mode.lower_margin +
1491                 fb_mode.vsync_len;
1492         hdmi_writeb(vblank, HDMI_FC_INVBLANK);
1493
1494         /* Set up HSYNC active edge delay width (in pixel clks) */
1495         hdmi_writeb(fb_mode.right_margin >> 8, HDMI_FC_HSYNCINDELAY1);
1496         hdmi_writeb(fb_mode.right_margin, HDMI_FC_HSYNCINDELAY0);
1497
1498         /* Set up VSYNC active edge delay (in pixel clks) */
1499         hdmi_writeb(fb_mode.lower_margin, HDMI_FC_VSYNCINDELAY);
1500
1501         /* Set up HSYNC active pulse width (in pixel clks) */
1502         hdmi_writeb(fb_mode.hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1503         hdmi_writeb(fb_mode.hsync_len, HDMI_FC_HSYNCINWIDTH0);
1504
1505         /* Set up VSYNC active edge delay (in pixel clks) */
1506         hdmi_writeb(fb_mode.vsync_len, HDMI_FC_VSYNCINWIDTH);
1507
1508         dev_dbg(&hdmi->pdev->dev, "%s exit\n", __func__);
1509 }
1510
1511 static int mxc_edid_read_internal(struct mxc_hdmi *hdmi, unsigned char *edid,
1512                         struct mxc_edid_cfg *cfg, struct fb_info *fbi)
1513 {
1514         int extblknum;
1515         int i, j, ret;
1516         unsigned char *ediddata = edid;
1517         unsigned char tmpedid[EDID_LENGTH];
1518
1519         dev_info(&hdmi->pdev->dev, "%s\n", __func__);
1520
1521         if (!edid || !cfg || !fbi)
1522                 return -EINVAL;
1523
1524         /* init HDMI I2CM for read edid*/
1525         hdmi_writeb(0x0, HDMI_I2CM_DIV);
1526         hdmi_writeb(0x00, HDMI_I2CM_SS_SCL_HCNT_1_ADDR);
1527         hdmi_writeb(0x79, HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
1528         hdmi_writeb(0x00, HDMI_I2CM_SS_SCL_LCNT_1_ADDR);
1529         hdmi_writeb(0x91, HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
1530
1531         hdmi_writeb(0x00, HDMI_I2CM_FS_SCL_HCNT_1_ADDR);
1532         hdmi_writeb(0x0F, HDMI_I2CM_FS_SCL_HCNT_0_ADDR);
1533         hdmi_writeb(0x00, HDMI_I2CM_FS_SCL_LCNT_1_ADDR);
1534         hdmi_writeb(0x21, HDMI_I2CM_FS_SCL_LCNT_0_ADDR);
1535
1536         hdmi_writeb(0x50, HDMI_I2CM_SLAVE);
1537         hdmi_writeb(0x30, HDMI_I2CM_SEGADDR);
1538
1539         /* Umask edid interrupt */
1540         hdmi_writeb(HDMI_I2CM_INT_DONE_POL,
1541                     HDMI_I2CM_INT);
1542
1543         hdmi_writeb(HDMI_I2CM_CTLINT_NAC_POL |
1544                     HDMI_I2CM_CTLINT_ARBITRATION_POL,
1545                     HDMI_I2CM_CTLINT);
1546
1547         /* reset edid data zero */
1548         memset(edid, 0, EDID_LENGTH*4);
1549         memset(cfg, 0, sizeof(struct mxc_edid_cfg));
1550
1551         /* Check first three byte of EDID head */
1552         if (!(hdmi_edid_i2c_read(hdmi, 0, 0) == 0x00) ||
1553                 !(hdmi_edid_i2c_read(hdmi, 1, 0) == 0xFF) ||
1554                 !(hdmi_edid_i2c_read(hdmi, 2, 0) == 0xFF)) {
1555                 dev_info(&hdmi->pdev->dev, "EDID head check failed!");
1556                 return -ENOENT;
1557         }
1558
1559         for (i = 0; i < 128; i++) {
1560                 *ediddata = hdmi_edid_i2c_read(hdmi, i, 0);
1561                 ediddata++;
1562         }
1563
1564         extblknum = edid[0x7E];
1565         if (extblknum < 0)
1566                 return extblknum;
1567
1568         if (extblknum) {
1569                 ediddata = edid + EDID_LENGTH;
1570                 for (i = 0; i < 128; i++) {
1571                         *ediddata = hdmi_edid_i2c_read(hdmi, i, 1);
1572                         ediddata++;
1573                 }
1574         }
1575
1576         /* edid first block parsing */
1577         memset(&fbi->monspecs, 0, sizeof(fbi->monspecs));
1578         fb_edid_to_monspecs(edid, &fbi->monspecs);
1579
1580         ret = mxc_edid_parse_ext_blk(edid + EDID_LENGTH,
1581                         cfg, &fbi->monspecs);
1582         if (ret < 0)
1583                 return -ENOENT;
1584
1585         /* need read segment block? */
1586         if (extblknum > 1) {
1587                 for (j = 1; j <= extblknum; j++) {
1588                         for (i = 0; i < 128; i++)
1589                                 *(tmpedid + 1) = hdmi_edid_i2c_read(hdmi, i, j);
1590
1591                         /* edid ext block parsing */
1592                         ret = mxc_edid_parse_ext_blk(tmpedid + EDID_LENGTH,
1593                                         cfg, &fbi->monspecs);
1594                         if (ret < 0)
1595                                 return -ENOENT;
1596                 }
1597         }
1598
1599         return 0;
1600 }
1601
1602 static int mxc_hdmi_read_edid(struct mxc_hdmi *hdmi)
1603 {
1604         int ret;
1605         u8 edid_old[HDMI_EDID_LEN];
1606         u8 clkdis;
1607
1608         dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1609
1610         /* save old edid */
1611         memcpy(edid_old, hdmi->edid, HDMI_EDID_LEN);
1612
1613         /* Read EDID via HDMI DDC when HDCP Enable */
1614         if (!hdcp_init)
1615                 ret = mxc_edid_read(hdmi_i2c->adapter, hdmi_i2c->addr,
1616                                 hdmi->edid, &hdmi->edid_cfg, hdmi->fbi);
1617         else {
1618
1619                 /* Disable HDCP clk */
1620                 if (hdmi->hdmi_data.hdcp_enable) {
1621                         clkdis = hdmi_readb(HDMI_MC_CLKDIS);
1622                         clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE;
1623                         hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
1624                 }
1625
1626                 ret = mxc_edid_read_internal(hdmi, hdmi->edid,
1627                                 &hdmi->edid_cfg, hdmi->fbi);
1628
1629                 /* Enable HDCP clk */
1630                 if (hdmi->hdmi_data.hdcp_enable) {
1631                         clkdis = hdmi_readb(HDMI_MC_CLKDIS);
1632                         clkdis &= ~HDMI_MC_CLKDIS_HDCPCLK_DISABLE;
1633                         hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
1634                 }
1635
1636         }
1637         if (ret < 0)
1638                 return HDMI_EDID_FAIL;
1639
1640         /* Save edid cfg for audio driver */
1641         hdmi_set_edid_cfg(&hdmi->edid_cfg);
1642
1643         if (!memcmp(edid_old, hdmi->edid, HDMI_EDID_LEN)) {
1644                 dev_info(&hdmi->pdev->dev, "same edid\n");
1645                 return HDMI_EDID_SAME;
1646         }
1647
1648         if (hdmi->fbi->monspecs.modedb_len == 0) {
1649                 dev_info(&hdmi->pdev->dev, "No modes read from edid\n");
1650                 return HDMI_EDID_NO_MODES;
1651         }
1652
1653         return HDMI_EDID_SUCCESS;
1654 }
1655
1656 static void mxc_hdmi_phy_disable(struct mxc_hdmi *hdmi)
1657 {
1658         dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1659
1660         if (!hdmi->phy_enabled)
1661                 return;
1662
1663         hdmi_disable_overflow_interrupts();
1664
1665         /* Setting PHY to reset status */
1666         hdmi_writeb(HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
1667
1668         /* Power down PHY */
1669         mxc_hdmi_phy_enable_tmds(0);
1670         mxc_hdmi_phy_enable_power(0);
1671         mxc_hdmi_phy_gen2_txpwron(0);
1672         mxc_hdmi_phy_gen2_pddq(1);
1673
1674         hdmi->phy_enabled = false;
1675         dev_dbg(&hdmi->pdev->dev, "%s - exit\n", __func__);
1676 }
1677
1678 /* HDMI Initialization Step B.4 */
1679 static void mxc_hdmi_enable_video_path(struct mxc_hdmi *hdmi)
1680 {
1681         u8 clkdis;
1682
1683         dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1684
1685         /* control period minimum duration */
1686         hdmi_writeb(12, HDMI_FC_CTRLDUR);
1687         hdmi_writeb(32, HDMI_FC_EXCTRLDUR);
1688         hdmi_writeb(1, HDMI_FC_EXCTRLSPAC);
1689
1690         /* Set to fill TMDS data channels */
1691         hdmi_writeb(0x0B, HDMI_FC_CH0PREAM);
1692         hdmi_writeb(0x16, HDMI_FC_CH1PREAM);
1693         hdmi_writeb(0x21, HDMI_FC_CH2PREAM);
1694
1695         /* Enable pixel clock and tmds data path */
1696         clkdis = 0x7F;
1697         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1698         hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
1699
1700         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1701         hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
1702
1703         /* Enable csc path */
1704         if (isColorSpaceConversion(hdmi)) {
1705                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1706                 hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
1707         }
1708 }
1709
1710 static void hdmi_enable_audio_clk(struct mxc_hdmi *hdmi)
1711 {
1712         u8 clkdis;
1713
1714         dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1715
1716         clkdis = hdmi_readb(HDMI_MC_CLKDIS);
1717         clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
1718         hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
1719 }
1720
1721 /* Workaround to clear the overflow condition */
1722 static void mxc_hdmi_clear_overflow(struct mxc_hdmi *hdmi)
1723 {
1724         int count;
1725         u8 val;
1726
1727         /* TMDS software reset */
1728         hdmi_writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1729
1730         val = hdmi_readb(HDMI_FC_INVIDCONF);
1731
1732         if (cpu_is_imx6dl(hdmi)) {
1733                  hdmi_writeb(val, HDMI_FC_INVIDCONF);
1734                  return;
1735         }
1736
1737         for (count = 0 ; count < 5 ; count++)
1738                 hdmi_writeb(val, HDMI_FC_INVIDCONF);
1739 }
1740
1741 static void hdmi_enable_overflow_interrupts(void)
1742 {
1743         pr_debug("%s\n", __func__);
1744         hdmi_writeb(0, HDMI_FC_MASK2);
1745         hdmi_writeb(0, HDMI_IH_MUTE_FC_STAT2);
1746 }
1747
1748 static void hdmi_disable_overflow_interrupts(void)
1749 {
1750         pr_debug("%s\n", __func__);
1751         hdmi_writeb(HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1752                     HDMI_IH_MUTE_FC_STAT2);
1753         hdmi_writeb(0xff, HDMI_FC_MASK2);
1754 }
1755
1756 static void mxc_hdmi_notify_fb(struct mxc_hdmi *hdmi)
1757 {
1758         dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1759
1760         /* Don't notify if we aren't registered yet */
1761         WARN_ON(!hdmi->fb_reg);
1762
1763         /* disable the phy before ipu changes mode */
1764         mxc_hdmi_phy_disable(hdmi);
1765
1766         /*
1767          * Note that fb_set_var will block.  During this time,
1768          * FB_EVENT_MODE_CHANGE callback will happen.
1769          * So by the end of this function, mxc_hdmi_setup()
1770          * will be done.
1771          */
1772         hdmi->fbi->var.activate |= FB_ACTIVATE_FORCE;
1773         console_lock();
1774         hdmi->fbi->flags |= FBINFO_MISC_USEREVENT;
1775         fb_set_var(hdmi->fbi, &hdmi->fbi->var);
1776         hdmi->fbi->flags &= ~FBINFO_MISC_USEREVENT;
1777         console_unlock();
1778
1779         dev_dbg(&hdmi->pdev->dev, "%s exit\n", __func__);
1780 }
1781
1782 static void mxc_hdmi_edid_rebuild_modelist(struct mxc_hdmi *hdmi)
1783 {
1784         int i;
1785         struct fb_videomode *mode;
1786
1787         dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1788
1789         console_lock();
1790
1791         fb_destroy_modelist(&hdmi->fbi->modelist);
1792         fb_add_videomode(&vga_mode, &hdmi->fbi->modelist);
1793
1794         for (i = 0; i < hdmi->fbi->monspecs.modedb_len; i++) {
1795                 /*
1796                  * We might check here if mode is supported by HDMI.
1797                  * We do not currently support interlaced modes.
1798                  * And add CEA modes in the modelist.
1799                  */
1800                 mode = &hdmi->fbi->monspecs.modedb[i];
1801
1802                 if (!(mode->vmode & FB_VMODE_INTERLACED) &&
1803                                 (mxc_edid_mode_to_vic(mode) != 0)) {
1804
1805                         dev_dbg(&hdmi->pdev->dev, "Added mode %d:", i);
1806                         dev_dbg(&hdmi->pdev->dev,
1807                                 "xres = %d, yres = %d, freq = %d, vmode = %d, flag = %d\n",
1808                                 hdmi->fbi->monspecs.modedb[i].xres,
1809                                 hdmi->fbi->monspecs.modedb[i].yres,
1810                                 hdmi->fbi->monspecs.modedb[i].refresh,
1811                                 hdmi->fbi->monspecs.modedb[i].vmode,
1812                                 hdmi->fbi->monspecs.modedb[i].flag);
1813
1814                         fb_add_videomode(mode, &hdmi->fbi->modelist);
1815                 }
1816         }
1817
1818         console_unlock();
1819 }
1820
1821 static void  mxc_hdmi_default_edid_cfg(struct mxc_hdmi *hdmi)
1822 {
1823         /* Default setting HDMI working in HDMI mode */
1824         hdmi->edid_cfg.hdmi_cap = true;
1825 }
1826
1827 static void  mxc_hdmi_default_modelist(struct mxc_hdmi *hdmi)
1828 {
1829         u32 i;
1830         const struct fb_videomode *mode;
1831
1832         dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1833
1834         /* If not EDID data read, set up default modelist  */
1835         dev_info(&hdmi->pdev->dev, "No modes read from edid\n");
1836         dev_info(&hdmi->pdev->dev, "create default modelist\n");
1837
1838         console_lock();
1839
1840         fb_destroy_modelist(&hdmi->fbi->modelist);
1841
1842         /*Add all no interlaced CEA mode to default modelist */
1843         for (i = 0; i < ARRAY_SIZE(mxc_cea_mode); i++) {
1844                 mode = &mxc_cea_mode[i];
1845                 if (!(mode->vmode & FB_VMODE_INTERLACED) && (mode->xres != 0))
1846                         fb_add_videomode(mode, &hdmi->fbi->modelist);
1847         }
1848
1849         console_unlock();
1850 }
1851
1852 static void mxc_hdmi_set_mode_to_vga_dvi(struct mxc_hdmi *hdmi)
1853 {
1854         dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1855
1856         hdmi_disable_overflow_interrupts();
1857
1858         fb_videomode_to_var(&hdmi->fbi->var, &vga_mode);
1859
1860         hdmi->requesting_vga_for_initialization = true;
1861         mxc_hdmi_notify_fb(hdmi);
1862         hdmi->requesting_vga_for_initialization = false;
1863 }
1864
1865 static void mxc_hdmi_set_mode(struct mxc_hdmi *hdmi)
1866 {
1867         const struct fb_videomode *mode;
1868         struct fb_videomode m;
1869         struct fb_var_screeninfo var;
1870
1871         dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1872
1873         /* Set the default mode only once. */
1874         if (!hdmi->dft_mode_set) {
1875                 fb_videomode_to_var(&var, &hdmi->default_mode);
1876                 hdmi->dft_mode_set = true;
1877         } else
1878                 fb_videomode_to_var(&var, &hdmi->previous_non_vga_mode);
1879
1880         fb_var_to_videomode(&m, &var);
1881         dump_fb_videomode(&m);
1882
1883         mode = fb_find_nearest_mode(&m, &hdmi->fbi->modelist);
1884         if (!mode) {
1885                 pr_err("%s: could not find mode in modelist\n", __func__);
1886                 return;
1887         }
1888
1889         /* If video mode same as previous, init HDMI again */
1890         if (fb_mode_is_equal(&hdmi->previous_non_vga_mode, mode)) {
1891                 dev_dbg(&hdmi->pdev->dev,
1892                                 "%s: Video mode same as previous\n", __func__);
1893                 /* update fbi mode in case modelist is updated */
1894                 hdmi->fbi->mode = (struct fb_videomode *)mode;
1895                 /* update hdmi setting in case EDID data updated  */
1896                 mxc_hdmi_setup(hdmi, 0);
1897         } else {
1898                 dev_dbg(&hdmi->pdev->dev, "%s: New video mode\n", __func__);
1899                 mxc_hdmi_set_mode_to_vga_dvi(hdmi);
1900                 fb_videomode_to_var(&hdmi->fbi->var, mode);
1901                 dump_fb_videomode((struct fb_videomode *)mode);
1902                 mxc_hdmi_notify_fb(hdmi);
1903         }
1904
1905 }
1906
1907 static void mxc_hdmi_cable_connected(struct mxc_hdmi *hdmi)
1908 {
1909         int edid_status;
1910
1911         dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1912
1913         hdmi->cable_plugin = true;
1914
1915         /* HDMI Initialization Step C */
1916         edid_status = mxc_hdmi_read_edid(hdmi);
1917
1918         /* Read EDID again if first EDID read failed */
1919         if (edid_status == HDMI_EDID_NO_MODES ||
1920                         edid_status == HDMI_EDID_FAIL) {
1921                 dev_info(&hdmi->pdev->dev, "Read EDID again\n");
1922                 edid_status = mxc_hdmi_read_edid(hdmi);
1923         }
1924
1925         /* HDMI Initialization Steps D, E, F */
1926         switch (edid_status) {
1927         case HDMI_EDID_SUCCESS:
1928                 mxc_hdmi_edid_rebuild_modelist(hdmi);
1929                 break;
1930
1931         /* Nothing to do if EDID same */
1932         case HDMI_EDID_SAME:
1933                 break;
1934
1935         case HDMI_EDID_FAIL:
1936                 mxc_hdmi_default_edid_cfg(hdmi);
1937                 /* No break here  */
1938         case HDMI_EDID_NO_MODES:
1939         default:
1940                 mxc_hdmi_default_modelist(hdmi);
1941                 break;
1942         }
1943
1944         /* Setting video mode */
1945         mxc_hdmi_set_mode(hdmi);
1946
1947         dev_dbg(&hdmi->pdev->dev, "%s exit\n", __func__);
1948 }
1949
1950 static int mxc_hdmi_power_on(struct mxc_dispdrv_handle *disp)
1951 {
1952         struct mxc_hdmi *hdmi = mxc_dispdrv_getdata(disp);
1953         mxc_hdmi_phy_init(hdmi);
1954         return 0;
1955 }
1956
1957 static void mxc_hdmi_power_off(struct mxc_dispdrv_handle *disp)
1958 {
1959         struct mxc_hdmi *hdmi = mxc_dispdrv_getdata(disp);
1960         mxc_hdmi_phy_disable(hdmi);
1961 }
1962
1963 static void mxc_hdmi_cable_disconnected(struct mxc_hdmi *hdmi)
1964 {
1965         dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
1966
1967         /* Disable All HDMI clock */
1968         hdmi_writeb(0xff, HDMI_MC_CLKDIS);
1969
1970         mxc_hdmi_phy_disable(hdmi);
1971
1972         hdmi_disable_overflow_interrupts();
1973
1974         hdmi->cable_plugin = false;
1975 }
1976
1977 static void hotplug_worker(struct work_struct *work)
1978 {
1979         struct delayed_work *delay_work = to_delayed_work(work);
1980         struct mxc_hdmi *hdmi =
1981                 container_of(delay_work, struct mxc_hdmi, hotplug_work);
1982         u32 phy_int_stat, phy_int_pol, phy_int_mask;
1983         u8 val;
1984         unsigned long flags;
1985         char event_string[32];
1986         char *envp[] = { event_string, NULL };
1987
1988         phy_int_stat = hdmi->latest_intr_stat;
1989         phy_int_pol = hdmi_readb(HDMI_PHY_POL0);
1990
1991         dev_dbg(&hdmi->pdev->dev, "phy_int_stat=0x%x, phy_int_pol=0x%x\n",
1992                         phy_int_stat, phy_int_pol);
1993
1994         /* check cable status */
1995         if (phy_int_stat & HDMI_IH_PHY_STAT0_HPD) {
1996                 /* cable connection changes */
1997                 if (phy_int_pol & HDMI_PHY_HPD) {
1998                         /* Plugin event */
1999                         dev_dbg(&hdmi->pdev->dev, "EVENT=plugin\n");
2000                         mxc_hdmi_cable_connected(hdmi);
2001
2002                         /* Make HPD intr active low to capture unplug event */
2003                         val = hdmi_readb(HDMI_PHY_POL0);
2004                         val &= ~HDMI_PHY_HPD;
2005                         hdmi_writeb(val, HDMI_PHY_POL0);
2006
2007                         sprintf(event_string, "EVENT=plugin");
2008                         kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
2009 #ifdef CONFIG_MXC_HDMI_CEC
2010                         mxc_hdmi_cec_handle(0x80);
2011 #endif
2012                         hdmi_set_cable_state(1);
2013
2014                 } else if (!(phy_int_pol & HDMI_PHY_HPD)) {
2015                         /* Plugout event */
2016                         dev_dbg(&hdmi->pdev->dev, "EVENT=plugout\n");
2017                         hdmi_set_cable_state(0);
2018                         mxc_hdmi_abort_stream();
2019                         mxc_hdmi_cable_disconnected(hdmi);
2020
2021                         /* Make HPD intr active high to capture plugin event */
2022                         val = hdmi_readb(HDMI_PHY_POL0);
2023                         val |= HDMI_PHY_HPD;
2024                         hdmi_writeb(val, HDMI_PHY_POL0);
2025
2026                         sprintf(event_string, "EVENT=plugout");
2027                         kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
2028 #ifdef CONFIG_MXC_HDMI_CEC
2029                         mxc_hdmi_cec_handle(0x100);
2030 #endif
2031
2032                 } else
2033                         dev_dbg(&hdmi->pdev->dev, "EVENT=none?\n");
2034         }
2035
2036         /* Lock here to ensure full powerdown sequence
2037          * completed before next interrupt processed */
2038         spin_lock_irqsave(&hdmi->irq_lock, flags);
2039
2040         /* Re-enable HPD interrupts */
2041         phy_int_mask = hdmi_readb(HDMI_PHY_MASK0);
2042         phy_int_mask &= ~HDMI_PHY_HPD;
2043         hdmi_writeb(phy_int_mask, HDMI_PHY_MASK0);
2044
2045         /* Unmute interrupts */
2046         hdmi_writeb(~HDMI_IH_MUTE_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
2047
2048         if (hdmi_readb(HDMI_IH_FC_STAT2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK)
2049                 mxc_hdmi_clear_overflow(hdmi);
2050
2051         spin_unlock_irqrestore(&hdmi->irq_lock, flags);
2052 }
2053
2054 static void hdcp_hdp_worker(struct work_struct *work)
2055 {
2056         struct delayed_work *delay_work = to_delayed_work(work);
2057         struct mxc_hdmi *hdmi =
2058                 container_of(delay_work, struct mxc_hdmi, hdcp_hdp_work);
2059         char event_string[32];
2060         char *envp[] = { event_string, NULL };
2061
2062         /* HDCP interrupt */
2063         sprintf(event_string, "EVENT=hdcpint");
2064         kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
2065
2066         /* Unmute interrupts in HDCP application*/
2067 }
2068
2069 static irqreturn_t mxc_hdmi_hotplug(int irq, void *data)
2070 {
2071         struct mxc_hdmi *hdmi = data;
2072         u8 val, intr_stat;
2073         unsigned long flags;
2074
2075         spin_lock_irqsave(&hdmi->irq_lock, flags);
2076
2077         /* Check and clean packet overflow interrupt.*/
2078         if (hdmi_readb(HDMI_IH_FC_STAT2) &
2079                         HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
2080                 mxc_hdmi_clear_overflow(hdmi);
2081
2082                 dev_dbg(&hdmi->pdev->dev, "Overflow interrupt received\n");
2083                 /* clear irq status */
2084                 hdmi_writeb(HDMI_IH_FC_STAT2_OVERFLOW_MASK,
2085                             HDMI_IH_FC_STAT2);
2086         }
2087
2088         /*
2089          * We could not disable the irq.  Probably the audio driver
2090          * has enabled it. Masking off the HDMI interrupts using
2091          * HDMI registers.
2092          */
2093         /* Capture status - used in hotplug_worker ISR */
2094         intr_stat = hdmi_readb(HDMI_IH_PHY_STAT0);
2095
2096         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2097
2098                 dev_dbg(&hdmi->pdev->dev, "Hotplug interrupt received\n");
2099                 hdmi->latest_intr_stat = intr_stat;
2100
2101                 /* Mute interrupts until handled */
2102
2103                 val = hdmi_readb(HDMI_IH_MUTE_PHY_STAT0);
2104                 val |= HDMI_IH_MUTE_PHY_STAT0_HPD;
2105                 hdmi_writeb(val, HDMI_IH_MUTE_PHY_STAT0);
2106
2107                 val = hdmi_readb(HDMI_PHY_MASK0);
2108                 val |= HDMI_PHY_HPD;
2109                 hdmi_writeb(val, HDMI_PHY_MASK0);
2110
2111                 /* Clear Hotplug interrupts */
2112                 hdmi_writeb(HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
2113
2114                 schedule_delayed_work(&(hdmi->hotplug_work), msecs_to_jiffies(20));
2115         }
2116
2117         /* Check HDCP  interrupt state */
2118         if (hdmi->hdmi_data.hdcp_enable) {
2119                 val = hdmi_readb(HDMI_A_APIINTSTAT);
2120                 if (val != 0) {
2121                         /* Mute interrupts until interrupt handled */
2122                         val = 0xFF;
2123                         hdmi_writeb(val, HDMI_A_APIINTMSK);
2124                         schedule_delayed_work(&(hdmi->hdcp_hdp_work), msecs_to_jiffies(50));
2125                 }
2126         }
2127
2128         spin_unlock_irqrestore(&hdmi->irq_lock, flags);
2129         return IRQ_HANDLED;
2130 }
2131
2132 static void mxc_hdmi_setup(struct mxc_hdmi *hdmi, unsigned long event)
2133 {
2134         struct fb_videomode m;
2135         const struct fb_videomode *edid_mode;
2136
2137         dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
2138
2139         fb_var_to_videomode(&m, &hdmi->fbi->var);
2140         dump_fb_videomode(&m);
2141
2142         dev_dbg(&hdmi->pdev->dev, "%s - video mode changed\n", __func__);
2143
2144         hdmi->vic = 0;
2145         if (!hdmi->requesting_vga_for_initialization) {
2146                 /* Save mode if this isn't the result of requesting
2147                  * vga default. */
2148                 memcpy(&hdmi->previous_non_vga_mode, &m,
2149                        sizeof(struct fb_videomode));
2150                 if (!list_empty(&hdmi->fbi->modelist)) {
2151                         edid_mode = fb_find_nearest_mode(&m, &hdmi->fbi->modelist);
2152                         pr_debug("edid mode ");
2153                         dump_fb_videomode((struct fb_videomode *)edid_mode);
2154                         /* update fbi mode */
2155                         hdmi->fbi->mode = (struct fb_videomode *)edid_mode;
2156                         hdmi->vic = mxc_edid_mode_to_vic(edid_mode);
2157                 }
2158         }
2159
2160         hdmi_disable_overflow_interrupts();
2161
2162         dev_dbg(&hdmi->pdev->dev, "CEA mode used vic=%d\n", hdmi->vic);
2163         if (hdmi->edid_cfg.hdmi_cap)
2164                 hdmi->hdmi_data.video_mode.mDVI = false;
2165         else {
2166                 dev_dbg(&hdmi->pdev->dev, "CEA mode vic=%d work in DVI\n", hdmi->vic);
2167                 hdmi->hdmi_data.video_mode.mDVI = true;
2168         }
2169
2170         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
2171                 (hdmi->vic == 21) || (hdmi->vic == 22) ||
2172                 (hdmi->vic == 2) || (hdmi->vic == 3) ||
2173                 (hdmi->vic == 17) || (hdmi->vic == 18))
2174                 hdmi->hdmi_data.colorimetry = eITU601;
2175         else
2176                 hdmi->hdmi_data.colorimetry = eITU709;
2177
2178         if ((hdmi->vic == 10) || (hdmi->vic == 11) ||
2179                 (hdmi->vic == 12) || (hdmi->vic == 13) ||
2180                 (hdmi->vic == 14) || (hdmi->vic == 15) ||
2181                 (hdmi->vic == 25) || (hdmi->vic == 26) ||
2182                 (hdmi->vic == 27) || (hdmi->vic == 28) ||
2183                 (hdmi->vic == 29) || (hdmi->vic == 30) ||
2184                 (hdmi->vic == 35) || (hdmi->vic == 36) ||
2185                 (hdmi->vic == 37) || (hdmi->vic == 38))
2186                 hdmi->hdmi_data.video_mode.mPixelRepetitionOutput = 1;
2187         else
2188                 hdmi->hdmi_data.video_mode.mPixelRepetitionOutput = 0;
2189
2190         hdmi->hdmi_data.video_mode.mPixelRepetitionInput = 0;
2191
2192         /* TODO: Get input format from IPU (via FB driver iface) */
2193         hdmi->hdmi_data.enc_in_format = RGB;
2194
2195         hdmi->hdmi_data.enc_out_format = RGB;
2196
2197         /* YCbCr only enabled in HDMI mode */
2198         if (!hdmi->hdmi_data.video_mode.mDVI &&
2199                 !hdmi->hdmi_data.rgb_out_enable) {
2200                 if (hdmi->edid_cfg.cea_ycbcr444)
2201                         hdmi->hdmi_data.enc_out_format = YCBCR444;
2202                 else if (hdmi->edid_cfg.cea_ycbcr422)
2203                         hdmi->hdmi_data.enc_out_format = YCBCR422_8BITS;
2204         }
2205
2206         /* IPU not support depth color output */
2207         hdmi->hdmi_data.enc_color_depth = 8;
2208         hdmi->hdmi_data.pix_repet_factor = 0;
2209         hdmi->hdmi_data.video_mode.mDataEnablePolarity = true;
2210
2211         /* HDMI Initialization Step B.1 */
2212         hdmi_av_composer(hdmi);
2213
2214         /* HDMI Initializateion Step B.2 */
2215         mxc_hdmi_phy_init(hdmi);
2216
2217         /* HDMI Initialization Step B.3 */
2218         mxc_hdmi_enable_video_path(hdmi);
2219
2220         /* not for DVI mode */
2221         if (hdmi->hdmi_data.video_mode.mDVI)
2222                 dev_dbg(&hdmi->pdev->dev, "%s DVI mode\n", __func__);
2223         else {
2224                 dev_dbg(&hdmi->pdev->dev, "%s CEA mode\n", __func__);
2225
2226                 /* HDMI Initialization Step E - Configure audio */
2227                 hdmi_clk_regenerator_update_pixel_clock(hdmi->fbi->var.pixclock);
2228                 hdmi_enable_audio_clk(hdmi);
2229
2230                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
2231                 hdmi_config_AVI(hdmi);
2232         }
2233
2234         hdmi_video_packetize(hdmi);
2235         hdmi_video_csc(hdmi);
2236         hdmi_video_sample(hdmi);
2237
2238         mxc_hdmi_clear_overflow(hdmi);
2239
2240         dev_dbg(&hdmi->pdev->dev, "%s exit\n\n", __func__);
2241
2242 }
2243
2244 /* Wait until we are registered to enable interrupts */
2245 static void mxc_hdmi_fb_registered(struct mxc_hdmi *hdmi)
2246 {
2247         unsigned long flags;
2248
2249         if (hdmi->fb_reg)
2250                 return;
2251
2252         spin_lock_irqsave(&hdmi->irq_lock, flags);
2253
2254         dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
2255
2256         hdmi_writeb(HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2257                     HDMI_PHY_I2CM_INT_ADDR);
2258
2259         hdmi_writeb(HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
2260                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2261                     HDMI_PHY_I2CM_CTLINT_ADDR);
2262
2263         /* enable cable hot plug irq */
2264         hdmi_writeb((u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
2265
2266         /* Clear Hotplug interrupts */
2267         hdmi_writeb(HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
2268
2269         /* Unmute interrupts */
2270         hdmi_writeb(~HDMI_IH_MUTE_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
2271
2272         hdmi->fb_reg = true;
2273
2274         spin_unlock_irqrestore(&hdmi->irq_lock, flags);
2275
2276 }
2277
2278 static int mxc_hdmi_fb_event(struct notifier_block *nb,
2279                                         unsigned long val, void *v)
2280 {
2281         struct fb_event *event = v;
2282         struct mxc_hdmi *hdmi = container_of(nb, struct mxc_hdmi, nb);
2283
2284         if (strcmp(event->info->fix.id, hdmi->fbi->fix.id))
2285                 return 0;
2286
2287         switch (val) {
2288         case FB_EVENT_FB_REGISTERED:
2289                 dev_dbg(&hdmi->pdev->dev, "event=FB_EVENT_FB_REGISTERED\n");
2290                 mxc_hdmi_fb_registered(hdmi);
2291                 hdmi_set_registered(1);
2292                 break;
2293
2294         case FB_EVENT_FB_UNREGISTERED:
2295                 dev_dbg(&hdmi->pdev->dev, "event=FB_EVENT_FB_UNREGISTERED\n");
2296                 hdmi->fb_reg = false;
2297                 hdmi_set_registered(0);
2298                 break;
2299
2300         case FB_EVENT_MODE_CHANGE:
2301                 dev_dbg(&hdmi->pdev->dev, "event=FB_EVENT_MODE_CHANGE\n");
2302                 if (hdmi->fb_reg)
2303                         mxc_hdmi_setup(hdmi, val);
2304                 break;
2305
2306         case FB_EVENT_BLANK:
2307                 if ((*((int *)event->data) == FB_BLANK_UNBLANK) &&
2308                         (*((int *)event->data) != hdmi->blank)) {
2309                         dev_dbg(&hdmi->pdev->dev,
2310                                 "event=FB_EVENT_BLANK - UNBLANK\n");
2311
2312                         hdmi->blank = *((int *)event->data);
2313
2314                         if (hdmi->fb_reg && hdmi->cable_plugin)
2315                                 mxc_hdmi_setup(hdmi, val);
2316                         hdmi_set_blank_state(1);
2317
2318                 } else if (*((int *)event->data) != hdmi->blank) {
2319                         dev_dbg(&hdmi->pdev->dev,
2320                                 "event=FB_EVENT_BLANK - BLANK\n");
2321                         hdmi_set_blank_state(0);
2322                         mxc_hdmi_abort_stream();
2323
2324                         mxc_hdmi_phy_disable(hdmi);
2325
2326                         hdmi->blank = *((int *)event->data);
2327                 } else
2328                         dev_dbg(&hdmi->pdev->dev,
2329                                 "FB BLANK state no changed!\n");
2330
2331                 break;
2332
2333         case FB_EVENT_SUSPEND:
2334                 dev_dbg(&hdmi->pdev->dev,
2335                         "event=FB_EVENT_SUSPEND\n");
2336
2337                 if (hdmi->blank == FB_BLANK_UNBLANK) {
2338                         mxc_hdmi_phy_disable(hdmi);
2339                         clk_disable(hdmi->hdmi_iahb_clk);
2340                         clk_disable(hdmi->hdmi_isfr_clk);
2341                 }
2342                 break;
2343
2344         case FB_EVENT_RESUME:
2345                 dev_dbg(&hdmi->pdev->dev,
2346                         "event=FB_EVENT_RESUME\n");
2347
2348                 if (hdmi->blank == FB_BLANK_UNBLANK) {
2349                         clk_enable(hdmi->hdmi_iahb_clk);
2350                         clk_enable(hdmi->hdmi_isfr_clk);
2351                         mxc_hdmi_phy_init(hdmi);
2352                 }
2353                 break;
2354
2355         }
2356         return 0;
2357 }
2358
2359 static void hdmi_init_route(struct mxc_hdmi *hdmi)
2360 {
2361         uint32_t hdmi_mux_setting, reg;
2362         int ipu_id, disp_id;
2363
2364         ipu_id = mxc_hdmi_ipu_id;
2365         disp_id = mxc_hdmi_disp_id;
2366
2367         if ((ipu_id > 1) || (ipu_id < 0)) {
2368                 pr_err("Invalid IPU select for HDMI: %d. Set to 0\n", ipu_id);
2369                 ipu_id = 0;
2370         }
2371
2372         if ((disp_id > 1) || (disp_id < 0)) {
2373                 pr_err("Invalid DI select for HDMI: %d. Set to 0\n", disp_id);
2374                 disp_id = 0;
2375         }
2376
2377         reg = readl(hdmi->gpr_hdmi_base);
2378
2379         /* Configure the connection between IPU1/2 and HDMI */
2380         hdmi_mux_setting = 2*ipu_id + disp_id;
2381
2382         /* GPR3, bits 2-3 = HDMI_MUX_CTL */
2383         reg &= ~0xd;
2384         reg |= hdmi_mux_setting << 2;
2385
2386         writel(reg, hdmi->gpr_hdmi_base);
2387
2388         /* Set HDMI event as SDMA event2 for HDMI audio */
2389         reg = readl(hdmi->gpr_sdma_base);
2390         reg |= 0x1;
2391         writel(reg, hdmi->gpr_sdma_base);
2392 }
2393
2394 static void hdmi_hdcp_get_property(struct platform_device *pdev)
2395 {
2396         struct device_node *np = pdev->dev.of_node;
2397
2398         /* Check hdcp enable by dts.*/
2399         hdcp_init = of_property_read_bool(np, "fsl,hdcp");
2400         if (hdcp_init)
2401                 dev_dbg(&pdev->dev, "hdcp enable\n");
2402         else
2403                 dev_dbg(&pdev->dev, "hdcp disable\n");
2404 }
2405
2406 static void hdmi_get_of_property(struct mxc_hdmi *hdmi)
2407 {
2408         struct platform_device *pdev = hdmi->pdev;
2409         struct device_node *np = pdev->dev.of_node;
2410         const struct of_device_id *of_id =
2411                         of_match_device(imx_hdmi_dt_ids, &pdev->dev);
2412         int ret;
2413         u32 phy_reg_vlev = 0, phy_reg_cksymtx = 0;
2414
2415         if (of_id) {
2416                 pdev->id_entry = of_id->data;
2417                 hdmi->cpu_type = pdev->id_entry->driver_data;
2418         }
2419
2420         /* HDMI PHY register vlev and cksymtx preperty is optional.
2421          * It is for specific board to pass HCT electrical part.
2422          * Default value will been setting in HDMI PHY config function
2423          * if it is not define in device tree.
2424          */
2425         ret = of_property_read_u32(np, "fsl,phy_reg_vlev", &phy_reg_vlev);
2426         if (ret)
2427                 dev_dbg(&pdev->dev, "No board specific HDMI PHY vlev\n");
2428
2429         ret = of_property_read_u32(np, "fsl,phy_reg_cksymtx", &phy_reg_cksymtx);
2430         if (ret)
2431                 dev_dbg(&pdev->dev, "No board specific HDMI PHY cksymtx\n");
2432
2433         /* Specific phy config */
2434         hdmi->phy_config.reg_cksymtx = phy_reg_cksymtx;
2435         hdmi->phy_config.reg_vlev = phy_reg_vlev;
2436
2437 }
2438
2439 /* HDMI Initialization Step A */
2440 static int mxc_hdmi_disp_init(struct mxc_dispdrv_handle *disp,
2441                               struct mxc_dispdrv_setting *setting)
2442 {
2443         int ret = 0;
2444         u32 i;
2445         const struct fb_videomode *mode;
2446         struct fb_videomode m;
2447         struct mxc_hdmi *hdmi = mxc_dispdrv_getdata(disp);
2448         int irq = platform_get_irq(hdmi->pdev, 0);
2449
2450         dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
2451
2452         /* Check hdmi disp init once */
2453         if (hdmi_inited) {
2454                 dev_err(&hdmi->pdev->dev,
2455                                 "Error only one HDMI output support now!\n");
2456                 return -1;
2457         }
2458
2459         hdmi_get_of_property(hdmi);
2460
2461         if (irq < 0)
2462                 return -ENODEV;
2463
2464         /* Setting HDMI default to blank state */
2465         hdmi->blank = FB_BLANK_POWERDOWN;
2466
2467         setting->dev_id = mxc_hdmi_ipu_id;
2468         setting->disp_id = mxc_hdmi_disp_id;
2469         setting->if_fmt = IPU_PIX_FMT_RGB24;
2470
2471         hdmi->dft_mode_str = setting->dft_mode_str;
2472         hdmi->default_bpp = setting->default_bpp;
2473         dev_dbg(&hdmi->pdev->dev, "%s - default mode %s bpp=%d\n",
2474                 __func__, hdmi->dft_mode_str, hdmi->default_bpp);
2475
2476         hdmi->fbi = setting->fbi;
2477
2478         hdmi_init_route(hdmi);
2479
2480         hdmi->hdmi_isfr_clk = clk_get(&hdmi->pdev->dev, "hdmi_isfr");
2481         if (IS_ERR(hdmi->hdmi_isfr_clk)) {
2482                 ret = PTR_ERR(hdmi->hdmi_isfr_clk);
2483                 dev_err(&hdmi->pdev->dev,
2484                         "Unable to get HDMI clk: %d\n", ret);
2485                 goto egetclk1;
2486         }
2487
2488         ret = clk_prepare_enable(hdmi->hdmi_isfr_clk);
2489         if (ret < 0) {
2490                 dev_err(&hdmi->pdev->dev,
2491                         "Cannot enable HDMI isfr clock: %d\n", ret);
2492                 goto erate1;
2493         }
2494
2495         hdmi->hdmi_iahb_clk = clk_get(&hdmi->pdev->dev, "hdmi_iahb");
2496         if (IS_ERR(hdmi->hdmi_iahb_clk)) {
2497                 ret = PTR_ERR(hdmi->hdmi_iahb_clk);
2498                 dev_err(&hdmi->pdev->dev,
2499                         "Unable to get HDMI clk: %d\n", ret);
2500                 goto egetclk2;
2501         }
2502
2503         ret = clk_prepare_enable(hdmi->hdmi_iahb_clk);
2504         if (ret < 0) {
2505                 dev_err(&hdmi->pdev->dev,
2506                         "Cannot enable HDMI iahb clock: %d\n", ret);
2507                 goto erate2;
2508         }
2509
2510         dev_dbg(&hdmi->pdev->dev, "Enabled HDMI clocks\n");
2511
2512         /* Init DDC pins for HDCP  */
2513         if (hdcp_init) {
2514                 hdmi->pinctrl = devm_pinctrl_get_select_default(&hdmi->pdev->dev);
2515                 if (IS_ERR(hdmi->pinctrl)) {
2516                         dev_err(&hdmi->pdev->dev, "can't get/select DDC pinctrl\n");
2517                         goto erate2;
2518                 }
2519         }
2520
2521         /* Product and revision IDs */
2522         dev_info(&hdmi->pdev->dev,
2523                 "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
2524                 hdmi_readb(HDMI_DESIGN_ID),
2525                 hdmi_readb(HDMI_REVISION_ID),
2526                 hdmi_readb(HDMI_PRODUCT_ID0),
2527                 hdmi_readb(HDMI_PRODUCT_ID1));
2528
2529         /* To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2530          * N and cts values before enabling phy */
2531         hdmi_init_clk_regenerator();
2532
2533         INIT_LIST_HEAD(&hdmi->fbi->modelist);
2534
2535         spin_lock_init(&hdmi->irq_lock);
2536
2537         /* Set the default mode and modelist when disp init. */
2538         fb_find_mode(&hdmi->fbi->var, hdmi->fbi,
2539                      hdmi->dft_mode_str, NULL, 0, NULL,
2540                      hdmi->default_bpp);
2541
2542         console_lock();
2543
2544         fb_destroy_modelist(&hdmi->fbi->modelist);
2545
2546         /*Add all no interlaced CEA mode to default modelist */
2547         for (i = 0; i < ARRAY_SIZE(mxc_cea_mode); i++) {
2548                 mode = &mxc_cea_mode[i];
2549                 if (!(mode->vmode & FB_VMODE_INTERLACED) && (mode->xres != 0))
2550                         fb_add_videomode(mode, &hdmi->fbi->modelist);
2551         }
2552
2553         console_unlock();
2554
2555         /* Find a nearest mode in default modelist */
2556         fb_var_to_videomode(&m, &hdmi->fbi->var);
2557         dump_fb_videomode(&m);
2558
2559         hdmi->dft_mode_set = false;
2560         /* Save default video mode */
2561         memcpy(&hdmi->default_mode, &m, sizeof(struct fb_videomode));
2562
2563         mode = fb_find_nearest_mode(&m, &hdmi->fbi->modelist);
2564         if (!mode) {
2565                 pr_err("%s: could not find mode in modelist\n", __func__);
2566                 return -1;
2567         }
2568
2569         fb_videomode_to_var(&hdmi->fbi->var, mode);
2570
2571         /* update fbi mode */
2572         hdmi->fbi->mode = (struct fb_videomode *)mode;
2573
2574         /* Default setting HDMI working in HDMI mode*/
2575         hdmi->edid_cfg.hdmi_cap = true;
2576
2577         INIT_DELAYED_WORK(&hdmi->hotplug_work, hotplug_worker);
2578         INIT_DELAYED_WORK(&hdmi->hdcp_hdp_work, hdcp_hdp_worker);
2579
2580         /* Configure registers related to HDMI interrupt
2581          * generation before registering IRQ. */
2582         hdmi_writeb(HDMI_PHY_HPD, HDMI_PHY_POL0);
2583
2584         /* Clear Hotplug interrupts */
2585         hdmi_writeb(HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
2586
2587         hdmi->nb.notifier_call = mxc_hdmi_fb_event;
2588         ret = fb_register_client(&hdmi->nb);
2589         if (ret < 0)
2590                 goto efbclient;
2591
2592         memset(&hdmi->hdmi_data, 0, sizeof(struct hdmi_data_info));
2593
2594         /* Default HDMI working in RGB mode */
2595         hdmi->hdmi_data.rgb_out_enable = true;
2596
2597         ret = devm_request_irq(&hdmi->pdev->dev, irq, mxc_hdmi_hotplug, IRQF_SHARED,
2598                         dev_name(&hdmi->pdev->dev), hdmi);
2599         if (ret < 0) {
2600                 dev_err(&hdmi->pdev->dev,
2601                         "Unable to request irq: %d\n", ret);
2602                 goto ereqirq;
2603         }
2604
2605         ret = device_create_file(&hdmi->pdev->dev, &dev_attr_fb_name);
2606         if (ret < 0)
2607                 dev_warn(&hdmi->pdev->dev,
2608                         "cound not create sys node for fb name\n");
2609         ret = device_create_file(&hdmi->pdev->dev, &dev_attr_cable_state);
2610         if (ret < 0)
2611                 dev_warn(&hdmi->pdev->dev,
2612                         "cound not create sys node for cable state\n");
2613         ret = device_create_file(&hdmi->pdev->dev, &dev_attr_edid);
2614         if (ret < 0)
2615                 dev_warn(&hdmi->pdev->dev,
2616                         "cound not create sys node for edid\n");
2617
2618         ret = device_create_file(&hdmi->pdev->dev, &dev_attr_rgb_out_enable);
2619         if (ret < 0)
2620                 dev_warn(&hdmi->pdev->dev,
2621                         "cound not create sys node for rgb out enable\n");
2622
2623         ret = device_create_file(&hdmi->pdev->dev, &dev_attr_hdcp_enable);
2624         if (ret < 0)
2625                 dev_warn(&hdmi->pdev->dev,
2626                         "cound not create sys node for hdcp enable\n");
2627
2628         dev_dbg(&hdmi->pdev->dev, "%s exit\n", __func__);
2629
2630         hdmi_inited = true;
2631
2632         return ret;
2633
2634 efbclient:
2635         free_irq(irq, hdmi);
2636 ereqirq:
2637         clk_disable_unprepare(hdmi->hdmi_iahb_clk);
2638 erate2:
2639         clk_put(hdmi->hdmi_iahb_clk);
2640 egetclk2:
2641         clk_disable_unprepare(hdmi->hdmi_isfr_clk);
2642 erate1:
2643         clk_put(hdmi->hdmi_isfr_clk);
2644 egetclk1:
2645         dev_dbg(&hdmi->pdev->dev, "%s error exit\n", __func__);
2646
2647         return ret;
2648 }
2649
2650 static void mxc_hdmi_disp_deinit(struct mxc_dispdrv_handle *disp)
2651 {
2652         struct mxc_hdmi *hdmi = mxc_dispdrv_getdata(disp);
2653
2654         dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
2655
2656         fb_unregister_client(&hdmi->nb);
2657
2658         clk_disable_unprepare(hdmi->hdmi_isfr_clk);
2659         clk_put(hdmi->hdmi_isfr_clk);
2660         clk_disable_unprepare(hdmi->hdmi_iahb_clk);
2661         clk_put(hdmi->hdmi_iahb_clk);
2662
2663         platform_device_unregister(hdmi->pdev);
2664
2665         hdmi_inited = false;
2666 }
2667
2668 static struct mxc_dispdrv_driver mxc_hdmi_drv = {
2669         .name   = DISPDRV_HDMI,
2670         .init   = mxc_hdmi_disp_init,
2671         .deinit = mxc_hdmi_disp_deinit,
2672         .enable = mxc_hdmi_power_on,
2673         .disable = mxc_hdmi_power_off,
2674 };
2675
2676
2677 static int mxc_hdmi_open(struct inode *inode, struct file *file)
2678 {
2679         return 0;
2680 }
2681
2682 static long mxc_hdmi_ioctl(struct file *file,
2683                 unsigned int cmd, unsigned long arg)
2684 {
2685         int __user *argp = (void __user *)arg;
2686         int ret = 0;
2687
2688         switch (cmd) {
2689         case HDMI_IOC_GET_RESOURCE:
2690                 ret = copy_to_user(argp, &g_hdmi->hdmi_data,
2691                                 sizeof(g_hdmi->hdmi_data)) ? -EFAULT : 0;
2692                 break;
2693         case HDMI_IOC_GET_CPU_TYPE:
2694                 *argp = g_hdmi->cpu_type;
2695                 break;
2696         default:
2697                 pr_debug("Unsupport cmd %d\n", cmd);
2698                 break;
2699      }
2700      return ret;
2701 }
2702
2703 static int mxc_hdmi_release(struct inode *inode, struct file *file)
2704 {
2705         return 0;
2706 }
2707
2708 static const struct file_operations mxc_hdmi_fops = {
2709         .owner = THIS_MODULE,
2710         .open = mxc_hdmi_open,
2711         .release = mxc_hdmi_release,
2712         .unlocked_ioctl = mxc_hdmi_ioctl,
2713 };
2714
2715
2716 static int mxc_hdmi_probe(struct platform_device *pdev)
2717 {
2718         struct mxc_hdmi *hdmi;
2719         struct device *temp_class;
2720         struct resource *res;
2721         int ret = 0;
2722
2723         /* Check I2C driver is loaded and available
2724          * check hdcp function is enable by dts */
2725         hdmi_hdcp_get_property(pdev);
2726         if (!hdmi_i2c && !hdcp_init)
2727                 return -ENODEV;
2728
2729         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2730         if (!res)
2731                 return -ENOENT;
2732
2733         hdmi = devm_kzalloc(&pdev->dev,
2734                                 sizeof(struct mxc_hdmi),
2735                                 GFP_KERNEL);
2736         if (!hdmi) {
2737                 dev_err(&pdev->dev, "Cannot allocate device data\n");
2738                 ret = -ENOMEM;
2739                 goto ealloc;
2740         }
2741         g_hdmi = hdmi;
2742
2743         hdmi_major = register_chrdev(hdmi_major, "mxc_hdmi", &mxc_hdmi_fops);
2744         if (hdmi_major < 0) {
2745                 printk(KERN_ERR "HDMI: unable to get a major for HDMI\n");
2746                 ret = -EBUSY;
2747                 goto ealloc;
2748         }
2749
2750         hdmi_class = class_create(THIS_MODULE, "mxc_hdmi");
2751         if (IS_ERR(hdmi_class)) {
2752                 ret = PTR_ERR(hdmi_class);
2753                 goto err_out_chrdev;
2754         }
2755
2756         temp_class = device_create(hdmi_class, NULL, MKDEV(hdmi_major, 0),
2757                                    NULL, "mxc_hdmi");
2758         if (IS_ERR(temp_class)) {
2759                 ret = PTR_ERR(temp_class);
2760                 goto err_out_class;
2761         }
2762
2763         hdmi->pdev = pdev;
2764
2765         hdmi->core_pdev = platform_device_alloc("mxc_hdmi_core", -1);
2766         if (!hdmi->core_pdev) {
2767                 pr_err("%s failed platform_device_alloc for hdmi core\n",
2768                         __func__);
2769                 ret = -ENOMEM;
2770                 goto ecore;
2771         }
2772
2773         hdmi->gpr_base = ioremap(res->start, resource_size(res));
2774         if (!hdmi->gpr_base) {
2775                 dev_err(&pdev->dev, "ioremap failed\n");
2776                 ret = -ENOMEM;
2777                 goto eiomap;
2778         }
2779
2780         hdmi->gpr_hdmi_base = hdmi->gpr_base + 3;
2781         hdmi->gpr_sdma_base = hdmi->gpr_base;
2782
2783         hdmi_inited = false;
2784
2785         hdmi->disp_mxc_hdmi = mxc_dispdrv_register(&mxc_hdmi_drv);
2786         if (IS_ERR(hdmi->disp_mxc_hdmi)) {
2787                 dev_err(&pdev->dev, "Failed to register dispdrv - 0x%x\n",
2788                         (int)hdmi->disp_mxc_hdmi);
2789                 ret = (int)hdmi->disp_mxc_hdmi;
2790                 goto edispdrv;
2791         }
2792         mxc_dispdrv_setdata(hdmi->disp_mxc_hdmi, hdmi);
2793
2794         platform_set_drvdata(pdev, hdmi);
2795
2796         return 0;
2797 edispdrv:
2798         iounmap(hdmi->gpr_base);
2799 eiomap:
2800         platform_device_put(hdmi->core_pdev);
2801 ecore:
2802         kfree(hdmi);
2803 err_out_class:
2804         device_destroy(hdmi_class, MKDEV(hdmi_major, 0));
2805         class_destroy(hdmi_class);
2806 err_out_chrdev:
2807         unregister_chrdev(hdmi_major, "mxc_hdmi");
2808 ealloc:
2809         return ret;
2810 }
2811
2812 static int mxc_hdmi_remove(struct platform_device *pdev)
2813 {
2814         struct mxc_hdmi *hdmi = platform_get_drvdata(pdev);
2815         int irq = platform_get_irq(pdev, 0);
2816
2817         fb_unregister_client(&hdmi->nb);
2818
2819         mxc_dispdrv_puthandle(hdmi->disp_mxc_hdmi);
2820         mxc_dispdrv_unregister(hdmi->disp_mxc_hdmi);
2821         iounmap(hdmi->gpr_base);
2822         /* No new work will be scheduled, wait for running ISR */
2823         free_irq(irq, hdmi);
2824         kfree(hdmi);
2825         g_hdmi = NULL;
2826
2827         return 0;
2828 }
2829
2830 static struct platform_driver mxc_hdmi_driver = {
2831         .probe = mxc_hdmi_probe,
2832         .remove = mxc_hdmi_remove,
2833         .driver = {
2834                 .name = "mxc_hdmi",
2835                 .of_match_table = imx_hdmi_dt_ids,
2836                 .owner = THIS_MODULE,
2837         },
2838 };
2839
2840 static int __init mxc_hdmi_init(void)
2841 {
2842         return platform_driver_register(&mxc_hdmi_driver);
2843 }
2844 module_init(mxc_hdmi_init);
2845
2846 static void __exit mxc_hdmi_exit(void)
2847 {
2848         if (hdmi_major > 0) {
2849                 device_destroy(hdmi_class, MKDEV(hdmi_major, 0));
2850                 class_destroy(hdmi_class);
2851                 unregister_chrdev(hdmi_major, "mxc_hdmi");
2852                 hdmi_major = 0;
2853         }
2854
2855         platform_driver_unregister(&mxc_hdmi_driver);
2856 }
2857 module_exit(mxc_hdmi_exit);
2858
2859 static int mxc_hdmi_i2c_probe(struct i2c_client *client,
2860                 const struct i2c_device_id *id)
2861 {
2862         if (!i2c_check_functionality(client->adapter,
2863                                 I2C_FUNC_SMBUS_BYTE | I2C_FUNC_I2C))
2864                 return -ENODEV;
2865
2866         hdmi_i2c = client;
2867
2868         return 0;
2869 }
2870
2871 static int mxc_hdmi_i2c_remove(struct i2c_client *client)
2872 {
2873         hdmi_i2c = NULL;
2874         return 0;
2875 }
2876
2877 static const struct of_device_id imx_hdmi_i2c_match[] = {
2878         { .compatible = "fsl,imx6-hdmi-i2c", },
2879         { /* sentinel */ }
2880 };
2881
2882 static const struct i2c_device_id mxc_hdmi_i2c_id[] = {
2883         { "mxc_hdmi_i2c", 0 },
2884         {},
2885 };
2886 MODULE_DEVICE_TABLE(i2c, mxc_hdmi_i2c_id);
2887
2888 static struct i2c_driver mxc_hdmi_i2c_driver = {
2889         .driver = {
2890                    .name = "mxc_hdmi_i2c",
2891                         .of_match_table = imx_hdmi_i2c_match,
2892                    },
2893         .probe = mxc_hdmi_i2c_probe,
2894         .remove = mxc_hdmi_i2c_remove,
2895         .id_table = mxc_hdmi_i2c_id,
2896 };
2897
2898 static int __init mxc_hdmi_i2c_init(void)
2899 {
2900         return i2c_add_driver(&mxc_hdmi_i2c_driver);
2901 }
2902
2903 static void __exit mxc_hdmi_i2c_exit(void)
2904 {
2905         i2c_del_driver(&mxc_hdmi_i2c_driver);
2906 }
2907
2908 module_init(mxc_hdmi_i2c_init);
2909 module_exit(mxc_hdmi_i2c_exit);
2910
2911 MODULE_AUTHOR("Freescale Semiconductor, Inc.");