drivers/video/mxsfb.c

   1 /*
   2  * Copyright (C) 2010 Juergen Beisert, Pengutronix
   3  *
   4  * This code is based on:
   5  * Author: Vitaly Wool <vital@embeddedalley.com>
   6  *
   7  * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
   8  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version 2
  13  * of the License, or (at your option) any later version.
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #define DRIVER_NAME "mxsfb"
  21
  22 /**
  23  * @file
  24  * @brief LCDIF driver for i.MX23 and i.MX28
  25  *
  26  * The LCDIF support four modes of operation
  27  * - MPU interface (to drive smart displays) -> not supported yet
  28  * - VSYNC interface (like MPU interface plus Vsync) -> not supported yet
  29  * - Dotclock interface (to drive LC displays with RGB data and sync signals)
  30  * - DVI (to drive ITU-R BT656)  -> not supported yet
  31  *
  32  * This driver depends on a correct setup of the pins used for this purpose
  33  * (platform specific).
  34  *
  35  * For the developer: Don't forget to set the data bus width to the display
  36  * in the imx_fb_videomode structure. You will else end up with ugly colours.
  37  * If you fight against jitter you can vary the clock delay. This is a feature
  38  * of the i.MX28 and you can vary it between 2 ns ... 8 ns in 2 ns steps. Give
  39  * the required value in the imx_fb_videomode structure.
  40  */
  41
  42 #include <linux/module.h>
  43 #include <linux/kernel.h>
  44 #include <linux/of_device.h>
  45 #include <linux/platform_device.h>
  46 #include <linux/clk.h>
  47 #include <linux/dma-mapping.h>
  48 #include <linux/io.h>
  49 #include <linux/fb.h>
  50 #include <linux/regulator/consumer.h>
  51 #include <video/of_display_timing.h>
  52 #include <video/videomode.h>
  53
  54 #define REG_SET 4
  55 #define REG_CLR 8
  56
  57 #define LCDC_CTRL                       0x00
  58 #define LCDC_CTRL1                      0x10
  59 #define LCDC_V4_CTRL2                   0x20
  60 #define LCDC_V3_TRANSFER_COUNT          0x20
  61 #define LCDC_V4_TRANSFER_COUNT          0x30
  62 #define LCDC_V4_CUR_BUF                 0x40
  63 #define LCDC_V4_NEXT_BUF                0x50
  64 #define LCDC_V3_CUR_BUF                 0x30
  65 #define LCDC_V3_NEXT_BUF                0x40
  66 #define LCDC_TIMING                     0x60
  67 #define LCDC_VDCTRL0                    0x70
  68 #define LCDC_VDCTRL1                    0x80
  69 #define LCDC_VDCTRL2                    0x90
  70 #define LCDC_VDCTRL3                    0xa0
  71 #define LCDC_VDCTRL4                    0xb0
  72 #define LCDC_DVICTRL0                   0xc0
  73 #define LCDC_DVICTRL1                   0xd0
  74 #define LCDC_DVICTRL2                   0xe0
  75 #define LCDC_DVICTRL3                   0xf0
  76 #define LCDC_DVICTRL4                   0x100
  77 #define LCDC_V4_DATA                    0x180
  78 #define LCDC_V3_DATA                    0x1b0
  79 #define LCDC_V4_DEBUG0                  0x1d0
  80 #define LCDC_V3_DEBUG0                  0x1f0
  81
  82 #define CTRL_SFTRST                     (1 << 31)
  83 #define CTRL_CLKGATE                    (1 << 30)
  84 #define CTRL_BYPASS_COUNT               (1 << 19)
  85 #define CTRL_VSYNC_MODE                 (1 << 18)
  86 #define CTRL_DOTCLK_MODE                (1 << 17)
  87 #define CTRL_DATA_SELECT                (1 << 16)
  88 #define CTRL_SET_BUS_WIDTH(x)           (((x) & 0x3) << 10)
  89 #define CTRL_GET_BUS_WIDTH(x)           (((x) >> 10) & 0x3)
  90 #define CTRL_SET_WORD_LENGTH(x)         (((x) & 0x3) << 8)
  91 #define CTRL_GET_WORD_LENGTH(x)         (((x) >> 8) & 0x3)
  92 #define CTRL_MASTER                     (1 << 5)
  93 #define CTRL_DF16                       (1 << 3)
  94 #define CTRL_DF18                       (1 << 2)
  95 #define CTRL_DF24                       (1 << 1)
  96 #define CTRL_RUN                        (1 << 0)
  97
  98 #define CTRL1_FIFO_CLEAR                (1 << 21)
  99 #define CTRL1_SET_BYTE_PACKAGING(x)     (((x) & 0xf) << 16)
 100 #define CTRL1_GET_BYTE_PACKAGING(x)     (((x) >> 16) & 0xf)
 101
 102 #define TRANSFER_COUNT_SET_VCOUNT(x)    (((x) & 0xffff) << 16)
 103 #define TRANSFER_COUNT_GET_VCOUNT(x)    (((x) >> 16) & 0xffff)
 104 #define TRANSFER_COUNT_SET_HCOUNT(x)    ((x) & 0xffff)
 105 #define TRANSFER_COUNT_GET_HCOUNT(x)    ((x) & 0xffff)
 106
 107
 108 #define VDCTRL0_ENABLE_PRESENT          (1 << 28)
 109 #define VDCTRL0_VSYNC_ACT_HIGH          (1 << 27)
 110 #define VDCTRL0_HSYNC_ACT_HIGH          (1 << 26)
 111 #define VDCTRL0_DOTCLK_ACT_FALLING      (1 << 25)
 112 #define VDCTRL0_ENABLE_ACT_HIGH         (1 << 24)
 113 #define VDCTRL0_VSYNC_PERIOD_UNIT       (1 << 21)
 114 #define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT  (1 << 20)
 115 #define VDCTRL0_HALF_LINE               (1 << 19)
 116 #define VDCTRL0_HALF_LINE_MODE          (1 << 18)
 117 #define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
 118 #define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
 119
 120 #define VDCTRL2_SET_HSYNC_PERIOD(x)     ((x) & 0x3ffff)
 121 #define VDCTRL2_GET_HSYNC_PERIOD(x)     ((x) & 0x3ffff)
 122
 123 #define VDCTRL3_MUX_SYNC_SIGNALS        (1 << 29)
 124 #define VDCTRL3_VSYNC_ONLY              (1 << 28)
 125 #define SET_HOR_WAIT_CNT(x)             (((x) & 0xfff) << 16)
 126 #define GET_HOR_WAIT_CNT(x)             (((x) >> 16) & 0xfff)
 127 #define SET_VERT_WAIT_CNT(x)            ((x) & 0xffff)
 128 #define GET_VERT_WAIT_CNT(x)            ((x) & 0xffff)
 129
 130 #define VDCTRL4_SET_DOTCLK_DLY(x)       (((x) & 0x7) << 29) /* v4 only */
 131 #define VDCTRL4_GET_DOTCLK_DLY(x)       (((x) >> 29) & 0x7) /* v4 only */
 132 #define VDCTRL4_SYNC_SIGNALS_ON         (1 << 18)
 133 #define SET_DOTCLK_H_VALID_DATA_CNT(x)  ((x) & 0x3ffff)
 134
 135 #define DEBUG0_HSYNC                    (1 < 26)
 136 #define DEBUG0_VSYNC                    (1 < 25)
 137
 138 #define MIN_XRES                        120
 139 #define MIN_YRES                        120
 140
 141 #define RED 0
 142 #define GREEN 1
 143 #define BLUE 2
 144 #define TRANSP 3
 145
 146 #define STMLCDIF_8BIT  1 /** pixel data bus to the display is of 8 bit width */
 147 #define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */
 148 #define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */
 149 #define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */
 150
 151 #define MXSFB_SYNC_DATA_ENABLE_HIGH_ACT (1 << 6)
 152 #define MXSFB_SYNC_DOTCLK_FALLING_ACT   (1 << 7) /* negtive edge sampling */
 153
 154 enum mxsfb_devtype {
 155         MXSFB_V3,
 156         MXSFB_V4,
 157 };
 158
 159 /* CPU dependent register offsets */
 160 struct mxsfb_devdata {
 161         unsigned transfer_count;
 162         unsigned cur_buf;
 163         unsigned next_buf;
 164         unsigned debug0;
 165         unsigned hs_wdth_mask;
 166         unsigned hs_wdth_shift;
 167         unsigned ipversion;
 168 };
 169
 170 struct mxsfb_info {
 171         struct fb_info fb_info;
 172         struct platform_device *pdev;
 173         struct clk *clk;
 174         void __iomem *base;     /* registers */
 175         unsigned allocated_size;
 176         int enabled;
 177         unsigned ld_intf_width;
 178         unsigned dotclk_delay;
 179         const struct mxsfb_devdata *devdata;
 180         u32 sync;
 181         struct regulator *reg_lcd;
 182 };
 183
 184 #define mxsfb_is_v3(host) (host->devdata->ipversion == 3)
 185 #define mxsfb_is_v4(host) (host->devdata->ipversion == 4)
 186
 187 static const struct mxsfb_devdata mxsfb_devdata[] = {
 188         [MXSFB_V3] = {
 189                 .transfer_count = LCDC_V3_TRANSFER_COUNT,
 190                 .cur_buf = LCDC_V3_CUR_BUF,
 191                 .next_buf = LCDC_V3_NEXT_BUF,
 192                 .debug0 = LCDC_V3_DEBUG0,
 193                 .hs_wdth_mask = 0xff,
 194                 .hs_wdth_shift = 24,
 195                 .ipversion = 3,
 196         },
 197         [MXSFB_V4] = {
 198                 .transfer_count = LCDC_V4_TRANSFER_COUNT,
 199                 .cur_buf = LCDC_V4_CUR_BUF,
 200                 .next_buf = LCDC_V4_NEXT_BUF,
 201                 .debug0 = LCDC_V4_DEBUG0,
 202                 .hs_wdth_mask = 0x3fff,
 203                 .hs_wdth_shift = 18,
 204                 .ipversion = 4,
 205         },
 206 };
 207
 208 #define to_imxfb_host(x) (container_of(x, struct mxsfb_info, fb_info))
 209
 210 /* mask and shift depends on architecture */
 211 static inline u32 set_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
 212 {
 213         return (val & host->devdata->hs_wdth_mask) <<
 214                 host->devdata->hs_wdth_shift;
 215 }
 216
 217 static inline u32 get_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
 218 {
 219         return (val >> host->devdata->hs_wdth_shift) &
 220                 host->devdata->hs_wdth_mask;
 221 }
 222
 223 static const struct fb_bitfield def_rgb565[] = {
 224         [RED] = {
 225                 .offset = 11,
 226                 .length = 5,
 227         },
 228         [GREEN] = {
 229                 .offset = 5,
 230                 .length = 6,
 231         },
 232         [BLUE] = {
 233                 .offset = 0,
 234                 .length = 5,
 235         },
 236         [TRANSP] = {    /* no support for transparency */
 237                 .length = 0,
 238         }
 239 };
 240
 241 static const struct fb_bitfield def_rgb666[] = {
 242         [RED] = {
 243                 .offset = 16,
 244                 .length = 6,
 245         },
 246         [GREEN] = {
 247                 .offset = 8,
 248                 .length = 6,
 249         },
 250         [BLUE] = {
 251                 .offset = 0,
 252                 .length = 6,
 253         },
 254         [TRANSP] = {    /* no support for transparency */
 255                 .length = 0,
 256         }
 257 };
 258
 259 static const struct fb_bitfield def_rgb888[] = {
 260         [RED] = {
 261                 .offset = 16,
 262                 .length = 8,
 263         },
 264         [GREEN] = {
 265                 .offset = 8,
 266                 .length = 8,
 267         },
 268         [BLUE] = {
 269                 .offset = 0,
 270                 .length = 8,
 271         },
 272         [TRANSP] = {    /* no support for transparency */
 273                 .length = 0,
 274         }
 275 };
 276
 277 static inline unsigned chan_to_field(unsigned chan, struct fb_bitfield *bf)
 278 {
 279         chan &= 0xffff;
 280         chan >>= 16 - bf->length;
 281         return chan << bf->offset;
 282 }
 283
 284 static int mxsfb_check_var(struct fb_var_screeninfo *var,
 285                 struct fb_info *fb_info)
 286 {
 287         struct mxsfb_info *host = to_imxfb_host(fb_info);
 288         const struct fb_bitfield *rgb = NULL;
 289
 290         if (var->xres < MIN_XRES)
 291                 var->xres = MIN_XRES;
 292         if (var->yres < MIN_YRES)
 293                 var->yres = MIN_YRES;
 294
 295         var->xres_virtual = var->xres;
 296
 297         var->yres_virtual = var->yres;
 298
 299         switch (var->bits_per_pixel) {
 300         case 16:
 301                 /* always expect RGB 565 */
 302                 rgb = def_rgb565;
 303                 break;
 304         case 32:
 305                 switch (host->ld_intf_width) {
 306                 case STMLCDIF_8BIT:
 307                         pr_debug("Unsupported LCD bus width mapping\n");
 308                         break;
 309                 case STMLCDIF_16BIT:
 310                 case STMLCDIF_18BIT:
 311                         /* 24 bit to 18 bit mapping */
 312                         rgb = def_rgb666;
 313                         break;
 314                 case STMLCDIF_24BIT:
 315                         /* real 24 bit */
 316                         rgb = def_rgb888;
 317                         break;
 318                 }
 319                 break;
 320         default:
 321                 pr_debug("Unsupported colour depth: %u\n", var->bits_per_pixel);
 322                 return -EINVAL;
 323         }
 324
 325         /*
 326          * Copy the RGB parameters for this display
 327          * from the machine specific parameters.
 328          */
 329         var->red    = rgb[RED];
 330         var->green  = rgb[GREEN];
 331         var->blue   = rgb[BLUE];
 332         var->transp = rgb[TRANSP];
 333
 334         return 0;
 335 }
 336
 337 static void mxsfb_enable_controller(struct fb_info *fb_info)
 338 {
 339         struct mxsfb_info *host = to_imxfb_host(fb_info);
 340         u32 reg;
 341         int ret;
 342
 343         dev_dbg(&host->pdev->dev, "%s\n", __func__);
 344
 345         if (host->reg_lcd) {
 346                 ret = regulator_enable(host->reg_lcd);
 347                 if (ret) {
 348                         dev_err(&host->pdev->dev,
 349                                 "lcd regulator enable failed:   %d\n", ret);
 350                         return;
 351                 }
 352         }
 353
 354         clk_prepare_enable(host->clk);
 355         clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U);
 356
 357         /* if it was disabled, re-enable the mode again */
 358         writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET);
 359
 360         /* enable the SYNC signals first, then the DMA engine */
 361         reg = readl(host->base + LCDC_VDCTRL4);
 362         reg |= VDCTRL4_SYNC_SIGNALS_ON;
 363         writel(reg, host->base + LCDC_VDCTRL4);
 364
 365         writel(CTRL_RUN, host->base + LCDC_CTRL + REG_SET);
 366
 367         host->enabled = 1;
 368 }
 369
 370 static void mxsfb_disable_controller(struct fb_info *fb_info)
 371 {
 372         struct mxsfb_info *host = to_imxfb_host(fb_info);
 373         unsigned loop;
 374         u32 reg;
 375         int ret;
 376
 377         dev_dbg(&host->pdev->dev, "%s\n", __func__);
 378
 379         /*
 380          * Even if we disable the controller here, it will still continue
 381          * until its FIFOs are running out of data
 382          */
 383         writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_CLR);
 384
 385         loop = 1000;
 386         while (loop) {
 387                 reg = readl(host->base + LCDC_CTRL);
 388                 if (!(reg & CTRL_RUN))
 389                         break;
 390                 loop--;
 391         }
 392
 393         reg = readl(host->base + LCDC_VDCTRL4);
 394         writel(reg & ~VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4);
 395
 396         clk_disable_unprepare(host->clk);
 397
 398         host->enabled = 0;
 399
 400         if (host->reg_lcd) {
 401                 ret = regulator_disable(host->reg_lcd);
 402                 if (ret)
 403                         dev_err(&host->pdev->dev,
 404                                 "lcd regulator disable failed: %d\n", ret);
 405         }
 406 }
 407
 408 static int mxsfb_set_par(struct fb_info *fb_info)
 409 {
 410         struct mxsfb_info *host = to_imxfb_host(fb_info);
 411         u32 ctrl, vdctrl0, vdctrl4;
 412         int line_size, fb_size;
 413         int reenable = 0;
 414
 415         line_size =  fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3);
 416         fb_size = fb_info->var.yres_virtual * line_size;
 417
 418         if (fb_size > fb_info->fix.smem_len)
 419                 return -ENOMEM;
 420
 421         fb_info->fix.line_length = line_size;
 422
 423         /*
 424          * It seems, you can't re-program the controller if it is still running.
 425          * This may lead into shifted pictures (FIFO issue?).
 426          * So, first stop the controller and drain its FIFOs
 427          */
 428         if (host->enabled) {
 429                 reenable = 1;
 430                 mxsfb_disable_controller(fb_info);
 431         }
 432
 433         /* clear the FIFOs */
 434         writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET);
 435
 436         ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER |
 437                 CTRL_SET_BUS_WIDTH(host->ld_intf_width);
 438
 439         switch (fb_info->var.bits_per_pixel) {
 440         case 16:
 441                 dev_dbg(&host->pdev->dev, "Setting up RGB565 mode\n");
 442                 ctrl |= CTRL_SET_WORD_LENGTH(0);
 443                 writel(CTRL1_SET_BYTE_PACKAGING(0xf), host->base + LCDC_CTRL1);
 444                 break;
 445         case 32:
 446                 dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n");
 447                 ctrl |= CTRL_SET_WORD_LENGTH(3);
 448                 switch (host->ld_intf_width) {
 449                 case STMLCDIF_8BIT:
 450                         dev_dbg(&host->pdev->dev,
 451                                         "Unsupported LCD bus width mapping\n");
 452                         return -EINVAL;
 453                 case STMLCDIF_16BIT:
 454                 case STMLCDIF_18BIT:
 455                         /* 24 bit to 18 bit mapping */
 456                         ctrl |= CTRL_DF24; /* ignore the upper 2 bits in
 457                                             *  each colour component
 458                                             */
 459                         break;
 460                 case STMLCDIF_24BIT:
 461                         /* real 24 bit */
 462                         break;
 463                 }
 464                 /* do not use packed pixels = one pixel per word instead */
 465                 writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1);
 466                 break;
 467         default:
 468                 dev_dbg(&host->pdev->dev, "Unhandled color depth of %u\n",
 469                                 fb_info->var.bits_per_pixel);
 470                 return -EINVAL;
 471         }
 472
 473         writel(ctrl, host->base + LCDC_CTRL);
 474
 475         writel(TRANSFER_COUNT_SET_VCOUNT(fb_info->var.yres) |
 476                         TRANSFER_COUNT_SET_HCOUNT(fb_info->var.xres),
 477                         host->base + host->devdata->transfer_count);
 478
 479         vdctrl0 = VDCTRL0_ENABLE_PRESENT |      /* always in DOTCLOCK mode */
 480                 VDCTRL0_VSYNC_PERIOD_UNIT |
 481                 VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
 482                 VDCTRL0_SET_VSYNC_PULSE_WIDTH(fb_info->var.vsync_len);
 483         if (fb_info->var.sync & FB_SYNC_HOR_HIGH_ACT)
 484                 vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH;
 485         if (fb_info->var.sync & FB_SYNC_VERT_HIGH_ACT)
 486                 vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH;
 487         if (host->sync & MXSFB_SYNC_DATA_ENABLE_HIGH_ACT)
 488                 vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH;
 489         if (host->sync & MXSFB_SYNC_DOTCLK_FALLING_ACT)
 490                 vdctrl0 |= VDCTRL0_DOTCLK_ACT_FALLING;
 491
 492         writel(vdctrl0, host->base + LCDC_VDCTRL0);
 493
 494         /* frame length in lines */
 495         writel(fb_info->var.upper_margin + fb_info->var.vsync_len +
 496                 fb_info->var.lower_margin + fb_info->var.yres,
 497                 host->base + LCDC_VDCTRL1);
 498
 499         /* line length in units of clocks or pixels */
 500         writel(set_hsync_pulse_width(host, fb_info->var.hsync_len) |
 501                 VDCTRL2_SET_HSYNC_PERIOD(fb_info->var.left_margin +
 502                 fb_info->var.hsync_len + fb_info->var.right_margin +
 503                 fb_info->var.xres),
 504                 host->base + LCDC_VDCTRL2);
 505
 506         writel(SET_HOR_WAIT_CNT(fb_info->var.left_margin +
 507                 fb_info->var.hsync_len) |
 508                 SET_VERT_WAIT_CNT(fb_info->var.upper_margin +
 509                         fb_info->var.vsync_len),
 510                 host->base + LCDC_VDCTRL3);
 511
 512         vdctrl4 = SET_DOTCLK_H_VALID_DATA_CNT(fb_info->var.xres);
 513         if (mxsfb_is_v4(host))
 514                 vdctrl4 |= VDCTRL4_SET_DOTCLK_DLY(host->dotclk_delay);
 515         writel(vdctrl4, host->base + LCDC_VDCTRL4);
 516
 517         writel(fb_info->fix.smem_start +
 518                         fb_info->fix.line_length * fb_info->var.yoffset,
 519                         host->base + host->devdata->next_buf);
 520
 521         if (reenable)
 522                 mxsfb_enable_controller(fb_info);
 523
 524         return 0;
 525 }
 526
 527 static int mxsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 528                 u_int transp, struct fb_info *fb_info)
 529 {
 530         unsigned int val;
 531         int ret = -EINVAL;
 532
 533         /*
 534          * If greyscale is true, then we convert the RGB value
 535          * to greyscale no matter what visual we are using.
 536          */
 537         if (fb_info->var.grayscale)
 538                 red = green = blue = (19595 * red + 38470 * green +
 539                                         7471 * blue) >> 16;
 540
 541         switch (fb_info->fix.visual) {
 542         case FB_VISUAL_TRUECOLOR:
 543                 /*
 544                  * 12 or 16-bit True Colour.  We encode the RGB value
 545                  * according to the RGB bitfield information.
 546                  */
 547                 if (regno < 16) {
 548                         u32 *pal = fb_info->pseudo_palette;
 549
 550                         val  = chan_to_field(red, &fb_info->var.red);
 551                         val |= chan_to_field(green, &fb_info->var.green);
 552                         val |= chan_to_field(blue, &fb_info->var.blue);
 553
 554                         pal[regno] = val;
 555                         ret = 0;
 556                 }
 557                 break;
 558
 559         case FB_VISUAL_STATIC_PSEUDOCOLOR:
 560         case FB_VISUAL_PSEUDOCOLOR:
 561                 break;
 562         }
 563
 564         return ret;
 565 }
 566
 567 static int mxsfb_blank(int blank, struct fb_info *fb_info)
 568 {
 569         struct mxsfb_info *host = to_imxfb_host(fb_info);
 570
 571         switch (blank) {
 572         case FB_BLANK_POWERDOWN:
 573         case FB_BLANK_VSYNC_SUSPEND:
 574         case FB_BLANK_HSYNC_SUSPEND:
 575         case FB_BLANK_NORMAL:
 576                 if (host->enabled)
 577                         mxsfb_disable_controller(fb_info);
 578                 break;
 579
 580         case FB_BLANK_UNBLANK:
 581                 if (!host->enabled)
 582                         mxsfb_enable_controller(fb_info);
 583                 break;
 584         }
 585         return 0;
 586 }
 587
 588 static int mxsfb_pan_display(struct fb_var_screeninfo *var,
 589                 struct fb_info *fb_info)
 590 {
 591         struct mxsfb_info *host = to_imxfb_host(fb_info);
 592         unsigned offset;
 593
 594         if (var->xoffset != 0)
 595                 return -EINVAL;
 596
 597         offset = fb_info->fix.line_length * var->yoffset;
 598
 599         /* update on next VSYNC */
 600         writel(fb_info->fix.smem_start + offset,
 601                         host->base + host->devdata->next_buf);
 602
 603         return 0;
 604 }
 605
 606 static struct fb_ops mxsfb_ops = {
 607         .owner = THIS_MODULE,
 608         .fb_check_var = mxsfb_check_var,
 609         .fb_set_par = mxsfb_set_par,
 610         .fb_setcolreg = mxsfb_setcolreg,
 611         .fb_blank = mxsfb_blank,
 612         .fb_pan_display = mxsfb_pan_display,
 613         .fb_fillrect = cfb_fillrect,
 614         .fb_copyarea = cfb_copyarea,
 615         .fb_imageblit = cfb_imageblit,
 616 };
 617
 618 static int mxsfb_restore_mode(struct mxsfb_info *host)
 619 {
 620         struct fb_info *fb_info = &host->fb_info;
 621         unsigned line_count;
 622         unsigned period;
 623         unsigned long pa, fbsize;
 624         int bits_per_pixel, ofs;
 625         u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl;
 626         struct fb_videomode vmode;
 627
 628         /* Only restore the mode when the controller is running */
 629         ctrl = readl(host->base + LCDC_CTRL);
 630         if (!(ctrl & CTRL_RUN))
 631                 return -EINVAL;
 632
 633         vdctrl0 = readl(host->base + LCDC_VDCTRL0);
 634         vdctrl2 = readl(host->base + LCDC_VDCTRL2);
 635         vdctrl3 = readl(host->base + LCDC_VDCTRL3);
 636         vdctrl4 = readl(host->base + LCDC_VDCTRL4);
 637
 638         transfer_count = readl(host->base + host->devdata->transfer_count);
 639
 640         vmode.xres = TRANSFER_COUNT_GET_HCOUNT(transfer_count);
 641         vmode.yres = TRANSFER_COUNT_GET_VCOUNT(transfer_count);
 642
 643         switch (CTRL_GET_WORD_LENGTH(ctrl)) {
 644         case 0:
 645                 bits_per_pixel = 16;
 646                 break;
 647         case 3:
 648                 bits_per_pixel = 32;
 649         case 1:
 650         default:
 651                 return -EINVAL;
 652         }
 653
 654         fb_info->var.bits_per_pixel = bits_per_pixel;
 655
 656         vmode.pixclock = KHZ2PICOS(clk_get_rate(host->clk) / 1000U);
 657         vmode.hsync_len = get_hsync_pulse_width(host, vdctrl2);
 658         vmode.left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode.hsync_len;
 659         vmode.right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) - vmode.hsync_len -
 660                 vmode.left_margin - vmode.xres;
 661         vmode.vsync_len = VDCTRL0_GET_VSYNC_PULSE_WIDTH(vdctrl0);
 662         period = readl(host->base + LCDC_VDCTRL1);
 663         vmode.upper_margin = GET_VERT_WAIT_CNT(vdctrl3) - vmode.vsync_len;
 664         vmode.lower_margin = period - vmode.vsync_len - vmode.upper_margin - vmode.yres;
 665
 666         vmode.vmode = FB_VMODE_NONINTERLACED;
 667
 668         vmode.sync = 0;
 669         if (vdctrl0 & VDCTRL0_HSYNC_ACT_HIGH)
 670                 vmode.sync |= FB_SYNC_HOR_HIGH_ACT;
 671         if (vdctrl0 & VDCTRL0_VSYNC_ACT_HIGH)
 672                 vmode.sync |= FB_SYNC_VERT_HIGH_ACT;
 673
 674         pr_debug("Reconstructed video mode:\n");
 675         pr_debug("%dx%d, hsync: %u left: %u, right: %u, vsync: %u, upper: %u, lower: %u\n",
 676                         vmode.xres, vmode.yres,
 677                         vmode.hsync_len, vmode.left_margin, vmode.right_margin,
 678                         vmode.vsync_len, vmode.upper_margin, vmode.lower_margin);
 679         pr_debug("pixclk: %ldkHz\n", PICOS2KHZ(vmode.pixclock));
 680
 681         fb_add_videomode(&vmode, &fb_info->modelist);
 682
 683         host->ld_intf_width = CTRL_GET_BUS_WIDTH(ctrl);
 684         host->dotclk_delay = VDCTRL4_GET_DOTCLK_DLY(vdctrl4);
 685
 686         fb_info->fix.line_length = vmode.xres * (bits_per_pixel >> 3);
 687
 688         pa = readl(host->base + host->devdata->cur_buf);
 689         fbsize = fb_info->fix.line_length * vmode.yres;
 690         if (pa < fb_info->fix.smem_start)
 691                 return -EINVAL;
 692         if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len)
 693                 return -EINVAL;
 694         ofs = pa - fb_info->fix.smem_start;
 695         if (ofs) {
 696                 memmove(fb_info->screen_base, fb_info->screen_base + ofs, fbsize);
 697                 writel(fb_info->fix.smem_start, host->base + host->devdata->next_buf);
 698         }
 699
 700         line_count = fb_info->fix.smem_len / fb_info->fix.line_length;
 701         fb_info->fix.ypanstep = 1;
 702
 703         clk_prepare_enable(host->clk);
 704         host->enabled = 1;
 705
 706         return 0;
 707 }
 708
 709 static int mxsfb_init_fbinfo_dt(struct mxsfb_info *host)
 710 {
 711         struct fb_info *fb_info = &host->fb_info;
 712         struct fb_var_screeninfo *var = &fb_info->var;
 713         struct device *dev = &host->pdev->dev;
 714         struct device_node *np = host->pdev->dev.of_node;
 715         struct device_node *display_np;
 716         struct device_node *timings_np;
 717         struct display_timings *timings;
 718         u32 width;
 719         int i;
 720         int ret = 0;
 721
 722         display_np = of_parse_phandle(np, "display", 0);
 723         if (!display_np) {
 724                 dev_err(dev, "failed to find display phandle\n");
 725                 return -ENOENT;
 726         }
 727
 728         ret = of_property_read_u32(display_np, "bus-width", &width);
 729         if (ret < 0) {
 730                 dev_err(dev, "failed to get property bus-width\n");
 731                 goto put_display_node;
 732         }
 733
 734         switch (width) {
 735         case 8:
 736                 host->ld_intf_width = STMLCDIF_8BIT;
 737                 break;
 738         case 16:
 739                 host->ld_intf_width = STMLCDIF_16BIT;
 740                 break;
 741         case 18:
 742                 host->ld_intf_width = STMLCDIF_18BIT;
 743                 break;
 744         case 24:
 745                 host->ld_intf_width = STMLCDIF_24BIT;
 746                 break;
 747         default:
 748                 dev_err(dev, "invalid bus-width value\n");
 749                 ret = -EINVAL;
 750                 goto put_display_node;
 751         }
 752
 753         ret = of_property_read_u32(display_np, "bits-per-pixel",
 754                                    &var->bits_per_pixel);
 755         if (ret < 0) {
 756                 dev_err(dev, "failed to get property bits-per-pixel\n");
 757                 goto put_display_node;
 758         }
 759
 760         timings = of_get_display_timings(display_np);
 761         if (!timings) {
 762                 dev_err(dev, "failed to get display timings\n");
 763                 ret = -ENOENT;
 764                 goto put_display_node;
 765         }
 766
 767         timings_np = of_find_node_by_name(display_np,
 768                                           "display-timings");
 769         if (!timings_np) {
 770                 dev_err(dev, "failed to find display-timings node\n");
 771                 ret = -ENOENT;
 772                 goto put_display_node;
 773         }
 774
 775         for (i = 0; i < of_get_child_count(timings_np); i++) {
 776                 struct videomode vm;
 777                 struct fb_videomode fb_vm;
 778
 779                 ret = videomode_from_timings(timings, &vm, i);
 780                 if (ret < 0)
 781                         goto put_timings_node;
 782                 ret = fb_videomode_from_videomode(&vm, &fb_vm);
 783                 if (ret < 0)
 784                         goto put_timings_node;
 785
 786                 if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
 787                         host->sync |= MXSFB_SYNC_DATA_ENABLE_HIGH_ACT;
 788                 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
 789                         host->sync |= MXSFB_SYNC_DOTCLK_FALLING_ACT;
 790                 fb_add_videomode(&fb_vm, &fb_info->modelist);
 791         }
 792
 793 put_timings_node:
 794         of_node_put(timings_np);
 795 put_display_node:
 796         of_node_put(display_np);
 797         return ret;
 798 }
 799
 800 static int mxsfb_init_fbinfo(struct mxsfb_info *host)
 801 {
 802         struct fb_info *fb_info = &host->fb_info;
 803         struct fb_var_screeninfo *var = &fb_info->var;
 804         dma_addr_t fb_phys;
 805         void *fb_virt;
 806         unsigned fb_size;
 807         int ret;
 808
 809         fb_info->fbops = &mxsfb_ops;
 810         fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST;
 811         strlcpy(fb_info->fix.id, "mxs", sizeof(fb_info->fix.id));
 812         fb_info->fix.type = FB_TYPE_PACKED_PIXELS;
 813         fb_info->fix.ypanstep = 1;
 814         fb_info->fix.visual = FB_VISUAL_TRUECOLOR,
 815         fb_info->fix.accel = FB_ACCEL_NONE;
 816
 817         ret = mxsfb_init_fbinfo_dt(host);
 818         if (ret)
 819                 return ret;
 820
 821         var->nonstd = 0;
 822         var->activate = FB_ACTIVATE_NOW;
 823         var->accel_flags = 0;
 824         var->vmode = FB_VMODE_NONINTERLACED;
 825
 826         /* Memory allocation for framebuffer */
 827         fb_size = SZ_2M;
 828         fb_virt = alloc_pages_exact(fb_size, GFP_DMA);
 829         if (!fb_virt)
 830                 return -ENOMEM;
 831
 832         fb_phys = virt_to_phys(fb_virt);
 833
 834         fb_info->fix.smem_start = fb_phys;
 835         fb_info->screen_base = fb_virt;
 836         fb_info->screen_size = fb_info->fix.smem_len = fb_size;
 837
 838         if (mxsfb_restore_mode(host))
 839                 memset(fb_virt, 0, fb_size);
 840
 841         return 0;
 842 }
 843
 844 static void mxsfb_free_videomem(struct mxsfb_info *host)
 845 {
 846         struct fb_info *fb_info = &host->fb_info;
 847
 848         free_pages_exact(fb_info->screen_base, fb_info->fix.smem_len);
 849 }
 850
 851 static struct platform_device_id mxsfb_devtype[] = {
 852         {
 853                 .name = "imx23-fb",
 854                 .driver_data = MXSFB_V3,
 855         }, {
 856                 .name = "imx28-fb",
 857                 .driver_data = MXSFB_V4,
 858         }, {
 859                 /* sentinel */
 860         }
 861 };
 862 MODULE_DEVICE_TABLE(platform, mxsfb_devtype);
 863
 864 static const struct of_device_id mxsfb_dt_ids[] = {
 865         { .compatible = "fsl,imx23-lcdif", .data = &mxsfb_devtype[0], },
 866         { .compatible = "fsl,imx28-lcdif", .data = &mxsfb_devtype[1], },
 867         { /* sentinel */ }
 868 };
 869 MODULE_DEVICE_TABLE(of, mxsfb_dt_ids);
 870
 871 static int mxsfb_probe(struct platform_device *pdev)
 872 {
 873         const struct of_device_id *of_id =
 874                         of_match_device(mxsfb_dt_ids, &pdev->dev);
 875         struct resource *res;
 876         struct mxsfb_info *host;
 877         struct fb_info *fb_info;
 878         struct fb_modelist *modelist;
 879         int ret;
 880
 881         if (of_id)
 882                 pdev->id_entry = of_id->data;
 883
 884         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 885         if (!res) {
 886                 dev_err(&pdev->dev, "Cannot get memory IO resource\n");
 887                 return -ENODEV;
 888         }
 889
 890         fb_info = framebuffer_alloc(sizeof(struct mxsfb_info), &pdev->dev);
 891         if (!fb_info) {
 892                 dev_err(&pdev->dev, "Failed to allocate fbdev\n");
 893                 return -ENOMEM;
 894         }
 895
 896         host = to_imxfb_host(fb_info);
 897
 898         host->base = devm_ioremap_resource(&pdev->dev, res);
 899         if (IS_ERR(host->base)) {
 900                 ret = PTR_ERR(host->base);
 901                 goto fb_release;
 902         }
 903
 904         host->pdev = pdev;
 905         platform_set_drvdata(pdev, host);
 906
 907         host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data];
 908
 909         host->clk = devm_clk_get(&host->pdev->dev, NULL);
 910         if (IS_ERR(host->clk)) {
 911                 ret = PTR_ERR(host->clk);
 912                 goto fb_release;
 913         }
 914
 915         host->reg_lcd = devm_regulator_get(&pdev->dev, "lcd");
 916         if (IS_ERR(host->reg_lcd))
 917                 host->reg_lcd = NULL;
 918
 919         fb_info->pseudo_palette = devm_kzalloc(&pdev->dev, sizeof(u32) * 16,
 920                                                GFP_KERNEL);
 921         if (!fb_info->pseudo_palette) {
 922                 ret = -ENOMEM;
 923                 goto fb_release;
 924         }
 925
 926         INIT_LIST_HEAD(&fb_info->modelist);
 927
 928         ret = mxsfb_init_fbinfo(host);
 929         if (ret != 0)
 930                 goto fb_release;
 931
 932         modelist = list_first_entry(&fb_info->modelist,
 933                         struct fb_modelist, list);
 934         fb_videomode_to_var(&fb_info->var, &modelist->mode);
 935
 936         /* init the color fields */
 937         mxsfb_check_var(&fb_info->var, fb_info);
 938
 939         platform_set_drvdata(pdev, fb_info);
 940
 941         ret = register_framebuffer(fb_info);
 942         if (ret != 0) {
 943                 dev_err(&pdev->dev,"Failed to register framebuffer\n");
 944                 goto fb_destroy;
 945         }
 946
 947         if (!host->enabled) {
 948                 writel(0, host->base + LCDC_CTRL);
 949                 mxsfb_set_par(fb_info);
 950                 mxsfb_enable_controller(fb_info);
 951         }
 952
 953         dev_info(&pdev->dev, "initialized\n");
 954
 955         return 0;
 956
 957 fb_destroy:
 958         if (host->enabled)
 959                 clk_disable_unprepare(host->clk);
 960         fb_destroy_modelist(&fb_info->modelist);
 961 fb_release:
 962         framebuffer_release(fb_info);
 963
 964         return ret;
 965 }
 966
 967 static int mxsfb_remove(struct platform_device *pdev)
 968 {
 969         struct fb_info *fb_info = platform_get_drvdata(pdev);
 970         struct mxsfb_info *host = to_imxfb_host(fb_info);
 971
 972         if (host->enabled)
 973                 mxsfb_disable_controller(fb_info);
 974
 975         unregister_framebuffer(fb_info);
 976         mxsfb_free_videomem(host);
 977
 978         framebuffer_release(fb_info);
 979
 980         return 0;
 981 }
 982
 983 static void mxsfb_shutdown(struct platform_device *pdev)
 984 {
 985         struct fb_info *fb_info = platform_get_drvdata(pdev);
 986         struct mxsfb_info *host = to_imxfb_host(fb_info);
 987
 988         /*
 989          * Force stop the LCD controller as keeping it running during reboot
 990          * might interfere with the BootROM's boot mode pads sampling.
 991          */
 992         writel(CTRL_RUN, host->base + LCDC_CTRL + REG_CLR);
 993 }
 994
 995 static struct platform_driver mxsfb_driver = {
 996         .probe = mxsfb_probe,
 997         .remove = mxsfb_remove,
 998         .shutdown = mxsfb_shutdown,
 999         .id_table = mxsfb_devtype,
1000         .driver = {
1001                    .name = DRIVER_NAME,
1002                    .of_match_table = mxsfb_dt_ids,
1003         },
1004 };
1005
1006 module_platform_driver(mxsfb_driver);
1007
1008 MODULE_DESCRIPTION("Freescale mxs framebuffer driver");
1009 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1010 MODULE_LICENSE("GPL");