drivers/video/omap2/dss/dss_features.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dss_features.c
   3  *
   4  * Copyright (C) 2010 Texas Instruments
   5  * Author: Archit Taneja <archit@ti.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/types.h>
  23 #include <linux/err.h>
  24 #include <linux/slab.h>
  25
  26 #include <video/omapdss.h>
  27
  28 #include "dss.h"
  29 #include "dss_features.h"
  30
  31 /* Defines a generic omap register field */
  32 struct dss_reg_field {
  33         u8 start, end;
  34 };
  35
  36 struct dss_param_range {
  37         int min, max;
  38 };
  39
  40 struct omap_dss_features {
  41         const struct dss_reg_field *reg_fields;
  42         const int num_reg_fields;
  43
  44         const enum dss_feat_id *features;
  45         const int num_features;
  46
  47         const int num_mgrs;
  48         const int num_ovls;
  49         const int num_wbs;
  50         const enum omap_display_type *supported_displays;
  51         const enum omap_dss_output_id *supported_outputs;
  52         const enum omap_color_mode *supported_color_modes;
  53         const enum omap_overlay_caps *overlay_caps;
  54         const char * const *clksrc_names;
  55         const struct dss_param_range *dss_params;
  56
  57         const enum omap_dss_rotation_type supported_rotation_types;
  58
  59         const u32 buffer_size_unit;
  60         const u32 burst_size_unit;
  61 };
  62
  63 /* This struct is assigned to one of the below during initialization */
  64 static const struct omap_dss_features *omap_current_dss_features;
  65
  66 static const struct dss_reg_field omap2_dss_reg_fields[] = {
  67         [FEAT_REG_FIRHINC]                      = { 11, 0 },
  68         [FEAT_REG_FIRVINC]                      = { 27, 16 },
  69         [FEAT_REG_FIFOLOWTHRESHOLD]             = { 8, 0 },
  70         [FEAT_REG_FIFOHIGHTHRESHOLD]            = { 24, 16 },
  71         [FEAT_REG_FIFOSIZE]                     = { 8, 0 },
  72         [FEAT_REG_HORIZONTALACCU]               = { 9, 0 },
  73         [FEAT_REG_VERTICALACCU]                 = { 25, 16 },
  74         [FEAT_REG_DISPC_CLK_SWITCH]             = { 0, 0 },
  75         [FEAT_REG_DSIPLL_REGN]                  = { 0, 0 },
  76         [FEAT_REG_DSIPLL_REGM]                  = { 0, 0 },
  77         [FEAT_REG_DSIPLL_REGM_DISPC]            = { 0, 0 },
  78         [FEAT_REG_DSIPLL_REGM_DSI]              = { 0, 0 },
  79 };
  80
  81 static const struct dss_reg_field omap3_dss_reg_fields[] = {
  82         [FEAT_REG_FIRHINC]                      = { 12, 0 },
  83         [FEAT_REG_FIRVINC]                      = { 28, 16 },
  84         [FEAT_REG_FIFOLOWTHRESHOLD]             = { 11, 0 },
  85         [FEAT_REG_FIFOHIGHTHRESHOLD]            = { 27, 16 },
  86         [FEAT_REG_FIFOSIZE]                     = { 10, 0 },
  87         [FEAT_REG_HORIZONTALACCU]               = { 9, 0 },
  88         [FEAT_REG_VERTICALACCU]                 = { 25, 16 },
  89         [FEAT_REG_DISPC_CLK_SWITCH]             = { 0, 0 },
  90         [FEAT_REG_DSIPLL_REGN]                  = { 7, 1 },
  91         [FEAT_REG_DSIPLL_REGM]                  = { 18, 8 },
  92         [FEAT_REG_DSIPLL_REGM_DISPC]            = { 22, 19 },
  93         [FEAT_REG_DSIPLL_REGM_DSI]              = { 26, 23 },
  94 };
  95
  96 static const struct dss_reg_field omap4_dss_reg_fields[] = {
  97         [FEAT_REG_FIRHINC]                      = { 12, 0 },
  98         [FEAT_REG_FIRVINC]                      = { 28, 16 },
  99         [FEAT_REG_FIFOLOWTHRESHOLD]             = { 15, 0 },
 100         [FEAT_REG_FIFOHIGHTHRESHOLD]            = { 31, 16 },
 101         [FEAT_REG_FIFOSIZE]                     = { 15, 0 },
 102         [FEAT_REG_HORIZONTALACCU]               = { 10, 0 },
 103         [FEAT_REG_VERTICALACCU]                 = { 26, 16 },
 104         [FEAT_REG_DISPC_CLK_SWITCH]             = { 9, 8 },
 105         [FEAT_REG_DSIPLL_REGN]                  = { 8, 1 },
 106         [FEAT_REG_DSIPLL_REGM]                  = { 20, 9 },
 107         [FEAT_REG_DSIPLL_REGM_DISPC]            = { 25, 21 },
 108         [FEAT_REG_DSIPLL_REGM_DSI]              = { 30, 26 },
 109 };
 110
 111 static const struct dss_reg_field omap5_dss_reg_fields[] = {
 112         [FEAT_REG_FIRHINC]                      = { 12, 0 },
 113         [FEAT_REG_FIRVINC]                      = { 28, 16 },
 114         [FEAT_REG_FIFOLOWTHRESHOLD]             = { 15, 0 },
 115         [FEAT_REG_FIFOHIGHTHRESHOLD]            = { 31, 16 },
 116         [FEAT_REG_FIFOSIZE]                     = { 15, 0 },
 117         [FEAT_REG_HORIZONTALACCU]               = { 10, 0 },
 118         [FEAT_REG_VERTICALACCU]                 = { 26, 16 },
 119         [FEAT_REG_DISPC_CLK_SWITCH]             = { 9, 7 },
 120         [FEAT_REG_DSIPLL_REGN]                  = { 8, 1 },
 121         [FEAT_REG_DSIPLL_REGM]                  = { 20, 9 },
 122         [FEAT_REG_DSIPLL_REGM_DISPC]            = { 25, 21 },
 123         [FEAT_REG_DSIPLL_REGM_DSI]              = { 30, 26 },
 124 };
 125
 126 static const enum omap_display_type omap2_dss_supported_displays[] = {
 127         /* OMAP_DSS_CHANNEL_LCD */
 128         OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI,
 129
 130         /* OMAP_DSS_CHANNEL_DIGIT */
 131         OMAP_DISPLAY_TYPE_VENC,
 132 };
 133
 134 static const enum omap_display_type omap3430_dss_supported_displays[] = {
 135         /* OMAP_DSS_CHANNEL_LCD */
 136         OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
 137         OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI,
 138
 139         /* OMAP_DSS_CHANNEL_DIGIT */
 140         OMAP_DISPLAY_TYPE_VENC,
 141 };
 142
 143 static const enum omap_display_type omap3630_dss_supported_displays[] = {
 144         /* OMAP_DSS_CHANNEL_LCD */
 145         OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
 146         OMAP_DISPLAY_TYPE_DSI,
 147
 148         /* OMAP_DSS_CHANNEL_DIGIT */
 149         OMAP_DISPLAY_TYPE_VENC,
 150 };
 151
 152 static const enum omap_display_type omap4_dss_supported_displays[] = {
 153         /* OMAP_DSS_CHANNEL_LCD */
 154         OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI,
 155
 156         /* OMAP_DSS_CHANNEL_DIGIT */
 157         OMAP_DISPLAY_TYPE_VENC | OMAP_DISPLAY_TYPE_HDMI,
 158
 159         /* OMAP_DSS_CHANNEL_LCD2 */
 160         OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
 161         OMAP_DISPLAY_TYPE_DSI,
 162 };
 163
 164 static const enum omap_display_type omap5_dss_supported_displays[] = {
 165         /* OMAP_DSS_CHANNEL_LCD */
 166         OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
 167         OMAP_DISPLAY_TYPE_DSI,
 168
 169         /* OMAP_DSS_CHANNEL_DIGIT */
 170         OMAP_DISPLAY_TYPE_HDMI | OMAP_DISPLAY_TYPE_DPI,
 171
 172         /* OMAP_DSS_CHANNEL_LCD2 */
 173         OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
 174         OMAP_DISPLAY_TYPE_DSI,
 175 };
 176
 177 static const enum omap_dss_output_id omap2_dss_supported_outputs[] = {
 178         /* OMAP_DSS_CHANNEL_LCD */
 179         OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI,
 180
 181         /* OMAP_DSS_CHANNEL_DIGIT */
 182         OMAP_DSS_OUTPUT_VENC,
 183 };
 184
 185 static const enum omap_dss_output_id omap3430_dss_supported_outputs[] = {
 186         /* OMAP_DSS_CHANNEL_LCD */
 187         OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
 188         OMAP_DSS_OUTPUT_SDI | OMAP_DSS_OUTPUT_DSI1,
 189
 190         /* OMAP_DSS_CHANNEL_DIGIT */
 191         OMAP_DSS_OUTPUT_VENC,
 192 };
 193
 194 static const enum omap_dss_output_id omap3630_dss_supported_outputs[] = {
 195         /* OMAP_DSS_CHANNEL_LCD */
 196         OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
 197         OMAP_DSS_OUTPUT_DSI1,
 198
 199         /* OMAP_DSS_CHANNEL_DIGIT */
 200         OMAP_DSS_OUTPUT_VENC,
 201 };
 202
 203 static const enum omap_dss_output_id omap4_dss_supported_outputs[] = {
 204         /* OMAP_DSS_CHANNEL_LCD */
 205         OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
 206         OMAP_DSS_OUTPUT_DSI1,
 207
 208         /* OMAP_DSS_CHANNEL_DIGIT */
 209         OMAP_DSS_OUTPUT_VENC | OMAP_DSS_OUTPUT_HDMI |
 210         OMAP_DSS_OUTPUT_DPI,
 211
 212         /* OMAP_DSS_CHANNEL_LCD2 */
 213         OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
 214         OMAP_DSS_OUTPUT_DSI2,
 215 };
 216
 217 static const enum omap_dss_output_id omap5_dss_supported_outputs[] = {
 218         /* OMAP_DSS_CHANNEL_LCD */
 219         OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
 220         OMAP_DSS_OUTPUT_DSI1 | OMAP_DSS_OUTPUT_DSI2,
 221
 222         /* OMAP_DSS_CHANNEL_DIGIT */
 223         OMAP_DSS_OUTPUT_HDMI | OMAP_DSS_OUTPUT_DPI,
 224
 225         /* OMAP_DSS_CHANNEL_LCD2 */
 226         OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
 227         OMAP_DSS_OUTPUT_DSI1,
 228
 229         /* OMAP_DSS_CHANNEL_LCD3 */
 230         OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
 231         OMAP_DSS_OUTPUT_DSI2,
 232 };
 233
 234 static const enum omap_color_mode omap2_dss_supported_color_modes[] = {
 235         /* OMAP_DSS_GFX */
 236         OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
 237         OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
 238         OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
 239         OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
 240
 241         /* OMAP_DSS_VIDEO1 */
 242         OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
 243         OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
 244         OMAP_DSS_COLOR_UYVY,
 245
 246         /* OMAP_DSS_VIDEO2 */
 247         OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
 248         OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
 249         OMAP_DSS_COLOR_UYVY,
 250 };
 251
 252 static const enum omap_color_mode omap3_dss_supported_color_modes[] = {
 253         /* OMAP_DSS_GFX */
 254         OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
 255         OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
 256         OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
 257         OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
 258         OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
 259         OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
 260
 261         /* OMAP_DSS_VIDEO1 */
 262         OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
 263         OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
 264         OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
 265
 266         /* OMAP_DSS_VIDEO2 */
 267         OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
 268         OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
 269         OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
 270         OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
 271         OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
 272 };
 273
 274 static const enum omap_color_mode omap4_dss_supported_color_modes[] = {
 275         /* OMAP_DSS_GFX */
 276         OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
 277         OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
 278         OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
 279         OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
 280         OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
 281         OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 |
 282         OMAP_DSS_COLOR_ARGB16_1555 | OMAP_DSS_COLOR_RGBX16 |
 283         OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_XRGB16_1555,
 284
 285         /* OMAP_DSS_VIDEO1 */
 286         OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
 287         OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
 288         OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
 289         OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
 290         OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
 291         OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
 292         OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
 293         OMAP_DSS_COLOR_RGBX32,
 294
 295        /* OMAP_DSS_VIDEO2 */
 296         OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
 297         OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
 298         OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
 299         OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
 300         OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
 301         OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
 302         OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
 303         OMAP_DSS_COLOR_RGBX32,
 304
 305         /* OMAP_DSS_VIDEO3 */
 306         OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
 307         OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
 308         OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
 309         OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
 310         OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
 311         OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
 312         OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
 313         OMAP_DSS_COLOR_RGBX32,
 314
 315         /* OMAP_DSS_WB */
 316         OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
 317         OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
 318         OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
 319         OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
 320         OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
 321         OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
 322         OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
 323         OMAP_DSS_COLOR_RGBX32,
 324 };
 325
 326 static const enum omap_overlay_caps omap2_dss_overlay_caps[] = {
 327         /* OMAP_DSS_GFX */
 328         OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
 329
 330         /* OMAP_DSS_VIDEO1 */
 331         OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
 332                 OMAP_DSS_OVL_CAP_REPLICATION,
 333
 334         /* OMAP_DSS_VIDEO2 */
 335         OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
 336                 OMAP_DSS_OVL_CAP_REPLICATION,
 337 };
 338
 339 static const enum omap_overlay_caps omap3430_dss_overlay_caps[] = {
 340         /* OMAP_DSS_GFX */
 341         OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_POS |
 342                 OMAP_DSS_OVL_CAP_REPLICATION,
 343
 344         /* OMAP_DSS_VIDEO1 */
 345         OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
 346                 OMAP_DSS_OVL_CAP_REPLICATION,
 347
 348         /* OMAP_DSS_VIDEO2 */
 349         OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
 350                 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
 351 };
 352
 353 static const enum omap_overlay_caps omap3630_dss_overlay_caps[] = {
 354         /* OMAP_DSS_GFX */
 355         OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA |
 356                 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
 357
 358         /* OMAP_DSS_VIDEO1 */
 359         OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
 360                 OMAP_DSS_OVL_CAP_REPLICATION,
 361
 362         /* OMAP_DSS_VIDEO2 */
 363         OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
 364                 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_POS |
 365                 OMAP_DSS_OVL_CAP_REPLICATION,
 366 };
 367
 368 static const enum omap_overlay_caps omap4_dss_overlay_caps[] = {
 369         /* OMAP_DSS_GFX */
 370         OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA |
 371                 OMAP_DSS_OVL_CAP_ZORDER | OMAP_DSS_OVL_CAP_POS |
 372                 OMAP_DSS_OVL_CAP_REPLICATION,
 373
 374         /* OMAP_DSS_VIDEO1 */
 375         OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
 376                 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
 377                 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
 378
 379         /* OMAP_DSS_VIDEO2 */
 380         OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
 381                 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
 382                 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
 383
 384         /* OMAP_DSS_VIDEO3 */
 385         OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
 386                 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
 387                 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
 388 };
 389
 390 static const char * const omap2_dss_clk_source_names[] = {
 391         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]  = "N/A",
 392         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]    = "N/A",
 393         [OMAP_DSS_CLK_SRC_FCK]                  = "DSS_FCLK1",
 394 };
 395
 396 static const char * const omap3_dss_clk_source_names[] = {
 397         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]  = "DSI1_PLL_FCLK",
 398         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]    = "DSI2_PLL_FCLK",
 399         [OMAP_DSS_CLK_SRC_FCK]                  = "DSS1_ALWON_FCLK",
 400 };
 401
 402 static const char * const omap4_dss_clk_source_names[] = {
 403         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]  = "PLL1_CLK1",
 404         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]    = "PLL1_CLK2",
 405         [OMAP_DSS_CLK_SRC_FCK]                  = "DSS_FCLK",
 406         [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "PLL2_CLK1",
 407         [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI]   = "PLL2_CLK2",
 408 };
 409
 410 static const char * const omap5_dss_clk_source_names[] = {
 411         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]  = "DPLL_DSI1_A_CLK1",
 412         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]    = "DPLL_DSI1_A_CLK2",
 413         [OMAP_DSS_CLK_SRC_FCK]                  = "DSS_CLK",
 414         [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "DPLL_DSI1_C_CLK1",
 415         [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI]   = "DPLL_DSI1_C_CLK2",
 416 };
 417
 418 static const struct dss_param_range omap2_dss_param_range[] = {
 419         [FEAT_PARAM_DSS_FCK]                    = { 0, 173000000 },
 420         [FEAT_PARAM_DSS_PCD]                    = { 2, 255 },
 421         [FEAT_PARAM_DSIPLL_REGN]                = { 0, 0 },
 422         [FEAT_PARAM_DSIPLL_REGM]                = { 0, 0 },
 423         [FEAT_PARAM_DSIPLL_REGM_DISPC]          = { 0, 0 },
 424         [FEAT_PARAM_DSIPLL_REGM_DSI]            = { 0, 0 },
 425         [FEAT_PARAM_DSIPLL_FINT]                = { 0, 0 },
 426         [FEAT_PARAM_DSIPLL_LPDIV]               = { 0, 0 },
 427         [FEAT_PARAM_DOWNSCALE]                  = { 1, 2 },
 428         /*
 429          * Assuming the line width buffer to be 768 pixels as OMAP2 DISPC
 430          * scaler cannot scale a image with width more than 768.
 431          */
 432         [FEAT_PARAM_LINEWIDTH]                  = { 1, 768 },
 433 };
 434
 435 static const struct dss_param_range omap3_dss_param_range[] = {
 436         [FEAT_PARAM_DSS_FCK]                    = { 0, 173000000 },
 437         [FEAT_PARAM_DSS_PCD]                    = { 1, 255 },
 438         [FEAT_PARAM_DSIPLL_REGN]                = { 0, (1 << 7) - 1 },
 439         [FEAT_PARAM_DSIPLL_REGM]                = { 0, (1 << 11) - 1 },
 440         [FEAT_PARAM_DSIPLL_REGM_DISPC]          = { 0, (1 << 4) - 1 },
 441         [FEAT_PARAM_DSIPLL_REGM_DSI]            = { 0, (1 << 4) - 1 },
 442         [FEAT_PARAM_DSIPLL_FINT]                = { 750000, 2100000 },
 443         [FEAT_PARAM_DSIPLL_LPDIV]               = { 1, (1 << 13) - 1},
 444         [FEAT_PARAM_DSI_FCK]                    = { 0, 173000000 },
 445         [FEAT_PARAM_DOWNSCALE]                  = { 1, 4 },
 446         [FEAT_PARAM_LINEWIDTH]                  = { 1, 1024 },
 447 };
 448
 449 static const struct dss_param_range omap4_dss_param_range[] = {
 450         [FEAT_PARAM_DSS_FCK]                    = { 0, 186000000 },
 451         [FEAT_PARAM_DSS_PCD]                    = { 1, 255 },
 452         [FEAT_PARAM_DSIPLL_REGN]                = { 0, (1 << 8) - 1 },
 453         [FEAT_PARAM_DSIPLL_REGM]                = { 0, (1 << 12) - 1 },
 454         [FEAT_PARAM_DSIPLL_REGM_DISPC]          = { 0, (1 << 5) - 1 },
 455         [FEAT_PARAM_DSIPLL_REGM_DSI]            = { 0, (1 << 5) - 1 },
 456         [FEAT_PARAM_DSIPLL_FINT]                = { 500000, 2500000 },
 457         [FEAT_PARAM_DSIPLL_LPDIV]               = { 0, (1 << 13) - 1 },
 458         [FEAT_PARAM_DSI_FCK]                    = { 0, 170000000 },
 459         [FEAT_PARAM_DOWNSCALE]                  = { 1, 4 },
 460         [FEAT_PARAM_LINEWIDTH]                  = { 1, 2048 },
 461 };
 462
 463 static const struct dss_param_range omap5_dss_param_range[] = {
 464         [FEAT_PARAM_DSS_FCK]                    = { 0, 200000000 },
 465         [FEAT_PARAM_DSS_PCD]                    = { 1, 255 },
 466         [FEAT_PARAM_DSIPLL_REGN]                = { 0, (1 << 8) - 1 },
 467         [FEAT_PARAM_DSIPLL_REGM]                = { 0, (1 << 12) - 1 },
 468         [FEAT_PARAM_DSIPLL_REGM_DISPC]          = { 0, (1 << 5) - 1 },
 469         [FEAT_PARAM_DSIPLL_REGM_DSI]            = { 0, (1 << 5) - 1 },
 470         [FEAT_PARAM_DSIPLL_FINT]                = { 500000, 2500000 },
 471         [FEAT_PARAM_DSIPLL_LPDIV]               = { 0, (1 << 13) - 1 },
 472         [FEAT_PARAM_DSI_FCK]                    = { 0, 170000000 },
 473         [FEAT_PARAM_DOWNSCALE]                  = { 1, 4 },
 474         [FEAT_PARAM_LINEWIDTH]                  = { 1, 2048 },
 475 };
 476
 477 static const enum dss_feat_id omap2_dss_feat_list[] = {
 478         FEAT_LCDENABLEPOL,
 479         FEAT_LCDENABLESIGNAL,
 480         FEAT_PCKFREEENABLE,
 481         FEAT_FUNCGATED,
 482         FEAT_ROWREPEATENABLE,
 483         FEAT_RESIZECONF,
 484 };
 485
 486 static const enum dss_feat_id omap3430_dss_feat_list[] = {
 487         FEAT_LCDENABLEPOL,
 488         FEAT_LCDENABLESIGNAL,
 489         FEAT_PCKFREEENABLE,
 490         FEAT_FUNCGATED,
 491         FEAT_LINEBUFFERSPLIT,
 492         FEAT_ROWREPEATENABLE,
 493         FEAT_RESIZECONF,
 494         FEAT_DSI_PLL_FREQSEL,
 495         FEAT_DSI_REVERSE_TXCLKESC,
 496         FEAT_VENC_REQUIRES_TV_DAC_CLK,
 497         FEAT_CPR,
 498         FEAT_PRELOAD,
 499         FEAT_FIR_COEF_V,
 500         FEAT_ALPHA_FIXED_ZORDER,
 501         FEAT_FIFO_MERGE,
 502         FEAT_OMAP3_DSI_FIFO_BUG,
 503         FEAT_DPI_USES_VDDS_DSI,
 504 };
 505
 506 static const enum dss_feat_id am35xx_dss_feat_list[] = {
 507         FEAT_LCDENABLEPOL,
 508         FEAT_LCDENABLESIGNAL,
 509         FEAT_PCKFREEENABLE,
 510         FEAT_FUNCGATED,
 511         FEAT_LINEBUFFERSPLIT,
 512         FEAT_ROWREPEATENABLE,
 513         FEAT_RESIZECONF,
 514         FEAT_DSI_PLL_FREQSEL,
 515         FEAT_DSI_REVERSE_TXCLKESC,
 516         FEAT_VENC_REQUIRES_TV_DAC_CLK,
 517         FEAT_CPR,
 518         FEAT_PRELOAD,
 519         FEAT_FIR_COEF_V,
 520         FEAT_ALPHA_FIXED_ZORDER,
 521         FEAT_FIFO_MERGE,
 522         FEAT_OMAP3_DSI_FIFO_BUG,
 523 };
 524
 525 static const enum dss_feat_id omap3630_dss_feat_list[] = {
 526         FEAT_LCDENABLEPOL,
 527         FEAT_LCDENABLESIGNAL,
 528         FEAT_PCKFREEENABLE,
 529         FEAT_FUNCGATED,
 530         FEAT_LINEBUFFERSPLIT,
 531         FEAT_ROWREPEATENABLE,
 532         FEAT_RESIZECONF,
 533         FEAT_DSI_PLL_PWR_BUG,
 534         FEAT_DSI_PLL_FREQSEL,
 535         FEAT_CPR,
 536         FEAT_PRELOAD,
 537         FEAT_FIR_COEF_V,
 538         FEAT_ALPHA_FIXED_ZORDER,
 539         FEAT_FIFO_MERGE,
 540         FEAT_OMAP3_DSI_FIFO_BUG,
 541         FEAT_DPI_USES_VDDS_DSI,
 542 };
 543
 544 static const enum dss_feat_id omap4430_es1_0_dss_feat_list[] = {
 545         FEAT_MGR_LCD2,
 546         FEAT_CORE_CLK_DIV,
 547         FEAT_LCD_CLK_SRC,
 548         FEAT_DSI_DCS_CMD_CONFIG_VC,
 549         FEAT_DSI_VC_OCP_WIDTH,
 550         FEAT_DSI_GNQ,
 551         FEAT_HANDLE_UV_SEPARATE,
 552         FEAT_ATTR2,
 553         FEAT_CPR,
 554         FEAT_PRELOAD,
 555         FEAT_FIR_COEF_V,
 556         FEAT_ALPHA_FREE_ZORDER,
 557         FEAT_FIFO_MERGE,
 558         FEAT_BURST_2D,
 559 };
 560
 561 static const enum dss_feat_id omap4430_es2_0_1_2_dss_feat_list[] = {
 562         FEAT_MGR_LCD2,
 563         FEAT_CORE_CLK_DIV,
 564         FEAT_LCD_CLK_SRC,
 565         FEAT_DSI_DCS_CMD_CONFIG_VC,
 566         FEAT_DSI_VC_OCP_WIDTH,
 567         FEAT_DSI_GNQ,
 568         FEAT_HDMI_CTS_SWMODE,
 569         FEAT_HANDLE_UV_SEPARATE,
 570         FEAT_ATTR2,
 571         FEAT_CPR,
 572         FEAT_PRELOAD,
 573         FEAT_FIR_COEF_V,
 574         FEAT_ALPHA_FREE_ZORDER,
 575         FEAT_FIFO_MERGE,
 576         FEAT_BURST_2D,
 577 };
 578
 579 static const enum dss_feat_id omap4_dss_feat_list[] = {
 580         FEAT_MGR_LCD2,
 581         FEAT_CORE_CLK_DIV,
 582         FEAT_LCD_CLK_SRC,
 583         FEAT_DSI_DCS_CMD_CONFIG_VC,
 584         FEAT_DSI_VC_OCP_WIDTH,
 585         FEAT_DSI_GNQ,
 586         FEAT_HDMI_CTS_SWMODE,
 587         FEAT_HDMI_AUDIO_USE_MCLK,
 588         FEAT_HANDLE_UV_SEPARATE,
 589         FEAT_ATTR2,
 590         FEAT_CPR,
 591         FEAT_PRELOAD,
 592         FEAT_FIR_COEF_V,
 593         FEAT_ALPHA_FREE_ZORDER,
 594         FEAT_FIFO_MERGE,
 595         FEAT_BURST_2D,
 596 };
 597
 598 static const enum dss_feat_id omap5_dss_feat_list[] = {
 599         FEAT_MGR_LCD2,
 600         FEAT_CORE_CLK_DIV,
 601         FEAT_LCD_CLK_SRC,
 602         FEAT_DSI_DCS_CMD_CONFIG_VC,
 603         FEAT_DSI_VC_OCP_WIDTH,
 604         FEAT_DSI_GNQ,
 605         FEAT_HDMI_CTS_SWMODE,
 606         FEAT_HDMI_AUDIO_USE_MCLK,
 607         FEAT_HANDLE_UV_SEPARATE,
 608         FEAT_ATTR2,
 609         FEAT_CPR,
 610         FEAT_PRELOAD,
 611         FEAT_FIR_COEF_V,
 612         FEAT_ALPHA_FREE_ZORDER,
 613         FEAT_FIFO_MERGE,
 614         FEAT_BURST_2D,
 615         FEAT_DSI_PLL_SELFREQDCO,
 616         FEAT_DSI_PLL_REFSEL,
 617         FEAT_DSI_PHY_DCC,
 618 };
 619
 620 /* OMAP2 DSS Features */
 621 static const struct omap_dss_features omap2_dss_features = {
 622         .reg_fields = omap2_dss_reg_fields,
 623         .num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields),
 624
 625         .features = omap2_dss_feat_list,
 626         .num_features = ARRAY_SIZE(omap2_dss_feat_list),
 627
 628         .num_mgrs = 2,
 629         .num_ovls = 3,
 630         .supported_displays = omap2_dss_supported_displays,
 631         .supported_outputs = omap2_dss_supported_outputs,
 632         .supported_color_modes = omap2_dss_supported_color_modes,
 633         .overlay_caps = omap2_dss_overlay_caps,
 634         .clksrc_names = omap2_dss_clk_source_names,
 635         .dss_params = omap2_dss_param_range,
 636         .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
 637         .buffer_size_unit = 1,
 638         .burst_size_unit = 8,
 639 };
 640
 641 /* OMAP3 DSS Features */
 642 static const struct omap_dss_features omap3430_dss_features = {
 643         .reg_fields = omap3_dss_reg_fields,
 644         .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
 645
 646         .features = omap3430_dss_feat_list,
 647         .num_features = ARRAY_SIZE(omap3430_dss_feat_list),
 648
 649         .num_mgrs = 2,
 650         .num_ovls = 3,
 651         .supported_displays = omap3430_dss_supported_displays,
 652         .supported_outputs = omap3430_dss_supported_outputs,
 653         .supported_color_modes = omap3_dss_supported_color_modes,
 654         .overlay_caps = omap3430_dss_overlay_caps,
 655         .clksrc_names = omap3_dss_clk_source_names,
 656         .dss_params = omap3_dss_param_range,
 657         .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
 658         .buffer_size_unit = 1,
 659         .burst_size_unit = 8,
 660 };
 661
 662 /*
 663  * AM35xx DSS Features. This is basically OMAP3 DSS Features without the
 664  * vdds_dsi regulator.
 665  */
 666 static const struct omap_dss_features am35xx_dss_features = {
 667         .reg_fields = omap3_dss_reg_fields,
 668         .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
 669
 670         .features = am35xx_dss_feat_list,
 671         .num_features = ARRAY_SIZE(am35xx_dss_feat_list),
 672
 673         .num_mgrs = 2,
 674         .num_ovls = 3,
 675         .supported_displays = omap3430_dss_supported_displays,
 676         .supported_outputs = omap3430_dss_supported_outputs,
 677         .supported_color_modes = omap3_dss_supported_color_modes,
 678         .overlay_caps = omap3430_dss_overlay_caps,
 679         .clksrc_names = omap3_dss_clk_source_names,
 680         .dss_params = omap3_dss_param_range,
 681         .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
 682         .buffer_size_unit = 1,
 683         .burst_size_unit = 8,
 684 };
 685
 686 static const struct omap_dss_features omap3630_dss_features = {
 687         .reg_fields = omap3_dss_reg_fields,
 688         .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
 689
 690         .features = omap3630_dss_feat_list,
 691         .num_features = ARRAY_SIZE(omap3630_dss_feat_list),
 692
 693         .num_mgrs = 2,
 694         .num_ovls = 3,
 695         .supported_displays = omap3630_dss_supported_displays,
 696         .supported_outputs = omap3630_dss_supported_outputs,
 697         .supported_color_modes = omap3_dss_supported_color_modes,
 698         .overlay_caps = omap3630_dss_overlay_caps,
 699         .clksrc_names = omap3_dss_clk_source_names,
 700         .dss_params = omap3_dss_param_range,
 701         .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
 702         .buffer_size_unit = 1,
 703         .burst_size_unit = 8,
 704 };
 705
 706 /* OMAP4 DSS Features */
 707 /* For OMAP4430 ES 1.0 revision */
 708 static const struct omap_dss_features omap4430_es1_0_dss_features  = {
 709         .reg_fields = omap4_dss_reg_fields,
 710         .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
 711
 712         .features = omap4430_es1_0_dss_feat_list,
 713         .num_features = ARRAY_SIZE(omap4430_es1_0_dss_feat_list),
 714
 715         .num_mgrs = 3,
 716         .num_ovls = 4,
 717         .num_wbs = 1,
 718         .supported_displays = omap4_dss_supported_displays,
 719         .supported_outputs = omap4_dss_supported_outputs,
 720         .supported_color_modes = omap4_dss_supported_color_modes,
 721         .overlay_caps = omap4_dss_overlay_caps,
 722         .clksrc_names = omap4_dss_clk_source_names,
 723         .dss_params = omap4_dss_param_range,
 724         .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
 725         .buffer_size_unit = 16,
 726         .burst_size_unit = 16,
 727 };
 728
 729 /* For OMAP4430 ES 2.0, 2.1 and 2.2 revisions */
 730 static const struct omap_dss_features omap4430_es2_0_1_2_dss_features = {
 731         .reg_fields = omap4_dss_reg_fields,
 732         .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
 733
 734         .features = omap4430_es2_0_1_2_dss_feat_list,
 735         .num_features = ARRAY_SIZE(omap4430_es2_0_1_2_dss_feat_list),
 736
 737         .num_mgrs = 3,
 738         .num_ovls = 4,
 739         .num_wbs = 1,
 740         .supported_displays = omap4_dss_supported_displays,
 741         .supported_outputs = omap4_dss_supported_outputs,
 742         .supported_color_modes = omap4_dss_supported_color_modes,
 743         .overlay_caps = omap4_dss_overlay_caps,
 744         .clksrc_names = omap4_dss_clk_source_names,
 745         .dss_params = omap4_dss_param_range,
 746         .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
 747         .buffer_size_unit = 16,
 748         .burst_size_unit = 16,
 749 };
 750
 751 /* For all the other OMAP4 versions */
 752 static const struct omap_dss_features omap4_dss_features = {
 753         .reg_fields = omap4_dss_reg_fields,
 754         .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
 755
 756         .features = omap4_dss_feat_list,
 757         .num_features = ARRAY_SIZE(omap4_dss_feat_list),
 758
 759         .num_mgrs = 3,
 760         .num_ovls = 4,
 761         .num_wbs = 1,
 762         .supported_displays = omap4_dss_supported_displays,
 763         .supported_outputs = omap4_dss_supported_outputs,
 764         .supported_color_modes = omap4_dss_supported_color_modes,
 765         .overlay_caps = omap4_dss_overlay_caps,
 766         .clksrc_names = omap4_dss_clk_source_names,
 767         .dss_params = omap4_dss_param_range,
 768         .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
 769         .buffer_size_unit = 16,
 770         .burst_size_unit = 16,
 771 };
 772
 773 /* OMAP5 DSS Features */
 774 static const struct omap_dss_features omap5_dss_features = {
 775         .reg_fields = omap5_dss_reg_fields,
 776         .num_reg_fields = ARRAY_SIZE(omap5_dss_reg_fields),
 777
 778         .features = omap5_dss_feat_list,
 779         .num_features = ARRAY_SIZE(omap5_dss_feat_list),
 780
 781         .num_mgrs = 3,
 782         .num_ovls = 4,
 783         .supported_displays = omap5_dss_supported_displays,
 784         .supported_outputs = omap5_dss_supported_outputs,
 785         .supported_color_modes = omap4_dss_supported_color_modes,
 786         .overlay_caps = omap4_dss_overlay_caps,
 787         .clksrc_names = omap5_dss_clk_source_names,
 788         .dss_params = omap5_dss_param_range,
 789         .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
 790         .buffer_size_unit = 16,
 791         .burst_size_unit = 16,
 792 };
 793
 794 #if defined(CONFIG_OMAP4_DSS_HDMI)
 795 /* HDMI OMAP4 Functions*/
 796 static const struct ti_hdmi_ip_ops omap4_hdmi_functions = {
 797
 798         .video_configure        =       ti_hdmi_4xxx_basic_configure,
 799         .phy_enable             =       ti_hdmi_4xxx_phy_enable,
 800         .phy_disable            =       ti_hdmi_4xxx_phy_disable,
 801         .read_edid              =       ti_hdmi_4xxx_read_edid,
 802         .detect                 =       ti_hdmi_4xxx_detect,
 803         .pll_enable             =       ti_hdmi_4xxx_pll_enable,
 804         .pll_disable            =       ti_hdmi_4xxx_pll_disable,
 805         .video_enable           =       ti_hdmi_4xxx_wp_video_start,
 806         .video_disable          =       ti_hdmi_4xxx_wp_video_stop,
 807         .dump_wrapper           =       ti_hdmi_4xxx_wp_dump,
 808         .dump_core              =       ti_hdmi_4xxx_core_dump,
 809         .dump_pll               =       ti_hdmi_4xxx_pll_dump,
 810         .dump_phy               =       ti_hdmi_4xxx_phy_dump,
 811 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
 812         .audio_enable           =       ti_hdmi_4xxx_wp_audio_enable,
 813         .audio_disable          =       ti_hdmi_4xxx_wp_audio_disable,
 814         .audio_start            =       ti_hdmi_4xxx_audio_start,
 815         .audio_stop             =       ti_hdmi_4xxx_audio_stop,
 816         .audio_config           =       ti_hdmi_4xxx_audio_config,
 817         .audio_get_dma_port     =       ti_hdmi_4xxx_audio_get_dma_port,
 818 #endif
 819
 820 };
 821
 822 void dss_init_hdmi_ip_ops(struct hdmi_ip_data *ip_data,
 823                 enum omapdss_version version)
 824 {
 825         switch (version) {
 826         case OMAPDSS_VER_OMAP4430_ES1:
 827         case OMAPDSS_VER_OMAP4430_ES2:
 828         case OMAPDSS_VER_OMAP4:
 829                 ip_data->ops = &omap4_hdmi_functions;
 830                 break;
 831         default:
 832                 ip_data->ops = NULL;
 833         }
 834
 835         WARN_ON(ip_data->ops == NULL);
 836 }
 837 #endif
 838
 839 /* Functions returning values related to a DSS feature */
 840 int dss_feat_get_num_mgrs(void)
 841 {
 842         return omap_current_dss_features->num_mgrs;
 843 }
 844 EXPORT_SYMBOL(dss_feat_get_num_mgrs);
 845
 846 int dss_feat_get_num_ovls(void)
 847 {
 848         return omap_current_dss_features->num_ovls;
 849 }
 850 EXPORT_SYMBOL(dss_feat_get_num_ovls);
 851
 852 int dss_feat_get_num_wbs(void)
 853 {
 854         return omap_current_dss_features->num_wbs;
 855 }
 856
 857 unsigned long dss_feat_get_param_min(enum dss_range_param param)
 858 {
 859         return omap_current_dss_features->dss_params[param].min;
 860 }
 861
 862 unsigned long dss_feat_get_param_max(enum dss_range_param param)
 863 {
 864         return omap_current_dss_features->dss_params[param].max;
 865 }
 866
 867 enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel)
 868 {
 869         return omap_current_dss_features->supported_displays[channel];
 870 }
 871 EXPORT_SYMBOL(dss_feat_get_supported_displays);
 872
 873 enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel)
 874 {
 875         return omap_current_dss_features->supported_outputs[channel];
 876 }
 877 EXPORT_SYMBOL(dss_feat_get_supported_outputs);
 878
 879 enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane)
 880 {
 881         return omap_current_dss_features->supported_color_modes[plane];
 882 }
 883 EXPORT_SYMBOL(dss_feat_get_supported_color_modes);
 884
 885 enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane plane)
 886 {
 887         return omap_current_dss_features->overlay_caps[plane];
 888 }
 889
 890 bool dss_feat_color_mode_supported(enum omap_plane plane,
 891                 enum omap_color_mode color_mode)
 892 {
 893         return omap_current_dss_features->supported_color_modes[plane] &
 894                         color_mode;
 895 }
 896
 897 const char *dss_feat_get_clk_source_name(enum omap_dss_clk_source id)
 898 {
 899         return omap_current_dss_features->clksrc_names[id];
 900 }
 901
 902 u32 dss_feat_get_buffer_size_unit(void)
 903 {
 904         return omap_current_dss_features->buffer_size_unit;
 905 }
 906
 907 u32 dss_feat_get_burst_size_unit(void)
 908 {
 909         return omap_current_dss_features->burst_size_unit;
 910 }
 911
 912 /* DSS has_feature check */
 913 bool dss_has_feature(enum dss_feat_id id)
 914 {
 915         int i;
 916         const enum dss_feat_id *features = omap_current_dss_features->features;
 917         const int num_features = omap_current_dss_features->num_features;
 918
 919         for (i = 0; i < num_features; i++) {
 920                 if (features[i] == id)
 921                         return true;
 922         }
 923
 924         return false;
 925 }
 926
 927 void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end)
 928 {
 929         if (id >= omap_current_dss_features->num_reg_fields)
 930                 BUG();
 931
 932         *start = omap_current_dss_features->reg_fields[id].start;
 933         *end = omap_current_dss_features->reg_fields[id].end;
 934 }
 935
 936 bool dss_feat_rotation_type_supported(enum omap_dss_rotation_type rot_type)
 937 {
 938         return omap_current_dss_features->supported_rotation_types & rot_type;
 939 }
 940
 941 void dss_features_init(enum omapdss_version version)
 942 {
 943         switch (version) {
 944         case OMAPDSS_VER_OMAP24xx:
 945                 omap_current_dss_features = &omap2_dss_features;
 946                 break;
 947
 948         case OMAPDSS_VER_OMAP34xx_ES1:
 949         case OMAPDSS_VER_OMAP34xx_ES3:
 950                 omap_current_dss_features = &omap3430_dss_features;
 951                 break;
 952
 953         case OMAPDSS_VER_OMAP3630:
 954                 omap_current_dss_features = &omap3630_dss_features;
 955                 break;
 956
 957         case OMAPDSS_VER_OMAP4430_ES1:
 958                 omap_current_dss_features = &omap4430_es1_0_dss_features;
 959                 break;
 960
 961         case OMAPDSS_VER_OMAP4430_ES2:
 962                 omap_current_dss_features = &omap4430_es2_0_1_2_dss_features;
 963                 break;
 964
 965         case OMAPDSS_VER_OMAP4:
 966                 omap_current_dss_features = &omap4_dss_features;
 967                 break;
 968
 969         case OMAPDSS_VER_OMAP5:
 970                 omap_current_dss_features = &omap5_dss_features;
 971                 break;
 972
 973         case OMAPDSS_VER_AM35xx:
 974                 omap_current_dss_features = &am35xx_dss_features;
 975                 break;
 976
 977         default:
 978                 DSSWARN("Unsupported OMAP version");
 979                 break;
 980         }
 981 }