2 * (C) Copyright 2007-2008
3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
4 * Based on the sequoia configuration file.
6 * (C) Copyright 2006-2007
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
10 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
11 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
13 * SPDX-License-Identifier: GPL-2.0+
16 /************************************************************************
17 * PMC440.h - configuration for esd PMC440 boards
18 ***********************************************************************/
22 /*-----------------------------------------------------------------------
23 * High Level Configuration Options
24 *----------------------------------------------------------------------*/
25 #define CONFIG_440EPX 1 /* Specific PPC440EPx */
26 #define CONFIG_440 1 /* ... PPC440 family */
27 #define CONFIG_4xx 1 /* ... PPC4xx family */
29 #ifndef CONFIG_SYS_TEXT_BASE
30 #define CONFIG_SYS_TEXT_BASE 0xFFF90000
33 #define CONFIG_SYS_CLK_FREQ 33333400
35 #if 0 /* temporary disabled because OS/9 does not like dcache on startup */
36 #define CONFIG_4xx_DCACHE /* enable dcache */
39 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
40 #define CONFIG_MISC_INIT_F 1
41 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
42 #define CONFIG_BOARD_TYPES 1 /* support board types */
43 /*-----------------------------------------------------------------------
44 * Base addresses -- Note these are effective addresses where the
45 * actual resources get mapped (not physical addresses)
46 *----------------------------------------------------------------------*/
47 #define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
48 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 256 kB for malloc() */
50 #define CONFIG_PRAM 0 /* use pram variable to overwrite */
52 #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
53 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
54 #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
55 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
56 #define CONFIG_SYS_NAND_ADDR 0xd0000000 /* NAND Flash */
57 #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
58 #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
59 #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
60 #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
61 #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
62 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
63 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
64 #define CONFIG_SYS_PCI_MEMSIZE 0x80000000 /* 2GB! */
66 #define CONFIG_SYS_USB2D0_BASE 0xe0000100
67 #define CONFIG_SYS_USB_DEVICE 0xe0000000
68 #define CONFIG_SYS_USB_HOST 0xe0000400
69 #define CONFIG_SYS_FPGA_BASE0 0xef000000 /* 32 bit */
70 #define CONFIG_SYS_FPGA_BASE1 0xef100000 /* 16 bit */
71 #define CONFIG_SYS_RESET_BASE 0xef200000
73 /*-----------------------------------------------------------------------
74 * Initial RAM & stack pointer
75 *----------------------------------------------------------------------*/
76 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
77 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
78 #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
79 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
80 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
82 /*-----------------------------------------------------------------------
84 *----------------------------------------------------------------------*/
85 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
86 #define CONFIG_SYS_NS16550
87 #define CONFIG_SYS_NS16550_SERIAL
88 #define CONFIG_SYS_NS16550_REG_SIZE 1
89 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
90 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
91 #define CONFIG_BAUDRATE 115200
93 #define CONFIG_SYS_BAUDRATE_TABLE \
94 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
96 /*-----------------------------------------------------------------------
98 *----------------------------------------------------------------------*/
99 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
100 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
102 #define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
103 #define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
106 /*-----------------------------------------------------------------------
108 *----------------------------------------------------------------------*/
109 #define CONFIG_RTC_RX8025
111 /*-----------------------------------------------------------------------
113 *----------------------------------------------------------------------*/
114 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
115 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
117 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
119 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
120 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
122 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
123 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
125 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
126 #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
128 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
129 #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
131 #ifdef CONFIG_ENV_IS_IN_FLASH
132 #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
133 #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
134 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
136 /* Address and size of Redundant Environment Sector */
137 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
138 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
141 #ifdef CONFIG_ENV_IS_IN_EEPROM
142 #define CONFIG_ENV_OFFSET 0 /* environment starts at the beginning of the EEPROM */
143 #define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
147 * IPL (Initial Program Loader, integrated inside CPU)
148 * Will load first 4k from NAND (SPL) into cache and execute it from there.
150 * SPL (Secondary Program Loader)
151 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
152 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
153 * controller and the NAND controller so that the special U-Boot image can be
154 * loaded from NAND to SDRAM.
157 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
158 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
160 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
161 * set up. While still running from cache, I experienced problems accessing
162 * the NAND controller. sr - 2006-08-25
164 #if defined (CONFIG_NAND_U_BOOT)
165 #define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
166 #define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
167 #define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */
168 #define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
169 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
170 #define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
173 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
175 #define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
176 #define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
179 * Now the NAND chip has to be defined (no autodetection used!)
181 #define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
182 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
183 #define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
184 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
185 #undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
187 #define CONFIG_SYS_NAND_ECCSIZE 256
188 #define CONFIG_SYS_NAND_ECCBYTES 3
189 #define CONFIG_SYS_NAND_OOBSIZE 16
190 #define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
193 #ifdef CONFIG_ENV_IS_IN_NAND
195 * For NAND booting the environment is embedded in the U-Boot image. Please take
196 * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
198 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
199 #define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
200 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
203 /*-----------------------------------------------------------------------
205 *----------------------------------------------------------------------*/
206 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
207 #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
209 #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
210 /* 440EPx errata CHIP 11 */
212 /*-----------------------------------------------------------------------
214 *----------------------------------------------------------------------*/
215 #define CONFIG_SYS_I2C
216 #define CONFIG_SYS_I2C_PPC4XX
217 #define CONFIG_SYS_I2C_PPC4XX_CH0
218 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
219 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
220 #define CONFIG_SYS_I2C_PPC4XX_CH1
221 #define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000
222 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
224 #define CONFIG_SYS_I2C_MULTI_EEPROMS
226 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
227 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
228 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
229 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
230 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
232 #define CONFIG_SYS_EEPROM_WREN 1
233 #define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
236 * standard dtt sensor configuration - bottom bit will determine local or
237 * remote sensor of the TMP401
239 #define CONFIG_DTT_SENSORS { 0, 1 }
242 * The PMC440 uses a TI TMP401 temperature sensor. This part
243 * is basically compatible to the ADM1021 that is supported
247 * - conversion rate 0x02 = 0.25 conversions/second
248 * - ALERT ouput disabled
249 * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
250 * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
252 #define CONFIG_DTT_ADM1021
253 #define CONFIG_SYS_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
255 #define CONFIG_PREBOOT "echo Add \\\"run fpga\\\" and " \
256 "\\\"painit\\\" to preboot command"
258 #undef CONFIG_BOOTARGS
260 /* Setup some board specific values for the default environment variables */
261 #define CONFIG_HOSTNAME pmc440
262 #define CONFIG_SYS_BOOTFILE "bootfile=/tftpboot/pmc440/uImage\0"
263 #define CONFIG_SYS_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
265 #define CONFIG_EXTRA_ENV_SETTINGS \
266 CONFIG_SYS_BOOTFILE \
267 CONFIG_SYS_ROOTPATH \
268 "fdt_file=/tftpboot/pmc440/pmc440.dtb\0" \
271 "nfsargs=setenv bootargs root=/dev/nfs rw " \
272 "nfsroot=${serverip}:${rootpath}\0" \
273 "ramargs=setenv bootargs root=/dev/ram rw\0" \
274 "addip=setenv bootargs ${bootargs} " \
275 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
276 ":${hostname}:${netdev}:off panic=1\0" \
277 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
278 "addmisc=setenv bootargs ${bootargs} mem=${mem}\0" \
279 "nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \
280 "nand_boot_fdt=run nandargs addip addtty addmisc;" \
281 "bootm ${kernel_addr} - ${fdt_addr}\0" \
282 "net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};" \
283 "tftp ${fdt_addr_r} ${fdt_file};" \
284 "run nfsargs addip addtty addmisc;" \
285 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
286 "kernel_addr=ffc00000\0" \
287 "kernel_addr_r=200000\0" \
288 "fpga_addr=fff00000\0" \
289 "fdt_addr=fff80000\0" \
290 "fdt_addr_r=800000\0" \
291 "fpga=fpga loadb 0 ${fpga_addr}\0" \
292 "load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0" \
293 "update=protect off fff90000 ffffffff;era fff90000 ffffffff;" \
294 "cp.b 200000 fff90000 70000\0" \
297 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
299 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
300 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
302 #define CONFIG_PPC4xx_EMAC
303 #define CONFIG_IBM_EMAC4_V4 1
304 #define CONFIG_MII 1 /* MII PHY management */
305 #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
307 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
309 #define CONFIG_HAS_ETH0
310 #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
312 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
313 #define CONFIG_PHY1_ADDR 1
314 #define CONFIG_RESET_PHY_R 1
317 #define CONFIG_USB_OHCI_NEW
318 #define CONFIG_USB_STORAGE
319 #define CONFIG_SYS_OHCI_BE_CONTROLLER
321 #define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
322 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
323 #define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
324 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
325 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
327 /* Comment this out to enable USB 1.1 device */
328 #define USB_2_0_DEVICE
331 #define CONFIG_MAC_PARTITION
332 #define CONFIG_DOS_PARTITION
333 #define CONFIG_ISO_PARTITION
335 #include <config_cmd_default.h>
337 #define CONFIG_CMD_BSP
338 #define CONFIG_CMD_DATE
339 #define CONFIG_CMD_DHCP
340 #define CONFIG_CMD_DTT
341 #define CONFIG_CMD_EEPROM
342 #define CONFIG_CMD_ELF
343 #define CONFIG_CMD_FAT
344 #define CONFIG_CMD_I2C
345 #define CONFIG_CMD_MII
346 #define CONFIG_CMD_NAND
347 #define CONFIG_CMD_NET
348 #define CONFIG_CMD_NFS
349 #define CONFIG_CMD_PCI
350 #define CONFIG_CMD_PING
351 #define CONFIG_CMD_USB
352 #define CONFIG_CMD_REGINFO
355 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
356 CONFIG_SYS_POST_CPU | \
357 CONFIG_SYS_POST_UART | \
358 CONFIG_SYS_POST_I2C | \
359 CONFIG_SYS_POST_CACHE | \
360 CONFIG_SYS_POST_FPU | \
361 CONFIG_SYS_POST_ETHER | \
364 #define CONFIG_LOGBUFFER
365 #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
367 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
369 #define CONFIG_SUPPORT_VFAT
371 /*-----------------------------------------------------------------------
372 * Miscellaneous configurable options
373 *----------------------------------------------------------------------*/
374 #define CONFIG_SYS_LONGHELP /* undef to save memory */
375 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
376 #if defined(CONFIG_CMD_KGDB)
377 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
379 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
381 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
382 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
383 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
385 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
386 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
388 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
389 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
391 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
393 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
394 #define CONFIG_LOOPW 1 /* enable loopw command */
395 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
396 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
397 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
399 #define CONFIG_AUTOBOOT_KEYED 1
400 #define CONFIG_AUTOBOOT_PROMPT \
401 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
402 #undef CONFIG_AUTOBOOT_DELAY_STR
403 #define CONFIG_AUTOBOOT_STOP_STR " "
405 /*-----------------------------------------------------------------------
407 *----------------------------------------------------------------------*/
409 #define CONFIG_PCI /* include pci support */
410 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
411 #define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
412 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
413 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
414 #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
416 /* Board-specific PCI */
417 #define CONFIG_SYS_PCI_TARGET_INIT
418 #define CONFIG_SYS_PCI_MASTER_INIT
419 #define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
421 #define CONFIG_PCI_BOOTDELAY 0
423 /* PCI identification */
424 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
425 #define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441 /* PCI Device ID: Non-Monarch */
426 #define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440 /* PCI Device ID: Monarch */
427 /* for weak __pci_target_init() */
428 #define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
429 #define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
430 #define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
433 * For booting Linux, the board info and command line data
434 * have to be in the first 8 MB of memory, since this is
435 * the maximum mapped by the Linux kernel during initialization.
437 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
439 /*-----------------------------------------------------------------------
441 *----------------------------------------------------------------------*/
443 #define CONFIG_FPGA_XILINX
444 #define CONFIG_FPGA_SPARTAN2
445 #define CONFIG_FPGA_SPARTAN3
447 #define CONFIG_FPGA_COUNT 2
448 /*-----------------------------------------------------------------------
449 * External Bus Controller (EBC) Setup
450 *----------------------------------------------------------------------*/
453 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
455 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
456 #define CONFIG_SYS_NAND_CS 2 /* NAND chip connected to CSx */
458 /* Memory Bank 0 (NOR-FLASH) initialization */
459 #define CONFIG_SYS_EBC_PB0AP 0x03017200
460 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
462 /* Memory Bank 2 (NAND-FLASH) initialization */
463 #define CONFIG_SYS_EBC_PB2AP 0x018003c0
464 #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
466 #define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
467 /* Memory Bank 2 (NOR-FLASH) initialization */
468 #define CONFIG_SYS_EBC_PB2AP 0x03017200
469 #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FLASH_BASE | 0xda000)
471 /* Memory Bank 0 (NAND-FLASH) initialization */
472 #define CONFIG_SYS_EBC_PB0AP 0x018003c0
473 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
476 /* Memory Bank 1 (RESET) initialization */
477 #define CONFIG_SYS_EBC_PB1AP 0x7f817200 /* 0x03017200 */
478 #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_RESET_BASE | 0x1c000)
480 /* Memory Bank 4 (FPGA / 32Bit) initialization */
481 #define CONFIG_SYS_EBC_PB4AP 0x03840f40 /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
482 #define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_FPGA_BASE0 | 0x1c000) /* BS=1M,BU=R/W,BW=32bit */
484 /* Memory Bank 5 (FPGA / 16Bit) initialization */
485 #define CONFIG_SYS_EBC_PB5AP 0x03840f40 /* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */
486 #define CONFIG_SYS_EBC_PB5CR (CONFIG_SYS_FPGA_BASE1 | 0x1a000) /* BS=1M,BU=R/W,BW=16bit */
488 /*-----------------------------------------------------------------------
490 *----------------------------------------------------------------------*/
491 #define CONFIG_SYS_MAX_NAND_DEVICE 1
492 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
493 #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
494 #define CONFIG_SYS_NAND_QUIET_TEST 1
496 #if defined(CONFIG_CMD_KGDB)
497 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
498 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
501 /* pass open firmware flat tree */
502 #define CONFIG_OF_LIBFDT 1
503 #define CONFIG_OF_BOARD_SETUP 1
507 #endif /* __CONFIG_H */