3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
37 #define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */
38 #define CONFIG_SCM 1 /* ...on a System Controller Module */
39 #define CONFIG_CPM2 1 /* Has a CPM2 */
41 #if (CONFIG_TQM8260 <= 100)
42 # error "TQM8260 module revison not supported"
45 /* We use a TQM8260 module with a 300MHz CPU */
48 /* Define 60x busmode only if your TQM8260 has L2 cache! */
49 #ifdef CONFIG_L2_CACHE
50 # define CONFIG_BUSMODE_60x 1 /* bus mode: 60x */
52 # undef CONFIG_BUSMODE_60x /* bus mode: 8260 */
55 /* The board with 300MHz CPU doesn't have L2 cache, but works in 60x bus mode */
57 # define CONFIG_BUSMODE_60x
60 #define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */
62 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
64 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
66 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
68 #undef CONFIG_BOOTARGS
69 #define CONFIG_BOOTCOMMAND \
71 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
72 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
75 /* enable I2C and select the hardware/software driver */
76 #undef CONFIG_HARD_I2C /* I2C with hardware support */
77 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
78 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
79 #define CFG_I2C_SLAVE 0x7F
82 * Software (bit-bang) I2C driver configuration
85 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
86 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
87 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
88 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
89 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
90 else iop->pdat &= ~0x00010000
91 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
92 else iop->pdat &= ~0x00020000
93 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
95 #define CFG_I2C_EEPROM_ADDR 0x50
96 #define CFG_I2C_EEPROM_ADDR_LEN 2
97 #define CFG_EEPROM_PAGE_WRITE_BITS 4
98 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
103 * select serial console configuration
105 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
106 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
109 * if CONFIG_CONS_NONE is defined, then the serial console routines must
110 * defined elsewhere (for example, on the cogent platform, there are serial
111 * ports on the motherboard which are used for the serial console - see
112 * cogent/cma101/serial.[ch]).
114 #define CONFIG_CONS_ON_SMC /* define if console on SMC */
115 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
116 #undef CONFIG_CONS_NONE /* define if console on something else*/
117 #ifdef CONFIG_82xx_CONS_SMC1
118 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
120 #ifdef CONFIG_82xx_CONS_SMC2
121 #define CONFIG_CONS_INDEX 2 /* which serial channel for console */
124 #undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
125 #define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
126 #define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */
129 * select ethernet configuration
131 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
132 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
135 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
136 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
137 * from CONFIG_COMMANDS to remove support for networking.
139 * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
140 * X.29 connector, and FCC2 is hardwired to the X.1 connector)
142 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
143 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
144 #undef CONFIG_ETHER_NONE /* define if ether on something else */
145 #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
147 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
152 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
153 * - Enable Full Duplex in FSMR
155 # define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
156 # define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK12|CMXFCR_TF1CS_CLK11)
157 # define CFG_CPMFCR_RAMTYPE 0
158 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
160 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
165 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
166 * - Enable Full Duplex in FSMR
168 # define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
169 # define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
170 # define CFG_CPMFCR_RAMTYPE 0
171 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
173 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
176 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
177 #ifndef CONFIG_300MHz
178 #define CONFIG_8260_CLKIN 66666666 /* in Hz */
180 #define CONFIG_8260_CLKIN 83333000 /* in Hz */
183 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
184 #define CONFIG_BAUDRATE 230400
186 #define CONFIG_BAUDRATE 115200
189 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
190 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
192 #undef CONFIG_WATCHDOG /* watchdog disabled */
194 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
198 * Command line configuration.
200 #include <config_cmd_default.h>
202 #define CONFIG_CMD_DHCP
203 #define CONFIG_CMD_I2C
204 #define CONFIG_CMD_EEPROM
205 #define CONFIG_CMD_BSP
209 * Miscellaneous configurable options
211 #define CFG_LONGHELP /* undef to save memory */
212 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
213 #if defined(CONFIG_CMD_KGDB)
214 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
216 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
218 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
219 #define CFG_MAXARGS 16 /* max number of command args */
220 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
222 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
223 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
225 #define CFG_LOAD_ADDR 0x100000 /* default load address */
227 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
229 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
231 #define CFG_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */
233 #define CONFIG_MISC_INIT_R /* have misc_init_r() function */
236 * For booting Linux, the board info and command line data
237 * have to be in the first 8 MB of memory, since this is
238 * the maximum mapped by the Linux kernel during initialization.
240 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
243 /* What should the base address of the main FLASH be and how big is
244 * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk
245 * The main FLASH is whichever is connected to *CS0.
247 #define CFG_FLASH0_BASE 0x40000000
248 #define CFG_FLASH1_BASE 0x60000000
249 #define CFG_FLASH0_SIZE 32
250 #define CFG_FLASH1_SIZE 32
252 /* Flash bank size (for preliminary settings)
254 #define CFG_FLASH_SIZE CFG_FLASH0_SIZE
256 /*-----------------------------------------------------------------------
259 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
260 #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
262 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
263 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
266 /* Start port with environment in flash; switch to EEPROM later */
267 #define CFG_ENV_IS_IN_FLASH 1
268 #define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000)
269 #define CFG_ENV_SIZE 0x40000
270 #define CFG_ENV_SECT_SIZE 0x40000
272 /* Final version: environment in EEPROM */
273 #define CFG_ENV_IS_IN_EEPROM 1
274 #define CFG_ENV_OFFSET 0
275 #define CFG_ENV_SIZE 2048
278 /*-----------------------------------------------------------------------
279 * Hardware Information Block
281 #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
282 #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
283 #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
285 /*-----------------------------------------------------------------------
286 * Hard Reset Configuration Words
288 * if you change bits in the HRCW, you must also change the CFG_*
289 * defines for the various registers affected by the HRCW e.g. changing
290 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
292 #if defined(CONFIG_266MHz)
293 #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
295 #elif defined(CONFIG_300MHz)
296 #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
299 #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
302 /* no slaves so just fill with zeros */
303 #define CFG_HRCW_SLAVE1 0
304 #define CFG_HRCW_SLAVE2 0
305 #define CFG_HRCW_SLAVE3 0
306 #define CFG_HRCW_SLAVE4 0
307 #define CFG_HRCW_SLAVE5 0
308 #define CFG_HRCW_SLAVE6 0
309 #define CFG_HRCW_SLAVE7 0
311 /*-----------------------------------------------------------------------
312 * Internal Memory Mapped Register
314 #define CFG_IMMR 0xFFF00000
316 /*-----------------------------------------------------------------------
317 * Definitions for initial stack pointer and data area (in DPRAM)
319 #define CFG_INIT_RAM_ADDR CFG_IMMR
320 #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
321 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
322 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
323 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
325 /*-----------------------------------------------------------------------
326 * Start addresses for the final memory configuration
327 * (Set up by the startup code)
328 * Please note that CFG_SDRAM_BASE _must_ start at 0
330 * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
331 * is mapped at SDRAM_BASE2_PRELIM.
333 #define CFG_SDRAM_BASE 0x00000000
334 #define CFG_FLASH_BASE CFG_FLASH0_BASE
335 #define CFG_MONITOR_BASE TEXT_BASE
336 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
337 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
340 * Internal Definitions
344 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
345 #define BOOTFLAG_WARM 0x02 /* Software reboot */
348 /*-----------------------------------------------------------------------
349 * Hardware Information Block
351 #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
352 #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
353 #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
355 /*-----------------------------------------------------------------------
356 * Cache Configuration
358 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
359 #if defined(CONFIG_CMD_KGDB)
360 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
363 /*-----------------------------------------------------------------------
364 * HIDx - Hardware Implementation-dependent Registers 2-11
365 *-----------------------------------------------------------------------
366 * HID0 also contains cache control - initially enable both caches and
367 * invalidate contents, then the final state leaves only the instruction
368 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
369 * but Soft reset does not.
371 * HID1 has only read-only information - nothing to set.
373 #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
375 #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
378 /*-----------------------------------------------------------------------
379 * RMR - Reset Mode Register 5-5
380 *-----------------------------------------------------------------------
381 * turn on Checkstop Reset Enable
383 #define CFG_RMR RMR_CSRE
385 /*-----------------------------------------------------------------------
386 * BCR - Bus Configuration 4-25
387 *-----------------------------------------------------------------------
389 #ifdef CONFIG_BUSMODE_60x
390 #define CFG_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\
391 BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */
393 #define BCR_APD01 0x10000000
394 #define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
397 /*-----------------------------------------------------------------------
398 * SIUMCR - SIU Module Configuration 4-31
399 *-----------------------------------------------------------------------
402 #define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10)
404 #define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10)
408 /*-----------------------------------------------------------------------
409 * SYPCR - System Protection Control 4-35
410 * SYPCR can only be written once after reset!
411 *-----------------------------------------------------------------------
412 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
414 #if defined(CONFIG_WATCHDOG)
415 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
416 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
418 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
419 SYPCR_SWRI|SYPCR_SWP)
420 #endif /* CONFIG_WATCHDOG */
422 /*-----------------------------------------------------------------------
423 * TMCNTSC - Time Counter Status and Control 4-40
424 *-----------------------------------------------------------------------
425 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
426 * and enable Time Counter
428 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
430 /*-----------------------------------------------------------------------
431 * PISCR - Periodic Interrupt Status and Control 4-42
432 *-----------------------------------------------------------------------
433 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
436 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
438 /*-----------------------------------------------------------------------
439 * SCCR - System Clock Control 9-8
440 *-----------------------------------------------------------------------
441 * Ensure DFBRG is Divide by 16
445 /*-----------------------------------------------------------------------
446 * RCCR - RISC Controller Configuration 13-7
447 *-----------------------------------------------------------------------
452 * Init Memory Controller:
454 * Bank Bus Machine PortSz Device
455 * ---- --- ------- ------ ------
456 * 0 60x GPCM 64 bit FLASH
457 * 1 60x SDRAM 64 bit SDRAM
458 * 2 Local SDRAM 32 bit SDRAM
462 /* Initialize SDRAM on local bus
464 #define CFG_INIT_LOCAL_SDRAM
466 #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
468 /* Minimum mask to separate preliminary
469 * address ranges for CS[0:2]
471 #define CFG_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */
472 #define CFG_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */
474 #define CFG_MPTPR 0x4000
476 /*-----------------------------------------------------------------------------
477 * Address for Mode Register Set (MRS) command
478 *-----------------------------------------------------------------------------
479 * In fact, the address is rather configuration data presented to the SDRAM on
480 * its address lines. Because the address lines may be mux'ed externally either
481 * for 8 column or 9 column devices, some bits appear twice in the 8260's
484 * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length |
485 * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 |
486 * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 |
487 * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 |
488 * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 |
489 *-----------------------------------------------------------------------------
491 #define CFG_MRS_OFFS 0x00000110
496 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
501 #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\
508 /* SDRAM on TQM8260 can have either 8 or 9 columns.
509 * The number affects configuration values.
512 /* Bank 1 - 60x bus SDRAM
514 #define CFG_PSRT 0x20
515 #define CFG_LSRT 0x20
517 #define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
522 #define CFG_OR1_PRELIM CFG_OR1_8COL
525 /* SDRAM initialization values for 8-column chips
527 #define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
529 ORxS_ROWST_PBI1_A7 |\
532 #define CFG_PSDMR_8COL (PSDMR_PBI |\
533 PSDMR_SDAM_A15_IS_A5 |\
534 PSDMR_BSMA_A12_A14 |\
535 PSDMR_SDA10_PBI1_A8 |\
544 /* SDRAM initialization values for 9-column chips
546 #define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
548 ORxS_ROWST_PBI1_A5 |\
551 #define CFG_PSDMR_9COL (PSDMR_PBI |\
552 PSDMR_SDAM_A16_IS_A5 |\
553 PSDMR_BSMA_A12_A14 |\
554 PSDMR_SDA10_PBI1_A7 |\
563 /* Bank 2 - Local bus SDRAM
565 #ifdef CFG_INIT_LOCAL_SDRAM
566 #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
571 #define CFG_OR2_PRELIM CFG_OR2_8COL
573 #define SDRAM_BASE2_PRELIM 0x80000000
575 /* SDRAM initialization values for 8-column chips
577 #define CFG_OR2_8COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
579 ORxS_ROWST_PBI1_A8 |\
582 #define CFG_LSDMR_8COL (PSDMR_PBI |\
583 PSDMR_SDAM_A15_IS_A5 |\
584 PSDMR_BSMA_A13_A15 |\
585 PSDMR_SDA10_PBI1_A9 |\
594 /* SDRAM initialization values for 9-column chips
596 #define CFG_OR2_9COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
598 ORxS_ROWST_PBI1_A6 |\
601 #define CFG_LSDMR_9COL (PSDMR_PBI |\
602 PSDMR_SDAM_A16_IS_A5 |\
603 PSDMR_BSMA_A13_A15 |\
604 PSDMR_SDA10_PBI1_A8 |\
613 #endif /* CFG_INIT_LOCAL_SDRAM */
615 #endif /* CFG_RAMBOOT */
617 #define CFG_CAN0_BASE 0xc0000000
618 #define CFG_CAN1_BASE 0xc0008000
619 #define CFG_FIOX_BASE 0xc0010000
620 #define CFG_FDOHM_BASE 0xc0018000
621 #define CFG_EXTPROM_BASE 0xc2000000
623 #define CFG_CAN_SIZE 0x00000100
624 #define CFG_FIOX_SIZE 0x00000020
625 #define CFG_FDOHM_SIZE 0x00002000
626 #define CFG_EXTPROM_BANK_SIZE 0x01000000
628 #define EXT_EEPROM_MAX_FLASH_BANKS 0x02
632 #define CFG_CAN0_BR3 ((CFG_CAN0_BASE & BRx_BA_MSK) |\
637 #define CFG_CAN0_OR3 (P2SZ_TO_AM(CFG_CAN_SIZE) |\
643 #define CFG_CAN1_BR4 ((CFG_CAN1_BASE & BRx_BA_MSK) |\
648 #define CFG_CAN1_OR4 (P2SZ_TO_AM(CFG_CAN_SIZE) |\
652 /* CS5 - Extended PROM (16MB optional)
654 #define CFG_EXTPROM_BR5 ((CFG_EXTPROM_BASE & BRx_BA_MSK)|\
659 #define CFG_EXTPROM_OR5 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\
665 /* CS6 - Extended PROM (16MB optional)
667 #define CFG_EXTPROM_BR6 (((CFG_EXTPROM_BASE + \
668 CFG_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\
673 #define CFG_EXTPROM_OR6 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\
679 /* CS7 - FPGA FIOX: Glue Logic
681 #define CFG_FIOX_BR7 ((CFG_FIOX_BASE & BRx_BA_MSK) |\
686 #define CFG_FIOX_OR7 (P2SZ_TO_AM(CFG_FIOX_SIZE) |\
691 /* CS8 - FPGA DOH Master
693 #define CFG_FDOHM_BR8 ((CFG_FDOHM_BASE & BRx_BA_MSK) |\
698 #define CFG_FDOHM_OR8 (P2SZ_TO_AM(CFG_FDOHM_SIZE) |\
704 /* FPGA configuration */
705 #define CFG_PD_FIOX_PROG (1 << (31- 5)) /* PD 5 */
706 #define CFG_PD_FIOX_DONE (1 << (31-28)) /* PD 28 */
707 #define CFG_PD_FIOX_INIT (1 << (31-29)) /* PD 29 */
709 #define CFG_PD_FDOHM_PROG (1 << (31- 4)) /* PD 4 */
710 #define CFG_PD_FDOHM_DONE (1 << (31-26)) /* PD 26 */
711 #define CFG_PD_FDOHM_INIT (1 << (31-27)) /* PD 27 */
714 #endif /* __CONFIG_H */