3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
32 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
33 #define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
34 #define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */
36 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
38 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
39 #define BOOTFLAG_WARM 0x02 /* Software reboot */
41 #define CONFIG_BOARD_EARLY_INIT_R
43 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
46 * Serial console configuration
48 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
49 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
50 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
56 #define CONFIG_BOOTP_BOOTFILESIZE
57 #define CONFIG_BOOTP_BOOTPATH
58 #define CONFIG_BOOTP_GATEWAY
59 #define CONFIG_BOOTP_HOSTNAME
63 * Command line configuration.
65 #include <config_cmd_default.h>
67 #define CONFIG_CMD_ASKENV
68 #define CONFIG_CMD_DATE
69 #define CONFIG_CMD_DHCP
70 #define CONFIG_CMD_IMMAP
71 #define CONFIG_CMD_MII
72 #define CONFIG_CMD_NFS
73 #define CONFIG_CMD_REGINFO
74 #define CONFIG_CMD_SNTP
78 * MUST be low boot - HIGHBOOT is not supported anymore
80 #if (TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */
81 # define CFG_LOWBOOT 1
82 # define CFG_LOWBOOT16 1
84 # error "TEXT_BASE must be 0xFE000000"
90 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
92 #define CONFIG_PREBOOT "echo;" \
93 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
96 #undef CONFIG_BOOTARGS
98 #define CONFIG_EXTRA_ENV_SETTINGS \
100 "nfsargs=setenv bootargs root=/dev/nfs rw " \
101 "nfsroot=${serverip}:${rootpath}\0" \
102 "ramargs=setenv bootargs root=/dev/ram rw\0" \
103 "addip=setenv bootargs ${bootargs} " \
104 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
105 ":${hostname}:${netdev}:off panic=1\0" \
106 "flash_nfs=run nfsargs addip;" \
107 "bootm ${kernel_addr}\0" \
108 "flash_self=run ramargs addip;" \
109 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
110 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
111 "rootpath=/opt/eldk/ppc_6xx\0" \
112 "bootfile=/tftpboot/canmb/uImage\0" \
115 #define CONFIG_BOOTCOMMAND "run flash_self"
118 * IPB Bus clocking configuration.
120 #undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
123 * Flash configuration, expect one 16 Megabyte Bank at most
125 #define CFG_FLASH_BASE 0xFE000000
126 #define CFG_FLASH_SIZE 0x02000000
127 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
128 #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
130 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
131 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
133 #define CONFIG_FLASH_CFI_DRIVER
134 #define CFG_FLASH_CFI
135 #define CFG_FLASH_EMPTY_INFO
138 * Environment settings
140 #define CFG_ENV_IS_IN_FLASH 1
141 #define CFG_ENV_OFFSET (2*128*1024)
142 #define CFG_ENV_SIZE 0x2000
143 #define CFG_ENV_SECT_SIZE (128*1024)
148 * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
150 #define CFG_MBAR 0xf0000000 /* DO NOT CHANGE this */
151 #define CFG_SDRAM_BASE 0x00000000
152 #define CFG_DEFAULT_MBAR 0x80000000
154 /* Use SRAM until RAM will be available */
155 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
156 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
159 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
160 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
161 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
163 #define CFG_MONITOR_BASE TEXT_BASE
164 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
165 # define CFG_RAMBOOT 1
168 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
169 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
170 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
173 * Ethernet configuration
175 #define CONFIG_MPC5xxx_FEC 1
176 #define CONFIG_PHY_ADDR 0x0
178 * GPIO configuration:
179 * PSC1,2,3 predefined as UART
181 * Ethernet 100 with MD
183 #define CFG_GPS_PORT_CONFIG 0x00058444
186 * Miscellaneous configurable options
188 #define CFG_LONGHELP /* undef to save memory */
189 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
190 #if defined(CONFIG_CMD_KGDB)
191 # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
193 # define CFG_CBSIZE 256 /* Console I/O Buffer Size */
195 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
196 #define CFG_MAXARGS 16 /* max number of command args */
197 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
199 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
200 #define CFG_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
202 #define CFG_LOAD_ADDR 0x200000 /* default load address */
204 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
206 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
208 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
209 #if defined(CONFIG_CMD_KGDB)
210 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
214 * Various low-level settings
216 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
217 #define CFG_HID0_FINAL HID0_ICE
219 #define CFG_BOOTCS_START CFG_FLASH_BASE
220 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
221 #define CFG_BOOTCS_CFG 0x00047D01
222 #define CFG_CS0_START CFG_FLASH_BASE
223 #define CFG_CS0_SIZE CFG_FLASH_SIZE
225 #define CFG_CS_BURST 0x00000000
226 #define CFG_CS_DEADCYCLE 0x33333333
228 #define CFG_RESET_ADDRESS 0x7f000000
230 #endif /* __CONFIG_H */