include/configs/kmeter1.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *                    Dave Liu <daveliu@freescale.com>
   4  *
   5  * Copyright (C) 2007 Logic Product Development, Inc.
   6  *                    Peter Barada <peterb@logicpd.com>
   7  *
   8  * Copyright (C) 2007 MontaVista Software, Inc.
   9  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  10  *
  11  * (C) Copyright 2008-2011
  12  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22
  23 /*
  24  * High Level Configuration Options
  25  */
  26 #define CONFIG_QE               /* Has QE */
  27 #define CONFIG_MPC8360          /* MPC8360 CPU specific */
  28 #define CONFIG_KMETER1          /* KMETER1 board specific */
  29 #define CONFIG_HOSTNAME         kmeter1
  30
  31 #define CONFIG_SYS_TEXT_BASE    0xF0000000
  32 #define CONFIG_KM_DEF_NETDEV    \
  33         "netdev=eth2\0"         \
  34
  35 /* include common defines/options for all Keymile boards */
  36 #include "keymile-common.h"
  37 #include "km-powerpc.h"
  38
  39 #define MTDIDS_DEFAULT          "nor0=boot"
  40 #define MTDPARTS_DEFAULT        "mtdparts="                     \
  41         "boot:"                                                 \
  42                 "768k(u-boot),"                                 \
  43                 "128k(env),"                                    \
  44                 "128k(envred),"                                 \
  45                 "-(" CONFIG_KM_UBI_PARTITION_NAME ")"
  46
  47 #define CONFIG_MISC_INIT_R
  48 /*
  49  * System Clock Setup
  50  */
  51 #define CONFIG_83XX_CLKIN               66000000
  52 #define CONFIG_SYS_CLK_FREQ             66000000
  53 #define CONFIG_83XX_PCICLK              66000000
  54
  55 /*
  56  * Hardware Reset Configuration Word
  57  */
  58 #define CONFIG_SYS_HRCW_LOW (\
  59         HRCWL_CSB_TO_CLKIN_4X1 | \
  60         HRCWL_CORE_TO_CSB_2X1 | \
  61         HRCWL_CE_PLL_VCO_DIV_2 | \
  62         HRCWL_CE_TO_PLL_1X6 )
  63
  64 #define CONFIG_SYS_HRCW_HIGH (\
  65         HRCWH_CORE_ENABLE | \
  66         HRCWH_FROM_0X00000100 | \
  67         HRCWH_BOOTSEQ_DISABLE | \
  68         HRCWH_SW_WATCHDOG_DISABLE | \
  69         HRCWH_ROM_LOC_LOCAL_16BIT | \
  70         HRCWH_BIG_ENDIAN | \
  71         HRCWH_LALE_EARLY | \
  72         HRCWH_LDP_CLEAR )
  73
  74 /*
  75  * System IO Config
  76  */
  77 #define CONFIG_SYS_SICRH                0x00000006
  78 #define CONFIG_SYS_SICRL                0x00000000
  79
  80 /*
  81  * IMMR new address
  82  */
  83 #define CONFIG_SYS_IMMR         0xE0000000
  84
  85 /*
  86  * Bus Arbitration Configuration Register (ACR)
  87  */
  88 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
  89 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
  90 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
  91 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
  92
  93 /*
  94  * DDR Setup
  95  */
  96 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  97 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  98 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  99 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
 100                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 101
 102 #define CFG_83XX_DDR_USES_CS0
 103
 104 #undef CONFIG_DDR_ECC
 105
 106 /*
 107  * DDRCDR - DDR Control Driver Register
 108  */
 109
 110 #undef CONFIG_SPD_EEPROM        /* Do not use SPD EEPROM for DDR setup */
 111
 112 /*
 113  * Manually set up DDR parameters
 114  */
 115 #define CONFIG_DDR_II
 116 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
 117 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 118 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 119                                         CSCONFIG_ROW_BIT_13 | \
 120                                         CSCONFIG_COL_BIT_10 | \
 121                                         CSCONFIG_ODT_WR_ACS)
 122
 123 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 124                                          SDRAM_CFG_SREN)
 125 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 126 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 127 #define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 128                                  (0x3cf << SDRAM_INTERVAL_REFINT_SHIFT))
 129
 130 #define CONFIG_SYS_DDRCDR               0x40000001
 131 #define CONFIG_SYS_DDR_MODE             0x47860452
 132 #define CONFIG_SYS_DDR_MODE2            0x8080c000
 133
 134 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 135                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 136                                  (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 137                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 138                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 139                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 140                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 141                                  (0 << TIMING_CFG0_RWT_SHIFT))
 142
 143 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
 144                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 145                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 146                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 147                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 148                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 149                                  (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 150                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 151
 152 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 153                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 154                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 155                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 156                                  (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 157                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 158                                  (5 << TIMING_CFG2_CPO_SHIFT))
 159
 160 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 161
 162 /*
 163  * The reserved memory
 164  */
 165 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 166 #define CONFIG_SYS_FLASH_BASE           0xF0000000
 167 #define CONFIG_SYS_PIGGY_BASE           0xE8000000
 168 #define CONFIG_SYS_PIGGY_SIZE           128
 169 #define CONFIG_SYS_PAXE_BASE            0xA0000000
 170 #define CONFIG_SYS_PAXE_SIZE            512
 171
 172 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 173 #define CONFIG_SYS_RAMBOOT
 174 #else
 175 #undef  CONFIG_SYS_RAMBOOT
 176 #endif
 177
 178 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024) /* Reserve for Mon */
 179
 180 /*
 181  * Initial RAM Base Address Setup
 182  */
 183 #define CONFIG_SYS_INIT_RAM_LOCK        1
 184 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 185 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 186 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 187                                         GENERATED_GBL_DATA_SIZE)
 188
 189 /*
 190  * Local Bus Configuration & Clock Setup
 191  */
 192 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 193 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_2
 194 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 195
 196 /*
 197  * Init Local Bus Memory Controller:
 198  *
 199  * Bank Bus     Machine PortSz  Size  Device
 200  * ---- ---     ------- ------  -----  ------
 201  *  0   Local   GPCM    16 bit  256MB FLASH
 202  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 203  *  3   Local   GPCM     8 bit  512MB PAXE
 204  *
 205  */
 206 /*
 207  * FLASH on the Local Bus
 208  */
 209 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 210 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 211 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 212 #define CONFIG_SYS_FLASH_PROTECTION     1
 213 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 214
 215 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 216 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x8000001b /* 256MB window size */
 217
 218 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
 219                                 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 220                                 BR_V)
 221
 222 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
 223                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 224                                 OR_GPCM_SCY_5 | \
 225                                 OR_GPCM_TRLX | OR_GPCM_EAD)
 226
 227 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks */
 228 /* max num of sects on one chip */
 229 #define CONFIG_SYS_MAX_FLASH_SECT       512
 230 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 231
 232 #undef  CONFIG_SYS_FLASH_CHECKSUM
 233
 234 /*
 235  * PRIO1/PIGGY on the local bus CS1
 236  */
 237 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_PIGGY_BASE
 238 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000001A /* 128MB window size */
 239
 240 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_PIGGY_BASE | \
 241                                 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
 242                                 BR_V)
 243 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | \
 244                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 245                                 OR_GPCM_SCY_2 | \
 246                                 OR_GPCM_TRLX | OR_GPCM_EAD)
 247
 248 /*
 249  * PAXE on the local bus CS3
 250  */
 251 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_PAXE_BASE
 252 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000001C /* 512MB window size */
 253
 254 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_PAXE_BASE | \
 255                                 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
 256                                 BR_V)
 257 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
 258                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 259                                 OR_GPCM_SCY_2 | \
 260                                 OR_GPCM_TRLX | OR_GPCM_EAD)
 261
 262 /*
 263  * Serial Port
 264  */
 265 #define CONFIG_CONS_INDEX       1
 266 #define CONFIG_SYS_NS16550
 267 #define CONFIG_SYS_NS16550_SERIAL
 268 #define CONFIG_SYS_NS16550_REG_SIZE     1
 269 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 270
 271 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 272 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 273
 274 /* Pass open firmware flat tree */
 275 #define CONFIG_OF_LIBFDT
 276 #define CONFIG_OF_BOARD_SETUP
 277 #define CONFIG_OF_STDOUT_VIA_ALIAS
 278
 279 /*
 280  * General PCI
 281  * Addresses are mapped 1-1.
 282  */
 283 #undef CONFIG_PCI               /* No PCI */
 284
 285 #ifndef CONFIG_NET_MULTI
 286 #define CONFIG_NET_MULTI
 287 #endif
 288 /*
 289  * QE UEC ethernet configuration
 290  */
 291 #define CONFIG_UEC_ETH
 292 #define CONFIG_ETHPRIME         "UEC0"
 293
 294 #define CONFIG_UEC_ETH1         /* GETH1 */
 295 #define UEC_VERBOSE_DEBUG       1
 296
 297 #ifdef CONFIG_UEC_ETH1
 298 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 299 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII */
 300 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 301 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 302 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 303 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 304 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 305 #endif
 306
 307 /*
 308  * Environment
 309  */
 310
 311 #ifndef CONFIG_SYS_RAMBOOT
 312 #define CONFIG_ENV_IS_IN_FLASH  1
 313 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 314                                 CONFIG_SYS_MONITOR_LEN)
 315 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 316 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 317
 318 /* Address and size of Redundant Environment Sector     */
 319 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 320                                         CONFIG_ENV_SECT_SIZE)
 321 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 322
 323 #else /* CFG_RAMBOOT */
 324 #define CONFIG_SYS_NO_FLASH     /* Flash is not usable now */
 325 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
 326 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 327 #define CONFIG_ENV_SIZE         0x2000
 328 #endif /* CFG_RAMBOOT */
 329
 330 /* I2C */
 331 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 332 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 333 #define CONFIG_FSL_I2C
 334 #define CONFIG_SYS_I2C_SPEED    200000  /* I2C speed and slave address */
 335 #define CONFIG_SYS_I2C_SLAVE    0x7F
 336 #define CONFIG_SYS_I2C_OFFSET   0x3000
 337 #define CONFIG_I2C_MULTI_BUS    1
 338 #define CONFIG_I2C_MUX          1
 339
 340 /* EEprom support */
 341 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 342
 343 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
 344 #define CONFIG_DTT_LM75         /* ON Semi's LM75 */
 345 #define CONFIG_DTT_SENSORS      {0, 1, 2, 3}    /* Sensor addresses */
 346 #define CONFIG_SYS_DTT_MAX_TEMP 70
 347 #define CONFIG_SYS_DTT_LOW_TEMP -30
 348 #define CONFIG_SYS_DTT_HYSTERESIS       3
 349 #define CONFIG_SYS_DTT_BUS_NUM          (CONFIG_SYS_MAX_I2C_BUS)
 350
 351 #if defined(CONFIG_CMD_NAND)
 352 #define CONFIG_NAND_KMETER1
 353 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 354 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_PIGGY_BASE
 355 #endif
 356
 357 #if defined(CONFIG_PCI)
 358 #define CONFIG_CMD_PCI
 359 #endif
 360
 361 #if defined(CFG_RAMBOOT)
 362 #undef CONFIG_CMD_SAVEENV
 363 #undef CONFIG_CMD_LOADS
 364 #endif
 365
 366 /*
 367  * For booting Linux, the board info and command line data
 368  * have to be in the first 256 MB of memory, since this is
 369  * the maximum mapped by the Linux kernel during initialization.
 370  */
 371 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 372
 373 /*
 374  * Core HID Setup
 375  */
 376 #define CONFIG_SYS_HID0_INIT            0x000000000
 377 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 378                                          HID0_ENABLE_INSTRUCTION_CACHE)
 379 #define CONFIG_SYS_HID2                 HID2_HBE
 380
 381 /*
 382  * MMU Setup
 383  */
 384
 385 #define CONFIG_HIGH_BATS        /* High BATs supported */
 386
 387 /* DDR: cache cacheable */
 388 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
 389                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 390 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
 391                                 BATU_VS | BATU_VP)
 392 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 393 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 394
 395 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 396 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_10 | \
 397                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 398 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | \
 399                                 BATU_VP)
 400 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 401 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 402
 403 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
 404 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
 405                                 BATL_MEMCOHERENCE)
 406 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | \
 407                                 BATU_VS | BATU_VP)
 408 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
 409                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 410 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 411
 412 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 413 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 414                                 BATL_MEMCOHERENCE)
 415 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
 416                                 BATU_VS | BATU_VP)
 417 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 418                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 419 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 420
 421 /* Stack in dcache: cacheable, no memory coherence */
 422 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
 423 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 424                                 BATU_VS | BATU_VP)
 425 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 426 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 427
 428 /* PAXE:  icache cacheable, but dcache-inhibit and guarded */
 429 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
 430                                 BATL_MEMCOHERENCE)
 431 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | \
 432                                 BATU_VS | BATU_VP)
 433 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
 434                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 435 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 436
 437 #ifdef CONFIG_PCI
 438 /* PCI MEM space: cacheable */
 439 #define CFG_IBAT6L      (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 440 #define CFG_IBAT6U      (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 441 #define CFG_DBAT6L      CFG_IBAT6L
 442 #define CFG_DBAT6U      CFG_IBAT6U
 443 /* PCI MMIO space: cache-inhibit and guarded */
 444 #define CFG_IBAT7L      (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
 445                          BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 446 #define CFG_IBAT7U      (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 447 #define CFG_DBAT7L      CFG_IBAT7L
 448 #define CFG_DBAT7U      CFG_IBAT7U
 449 #else /* CONFIG_PCI */
 450 #define CONFIG_SYS_IBAT6L       (0)
 451 #define CONFIG_SYS_IBAT6U       (0)
 452 #define CONFIG_SYS_IBAT7L       (0)
 453 #define CONFIG_SYS_IBAT7U       (0)
 454 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 455 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 456 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 457 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 458 #endif /* CONFIG_PCI */
 459
 460 #define BOOTFLASH_START F0000000
 461
 462 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 463
 464 /*
 465  * Environment Configuration
 466  */
 467 #define CONFIG_ENV_OVERWRITE
 468 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 469 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 470 #endif
 471
 472 #define CONFIG_EXTRA_ENV_SETTINGS \
 473        CONFIG_KM_DEF_ENV                                                \
 474         "dtt_bus=pca9547:70:a\0"                                        \
 475         "EEprom_ivm=pca9547:70:9\0"                                     \
 476         "newenv="                                                       \
 477                 "prot off 0xF00C0000 +0x40000 && "                      \
 478                 "era 0xF00C0000 +0x40000\0"                             \
 479         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
 480         "unlock=yes\0"                                                  \
 481         ""
 482
 483 #if defined(CONFIG_UEC_ETH)
 484 #define CONFIG_HAS_ETH0
 485 #endif
 486
 487 #endif /* __CONFIG_H */