include/configs/ls2085a_common.h

   1 /*
   2  * Copyright (C) 2014 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS2_COMMON_H
   8 #define __LS2_COMMON_H
   9
  10 #define CONFIG_SYS_GENERIC_BOARD
  11
  12 #define CONFIG_REMAKE_ELF
  13 #define CONFIG_FSL_LSCH3
  14 #define CONFIG_LS2085A
  15 #define CONFIG_GICV3
  16
  17 /* Link Definitions */
  18 #define CONFIG_SYS_TEXT_BASE            0x30000000
  19
  20 #ifdef CONFIG_EMU
  21 #define CONFIG_SYS_NO_FLASH
  22 #endif
  23
  24 #define CONFIG_SUPPORT_RAW_INITRD
  25
  26 #define CONFIG_SKIP_LOWLEVEL_INIT
  27 #define CONFIG_BOARD_EARLY_INIT_F       1
  28
  29 #define CONFIG_IDENT_STRING             " LS2085A-EMU"
  30 #define CONFIG_BOOTP_VCI_STRING         "U-boot.LS2085A-EMU"
  31
  32 /* Flat Device Tree Definitions */
  33 #define CONFIG_OF_LIBFDT
  34 #define CONFIG_OF_BOARD_SETUP
  35
  36 /* new uImage format support */
  37 #define CONFIG_FIT
  38 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
  39
  40 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  41 #ifndef CONFIG_SYS_FSL_DDR4
  42 #define CONFIG_SYS_FSL_DDR3             /* Use DDR3 memory */
  43 #define CONFIG_SYS_DDR_RAW_TIMING
  44 #endif
  45 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  46 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  47
  48 #define CONFIG_SYS_FSL_DDR_INTLV_256B   /* force 256 byte interleaving */
  49
  50 /* SMP Definitions */
  51 #define CPU_RELEASE_ADDR                CONFIG_SYS_INIT_SP_ADDR
  52
  53 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  54 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
  55 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  56 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x8080000000ULL
  57
  58 /* Generic Timer Definitions */
  59 #define COUNTER_FREQUENCY               12000000        /* 12MHz */
  60
  61 /* Size of malloc() pool */
  62 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 128 * 1024)
  63
  64 /* I2C */
  65 #define CONFIG_CMD_I2C
  66 #define CONFIG_SYS_I2C
  67 #define CONFIG_SYS_I2C_MXC
  68 #define CONFIG_SYS_MXC_I2C1_SPEED       40000000
  69 #define CONFIG_SYS_MXC_I2C2_SPEED       40000000
  70
  71 /* Serial Port */
  72 #define CONFIG_CONS_INDEX       2
  73 #define CONFIG_SYS_NS16550
  74 #define CONFIG_SYS_NS16550_SERIAL
  75 #define CONFIG_SYS_NS16550_REG_SIZE     1
  76 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
  77
  78 #define CONFIG_BAUDRATE                 115200
  79 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  80
  81 /* IFC */
  82 #define CONFIG_FSL_IFC
  83 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  84 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
  85 /*
  86  * During booting, CS0 needs to be at the region of 0x30000000, i.e. the IFC
  87  * address 0. But this region is limited to 256MB. To accommodate bigger NOR
  88  * flash and other devices, we will map CS0 to 0x580000000 after relocation.
  89  * CONFIG_SYS_FLASH_BASE has the final address (core view)
  90  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  91  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  92  * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
  93  */
  94 #define CONFIG_SYS_FLASH_BASE                   0x580000000ULL
  95 #define CONFIG_SYS_FLASH_BASE_PHYS              0x80000000
  96 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
  97
  98 /*
  99  * NOR Flash Timing Params
 100  */
 101 #define CONFIG_SYS_NOR0_CSPR                                    \
 102         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
 103         CSPR_PORT_SIZE_16                                       | \
 104         CSPR_MSEL_NOR                                           | \
 105         CSPR_V)
 106 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
 107         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
 108         CSPR_PORT_SIZE_16                                       | \
 109         CSPR_MSEL_NOR                                           | \
 110         CSPR_V)
 111 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
 112 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x1) | \
 113                                 FTIM0_NOR_TEADC(0x1) | \
 114                                 FTIM0_NOR_TEAHC(0x1))
 115 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x1) | \
 116                                 FTIM1_NOR_TRAD_NOR(0x1))
 117 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x0) | \
 118                                 FTIM2_NOR_TCH(0x0) | \
 119                                 FTIM2_NOR_TWP(0x1))
 120 #define CONFIG_SYS_NOR_FTIM3    0x04000000
 121 #define CONFIG_SYS_IFC_CCR      0x01000000
 122
 123 #ifndef CONFIG_SYS_NO_FLASH
 124 #define CONFIG_FLASH_CFI_DRIVER
 125 #define CONFIG_SYS_FLASH_CFI
 126 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 127 #define CONFIG_SYS_FLASH_QUIET_TEST
 128 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 129
 130 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 131 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 132 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 133 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 134
 135 #define CONFIG_SYS_FLASH_EMPTY_INFO
 136 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 137 #endif
 138
 139 #define CONFIG_NAND_FSL_IFC
 140 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 141 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 142 #define CONFIG_SYS_NAND_BASE            0x520000000
 143 #define CONFIG_SYS_NAND_BASE_PHYS       0x20000000
 144
 145 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 146 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 147                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 148                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 149                                 | CSPR_V)
 150 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 151
 152 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 153                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 154                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 155                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 156                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 157                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 158                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 159
 160 #define CONFIG_SYS_NAND_ONFI_DETECTION
 161
 162 /* ONFI NAND Flash mode0 Timing Params */
 163 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 164                                         FTIM0_NAND_TWP(0x18)   | \
 165                                         FTIM0_NAND_TWCHT(0x07) | \
 166                                         FTIM0_NAND_TWH(0x0a))
 167 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 168                                         FTIM1_NAND_TWBE(0x39)  | \
 169                                         FTIM1_NAND_TRR(0x0e)   | \
 170                                         FTIM1_NAND_TRP(0x18))
 171 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 172                                         FTIM2_NAND_TREH(0x0a) | \
 173                                         FTIM2_NAND_TWHRE(0x1e))
 174 #define CONFIG_SYS_NAND_FTIM3           0x0
 175
 176 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 177 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 178 #define CONFIG_MTD_NAND_VERIFY_WRITE
 179 #define CONFIG_CMD_NAND
 180
 181 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 182
 183 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 184 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 185 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 186 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 187 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 188 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 189 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 190 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 191 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 192
 193 /* MC firmware */
 194 #define CONFIG_FSL_MC_ENET
 195 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE    (512UL * 1024 * 1024)
 196 #define CONFIG_SYS_LS_MC_FW_IN_NOR
 197 #define CONFIG_SYS_LS_MC_FW_ADDR        0x580200000ULL
 198 /* TODO Actual FW length needs to be determined at runtime from FW header */
 199 #define CONFIG_SYS_LS_MC_FW_LENGTH      (4U * 1024 * 1024)
 200 #define CONFIG_SYS_LS_MC_DPL_IN_NOR
 201 #define CONFIG_SYS_LS_MC_DPL_ADDR       0x5806C0000ULL
 202 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
 203 #define CONFIG_SYS_LS_MC_DPL_LENGTH     4096
 204 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0xe00000
 205
 206 /* Carve the MC private DRAM block from the end of DRAM */
 207 #ifdef CONFIG_FSL_MC_ENET
 208 #define CONFIG_SYS_MEM_TOP_HIDE         mc_get_dram_block_size()
 209 #endif
 210
 211 /* Command line configuration */
 212 #define CONFIG_CMD_CACHE
 213 #define CONFIG_CMD_BDI
 214 #define CONFIG_CMD_DHCP
 215 #define CONFIG_CMD_ENV
 216 #define CONFIG_CMD_FLASH
 217 #define CONFIG_CMD_IMI
 218 #define CONFIG_CMD_MEMORY
 219 #define CONFIG_CMD_MII
 220 #define CONFIG_CMD_NET
 221 #define CONFIG_CMD_PING
 222 #define CONFIG_CMD_SAVEENV
 223 #define CONFIG_CMD_RUN
 224 #define CONFIG_CMD_BOOTD
 225 #define CONFIG_CMD_ECHO
 226 #define CONFIG_CMD_SOURCE
 227 #define CONFIG_CMD_FAT
 228 #define CONFIG_DOS_PARTITION
 229
 230 /* Miscellaneous configurable options */
 231 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
 232
 233 /* Physical Memory Map */
 234 /* fixme: these need to be checked against the board */
 235 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 236 #define CONFIG_SYS_CLK_FREQ     133333333
 237
 238
 239 #define CONFIG_NR_DRAM_BANKS            2
 240
 241 #define CONFIG_SYS_HZ                   1000
 242
 243 #define CONFIG_HWCONFIG
 244 #define HWCONFIG_BUFFER_SIZE            128
 245
 246 #define CONFIG_DISPLAY_CPUINFO
 247
 248 /* Initial environment variables */
 249 #define CONFIG_EXTRA_ENV_SETTINGS               \
 250         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 251         "loadaddr=0x80100000\0"                 \
 252         "kernel_addr=0x100000\0"                \
 253         "ramdisk_addr=0x800000\0"               \
 254         "ramdisk_size=0x2000000\0"              \
 255         "fdt_high=0xffffffffffffffff\0"         \
 256         "initrd_high=0xffffffffffffffff\0"      \
 257         "kernel_start=0x581200000\0"            \
 258         "kernel_load=0x806f0000\0"              \
 259         "kernel_size=0x1000000\0"               \
 260         "console=ttyAMA0,38400n8\0"
 261
 262 #define CONFIG_BOOTARGS                 "console=ttyS1,115200 root=/dev/ram0 " \
 263                                         "earlyprintk=uart8250-8bit,0x21c0600"
 264 #define CONFIG_BOOTCOMMAND              "cp.b $kernel_start $kernel_load "     \
 265                                         "$kernel_size && bootm $kernel_load"
 266 #define CONFIG_BOOTDELAY                1
 267
 268 /* Store environment at top of flash */
 269 #define CONFIG_ENV_IS_NOWHERE           1
 270 #define CONFIG_ENV_SIZE                 0x1000
 271
 272 /* Monitor Command Prompt */
 273 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 274 #define CONFIG_SYS_PROMPT               "> "
 275 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 276                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 277 #define CONFIG_SYS_HUSH_PARSER
 278 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 279 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot args buffer */
 280 #define CONFIG_SYS_LONGHELP
 281 #define CONFIG_CMDLINE_EDITING          1
 282 #define CONFIG_SYS_MAXARGS              64      /* max command args */
 283
 284 #ifndef __ASSEMBLY__
 285 unsigned long mc_get_dram_block_size(void);
 286 #endif
 287
 288 #endif /* __LS2_COMMON_H */