2 * esd vme8349 U-Boot configuration file
3 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
5 * (C) Copyright 2006-2010
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * reinhard.arlt@esd-electronics.de
9 * Based on the MPC8349EMDS config.
11 * SPDX-License-Identifier: GPL-2.0+
15 * vme8349 board configuration file.
22 * Top level Makefile configuration choices
29 * High Level Configuration Options
31 #define CONFIG_E300 1 /* E300 Family */
32 #define CONFIG_MPC83xx 1 /* MPC83xx family */
33 #define CONFIG_MPC834x 1 /* MPC834x family */
34 #define CONFIG_MPC8349 1 /* MPC8349 specific */
35 #define CONFIG_VME8349 1 /* ESD VME8349 board specific */
37 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
39 #define CONFIG_MISC_INIT_R
42 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
43 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
45 #define CONFIG_PCI_66M
47 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
49 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */
52 #ifndef CONFIG_SYS_CLK_FREQ
54 #define CONFIG_SYS_CLK_FREQ 66000000
55 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
57 #define CONFIG_SYS_CLK_FREQ 33000000
58 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
62 #define CONFIG_SYS_IMMR 0xE0000000
64 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
65 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
66 #define CONFIG_SYS_MEMTEST_END 0x00100000
71 #define CONFIG_DDR_ECC /* only for ECC DDR module */
72 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
73 #define CONFIG_SPD_EEPROM
74 #define SPD_EEPROM_ADDRESS 0x54
75 #define CONFIG_SYS_READ_SPD vme8349_read_spd
76 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
79 * 32-bit data path mode.
81 * Please note that using this mode for devices with the real density of 64-bit
82 * effectively reduces the amount of available memory due to the effect of
83 * wrapping around while translating address to row/columns, for example in the
84 * 256MB module the upper 128MB get aliased with contents of the lower
85 * 128MB); normally this define should be used for devices with real 32-bit
88 #undef CONFIG_DDR_32BIT
90 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
91 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
92 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
93 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
94 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
95 #define CONFIG_DDR_2T_TIMING
96 #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
102 * FLASH on the Local Bus
104 #define CONFIG_SYS_FLASH_CFI
105 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
107 #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
108 #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
109 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
110 BR_PS_16 | /* 16bit */ \
111 BR_MS_GPCM | /* MSEL = GPCM */ \
114 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
124 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
125 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB)
127 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
128 #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
129 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
130 BR_PS_16 | /* 16bit */ \
131 BR_MS_GPCM | /* MSEL = GPCM */ \
134 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
144 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
145 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
147 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
149 #define CONFIG_SYS_WINDOW1_BASE 0xf0000000
150 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \
155 #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \
158 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE
159 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
161 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
162 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
164 #undef CONFIG_SYS_FLASH_CHECKSUM
165 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
166 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
168 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
170 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
171 #define CONFIG_SYS_RAMBOOT
173 #undef CONFIG_SYS_RAMBOOT
176 #define CONFIG_SYS_INIT_RAM_LOCK 1
177 #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
178 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
180 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
181 GENERATED_GBL_DATA_SIZE)
182 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
184 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
185 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
188 * Local Bus LCRR and LBCR regs
189 * LCRR: no DLL bypass, Clock divider is 4
190 * External Local Bus rate is
191 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
193 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
194 #define CONFIG_SYS_LBC_LBCR 0x00000000
196 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
201 #define CONFIG_CONS_INDEX 1
202 #define CONFIG_SYS_NS16550
203 #define CONFIG_SYS_NS16550_SERIAL
204 #define CONFIG_SYS_NS16550_REG_SIZE 1
205 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
207 #define CONFIG_SYS_BAUDRATE_TABLE \
208 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
210 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
211 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
213 #define CONFIG_CMDLINE_EDITING /* add command line history */
214 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
215 /* Use the HUSH parser */
216 #define CONFIG_SYS_HUSH_PARSER
218 /* pass open firmware flat tree */
219 #define CONFIG_OF_LIBFDT
220 #define CONFIG_OF_BOARD_SETUP
221 #define CONFIG_OF_STDOUT_VIA_ALIAS
224 #define CONFIG_I2C_MULTI_BUS
225 #define CONFIG_HARD_I2C /* I2C with hardware support*/
226 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
227 #define CONFIG_FSL_I2C
228 #define CONFIG_I2C_CMD_TREE
229 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
230 #define CONFIG_SYS_I2C_SLAVE 0x7F
231 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
232 #define CONFIG_SYS_I2C1_OFFSET 0x3000
233 #define CONFIG_SYS_I2C2_OFFSET 0x3100
234 #define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET
235 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
237 #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
240 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
241 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
242 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
243 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
247 * Addresses are mapped 1-1.
249 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
250 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
251 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
252 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
253 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
254 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
255 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
256 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
257 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
259 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
260 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
261 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
262 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
263 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
264 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
265 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
266 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
267 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
269 #if defined(CONFIG_PCI)
273 #if defined(PCI_64BIT)
281 #define CONFIG_PCI_PNP /* do pci plug-and-play */
283 #undef CONFIG_EEPRO100
286 #if !defined(CONFIG_PCI_PNP)
287 #define PCI_ENET0_IOADDR 0xFIXME
288 #define PCI_ENET0_MEMADDR 0xFIXME
289 #define PCI_IDSEL_NUMBER 0xFIXME
292 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
293 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
295 #endif /* CONFIG_PCI */
303 #define CONFIG_TSEC_ENET /* TSEC ethernet support */
306 #if defined(CONFIG_TSEC_ENET)
308 #define CONFIG_GMII /* MII PHY management */
310 #define CONFIG_TSEC1_NAME "TSEC0"
312 #define CONFIG_TSEC2_NAME "TSEC1"
313 #define CONFIG_PHY_M88E1111
314 #define TSEC1_PHY_ADDR 0x08
315 #define TSEC2_PHY_ADDR 0x10
316 #define TSEC1_PHYIDX 0
317 #define TSEC2_PHYIDX 0
318 #define TSEC1_FLAGS TSEC_GIGABIT
319 #define TSEC2_FLAGS TSEC_GIGABIT
321 /* Options are: TSEC[0-1] */
322 #define CONFIG_ETHPRIME "TSEC0"
324 #endif /* CONFIG_TSEC_ENET */
329 #ifndef CONFIG_SYS_RAMBOOT
330 #define CONFIG_ENV_IS_IN_FLASH
331 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
332 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
333 #define CONFIG_ENV_SIZE 0x2000
335 /* Address and size of Redundant Environment Sector */
336 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
337 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
340 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
341 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
342 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
343 #define CONFIG_ENV_SIZE 0x2000
346 #define CONFIG_LOADS_ECHO /* echo on for serial download */
347 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
352 #define CONFIG_BOOTP_BOOTFILESIZE
353 #define CONFIG_BOOTP_BOOTPATH
354 #define CONFIG_BOOTP_GATEWAY
355 #define CONFIG_BOOTP_HOSTNAME
358 * Command line configuration.
360 #include <config_cmd_default.h>
362 #define CONFIG_CMD_I2C
363 #define CONFIG_CMD_MII
364 #define CONFIG_CMD_PING
365 #define CONFIG_CMD_DATE
366 #define CONFIG_SYS_RTC_BUS_NUM 0x01
367 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
368 #define CONFIG_RTC_RX8025
369 #define CONFIG_CMD_TSI148
371 #if defined(CONFIG_PCI)
372 #define CONFIG_CMD_PCI
375 #if defined(CONFIG_SYS_RAMBOOT)
376 #undef CONFIG_CMD_ENV
377 #undef CONFIG_CMD_LOADS
380 #define CONFIG_CMD_ELF
381 /* Pass Ethernet MAC to VxWorks */
382 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
384 #undef CONFIG_WATCHDOG /* watchdog disabled */
387 * Miscellaneous configurable options
389 #define CONFIG_SYS_LONGHELP /* undef to save memory */
390 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
391 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
393 #if defined(CONFIG_CMD_KGDB)
394 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
396 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
399 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
400 #define CONFIG_SYS_MAXARGS 16 /* max num of command args */
401 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */
402 #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
405 * For booting Linux, the board info and command line data
406 * have to be in the first 256 MB of memory, since this is
407 * the maximum mapped by the Linux kernel during initialization.
409 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
411 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
413 #define CONFIG_SYS_HRCW_LOW (\
414 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
415 HRCWL_DDR_TO_SCB_CLK_1X1 |\
416 HRCWL_CSB_TO_CLKIN |\
418 HRCWL_CORE_TO_CSB_2X1)
420 #if defined(PCI_64BIT)
421 #define CONFIG_SYS_HRCW_HIGH (\
424 HRCWH_PCI1_ARBITER_ENABLE |\
425 HRCWH_PCI2_ARBITER_DISABLE |\
427 HRCWH_FROM_0X00000100 |\
428 HRCWH_BOOTSEQ_DISABLE |\
429 HRCWH_SW_WATCHDOG_DISABLE |\
430 HRCWH_ROM_LOC_LOCAL_16BIT |\
431 HRCWH_TSEC1M_IN_GMII |\
432 HRCWH_TSEC2M_IN_GMII)
434 #define CONFIG_SYS_HRCW_HIGH (\
437 HRCWH_PCI1_ARBITER_ENABLE |\
438 HRCWH_PCI2_ARBITER_ENABLE |\
440 HRCWH_FROM_0X00000100 |\
441 HRCWH_BOOTSEQ_DISABLE |\
442 HRCWH_SW_WATCHDOG_DISABLE |\
443 HRCWH_ROM_LOC_LOCAL_16BIT |\
444 HRCWH_TSEC1M_IN_GMII |\
445 HRCWH_TSEC2M_IN_GMII)
448 /* System IO Config */
449 #define CONFIG_SYS_SICRH 0
450 #define CONFIG_SYS_SICRL SICRL_LDP_A
452 #define CONFIG_SYS_HID0_INIT 0x000000000
453 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
454 HID0_ENABLE_INSTRUCTION_CACHE)
456 #define CONFIG_SYS_HID2 HID2_HBE
458 #define CONFIG_SYS_GPIO1_PRELIM
459 #define CONFIG_SYS_GPIO1_DIR 0x00100000
460 #define CONFIG_SYS_GPIO1_DAT 0x00100000
462 #define CONFIG_SYS_GPIO2_PRELIM
463 #define CONFIG_SYS_GPIO2_DIR 0x78900000
464 #define CONFIG_SYS_GPIO2_DAT 0x70100000
466 #define CONFIG_HIGH_BATS /* High BATs supported */
468 /* DDR @ 0x00000000 */
469 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
471 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
474 /* PCI @ 0x80000000 */
476 #define CONFIG_PCI_INDIRECT_BRIDGE
477 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
479 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
481 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
482 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
483 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
486 #define CONFIG_SYS_IBAT1L (0)
487 #define CONFIG_SYS_IBAT1U (0)
488 #define CONFIG_SYS_IBAT2L (0)
489 #define CONFIG_SYS_IBAT2U (0)
492 #ifdef CONFIG_MPC83XX_PCI2
493 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
495 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
497 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
498 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
499 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
502 #define CONFIG_SYS_IBAT3L (0)
503 #define CONFIG_SYS_IBAT3U (0)
504 #define CONFIG_SYS_IBAT4L (0)
505 #define CONFIG_SYS_IBAT4U (0)
508 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
509 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \
510 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
511 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
514 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
515 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
517 #if (CONFIG_SYS_DDR_SIZE == 512)
518 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
519 BATL_PP_RW | BATL_MEMCOHERENCE)
520 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
521 BATU_BL_256M | BATU_VS | BATU_VP)
523 #define CONFIG_SYS_IBAT7L (0)
524 #define CONFIG_SYS_IBAT7U (0)
527 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
528 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
529 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
530 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
531 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
532 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
533 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
534 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
535 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
536 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
537 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
538 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
539 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
540 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
541 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
542 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
544 #if defined(CONFIG_CMD_KGDB)
545 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
546 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
550 * Environment Configuration
552 #define CONFIG_ENV_OVERWRITE
554 #if defined(CONFIG_TSEC_ENET)
555 #define CONFIG_HAS_ETH0
556 #define CONFIG_HAS_ETH1
559 #define CONFIG_HOSTNAME VME8349
560 #define CONFIG_ROOTPATH "/tftpboot/rootfs"
561 #define CONFIG_BOOTFILE "uImage"
563 #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
565 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
566 #undef CONFIG_BOOTARGS /* boot command will set bootargs */
568 #define CONFIG_BAUDRATE 9600
570 #define CONFIG_EXTRA_ENV_SETTINGS \
572 "hostname=vme8349\0" \
573 "nfsargs=setenv bootargs root=/dev/nfs rw " \
574 "nfsroot=${serverip}:${rootpath}\0" \
575 "ramargs=setenv bootargs root=/dev/ram rw\0" \
576 "addip=setenv bootargs ${bootargs} " \
577 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
578 ":${hostname}:${netdev}:off panic=1\0" \
579 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
580 "flash_nfs=run nfsargs addip addtty;" \
581 "bootm ${kernel_addr}\0" \
582 "flash_self=run ramargs addip addtty;" \
583 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
584 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
586 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
587 "update=protect off fff00000 fff3ffff; " \
588 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
589 "upd=run load update\0" \
591 "fdtfile=vme8349.dtb\0" \
594 #define CONFIG_NFSBOOTCOMMAND \
595 "setenv bootargs root=/dev/nfs rw " \
596 "nfsroot=$serverip:$rootpath " \
597 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
599 "console=$consoledev,$baudrate $othbootargs;" \
600 "tftp $loadaddr $bootfile;" \
601 "tftp $fdtaddr $fdtfile;" \
602 "bootm $loadaddr - $fdtaddr"
604 #define CONFIG_RAMBOOTCOMMAND \
605 "setenv bootargs root=/dev/ram rw " \
606 "console=$consoledev,$baudrate $othbootargs;" \
607 "tftp $ramdiskaddr $ramdiskfile;" \
608 "tftp $loadaddr $bootfile;" \
609 "tftp $fdtaddr $fdtfile;" \
610 "bootm $loadaddr $ramdiskaddr $fdtaddr"
612 #define CONFIG_BOOTCOMMAND "run flash_self"
615 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
616 unsigned char *buffer, int len);
619 #endif /* __CONFIG_H */