2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
21 #ifndef LINUX_DMAENGINE_H
22 #define LINUX_DMAENGINE_H
24 #include <linux/device.h>
25 #include <linux/uio.h>
26 #include <linux/scatterlist.h>
27 #include <linux/bitmap.h>
28 #include <linux/types.h>
32 * typedef dma_cookie_t - an opaque DMA cookie
34 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
36 typedef s32 dma_cookie_t;
37 #define DMA_MIN_COOKIE 1
38 #define DMA_MAX_COOKIE INT_MAX
40 #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
43 * enum dma_status - DMA transaction status
44 * @DMA_SUCCESS: transaction completed successfully
45 * @DMA_IN_PROGRESS: transaction not yet processed
46 * @DMA_PAUSED: transaction is paused
47 * @DMA_ERROR: transaction failed
57 * enum dma_transaction_type - DMA transaction types/indexes
59 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
60 * automatically set as dma devices are registered.
62 enum dma_transaction_type {
76 /* last transaction type for creation of the capabilities mask */
81 * enum dma_transfer_direction - dma transfer mode and direction indicator
82 * @DMA_MEM_TO_MEM: Async/Memcpy mode
83 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
84 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
85 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
87 enum dma_transfer_direction {
96 * Interleaved Transfer Request
97 * ----------------------------
98 * A chunk is collection of contiguous bytes to be transfered.
99 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
100 * ICGs may or maynot change between chunks.
101 * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
102 * that when repeated an integral number of times, specifies the transfer.
103 * A transfer template is specification of a Frame, the number of times
104 * it is to be repeated and other per-transfer attributes.
106 * Practically, a client driver would have ready a template for each
107 * type of transfer it is going to need during its lifetime and
108 * set only 'src_start' and 'dst_start' before submitting the requests.
111 * | Frame-1 | Frame-2 | ~ | Frame-'numf' |
112 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
119 * struct data_chunk - Element of scatter-gather list that makes a frame.
120 * @size: Number of bytes to read from source.
121 * size_dst := fn(op, size_src), so doesn't mean much for destination.
122 * @icg: Number of bytes to jump after last src/dst address of this
123 * chunk and before first src/dst address for next chunk.
124 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
125 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
133 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
135 * @src_start: Bus address of source for the first chunk.
136 * @dst_start: Bus address of destination for the first chunk.
137 * @dir: Specifies the type of Source and Destination.
138 * @src_inc: If the source address increments after reading from it.
139 * @dst_inc: If the destination address increments after writing to it.
140 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
141 * Otherwise, source is read contiguously (icg ignored).
142 * Ignored if src_inc is false.
143 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
144 * Otherwise, destination is filled contiguously (icg ignored).
145 * Ignored if dst_inc is false.
146 * @numf: Number of frames in this template.
147 * @frame_size: Number of chunks in a frame i.e, size of sgl[].
148 * @sgl: Array of {chunk,icg} pairs that make up a frame.
150 struct dma_interleaved_template {
151 dma_addr_t src_start;
152 dma_addr_t dst_start;
153 enum dma_transfer_direction dir;
160 struct data_chunk sgl[0];
164 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
165 * control completion, and communicate status.
166 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
168 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
169 * acknowledges receipt, i.e. has has a chance to establish any dependency
171 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
172 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
173 * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single
174 * (if not set, do the source dma-unmapping as page)
175 * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single
176 * (if not set, do the destination dma-unmapping as page)
177 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
178 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
179 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
180 * sources that were the result of a previous operation, in the case of a PQ
181 * operation it continues the calculation with new sources
182 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
183 * on the result of this operation
185 enum dma_ctrl_flags {
186 DMA_PREP_INTERRUPT = (1 << 0),
187 DMA_CTRL_ACK = (1 << 1),
188 DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
189 DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
190 DMA_COMPL_SRC_UNMAP_SINGLE = (1 << 4),
191 DMA_COMPL_DEST_UNMAP_SINGLE = (1 << 5),
192 DMA_PREP_PQ_DISABLE_P = (1 << 6),
193 DMA_PREP_PQ_DISABLE_Q = (1 << 7),
194 DMA_PREP_CONTINUE = (1 << 8),
195 DMA_PREP_FENCE = (1 << 9),
199 * enum dma_ctrl_cmd - DMA operations that can optionally be exercised
200 * on a running channel.
201 * @DMA_TERMINATE_ALL: terminate all ongoing transfers
202 * @DMA_PAUSE: pause ongoing transfers
203 * @DMA_RESUME: resume paused transfer
204 * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers
205 * that need to runtime reconfigure the slave channels (as opposed to passing
206 * configuration data in statically from the platform). An additional
207 * argument of struct dma_slave_config must be passed in with this
209 * @FSLDMA_EXTERNAL_START: this command will put the Freescale DMA controller
210 * into external start mode.
217 FSLDMA_EXTERNAL_START,
221 * enum sum_check_bits - bit position of pq_check_flags
223 enum sum_check_bits {
229 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
230 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
231 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
233 enum sum_check_flags {
234 SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
235 SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
240 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
241 * See linux/cpumask.h
243 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
246 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
247 * @memcpy_count: transaction counter
248 * @bytes_transferred: byte counter
251 struct dma_chan_percpu {
253 unsigned long memcpy_count;
254 unsigned long bytes_transferred;
258 * struct dma_chan - devices supply DMA channels, clients use them
259 * @device: ptr to the dma device who supplies this channel, always !%NULL
260 * @cookie: last cookie value returned to client
261 * @completed_cookie: last completed cookie for this channel
262 * @chan_id: channel ID for sysfs
263 * @dev: class device for sysfs
264 * @device_node: used to add this to the device chan list
265 * @local: per-cpu pointer to a struct dma_chan_percpu
266 * @client-count: how many clients are using this channel
267 * @table_count: number of appearances in the mem-to-mem allocation table
268 * @private: private data for certain client-channel associations
271 struct dma_device *device;
273 dma_cookie_t completed_cookie;
277 struct dma_chan_dev *dev;
279 struct list_head device_node;
280 struct dma_chan_percpu __percpu *local;
287 * struct dma_chan_dev - relate sysfs device node to backing channel device
288 * @chan - driver channel device
289 * @device - sysfs device
290 * @dev_id - parent dma_device dev_id
291 * @idr_ref - reference count to gate release of dma_device dev_id
293 struct dma_chan_dev {
294 struct dma_chan *chan;
295 struct device device;
301 * enum dma_slave_buswidth - defines bus with of the DMA slave
302 * device, source or target buses
304 enum dma_slave_buswidth {
305 DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
306 DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
307 DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
308 DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
309 DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
313 * struct dma_slave_config - dma slave channel runtime config
314 * @direction: whether the data shall go in or out on this slave
315 * channel, right now. DMA_TO_DEVICE and DMA_FROM_DEVICE are
316 * legal values, DMA_BIDIRECTIONAL is not acceptable since we
317 * need to differentiate source and target addresses.
318 * @src_addr: this is the physical address where DMA slave data
319 * should be read (RX), if the source is memory this argument is
321 * @dst_addr: this is the physical address where DMA slave data
322 * should be written (TX), if the source is memory this argument
324 * @src_addr_width: this is the width in bytes of the source (RX)
325 * register where DMA data shall be read. If the source
326 * is memory this may be ignored depending on architecture.
327 * Legal values: 1, 2, 4, 8.
328 * @dst_addr_width: same as src_addr_width but for destination
329 * target (TX) mutatis mutandis.
330 * @src_maxburst: the maximum number of words (note: words, as in
331 * units of the src_addr_width member, not bytes) that can be sent
332 * in one burst to the device. Typically something like half the
333 * FIFO depth on I/O peripherals so you don't overflow it. This
334 * may or may not be applicable on memory sources.
335 * @dst_maxburst: same as src_maxburst but for destination target
337 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
338 * with 'true' if peripheral should be flow controller. Direction will be
339 * selected at Runtime.
341 * This struct is passed in as configuration data to a DMA engine
342 * in order to set up a certain channel for DMA transport at runtime.
343 * The DMA device/engine has to provide support for an additional
344 * command in the channel config interface, DMA_SLAVE_CONFIG
345 * and this struct will then be passed in as an argument to the
346 * DMA engine device_control() function.
348 * The rationale for adding configuration information to this struct
349 * is as follows: if it is likely that most DMA slave controllers in
350 * the world will support the configuration option, then make it
351 * generic. If not: if it is fixed so that it be sent in static from
352 * the platform data, then prefer to do that. Else, if it is neither
353 * fixed at runtime, nor generic enough (such as bus mastership on
354 * some CPU family and whatnot) then create a custom slave config
355 * struct and pass that, then make this config a member of that
356 * struct, if applicable.
358 struct dma_slave_config {
359 enum dma_transfer_direction direction;
362 enum dma_slave_buswidth src_addr_width;
363 enum dma_slave_buswidth dst_addr_width;
369 static inline const char *dma_chan_name(struct dma_chan *chan)
371 return dev_name(&chan->dev->device);
374 void dma_chan_cleanup(struct kref *kref);
377 * typedef dma_filter_fn - callback filter for dma_request_channel
378 * @chan: channel to be reviewed
379 * @filter_param: opaque parameter passed through dma_request_channel
381 * When this optional parameter is specified in a call to dma_request_channel a
382 * suitable channel is passed to this routine for further dispositioning before
383 * being returned. Where 'suitable' indicates a non-busy channel that
384 * satisfies the given capability mask. It returns 'true' to indicate that the
385 * channel is suitable.
387 typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
389 typedef void (*dma_async_tx_callback)(void *dma_async_param);
391 * struct dma_async_tx_descriptor - async transaction descriptor
392 * ---dma generic offload fields---
393 * @cookie: tracking cookie for this transaction, set to -EBUSY if
394 * this tx is sitting on a dependency list
395 * @flags: flags to augment operation preparation, control completion, and
397 * @phys: physical address of the descriptor
398 * @chan: target channel for this operation
399 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
400 * @callback: routine to call after this operation is complete
401 * @callback_param: general parameter to pass to the callback routine
402 * ---async_tx api specific fields---
403 * @next: at completion submit this descriptor
404 * @parent: pointer to the next level up in the dependency chain
405 * @lock: protect the parent and next pointers
407 struct dma_async_tx_descriptor {
409 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
411 struct dma_chan *chan;
412 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
413 dma_async_tx_callback callback;
414 void *callback_param;
415 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
416 struct dma_async_tx_descriptor *next;
417 struct dma_async_tx_descriptor *parent;
422 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
423 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
426 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
429 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
433 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
436 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
439 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
443 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
449 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
451 spin_lock_bh(&txd->lock);
453 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
455 spin_unlock_bh(&txd->lock);
457 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
462 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
466 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
470 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
474 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
481 * struct dma_tx_state - filled in to report the status of
483 * @last: last completed DMA cookie
484 * @used: last issued DMA cookie (i.e. the one in progress)
485 * @residue: the remaining number of bytes left to transmit
486 * on the selected transfer for states DMA_IN_PROGRESS and
487 * DMA_PAUSED if this is implemented in the driver, else 0
489 struct dma_tx_state {
496 * struct dma_device - info on the entity supplying DMA services
497 * @chancnt: how many DMA channels are supported
498 * @privatecnt: how many DMA channels are requested by dma_request_channel
499 * @channels: the list of struct dma_chan
500 * @global_node: list_head for global dma_device_list
501 * @cap_mask: one or more dma_capability flags
502 * @max_xor: maximum number of xor sources, 0 if no capability
503 * @max_pq: maximum number of PQ sources and PQ-continue capability
504 * @copy_align: alignment shift for memcpy operations
505 * @xor_align: alignment shift for xor operations
506 * @pq_align: alignment shift for pq operations
507 * @fill_align: alignment shift for memset operations
508 * @dev_id: unique device ID
509 * @dev: struct device reference for dma mapping api
510 * @device_alloc_chan_resources: allocate resources and return the
511 * number of allocated descriptors
512 * @device_free_chan_resources: release DMA channel's resources
513 * @device_prep_dma_memcpy: prepares a memcpy operation
514 * @device_prep_dma_xor: prepares a xor operation
515 * @device_prep_dma_xor_val: prepares a xor validation operation
516 * @device_prep_dma_pq: prepares a pq operation
517 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
518 * @device_prep_dma_memset: prepares a memset operation
519 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
520 * @device_prep_slave_sg: prepares a slave dma operation
521 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
522 * The function takes a buffer of size buf_len. The callback function will
523 * be called after period_len bytes have been transferred.
524 * @device_prep_interleaved_dma: Transfer expression in a generic way.
525 * @device_control: manipulate all pending operations on a channel, returns
527 * @device_tx_status: poll for transaction completion, the optional
528 * txstate parameter can be supplied with a pointer to get a
529 * struct with auxiliary transfer status information, otherwise the call
530 * will just return a simple status code
531 * @device_issue_pending: push pending transactions to hardware
535 unsigned int chancnt;
536 unsigned int privatecnt;
537 struct list_head channels;
538 struct list_head global_node;
539 dma_cap_mask_t cap_mask;
540 unsigned short max_xor;
541 unsigned short max_pq;
546 #define DMA_HAS_PQ_CONTINUE (1 << 15)
551 int (*device_alloc_chan_resources)(struct dma_chan *chan);
552 void (*device_free_chan_resources)(struct dma_chan *chan);
554 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
555 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
556 size_t len, unsigned long flags);
557 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
558 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
559 unsigned int src_cnt, size_t len, unsigned long flags);
560 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
561 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
562 size_t len, enum sum_check_flags *result, unsigned long flags);
563 struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
564 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
565 unsigned int src_cnt, const unsigned char *scf,
566 size_t len, unsigned long flags);
567 struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
568 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
569 unsigned int src_cnt, const unsigned char *scf, size_t len,
570 enum sum_check_flags *pqres, unsigned long flags);
571 struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
572 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
573 unsigned long flags);
574 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
575 struct dma_chan *chan, unsigned long flags);
576 struct dma_async_tx_descriptor *(*device_prep_dma_sg)(
577 struct dma_chan *chan,
578 struct scatterlist *dst_sg, unsigned int dst_nents,
579 struct scatterlist *src_sg, unsigned int src_nents,
580 unsigned long flags);
582 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
583 struct dma_chan *chan, struct scatterlist *sgl,
584 unsigned int sg_len, enum dma_transfer_direction direction,
585 unsigned long flags, void *context);
586 struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
587 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
588 size_t period_len, enum dma_transfer_direction direction,
590 struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
591 struct dma_chan *chan, struct dma_interleaved_template *xt,
592 unsigned long flags);
593 int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
596 enum dma_status (*device_tx_status)(struct dma_chan *chan,
598 struct dma_tx_state *txstate);
599 void (*device_issue_pending)(struct dma_chan *chan);
602 static inline int dmaengine_device_control(struct dma_chan *chan,
603 enum dma_ctrl_cmd cmd,
606 return chan->device->device_control(chan, cmd, arg);
609 static inline int dmaengine_slave_config(struct dma_chan *chan,
610 struct dma_slave_config *config)
612 return dmaengine_device_control(chan, DMA_SLAVE_CONFIG,
613 (unsigned long)config);
616 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
617 struct dma_chan *chan, void *buf, size_t len,
618 enum dma_transfer_direction dir, unsigned long flags)
620 struct scatterlist sg;
621 sg_init_one(&sg, buf, len);
623 return chan->device->device_prep_slave_sg(chan, &sg, 1,
627 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
628 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
629 enum dma_transfer_direction dir, unsigned long flags)
631 return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
635 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
636 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
637 size_t period_len, enum dma_transfer_direction dir)
639 return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
640 period_len, dir, NULL);
643 static inline int dmaengine_terminate_all(struct dma_chan *chan)
645 return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
648 static inline int dmaengine_pause(struct dma_chan *chan)
650 return dmaengine_device_control(chan, DMA_PAUSE, 0);
653 static inline int dmaengine_resume(struct dma_chan *chan)
655 return dmaengine_device_control(chan, DMA_RESUME, 0);
658 static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
660 return desc->tx_submit(desc);
663 static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len)
669 mask = (1 << align) - 1;
670 if (mask & (off1 | off2 | len))
675 static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
676 size_t off2, size_t len)
678 return dmaengine_check_align(dev->copy_align, off1, off2, len);
681 static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
682 size_t off2, size_t len)
684 return dmaengine_check_align(dev->xor_align, off1, off2, len);
687 static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
688 size_t off2, size_t len)
690 return dmaengine_check_align(dev->pq_align, off1, off2, len);
693 static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
694 size_t off2, size_t len)
696 return dmaengine_check_align(dev->fill_align, off1, off2, len);
700 dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
704 dma->max_pq |= DMA_HAS_PQ_CONTINUE;
707 static inline bool dmaf_continue(enum dma_ctrl_flags flags)
709 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
712 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
714 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
716 return (flags & mask) == mask;
719 static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
721 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
724 static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
726 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
729 /* dma_maxpq - reduce maxpq in the face of continued operations
730 * @dma - dma device with PQ capability
731 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
733 * When an engine does not support native continuation we need 3 extra
734 * source slots to reuse P and Q with the following coefficients:
735 * 1/ {00} * P : remove P from Q', but use it as a source for P'
736 * 2/ {01} * Q : use Q to continue Q' calculation
737 * 3/ {00} * Q : subtract Q from P' to cancel (2)
739 * In the case where P is disabled we only need 1 extra source:
740 * 1/ {01} * Q : use Q to continue Q' calculation
742 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
744 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
745 return dma_dev_to_maxpq(dma);
746 else if (dmaf_p_disabled_continue(flags))
747 return dma_dev_to_maxpq(dma) - 1;
748 else if (dmaf_continue(flags))
749 return dma_dev_to_maxpq(dma) - 3;
753 /* --- public DMA engine API --- */
755 #ifdef CONFIG_DMA_ENGINE
756 void dmaengine_get(void);
757 void dmaengine_put(void);
759 static inline void dmaengine_get(void)
762 static inline void dmaengine_put(void)
767 #ifdef CONFIG_NET_DMA
768 #define net_dmaengine_get() dmaengine_get()
769 #define net_dmaengine_put() dmaengine_put()
771 static inline void net_dmaengine_get(void)
774 static inline void net_dmaengine_put(void)
779 #ifdef CONFIG_ASYNC_TX_DMA
780 #define async_dmaengine_get() dmaengine_get()
781 #define async_dmaengine_put() dmaengine_put()
782 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
783 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
785 #define async_dma_find_channel(type) dma_find_channel(type)
786 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
788 static inline void async_dmaengine_get(void)
791 static inline void async_dmaengine_put(void)
794 static inline struct dma_chan *
795 async_dma_find_channel(enum dma_transaction_type type)
799 #endif /* CONFIG_ASYNC_TX_DMA */
801 dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
802 void *dest, void *src, size_t len);
803 dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
804 struct page *page, unsigned int offset, void *kdata, size_t len);
805 dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
806 struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
807 unsigned int src_off, size_t len);
808 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
809 struct dma_chan *chan);
811 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
813 tx->flags |= DMA_CTRL_ACK;
816 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
818 tx->flags &= ~DMA_CTRL_ACK;
821 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
823 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
826 #define first_dma_cap(mask) __first_dma_cap(&(mask))
827 static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
829 return min_t(int, DMA_TX_TYPE_END,
830 find_first_bit(srcp->bits, DMA_TX_TYPE_END));
833 #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
834 static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
836 return min_t(int, DMA_TX_TYPE_END,
837 find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
840 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
842 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
844 set_bit(tx_type, dstp->bits);
847 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
849 __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
851 clear_bit(tx_type, dstp->bits);
854 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
855 static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
857 bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
860 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
862 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
864 return test_bit(tx_type, srcp->bits);
867 #define for_each_dma_cap_mask(cap, mask) \
868 for ((cap) = first_dma_cap(mask); \
869 (cap) < DMA_TX_TYPE_END; \
870 (cap) = next_dma_cap((cap), (mask)))
873 * dma_async_issue_pending - flush pending transactions to HW
874 * @chan: target DMA channel
876 * This allows drivers to push copies to HW in batches,
877 * reducing MMIO writes where possible.
879 static inline void dma_async_issue_pending(struct dma_chan *chan)
881 chan->device->device_issue_pending(chan);
884 #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
887 * dma_async_is_tx_complete - poll for transaction completion
889 * @cookie: transaction identifier to check status of
890 * @last: returns last completed cookie, can be NULL
891 * @used: returns last issued cookie, can be NULL
893 * If @last and @used are passed in, upon return they reflect the driver
894 * internal state and can be used with dma_async_is_complete() to check
895 * the status of multiple cookies without re-checking hardware state.
897 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
898 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
900 struct dma_tx_state state;
901 enum dma_status status;
903 status = chan->device->device_tx_status(chan, cookie, &state);
911 #define dma_async_memcpy_complete(chan, cookie, last, used)\
912 dma_async_is_tx_complete(chan, cookie, last, used)
915 * dma_async_is_complete - test a cookie against chan state
916 * @cookie: transaction identifier to test status of
917 * @last_complete: last know completed transaction
918 * @last_used: last cookie value handed out
920 * dma_async_is_complete() is used in dma_async_memcpy_complete()
921 * the test logic is separated for lightweight testing of multiple cookies
923 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
924 dma_cookie_t last_complete, dma_cookie_t last_used)
926 if (last_complete <= last_used) {
927 if ((cookie <= last_complete) || (cookie > last_used))
930 if ((cookie <= last_complete) && (cookie > last_used))
933 return DMA_IN_PROGRESS;
937 dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
942 st->residue = residue;
946 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
947 #ifdef CONFIG_DMA_ENGINE
948 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
949 void dma_issue_pending_all(void);
950 struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
951 void dma_release_channel(struct dma_chan *chan);
953 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
957 static inline void dma_issue_pending_all(void)
960 static inline struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask,
961 dma_filter_fn fn, void *fn_param)
965 static inline void dma_release_channel(struct dma_chan *chan)
970 /* --- DMA device --- */
972 int dma_async_device_register(struct dma_device *device);
973 void dma_async_device_unregister(struct dma_device *device);
974 void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
975 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
976 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
978 /* --- Helper iov-locking functions --- */
980 struct dma_page_list {
981 char __user *base_address;
986 struct dma_pinned_list {
988 struct dma_page_list page_list[0];
991 struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
992 void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
994 dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
995 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
996 dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
997 struct dma_pinned_list *pinned_list, struct page *page,
998 unsigned int offset, size_t len);
1000 #endif /* DMAENGINE_H */