2 * Definitions for Intel 82593 CSMA/CD Core LAN Controller
3 * The definitions are taken from the 1992 users manual with Intel
4 * order number 297125-001.
6 * /usr/src/pc/RCS/i82593.h,v 1.1 1996/07/17 15:23:12 root Exp
8 * Copyright 1994, Anders Klemets <klemets@it.kth.se>
12 * Revision 1.4 2005/11/4 09:15:00 baroniunas
13 * Modified copyright with permission of author as follows:
15 * "If I82539.H is the only file with my copyright statement
16 * that is included in the Source Forge project, then you have
17 * my approval to change the copyright statement to be a GPL
18 * license, in the way you proposed on October 10."
20 * Revision 1.1 1996/07/17 15:23:12 root
23 * Revision 1.3 1995/04/05 15:13:58 adj
24 * Initial alpha release
26 * Revision 1.2 1994/06/16 23:57:31 klemets
27 * Mirrored all the fields in the configuration block.
29 * Revision 1.1 1994/06/02 20:25:34 klemets
37 /* Intel 82593 CSMA/CD Core LAN Controller */
39 /* Port 0 Command Register definitions */
41 /* Execution operations */
42 #define OP0_NOP 0 /* CHNL = 0 */
43 #define OP0_SWIT_TO_PORT_1 0 /* CHNL = 1 */
44 #define OP0_IA_SETUP 1
45 #define OP0_CONFIGURE 2
46 #define OP0_MC_SETUP 3
47 #define OP0_TRANSMIT 4
50 #define OP0_DIAGNOSE 7
51 #define OP0_TRANSMIT_NO_CRC 9
52 #define OP0_RETRANSMIT 12
54 /* Reception operations */
55 #define OP0_RCV_ENABLE 8
56 #define OP0_RCV_DISABLE 10
57 #define OP0_STOP_RCV 11
58 /* Status pointer control operations */
59 #define OP0_FIX_PTR 15 /* CHNL = 1 */
60 #define OP0_RLS_PTR 15 /* CHNL = 0 */
63 #define CR0_CHNL (1 << 4) /* 0=Channel 0, 1=Channel 1 */
64 #define CR0_STATUS_0 0x00
65 #define CR0_STATUS_1 0x20
66 #define CR0_STATUS_2 0x40
67 #define CR0_STATUS_3 0x60
68 #define CR0_INT_ACK (1 << 7) /* 0=No ack, 1=acknowledge */
70 /* Port 0 Status Register definitions */
72 #define SR0_NO_RESULT 0 /* dummy */
73 #define SR0_EVENT_MASK 0x0f
74 #define SR0_IA_SETUP_DONE 1
75 #define SR0_CONFIGURE_DONE 2
76 #define SR0_MC_SETUP_DONE 3
77 #define SR0_TRANSMIT_DONE 4
78 #define SR0_TDR_DONE 5
79 #define SR0_DUMP_DONE 6
80 #define SR0_DIAGNOSE_PASSED 7
81 #define SR0_TRANSMIT_NO_CRC_DONE 9
82 #define SR0_RETRANSMIT_DONE 12
83 #define SR0_EXECUTION_ABORTED 13
84 #define SR0_END_OF_FRAME 8
85 #define SR0_RECEPTION_ABORTED 10
86 #define SR0_DIAGNOSE_FAILED 15
87 #define SR0_STOP_REG_HIT 11
89 #define SR0_CHNL (1 << 4)
90 #define SR0_EXECUTION (1 << 5)
91 #define SR0_RECEPTION (1 << 6)
92 #define SR0_INTERRUPT (1 << 7)
93 #define SR0_BOTH_RX_TX (SR0_EXECUTION | SR0_RECEPTION)
95 #define SR3_EXEC_STATE_MASK 0x03
96 #define SR3_EXEC_IDLE 0
97 #define SR3_TX_ABORT_IN_PROGRESS 1
98 #define SR3_EXEC_ACTIVE 2
99 #define SR3_ABORT_IN_PROGRESS 3
100 #define SR3_EXEC_CHNL (1 << 2)
101 #define SR3_STP_ON_NO_RSRC (1 << 3)
102 #define SR3_RCVING_NO_RSRC (1 << 4)
103 #define SR3_RCV_STATE_MASK 0x60
104 #define SR3_RCV_IDLE 0x00
105 #define SR3_RCV_READY 0x20
106 #define SR3_RCV_ACTIVE 0x40
107 #define SR3_RCV_STOP_IN_PROG 0x60
108 #define SR3_RCV_CHNL (1 << 7)
110 /* Port 1 Command Register definitions */
113 #define OP1_SWIT_TO_PORT_0 1
114 #define OP1_INT_DISABLE 2
115 #define OP1_INT_ENABLE 3
118 #define OP1_POWER_DOWN 8
119 #define OP1_RESET_RING_MNGMT 11
121 #define OP1_SEL_RST 15
123 #define CR1_STATUS_4 0x00
124 #define CR1_STATUS_5 0x20
125 #define CR1_STATUS_6 0x40
126 #define CR1_STOP_REG_UPDATE (1 << 7)
128 /* Receive frame status bits */
130 #define RX_RCLD (1 << 0)
131 #define RX_IA_MATCH (1 << 1)
132 #define RX_NO_AD_MATCH (1 << 2)
133 #define RX_NO_SFD (1 << 3)
134 #define RX_SRT_FRM (1 << 7)
135 #define RX_OVRRUN (1 << 8)
136 #define RX_ALG_ERR (1 << 10)
137 #define RX_CRC_ERR (1 << 11)
138 #define RX_LEN_ERR (1 << 12)
139 #define RX_RCV_OK (1 << 13)
140 #define RX_TYP_LEN (1 << 15)
142 /* Transmit status bits */
144 #define TX_NCOL_MASK 0x0f
145 #define TX_FRTL (1 << 4)
146 #define TX_MAX_COL (1 << 5)
147 #define TX_HRT_BEAT (1 << 6)
148 #define TX_DEFER (1 << 7)
149 #define TX_UND_RUN (1 << 8)
150 #define TX_LOST_CTS (1 << 9)
151 #define TX_LOST_CRS (1 << 10)
152 #define TX_LTCOL (1 << 11)
153 #define TX_OK (1 << 13)
154 #define TX_COLL (1 << 15)
156 struct i82593_conf_block {
157 u_char fifo_limit : 4,
177 u_char slottim_hi : 3,
188 u_char cs_filter : 3,
199 tx_jabber : 1, /* why is this called max_len in the manual? */
205 u_char dummy_6 : 6, /* supposed to be ones */
208 u_char dummy_1 : 1, /* supposed to be one */
222 u_char rbuf_size : 5,
227 #define I82593_MAX_MULTICAST_ADDRESSES 128 /* Hardware hashed filter */
229 #endif /* _I82593_H */