include/linux/nvme.h

   1 /*
   2  * Definitions for the NVM Express interface
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #ifndef _LINUX_NVME_H
  16 #define _LINUX_NVME_H
  17
  18 #include <linux/types.h>
  19
  20 enum {
  21         NVME_REG_CAP    = 0x0000,       /* Controller Capabilities */
  22         NVME_REG_VS     = 0x0008,       /* Version */
  23         NVME_REG_INTMS  = 0x000c,       /* Interrupt Mask Set */
  24         NVME_REG_INTMC  = 0x0010,       /* Interrupt Mask Clear */
  25         NVME_REG_CC     = 0x0014,       /* Controller Configuration */
  26         NVME_REG_CSTS   = 0x001c,       /* Controller Status */
  27         NVME_REG_NSSR   = 0x0020,       /* NVM Subsystem Reset */
  28         NVME_REG_AQA    = 0x0024,       /* Admin Queue Attributes */
  29         NVME_REG_ASQ    = 0x0028,       /* Admin SQ Base Address */
  30         NVME_REG_ACQ    = 0x0030,       /* Admin CQ Base Address */
  31         NVME_REG_CMBLOC = 0x0038,       /* Controller Memory Buffer Location */
  32         NVME_REG_CMBSZ  = 0x003c,       /* Controller Memory Buffer Size */
  33 };
  34
  35 #define NVME_CAP_MQES(cap)      ((cap) & 0xffff)
  36 #define NVME_CAP_TIMEOUT(cap)   (((cap) >> 24) & 0xff)
  37 #define NVME_CAP_STRIDE(cap)    (((cap) >> 32) & 0xf)
  38 #define NVME_CAP_NSSRC(cap)     (((cap) >> 36) & 0x1)
  39 #define NVME_CAP_MPSMIN(cap)    (((cap) >> 48) & 0xf)
  40 #define NVME_CAP_MPSMAX(cap)    (((cap) >> 52) & 0xf)
  41
  42 #define NVME_CMB_BIR(cmbloc)    ((cmbloc) & 0x7)
  43 #define NVME_CMB_OFST(cmbloc)   (((cmbloc) >> 12) & 0xfffff)
  44 #define NVME_CMB_SZ(cmbsz)      (((cmbsz) >> 12) & 0xfffff)
  45 #define NVME_CMB_SZU(cmbsz)     (((cmbsz) >> 8) & 0xf)
  46
  47 #define NVME_CMB_WDS(cmbsz)     ((cmbsz) & 0x10)
  48 #define NVME_CMB_RDS(cmbsz)     ((cmbsz) & 0x8)
  49 #define NVME_CMB_LISTS(cmbsz)   ((cmbsz) & 0x4)
  50 #define NVME_CMB_CQS(cmbsz)     ((cmbsz) & 0x2)
  51 #define NVME_CMB_SQS(cmbsz)     ((cmbsz) & 0x1)
  52
  53 enum {
  54         NVME_CC_ENABLE          = 1 << 0,
  55         NVME_CC_CSS_NVM         = 0 << 4,
  56         NVME_CC_MPS_SHIFT       = 7,
  57         NVME_CC_ARB_RR          = 0 << 11,
  58         NVME_CC_ARB_WRRU        = 1 << 11,
  59         NVME_CC_ARB_VS          = 7 << 11,
  60         NVME_CC_SHN_NONE        = 0 << 14,
  61         NVME_CC_SHN_NORMAL      = 1 << 14,
  62         NVME_CC_SHN_ABRUPT      = 2 << 14,
  63         NVME_CC_SHN_MASK        = 3 << 14,
  64         NVME_CC_IOSQES          = 6 << 16,
  65         NVME_CC_IOCQES          = 4 << 20,
  66         NVME_CSTS_RDY           = 1 << 0,
  67         NVME_CSTS_CFS           = 1 << 1,
  68         NVME_CSTS_NSSRO         = 1 << 4,
  69         NVME_CSTS_SHST_NORMAL   = 0 << 2,
  70         NVME_CSTS_SHST_OCCUR    = 1 << 2,
  71         NVME_CSTS_SHST_CMPLT    = 2 << 2,
  72         NVME_CSTS_SHST_MASK     = 3 << 2,
  73 };
  74
  75 struct nvme_id_power_state {
  76         __le16                  max_power;      /* centiwatts */
  77         __u8                    rsvd2;
  78         __u8                    flags;
  79         __le32                  entry_lat;      /* microseconds */
  80         __le32                  exit_lat;       /* microseconds */
  81         __u8                    read_tput;
  82         __u8                    read_lat;
  83         __u8                    write_tput;
  84         __u8                    write_lat;
  85         __le16                  idle_power;
  86         __u8                    idle_scale;
  87         __u8                    rsvd19;
  88         __le16                  active_power;
  89         __u8                    active_work_scale;
  90         __u8                    rsvd23[9];
  91 };
  92
  93 enum {
  94         NVME_PS_FLAGS_MAX_POWER_SCALE   = 1 << 0,
  95         NVME_PS_FLAGS_NON_OP_STATE      = 1 << 1,
  96 };
  97
  98 struct nvme_id_ctrl {
  99         __le16                  vid;
 100         __le16                  ssvid;
 101         char                    sn[20];
 102         char                    mn[40];
 103         char                    fr[8];
 104         __u8                    rab;
 105         __u8                    ieee[3];
 106         __u8                    mic;
 107         __u8                    mdts;
 108         __le16                  cntlid;
 109         __le32                  ver;
 110         __le32                  rtd3r;
 111         __le32                  rtd3e;
 112         __le32                  oaes;
 113         __u8                    rsvd96[160];
 114         __le16                  oacs;
 115         __u8                    acl;
 116         __u8                    aerl;
 117         __u8                    frmw;
 118         __u8                    lpa;
 119         __u8                    elpe;
 120         __u8                    npss;
 121         __u8                    avscc;
 122         __u8                    apsta;
 123         __le16                  wctemp;
 124         __le16                  cctemp;
 125         __u8                    rsvd270[242];
 126         __u8                    sqes;
 127         __u8                    cqes;
 128         __u8                    rsvd514[2];
 129         __le32                  nn;
 130         __le16                  oncs;
 131         __le16                  fuses;
 132         __u8                    fna;
 133         __u8                    vwc;
 134         __le16                  awun;
 135         __le16                  awupf;
 136         __u8                    nvscc;
 137         __u8                    rsvd531;
 138         __le16                  acwu;
 139         __u8                    rsvd534[2];
 140         __le32                  sgls;
 141         __u8                    rsvd540[1508];
 142         struct nvme_id_power_state      psd[32];
 143         __u8                    vs[1024];
 144 };
 145
 146 enum {
 147         NVME_CTRL_ONCS_COMPARE                  = 1 << 0,
 148         NVME_CTRL_ONCS_WRITE_UNCORRECTABLE      = 1 << 1,
 149         NVME_CTRL_ONCS_DSM                      = 1 << 2,
 150         NVME_CTRL_VWC_PRESENT                   = 1 << 0,
 151 };
 152
 153 struct nvme_lbaf {
 154         __le16                  ms;
 155         __u8                    ds;
 156         __u8                    rp;
 157 };
 158
 159 struct nvme_id_ns {
 160         __le64                  nsze;
 161         __le64                  ncap;
 162         __le64                  nuse;
 163         __u8                    nsfeat;
 164         __u8                    nlbaf;
 165         __u8                    flbas;
 166         __u8                    mc;
 167         __u8                    dpc;
 168         __u8                    dps;
 169         __u8                    nmic;
 170         __u8                    rescap;
 171         __u8                    fpi;
 172         __u8                    rsvd33;
 173         __le16                  nawun;
 174         __le16                  nawupf;
 175         __le16                  nacwu;
 176         __le16                  nabsn;
 177         __le16                  nabo;
 178         __le16                  nabspf;
 179         __u16                   rsvd46;
 180         __le64                  nvmcap[2];
 181         __u8                    rsvd64[40];
 182         __u8                    nguid[16];
 183         __u8                    eui64[8];
 184         struct nvme_lbaf        lbaf[16];
 185         __u8                    rsvd192[192];
 186         __u8                    vs[3712];
 187 };
 188
 189 enum {
 190         NVME_NS_FEAT_THIN       = 1 << 0,
 191         NVME_NS_FLBAS_LBA_MASK  = 0xf,
 192         NVME_NS_FLBAS_META_EXT  = 0x10,
 193         NVME_LBAF_RP_BEST       = 0,
 194         NVME_LBAF_RP_BETTER     = 1,
 195         NVME_LBAF_RP_GOOD       = 2,
 196         NVME_LBAF_RP_DEGRADED   = 3,
 197         NVME_NS_DPC_PI_LAST     = 1 << 4,
 198         NVME_NS_DPC_PI_FIRST    = 1 << 3,
 199         NVME_NS_DPC_PI_TYPE3    = 1 << 2,
 200         NVME_NS_DPC_PI_TYPE2    = 1 << 1,
 201         NVME_NS_DPC_PI_TYPE1    = 1 << 0,
 202         NVME_NS_DPS_PI_FIRST    = 1 << 3,
 203         NVME_NS_DPS_PI_MASK     = 0x7,
 204         NVME_NS_DPS_PI_TYPE1    = 1,
 205         NVME_NS_DPS_PI_TYPE2    = 2,
 206         NVME_NS_DPS_PI_TYPE3    = 3,
 207 };
 208
 209 struct nvme_smart_log {
 210         __u8                    critical_warning;
 211         __u8                    temperature[2];
 212         __u8                    avail_spare;
 213         __u8                    spare_thresh;
 214         __u8                    percent_used;
 215         __u8                    rsvd6[26];
 216         __u8                    data_units_read[16];
 217         __u8                    data_units_written[16];
 218         __u8                    host_reads[16];
 219         __u8                    host_writes[16];
 220         __u8                    ctrl_busy_time[16];
 221         __u8                    power_cycles[16];
 222         __u8                    power_on_hours[16];
 223         __u8                    unsafe_shutdowns[16];
 224         __u8                    media_errors[16];
 225         __u8                    num_err_log_entries[16];
 226         __le32                  warning_temp_time;
 227         __le32                  critical_comp_time;
 228         __le16                  temp_sensor[8];
 229         __u8                    rsvd216[296];
 230 };
 231
 232 enum {
 233         NVME_SMART_CRIT_SPARE           = 1 << 0,
 234         NVME_SMART_CRIT_TEMPERATURE     = 1 << 1,
 235         NVME_SMART_CRIT_RELIABILITY     = 1 << 2,
 236         NVME_SMART_CRIT_MEDIA           = 1 << 3,
 237         NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
 238 };
 239
 240 enum {
 241         NVME_AER_NOTICE_NS_CHANGED      = 0x0002,
 242 };
 243
 244 struct nvme_lba_range_type {
 245         __u8                    type;
 246         __u8                    attributes;
 247         __u8                    rsvd2[14];
 248         __u64                   slba;
 249         __u64                   nlb;
 250         __u8                    guid[16];
 251         __u8                    rsvd48[16];
 252 };
 253
 254 enum {
 255         NVME_LBART_TYPE_FS      = 0x01,
 256         NVME_LBART_TYPE_RAID    = 0x02,
 257         NVME_LBART_TYPE_CACHE   = 0x03,
 258         NVME_LBART_TYPE_SWAP    = 0x04,
 259
 260         NVME_LBART_ATTRIB_TEMP  = 1 << 0,
 261         NVME_LBART_ATTRIB_HIDE  = 1 << 1,
 262 };
 263
 264 struct nvme_reservation_status {
 265         __le32  gen;
 266         __u8    rtype;
 267         __u8    regctl[2];
 268         __u8    resv5[2];
 269         __u8    ptpls;
 270         __u8    resv10[13];
 271         struct {
 272                 __le16  cntlid;
 273                 __u8    rcsts;
 274                 __u8    resv3[5];
 275                 __le64  hostid;
 276                 __le64  rkey;
 277         } regctl_ds[];
 278 };
 279
 280 /* I/O commands */
 281
 282 enum nvme_opcode {
 283         nvme_cmd_flush          = 0x00,
 284         nvme_cmd_write          = 0x01,
 285         nvme_cmd_read           = 0x02,
 286         nvme_cmd_write_uncor    = 0x04,
 287         nvme_cmd_compare        = 0x05,
 288         nvme_cmd_write_zeroes   = 0x08,
 289         nvme_cmd_dsm            = 0x09,
 290         nvme_cmd_resv_register  = 0x0d,
 291         nvme_cmd_resv_report    = 0x0e,
 292         nvme_cmd_resv_acquire   = 0x11,
 293         nvme_cmd_resv_release   = 0x15,
 294 };
 295
 296 struct nvme_common_command {
 297         __u8                    opcode;
 298         __u8                    flags;
 299         __u16                   command_id;
 300         __le32                  nsid;
 301         __le32                  cdw2[2];
 302         __le64                  metadata;
 303         __le64                  prp1;
 304         __le64                  prp2;
 305         __le32                  cdw10[6];
 306 };
 307
 308 struct nvme_rw_command {
 309         __u8                    opcode;
 310         __u8                    flags;
 311         __u16                   command_id;
 312         __le32                  nsid;
 313         __u64                   rsvd2;
 314         __le64                  metadata;
 315         __le64                  prp1;
 316         __le64                  prp2;
 317         __le64                  slba;
 318         __le16                  length;
 319         __le16                  control;
 320         __le32                  dsmgmt;
 321         __le32                  reftag;
 322         __le16                  apptag;
 323         __le16                  appmask;
 324 };
 325
 326 enum {
 327         NVME_RW_LR                      = 1 << 15,
 328         NVME_RW_FUA                     = 1 << 14,
 329         NVME_RW_DSM_FREQ_UNSPEC         = 0,
 330         NVME_RW_DSM_FREQ_TYPICAL        = 1,
 331         NVME_RW_DSM_FREQ_RARE           = 2,
 332         NVME_RW_DSM_FREQ_READS          = 3,
 333         NVME_RW_DSM_FREQ_WRITES         = 4,
 334         NVME_RW_DSM_FREQ_RW             = 5,
 335         NVME_RW_DSM_FREQ_ONCE           = 6,
 336         NVME_RW_DSM_FREQ_PREFETCH       = 7,
 337         NVME_RW_DSM_FREQ_TEMP           = 8,
 338         NVME_RW_DSM_LATENCY_NONE        = 0 << 4,
 339         NVME_RW_DSM_LATENCY_IDLE        = 1 << 4,
 340         NVME_RW_DSM_LATENCY_NORM        = 2 << 4,
 341         NVME_RW_DSM_LATENCY_LOW         = 3 << 4,
 342         NVME_RW_DSM_SEQ_REQ             = 1 << 6,
 343         NVME_RW_DSM_COMPRESSED          = 1 << 7,
 344         NVME_RW_PRINFO_PRCHK_REF        = 1 << 10,
 345         NVME_RW_PRINFO_PRCHK_APP        = 1 << 11,
 346         NVME_RW_PRINFO_PRCHK_GUARD      = 1 << 12,
 347         NVME_RW_PRINFO_PRACT            = 1 << 13,
 348 };
 349
 350 struct nvme_dsm_cmd {
 351         __u8                    opcode;
 352         __u8                    flags;
 353         __u16                   command_id;
 354         __le32                  nsid;
 355         __u64                   rsvd2[2];
 356         __le64                  prp1;
 357         __le64                  prp2;
 358         __le32                  nr;
 359         __le32                  attributes;
 360         __u32                   rsvd12[4];
 361 };
 362
 363 enum {
 364         NVME_DSMGMT_IDR         = 1 << 0,
 365         NVME_DSMGMT_IDW         = 1 << 1,
 366         NVME_DSMGMT_AD          = 1 << 2,
 367 };
 368
 369 struct nvme_dsm_range {
 370         __le32                  cattr;
 371         __le32                  nlb;
 372         __le64                  slba;
 373 };
 374
 375 /* Admin commands */
 376
 377 enum nvme_admin_opcode {
 378         nvme_admin_delete_sq            = 0x00,
 379         nvme_admin_create_sq            = 0x01,
 380         nvme_admin_get_log_page         = 0x02,
 381         nvme_admin_delete_cq            = 0x04,
 382         nvme_admin_create_cq            = 0x05,
 383         nvme_admin_identify             = 0x06,
 384         nvme_admin_abort_cmd            = 0x08,
 385         nvme_admin_set_features         = 0x09,
 386         nvme_admin_get_features         = 0x0a,
 387         nvme_admin_async_event          = 0x0c,
 388         nvme_admin_activate_fw          = 0x10,
 389         nvme_admin_download_fw          = 0x11,
 390         nvme_admin_format_nvm           = 0x80,
 391         nvme_admin_security_send        = 0x81,
 392         nvme_admin_security_recv        = 0x82,
 393 };
 394
 395 enum {
 396         NVME_QUEUE_PHYS_CONTIG  = (1 << 0),
 397         NVME_CQ_IRQ_ENABLED     = (1 << 1),
 398         NVME_SQ_PRIO_URGENT     = (0 << 1),
 399         NVME_SQ_PRIO_HIGH       = (1 << 1),
 400         NVME_SQ_PRIO_MEDIUM     = (2 << 1),
 401         NVME_SQ_PRIO_LOW        = (3 << 1),
 402         NVME_FEAT_ARBITRATION   = 0x01,
 403         NVME_FEAT_POWER_MGMT    = 0x02,
 404         NVME_FEAT_LBA_RANGE     = 0x03,
 405         NVME_FEAT_TEMP_THRESH   = 0x04,
 406         NVME_FEAT_ERR_RECOVERY  = 0x05,
 407         NVME_FEAT_VOLATILE_WC   = 0x06,
 408         NVME_FEAT_NUM_QUEUES    = 0x07,
 409         NVME_FEAT_IRQ_COALESCE  = 0x08,
 410         NVME_FEAT_IRQ_CONFIG    = 0x09,
 411         NVME_FEAT_WRITE_ATOMIC  = 0x0a,
 412         NVME_FEAT_ASYNC_EVENT   = 0x0b,
 413         NVME_FEAT_AUTO_PST      = 0x0c,
 414         NVME_FEAT_SW_PROGRESS   = 0x80,
 415         NVME_FEAT_HOST_ID       = 0x81,
 416         NVME_FEAT_RESV_MASK     = 0x82,
 417         NVME_FEAT_RESV_PERSIST  = 0x83,
 418         NVME_LOG_ERROR          = 0x01,
 419         NVME_LOG_SMART          = 0x02,
 420         NVME_LOG_FW_SLOT        = 0x03,
 421         NVME_LOG_RESERVATION    = 0x80,
 422         NVME_FWACT_REPL         = (0 << 3),
 423         NVME_FWACT_REPL_ACTV    = (1 << 3),
 424         NVME_FWACT_ACTV         = (2 << 3),
 425 };
 426
 427 struct nvme_identify {
 428         __u8                    opcode;
 429         __u8                    flags;
 430         __u16                   command_id;
 431         __le32                  nsid;
 432         __u64                   rsvd2[2];
 433         __le64                  prp1;
 434         __le64                  prp2;
 435         __le32                  cns;
 436         __u32                   rsvd11[5];
 437 };
 438
 439 struct nvme_features {
 440         __u8                    opcode;
 441         __u8                    flags;
 442         __u16                   command_id;
 443         __le32                  nsid;
 444         __u64                   rsvd2[2];
 445         __le64                  prp1;
 446         __le64                  prp2;
 447         __le32                  fid;
 448         __le32                  dword11;
 449         __u32                   rsvd12[4];
 450 };
 451
 452 struct nvme_create_cq {
 453         __u8                    opcode;
 454         __u8                    flags;
 455         __u16                   command_id;
 456         __u32                   rsvd1[5];
 457         __le64                  prp1;
 458         __u64                   rsvd8;
 459         __le16                  cqid;
 460         __le16                  qsize;
 461         __le16                  cq_flags;
 462         __le16                  irq_vector;
 463         __u32                   rsvd12[4];
 464 };
 465
 466 struct nvme_create_sq {
 467         __u8                    opcode;
 468         __u8                    flags;
 469         __u16                   command_id;
 470         __u32                   rsvd1[5];
 471         __le64                  prp1;
 472         __u64                   rsvd8;
 473         __le16                  sqid;
 474         __le16                  qsize;
 475         __le16                  sq_flags;
 476         __le16                  cqid;
 477         __u32                   rsvd12[4];
 478 };
 479
 480 struct nvme_delete_queue {
 481         __u8                    opcode;
 482         __u8                    flags;
 483         __u16                   command_id;
 484         __u32                   rsvd1[9];
 485         __le16                  qid;
 486         __u16                   rsvd10;
 487         __u32                   rsvd11[5];
 488 };
 489
 490 struct nvme_abort_cmd {
 491         __u8                    opcode;
 492         __u8                    flags;
 493         __u16                   command_id;
 494         __u32                   rsvd1[9];
 495         __le16                  sqid;
 496         __u16                   cid;
 497         __u32                   rsvd11[5];
 498 };
 499
 500 struct nvme_download_firmware {
 501         __u8                    opcode;
 502         __u8                    flags;
 503         __u16                   command_id;
 504         __u32                   rsvd1[5];
 505         __le64                  prp1;
 506         __le64                  prp2;
 507         __le32                  numd;
 508         __le32                  offset;
 509         __u32                   rsvd12[4];
 510 };
 511
 512 struct nvme_format_cmd {
 513         __u8                    opcode;
 514         __u8                    flags;
 515         __u16                   command_id;
 516         __le32                  nsid;
 517         __u64                   rsvd2[4];
 518         __le32                  cdw10;
 519         __u32                   rsvd11[5];
 520 };
 521
 522 struct nvme_command {
 523         union {
 524                 struct nvme_common_command common;
 525                 struct nvme_rw_command rw;
 526                 struct nvme_identify identify;
 527                 struct nvme_features features;
 528                 struct nvme_create_cq create_cq;
 529                 struct nvme_create_sq create_sq;
 530                 struct nvme_delete_queue delete_queue;
 531                 struct nvme_download_firmware dlfw;
 532                 struct nvme_format_cmd format;
 533                 struct nvme_dsm_cmd dsm;
 534                 struct nvme_abort_cmd abort;
 535         };
 536 };
 537
 538 enum {
 539         NVME_SC_SUCCESS                 = 0x0,
 540         NVME_SC_INVALID_OPCODE          = 0x1,
 541         NVME_SC_INVALID_FIELD           = 0x2,
 542         NVME_SC_CMDID_CONFLICT          = 0x3,
 543         NVME_SC_DATA_XFER_ERROR         = 0x4,
 544         NVME_SC_POWER_LOSS              = 0x5,
 545         NVME_SC_INTERNAL                = 0x6,
 546         NVME_SC_ABORT_REQ               = 0x7,
 547         NVME_SC_ABORT_QUEUE             = 0x8,
 548         NVME_SC_FUSED_FAIL              = 0x9,
 549         NVME_SC_FUSED_MISSING           = 0xa,
 550         NVME_SC_INVALID_NS              = 0xb,
 551         NVME_SC_CMD_SEQ_ERROR           = 0xc,
 552         NVME_SC_SGL_INVALID_LAST        = 0xd,
 553         NVME_SC_SGL_INVALID_COUNT       = 0xe,
 554         NVME_SC_SGL_INVALID_DATA        = 0xf,
 555         NVME_SC_SGL_INVALID_METADATA    = 0x10,
 556         NVME_SC_SGL_INVALID_TYPE        = 0x11,
 557         NVME_SC_LBA_RANGE               = 0x80,
 558         NVME_SC_CAP_EXCEEDED            = 0x81,
 559         NVME_SC_NS_NOT_READY            = 0x82,
 560         NVME_SC_RESERVATION_CONFLICT    = 0x83,
 561         NVME_SC_CQ_INVALID              = 0x100,
 562         NVME_SC_QID_INVALID             = 0x101,
 563         NVME_SC_QUEUE_SIZE              = 0x102,
 564         NVME_SC_ABORT_LIMIT             = 0x103,
 565         NVME_SC_ABORT_MISSING           = 0x104,
 566         NVME_SC_ASYNC_LIMIT             = 0x105,
 567         NVME_SC_FIRMWARE_SLOT           = 0x106,
 568         NVME_SC_FIRMWARE_IMAGE          = 0x107,
 569         NVME_SC_INVALID_VECTOR          = 0x108,
 570         NVME_SC_INVALID_LOG_PAGE        = 0x109,
 571         NVME_SC_INVALID_FORMAT          = 0x10a,
 572         NVME_SC_FIRMWARE_NEEDS_RESET    = 0x10b,
 573         NVME_SC_INVALID_QUEUE           = 0x10c,
 574         NVME_SC_FEATURE_NOT_SAVEABLE    = 0x10d,
 575         NVME_SC_FEATURE_NOT_CHANGEABLE  = 0x10e,
 576         NVME_SC_FEATURE_NOT_PER_NS      = 0x10f,
 577         NVME_SC_FW_NEEDS_RESET_SUBSYS   = 0x110,
 578         NVME_SC_BAD_ATTRIBUTES          = 0x180,
 579         NVME_SC_INVALID_PI              = 0x181,
 580         NVME_SC_READ_ONLY               = 0x182,
 581         NVME_SC_WRITE_FAULT             = 0x280,
 582         NVME_SC_READ_ERROR              = 0x281,
 583         NVME_SC_GUARD_CHECK             = 0x282,
 584         NVME_SC_APPTAG_CHECK            = 0x283,
 585         NVME_SC_REFTAG_CHECK            = 0x284,
 586         NVME_SC_COMPARE_FAILED          = 0x285,
 587         NVME_SC_ACCESS_DENIED           = 0x286,
 588         NVME_SC_DNR                     = 0x4000,
 589 };
 590
 591 struct nvme_completion {
 592         __le32  result;         /* Used by admin commands to return data */
 593         __u32   rsvd;
 594         __le16  sq_head;        /* how much of this queue may be reclaimed */
 595         __le16  sq_id;          /* submission queue that generated this entry */
 596         __u16   command_id;     /* of the command which completed */
 597         __le16  status;         /* did the command fail, and if so, why? */
 598 };
 599
 600 #define NVME_VS(major, minor) (((major) << 16) | ((minor) << 8))
 601
 602 #endif /* _LINUX_NVME_H */