1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/types.h>
37 #include <linux/interrupt.h>
38 #include <linux/netdevice.h>
39 #include <linux/pci.h>
40 #include <linux/skbuff.h>
41 #include <linux/types.h>
42 #include <asm/byteorder.h>
44 #include <linux/compiler.h>
45 #include <linux/kernel.h>
46 #include <linux/list.h>
47 #include <linux/slab.h>
48 #include <linux/qed/common_hsi.h>
49 #include <linux/qed/qed_chain.h>
51 enum dcbx_protocol_type {
55 DCBX_PROTOCOL_ROCE_V2,
57 DCBX_MAX_PROTOCOL_TYPE
60 #define QED_ROCE_PROTOCOL_INDEX (3)
62 #define QED_LLDP_CHASSIS_ID_STAT_LEN 4
63 #define QED_LLDP_PORT_ID_STAT_LEN 4
64 #define QED_DCBX_MAX_APP_PROTOCOL 32
65 #define QED_MAX_PFC_PRIORITIES 8
66 #define QED_DCBX_DSCP_SIZE 64
68 struct qed_dcbx_lldp_remote {
69 u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
70 u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN];
77 struct qed_dcbx_lldp_local {
78 u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
79 u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN];
82 struct qed_dcbx_app_prio {
90 struct qed_dbcx_pfc_params {
93 u8 prio[QED_MAX_PFC_PRIORITIES];
97 enum qed_dcbx_sf_ieee_type {
98 QED_DCBX_SF_IEEE_ETHTYPE,
99 QED_DCBX_SF_IEEE_TCP_PORT,
100 QED_DCBX_SF_IEEE_UDP_PORT,
101 QED_DCBX_SF_IEEE_TCP_UDP_PORT
104 struct qed_app_entry {
106 enum qed_dcbx_sf_ieee_type sf_ieee;
110 enum dcbx_protocol_type proto_type;
113 struct qed_dcbx_params {
114 struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL];
123 u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES];
124 u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES];
125 u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES];
126 struct qed_dbcx_pfc_params pfc;
130 struct qed_dcbx_admin_params {
131 struct qed_dcbx_params params;
135 struct qed_dcbx_remote_params {
136 struct qed_dcbx_params params;
140 struct qed_dcbx_operational_params {
141 struct qed_dcbx_app_prio app_prio;
142 struct qed_dcbx_params params;
151 struct qed_dcbx_get {
152 struct qed_dcbx_operational_params operational;
153 struct qed_dcbx_lldp_remote lldp_remote;
154 struct qed_dcbx_lldp_local lldp_local;
155 struct qed_dcbx_remote_params remote;
156 struct qed_dcbx_admin_params local;
165 #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
166 (void __iomem *)(reg_addr))
168 #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
170 #define QED_COALESCE_MAX 0xFF
171 #define QED_DEFAULT_RX_USECS 12
176 struct qed_eth_pf_params {
177 /* The following parameters are used during HW-init
178 * and these parameters need to be passed as arguments
179 * to update_pf_params routine invoked before slowpath start
183 /* To enable arfs, previous to HW-init a positive number needs to be
184 * set [as filters require allocated searcher ILT memory].
185 * This will set the maximal number of configured steering-filters.
187 u32 num_arfs_filters;
190 struct qed_fcoe_pf_params {
191 /* The following parameters are used during protocol-init */
192 u64 glbl_q_params_addr;
193 u64 bdq_pbl_base_addr[2];
195 /* The following parameters are used during HW-init
196 * and these parameters need to be passed as arguments
197 * to update_pf_params routine invoked before slowpath start
202 /* The following parameters are used during protocol-init */
203 u16 sq_num_pbl_pages;
206 u16 cmdq_num_entries;
207 u16 rq_buffer_log_size;
210 u16 bdq_xoff_threshold[2];
211 u16 bdq_xon_threshold[2];
213 u8 num_cqs; /* num of global CQs */
219 u8 bdq_pbl_num_entries[2];
222 /* Most of the the parameters below are described in the FW iSCSI / TCP HSI */
223 struct qed_iscsi_pf_params {
224 u64 glbl_q_params_addr;
225 u64 bdq_pbl_base_addr[2];
228 u16 cmdq_num_entries;
230 u16 dup_ack_threshold;
236 /* The following parameters are used during HW-init
237 * and these parameters need to be passed as arguments
238 * to update_pf_params routine invoked before slowpath start
243 /* The following parameters are used during protocol-init */
244 u16 half_way_close_timeout;
245 u16 bdq_xoff_threshold[2];
246 u16 bdq_xon_threshold[2];
247 u16 cmdq_xoff_threshold;
248 u16 cmdq_xon_threshold;
251 u8 num_sq_pages_in_ring;
252 u8 num_r2tq_pages_in_ring;
253 u8 num_uhq_pages_in_ring;
265 u8 bdq_pbl_num_entries[2];
268 struct qed_rdma_pf_params {
269 /* Supplied to QED during resource allocation (may affect the ILT and
272 u32 min_dpis; /* number of requested DPIs */
273 u32 num_qps; /* number of requested Queue Pairs */
274 u32 num_srqs; /* number of requested SRQ */
275 u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */
276 u8 gl_pi; /* protocol index */
278 /* Will allocate rate limiters to be used with QPs */
282 struct qed_pf_params {
283 struct qed_eth_pf_params eth_pf_params;
284 struct qed_fcoe_pf_params fcoe_pf_params;
285 struct qed_iscsi_pf_params iscsi_pf_params;
286 struct qed_rdma_pf_params rdma_pf_params;
297 struct status_block *sb_virt;
299 u32 sb_ack; /* Last given ack */
301 void __iomem *igu_addr;
303 #define QED_SB_INFO_INIT 0x1
304 #define QED_SB_INFO_SETUP 0x2
306 struct qed_dev *cdev;
314 struct qed_dev_info {
315 unsigned long pci_mem_start;
316 unsigned long pci_mem_end;
317 unsigned int pci_irq;
331 #define QED_MFW_VERSION_0_MASK 0x000000FF
332 #define QED_MFW_VERSION_0_OFFSET 0
333 #define QED_MFW_VERSION_1_MASK 0x0000FF00
334 #define QED_MFW_VERSION_1_OFFSET 8
335 #define QED_MFW_VERSION_2_MASK 0x00FF0000
336 #define QED_MFW_VERSION_2_OFFSET 16
337 #define QED_MFW_VERSION_3_MASK 0xFF000000
338 #define QED_MFW_VERSION_3_OFFSET 24
350 #define QED_MBI_VERSION_0_MASK 0x000000FF
351 #define QED_MBI_VERSION_0_OFFSET 0
352 #define QED_MBI_VERSION_1_MASK 0x0000FF00
353 #define QED_MBI_VERSION_1_OFFSET 8
354 #define QED_MBI_VERSION_2_MASK 0x00FF0000
355 #define QED_MBI_VERSION_2_OFFSET 16
357 enum qed_dev_type dev_type;
359 /* Output parameters for qede */
366 QED_SB_TYPE_L2_QUEUE,
377 enum qed_link_mode_bits {
378 QED_LM_FIBRE_BIT = BIT(0),
379 QED_LM_Autoneg_BIT = BIT(1),
380 QED_LM_Asym_Pause_BIT = BIT(2),
381 QED_LM_Pause_BIT = BIT(3),
382 QED_LM_1000baseT_Half_BIT = BIT(4),
383 QED_LM_1000baseT_Full_BIT = BIT(5),
384 QED_LM_10000baseKR_Full_BIT = BIT(6),
385 QED_LM_25000baseKR_Full_BIT = BIT(7),
386 QED_LM_40000baseLR4_Full_BIT = BIT(8),
387 QED_LM_50000baseKR2_Full_BIT = BIT(9),
388 QED_LM_100000baseKR4_Full_BIT = BIT(10),
392 struct qed_link_params {
395 #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0)
396 #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1)
397 #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2)
398 #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3)
399 #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4)
404 #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0)
405 #define QED_LINK_PAUSE_RX_ENABLE BIT(1)
406 #define QED_LINK_PAUSE_TX_ENABLE BIT(2)
408 #define QED_LINK_LOOPBACK_NONE BIT(0)
409 #define QED_LINK_LOOPBACK_INT_PHY BIT(1)
410 #define QED_LINK_LOOPBACK_EXT_PHY BIT(2)
411 #define QED_LINK_LOOPBACK_EXT BIT(3)
412 #define QED_LINK_LOOPBACK_MAC BIT(4)
416 struct qed_link_output {
419 /* In QED_LM_* defs */
424 u32 speed; /* In Mb/s */
425 u8 duplex; /* In DUPLEX defs */
426 u8 port; /* In PORT defs */
431 struct qed_probe_params {
432 enum qed_protocol protocol;
438 #define QED_DRV_VER_STR_SIZE 12
439 struct qed_slowpath_params {
445 u8 name[QED_DRV_VER_STR_SIZE];
448 #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */
450 struct qed_int_info {
451 struct msix_entry *msix;
454 /* This should be updated by the protocol driver */
458 struct qed_common_cb_ops {
459 void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc);
460 void (*link_update)(void *dev,
461 struct qed_link_output *link);
462 void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type);
465 struct qed_selftest_ops {
467 * @brief selftest_interrupt - Perform interrupt test
471 * @return 0 on success, error otherwise.
473 int (*selftest_interrupt)(struct qed_dev *cdev);
476 * @brief selftest_memory - Perform memory test
480 * @return 0 on success, error otherwise.
482 int (*selftest_memory)(struct qed_dev *cdev);
485 * @brief selftest_register - Perform register test
489 * @return 0 on success, error otherwise.
491 int (*selftest_register)(struct qed_dev *cdev);
494 * @brief selftest_clock - Perform clock test
498 * @return 0 on success, error otherwise.
500 int (*selftest_clock)(struct qed_dev *cdev);
503 * @brief selftest_nvram - Perform nvram test
507 * @return 0 on success, error otherwise.
509 int (*selftest_nvram) (struct qed_dev *cdev);
512 struct qed_common_ops {
513 struct qed_selftest_ops *selftest;
515 struct qed_dev* (*probe)(struct pci_dev *dev,
516 struct qed_probe_params *params);
518 void (*remove)(struct qed_dev *cdev);
520 int (*set_power_state)(struct qed_dev *cdev,
523 void (*set_name) (struct qed_dev *cdev, char name[]);
525 /* Client drivers need to make this call before slowpath_start.
526 * PF params required for the call before slowpath_start is
527 * documented within the qed_pf_params structure definition.
529 void (*update_pf_params)(struct qed_dev *cdev,
530 struct qed_pf_params *params);
531 int (*slowpath_start)(struct qed_dev *cdev,
532 struct qed_slowpath_params *params);
534 int (*slowpath_stop)(struct qed_dev *cdev);
536 /* Requests to use `cnt' interrupts for fastpath.
537 * upon success, returns number of interrupts allocated for fastpath.
539 int (*set_fp_int)(struct qed_dev *cdev,
542 /* Fills `info' with pointers required for utilizing interrupts */
543 int (*get_fp_int)(struct qed_dev *cdev,
544 struct qed_int_info *info);
546 u32 (*sb_init)(struct qed_dev *cdev,
547 struct qed_sb_info *sb_info,
549 dma_addr_t sb_phy_addr,
551 enum qed_sb_type type);
553 u32 (*sb_release)(struct qed_dev *cdev,
554 struct qed_sb_info *sb_info,
557 void (*simd_handler_config)(struct qed_dev *cdev,
560 void (*handler)(void *));
562 void (*simd_handler_clean)(struct qed_dev *cdev,
564 int (*dbg_grc)(struct qed_dev *cdev,
565 void *buffer, u32 *num_dumped_bytes);
567 int (*dbg_grc_size)(struct qed_dev *cdev);
569 int (*dbg_all_data) (struct qed_dev *cdev, void *buffer);
571 int (*dbg_all_data_size) (struct qed_dev *cdev);
574 * @brief can_link_change - can the instance change the link or not
578 * @return true if link-change is allowed, false otherwise.
580 bool (*can_link_change)(struct qed_dev *cdev);
583 * @brief set_link - set links according to params
586 * @param params - values used to override the default link configuration
588 * @return 0 on success, error otherwise.
590 int (*set_link)(struct qed_dev *cdev,
591 struct qed_link_params *params);
594 * @brief get_link - returns the current link state.
597 * @param if_link - structure to be filled with current link configuration.
599 void (*get_link)(struct qed_dev *cdev,
600 struct qed_link_output *if_link);
603 * @brief - drains chip in case Tx completions fail to arrive due to pause.
607 int (*drain)(struct qed_dev *cdev);
610 * @brief update_msglvl - update module debug level
616 void (*update_msglvl)(struct qed_dev *cdev,
620 int (*chain_alloc)(struct qed_dev *cdev,
621 enum qed_chain_use_mode intended_use,
622 enum qed_chain_mode mode,
623 enum qed_chain_cnt_type cnt_type,
626 struct qed_chain *p_chain);
628 void (*chain_free)(struct qed_dev *cdev,
629 struct qed_chain *p_chain);
632 * @brief get_coalesce - Get coalesce parameters in usec
635 * @param rx_coal - Rx coalesce value in usec
636 * @param tx_coal - Tx coalesce value in usec
639 void (*get_coalesce)(struct qed_dev *cdev, u16 *rx_coal, u16 *tx_coal);
642 * @brief set_coalesce - Configure Rx coalesce value in usec
645 * @param rx_coal - Rx coalesce value in usec
646 * @param tx_coal - Tx coalesce value in usec
647 * @param qid - Queue index
648 * @param sb_id - Status Block Id
650 * @return 0 on success, error otherwise.
652 int (*set_coalesce)(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal,
656 * @brief set_led - Configure LED mode
659 * @param mode - LED mode
661 * @return 0 on success, error otherwise.
663 int (*set_led)(struct qed_dev *cdev,
664 enum qed_led_mode mode);
667 * @brief update_drv_state - API to inform the change in the driver state.
673 int (*update_drv_state)(struct qed_dev *cdev, bool active);
676 * @brief update_mac - API to inform the change in the mac address
682 int (*update_mac)(struct qed_dev *cdev, u8 *mac);
685 * @brief update_mtu - API to inform the change in the mtu
691 int (*update_mtu)(struct qed_dev *cdev, u16 mtu);
694 * @brief update_wol - update of changes in the WoL configuration
697 * @param enabled - true iff WoL should be enabled.
699 int (*update_wol) (struct qed_dev *cdev, bool enabled);
702 #define MASK_FIELD(_name, _value) \
703 ((_value) &= (_name ## _MASK))
705 #define FIELD_VALUE(_name, _value) \
706 ((_value & _name ## _MASK) << _name ## _SHIFT)
708 #define SET_FIELD(value, name, flag) \
710 (value) &= ~(name ## _MASK << name ## _SHIFT); \
711 (value) |= (((u64)flag) << (name ## _SHIFT)); \
714 #define GET_FIELD(value, name) \
715 (((value) >> (name ## _SHIFT)) & name ## _MASK)
717 /* Debug print definitions */
718 #define DP_ERR(cdev, fmt, ...) \
720 pr_err("[%s:%d(%s)]" fmt, \
721 __func__, __LINE__, \
722 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
726 #define DP_NOTICE(cdev, fmt, ...) \
728 if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
729 pr_notice("[%s:%d(%s)]" fmt, \
730 __func__, __LINE__, \
731 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
737 #define DP_INFO(cdev, fmt, ...) \
739 if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \
740 pr_notice("[%s:%d(%s)]" fmt, \
741 __func__, __LINE__, \
742 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
747 #define DP_VERBOSE(cdev, module, fmt, ...) \
749 if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \
750 ((cdev)->dp_module & module))) { \
751 pr_notice("[%s:%d(%s)]" fmt, \
752 __func__, __LINE__, \
753 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
759 QED_LEVEL_VERBOSE = 0x0,
760 QED_LEVEL_INFO = 0x1,
761 QED_LEVEL_NOTICE = 0x2,
765 #define QED_LOG_LEVEL_SHIFT (30)
766 #define QED_LOG_VERBOSE_MASK (0x3fffffff)
767 #define QED_LOG_INFO_MASK (0x40000000)
768 #define QED_LOG_NOTICE_MASK (0x80000000)
771 QED_MSG_SPQ = 0x10000,
772 QED_MSG_STATS = 0x20000,
773 QED_MSG_DCB = 0x40000,
774 QED_MSG_IOV = 0x80000,
775 QED_MSG_SP = 0x100000,
776 QED_MSG_STORAGE = 0x200000,
777 QED_MSG_CXT = 0x800000,
778 QED_MSG_LL2 = 0x1000000,
779 QED_MSG_ILT = 0x2000000,
780 QED_MSG_RDMA = 0x4000000,
781 QED_MSG_DEBUG = 0x8000000,
782 /* to be added...up to 0x8000000 */
791 struct qed_eth_stats_common {
792 u64 no_buff_discards;
793 u64 packet_too_big_discard;
801 u64 mftag_filter_discards;
802 u64 mac_filter_discards;
809 u64 tx_err_drop_pkts;
810 u64 tpa_coalesced_pkts;
811 u64 tpa_coalesced_events;
813 u64 tpa_not_coalesced_pkts;
814 u64 tpa_coalesced_bytes;
817 u64 rx_64_byte_packets;
818 u64 rx_65_to_127_byte_packets;
819 u64 rx_128_to_255_byte_packets;
820 u64 rx_256_to_511_byte_packets;
821 u64 rx_512_to_1023_byte_packets;
822 u64 rx_1024_to_1518_byte_packets;
824 u64 rx_mac_crtl_frames;
828 u64 rx_carrier_errors;
829 u64 rx_oversize_packets;
831 u64 rx_undersize_packets;
833 u64 tx_64_byte_packets;
834 u64 tx_65_to_127_byte_packets;
835 u64 tx_128_to_255_byte_packets;
836 u64 tx_256_to_511_byte_packets;
837 u64 tx_512_to_1023_byte_packets;
838 u64 tx_1024_to_1518_byte_packets;
844 u64 rx_mac_uc_packets;
845 u64 rx_mac_mc_packets;
846 u64 rx_mac_bc_packets;
847 u64 rx_mac_frames_ok;
849 u64 tx_mac_uc_packets;
850 u64 tx_mac_mc_packets;
851 u64 tx_mac_bc_packets;
852 u64 tx_mac_ctrl_frames;
855 struct qed_eth_stats_bb {
856 u64 rx_1519_to_1522_byte_packets;
857 u64 rx_1519_to_2047_byte_packets;
858 u64 rx_2048_to_4095_byte_packets;
859 u64 rx_4096_to_9216_byte_packets;
860 u64 rx_9217_to_16383_byte_packets;
861 u64 tx_1519_to_2047_byte_packets;
862 u64 tx_2048_to_4095_byte_packets;
863 u64 tx_4096_to_9216_byte_packets;
864 u64 tx_9217_to_16383_byte_packets;
865 u64 tx_lpi_entry_count;
866 u64 tx_total_collisions;
869 struct qed_eth_stats_ah {
870 u64 rx_1519_to_max_byte_packets;
871 u64 tx_1519_to_max_byte_packets;
874 struct qed_eth_stats {
875 struct qed_eth_stats_common common;
878 struct qed_eth_stats_bb bb;
879 struct qed_eth_stats_ah ah;
883 #define QED_SB_IDX 0x0002
886 #define TX_PI(tc) (RX_PI + 1 + tc)
888 struct qed_sb_cnt_info {
889 /* Original, current, and free SBs for PF */
894 /* Original, current and free SBS for child VFs */
900 static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
905 prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
906 STATUS_BLOCK_PROD_INDEX_MASK;
907 if (sb_info->sb_ack != prod) {
908 sb_info->sb_ack = prod;
919 * @brief This function creates an update command for interrupts that is
920 * written to the IGU.
922 * @param sb_info - This is the structure allocated and
923 * initialized per status block. Assumption is
924 * that it was initialized using qed_sb_init
925 * @param int_cmd - Enable/Disable/Nop
926 * @param upd_flg - whether igu consumer should be
929 * @return inline void
931 static inline void qed_sb_ack(struct qed_sb_info *sb_info,
932 enum igu_int_cmd int_cmd,
935 struct igu_prod_cons_update igu_ack = { 0 };
937 igu_ack.sb_id_and_flags =
938 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
939 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
940 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
941 (IGU_SEG_ACCESS_REG <<
942 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
944 DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags);
946 /* Both segments (interrupts & acks) are written to same place address;
947 * Need to guarantee all commands will be received (in-order) by HW.
953 static inline void __internal_ram_wr(void *p_hwfn,
961 for (i = 0; i < size / sizeof(*data); i++)
962 DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
965 static inline void internal_ram_wr(void __iomem *addr,
969 __internal_ram_wr(NULL, addr, size, data);
975 QED_RSS_IPV4_TCP = 0x4,
976 QED_RSS_IPV6_TCP = 0x8,
977 QED_RSS_IPV4_UDP = 0x10,
978 QED_RSS_IPV6_UDP = 0x20,
981 #define QED_RSS_IND_TABLE_SIZE 128
982 #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */