2 * Copyright (c) 2005, 2009 Freescale Semiconductor, Inc
3 * Copyright (c) 2005 MontaVista Software
4 * Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/processor.h>
14 #define CONTROL_REGISTER_W1C_MASK 0x00020000 /* W1C: PHY_CLK_VALID */
17 #define FSL_SKIP_PCI 0x100
19 /* offsets for the non-ehci registers in the FSL SOC USB controller */
20 #define FSL_SOC_USB_ULPIVP 0x170
21 #define FSL_SOC_USB_PORTSC1 0x184
22 #define PORT_PTS_MSK (3 << 30)
23 #define PORT_PTS_UTMI (0 << 30)
24 #define PORT_PTS_ULPI (2 << 30)
25 #define PORT_PTS_SERIAL (3 << 30)
26 #define PORT_PTS_PTW (1 << 28)
27 #define PORT_PFSC (1 << 24) /* Defined on Page 39-44 of the mpc5151 ERM */
28 #define PORT_PTS_PHCD (1 << 23)
29 #define PORT_PP (1 << 12)
30 #define PORT_PR (1 << 8)
32 /* USBMODE Register bits */
33 #define CM_IDLE (0 << 0)
34 #define CM_RESERVED (1 << 0)
35 #define CM_DEVICE (2 << 0)
36 #define CM_HOST (3 << 0)
37 #define ES_BE (1 << 2) /* Big Endian Select, default is LE */
38 #define USBMODE_RESERVED_2 (0 << 2)
42 /* CONTROL Register bits */
43 #define ULPI_INT_EN (1 << 0)
44 #define WU_INT_EN (1 << 1)
45 #define USB_EN (1 << 2)
46 #define LSF_EN (1 << 3)
47 #define KEEP_OTG_ON (1 << 4)
48 #define OTG_PORT (1 << 5)
49 #define REFSEL_12MHZ (0 << 6)
50 #define REFSEL_16MHZ (1 << 6)
51 #define REFSEL_48MHZ (2 << 6)
52 #define PLL_RESET (1 << 8)
53 #define UTMI_PHY_EN (1 << 9)
54 #define PHY_CLK_SEL_UTMI (0 << 10)
55 #define PHY_CLK_SEL_ULPI (1 << 10)
56 #define CLKIN_SEL_USB_CLK (0 << 11)
57 #define CLKIN_SEL_USB_CLK2 (1 << 11)
58 #define CLKIN_SEL_SYS_CLK (2 << 11)
59 #define CLKIN_SEL_SYS_CLK2 (3 << 11)
60 #define RESERVED_18 (0 << 13)
61 #define RESERVED_17 (0 << 14)
62 #define RESERVED_16 (0 << 15)
63 #define WU_INT (1 << 16)
64 #define PHY_CLK_VALID (1 << 17)
66 #define FSL_SOC_USB_PORTSC2 0x188
68 /* OTG Status Control Register bits */
69 #define FSL_SOC_USB_OTGSC 0x1a4
70 #define CTRL_VBUS_DISCHARGE (0x1<<0)
71 #define CTRL_VBUS_CHARGE (0x1<<1)
72 #define CTRL_OTG_TERMINATION (0x1<<3)
73 #define CTRL_DATA_PULSING (0x1<<4)
74 #define CTRL_ID_PULL_EN (0x1<<5)
75 #define HA_DATA_PULSE (0x1<<6)
76 #define HA_BA (0x1<<7)
77 #define STS_USB_ID (0x1<<8)
78 #define STS_A_VBUS_VALID (0x1<<9)
79 #define STS_A_SESSION_VALID (0x1<<10)
80 #define STS_B_SESSION_VALID (0x1<<11)
81 #define STS_B_SESSION_END (0x1<<12)
82 #define STS_1MS_TOGGLE (0x1<<13)
83 #define STS_DATA_PULSING (0x1<<14)
84 #define INTSTS_USB_ID (0x1<<16)
85 #define INTSTS_A_VBUS_VALID (0x1<<17)
86 #define INTSTS_A_SESSION_VALID (0x1<<18)
87 #define INTSTS_B_SESSION_VALID (0x1<<19)
88 #define INTSTS_B_SESSION_END (0x1<<20)
89 #define INTSTS_1MS (0x1<<21)
90 #define INTSTS_DATA_PULSING (0x1<<22)
91 #define INTR_USB_ID_EN (0x1<<24)
92 #define INTR_A_VBUS_VALID_EN (0x1<<25)
93 #define INTR_A_SESSION_VALID_EN (0x1<<26)
94 #define INTR_B_SESSION_VALID_EN (0x1<<27)
95 #define INTR_B_SESSION_END_EN (0x1<<28)
96 #define INTR_1MS_TIMER_EN (0x1<<29)
97 #define INTR_DATA_PULSING_EN (0x1<<30)
98 #define INTSTS_MASK (0x00ff0000)
100 /* USBCMD Bits of interest */
101 #define EHCI_FSL_USBCMD_RST (1 << 1)
102 #define EHCI_FSL_USBCMD_RS (1 << 0)
104 #define INTERRUPT_ENABLE_BITS_MASK \
106 INTR_1MS_TIMER_EN | \
107 INTR_A_VBUS_VALID_EN | \
108 INTR_A_SESSION_VALID_EN | \
109 INTR_B_SESSION_VALID_EN | \
110 INTR_B_SESSION_END_EN | \
111 INTR_DATA_PULSING_EN)
113 #define INTERRUPT_STATUS_BITS_MASK \
115 INTR_1MS_TIMER_EN | \
116 INTSTS_A_VBUS_VALID | \
117 INTSTS_A_SESSION_VALID | \
118 INTSTS_B_SESSION_VALID | \
119 INTSTS_B_SESSION_END | \
122 #define FSL_SOC_USB_USBMODE 0x1a8
124 #define USBGENCTRL 0x200 /* NOTE: big endian */
125 #define GC_WU_INT_CLR (1 << 5) /* Wakeup int clear */
126 #define GC_ULPI_SEL (1 << 4) /* ULPI i/f select (usb0 only)*/
127 #define GC_PPP (1 << 3) /* Port Power Polarity */
128 #define GC_PFP (1 << 2) /* Power Fault Polarity */
129 #define GC_WU_ULPI_EN (1 << 1) /* Wakeup on ULPI event */
130 #define GC_WU_IE (1 << 1) /* Wakeup interrupt enable */
132 #define ISIPHYCTRL 0x204 /* NOTE: big endian */
133 #define PHYCTRL_PHYE (1 << 4) /* On-chip UTMI PHY enable */
134 #define PHYCTRL_BSENH (1 << 3) /* Bit Stuff Enable High */
135 #define PHYCTRL_BSEN (1 << 2) /* Bit Stuff Enable */
136 #define PHYCTRL_LSFE (1 << 1) /* Line State Filter Enable */
137 #define PHYCTRL_PXE (1 << 0) /* PHY oscillator enable */
139 #define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */
140 #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */
141 #define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */
142 #define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
143 #define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
144 #define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
145 #define SNOOP_SIZE_2GB 0x1e
147 /* System Clock Control Register */
148 #define MPC83XX_SCCR_USB_MASK 0x00f00000
149 #define MPC83XX_SCCR_USB_DRCM_11 0x00300000
150 #define MPC83XX_SCCR_USB_DRCM_01 0x00100000
151 #define MPC83XX_SCCR_USB_DRCM_10 0x00200000
153 #if defined(CONFIG_MPC83xx)
154 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC83xx_USB1_ADDR
155 #if defined(CONFIG_MPC834x)
156 #define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC83xx_USB2_ADDR
158 #define CONFIG_SYS_FSL_USB2_ADDR 0
160 #elif defined(CONFIG_MPC85xx)
161 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR
162 #define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR
163 #elif defined(CONFIG_MPC512X)
164 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
165 #define CONFIG_SYS_FSL_USB2_ADDR 0
169 * Increasing TX FIFO threshold value from 2 to 4 decreases
170 * data burst rate with which data packets are posted from the TX
171 * latency FIFO to compensate for latencies in DDR pipeline during DMA
173 #define TXFIFOTHRESH 4
179 u32 id; /* 0x000 - Identification register */
180 u32 hwgeneral; /* 0x004 - General hardware parameters */
181 u32 hwhost; /* 0x008 - Host hardware parameters */
182 u32 hwdevice; /* 0x00C - Device hardware parameters */
183 u32 hwtxbuf; /* 0x010 - TX buffer hardware parameters */
184 u32 hwrxbuf; /* 0x014 - RX buffer hardware parameters */
186 u32 gptimer0_ld; /* 0x080 - General Purpose Timer 0 load value */
187 u32 gptimer0_ctrl; /* 0x084 - General Purpose Timer 0 control */
188 u32 gptimer1_ld; /* 0x088 - General Purpose Timer 1 load value */
189 u32 gptimer1_ctrl; /* 0x08C - General Purpose Timer 1 control */
190 u32 sbuscfg; /* 0x090 - System Bus Interface Control */
192 u8 caplength; /* 0x100 - Capability Register Length */
194 u16 hciversion; /* 0x102 - Host Interface Version */
195 u32 hcsparams; /* 0x104 - Host Structural Parameters */
196 u32 hccparams; /* 0x108 - Host Capability Parameters */
198 u32 dciversion; /* 0x120 - Device Interface Version */
199 u32 dciparams; /* 0x124 - Device Controller Params */
201 u32 usbcmd; /* 0x140 - USB Command */
202 u32 usbsts; /* 0x144 - USB Status */
203 u32 usbintr; /* 0x148 - USB Interrupt Enable */
204 u32 frindex; /* 0x14C - USB Frame Index */
206 u32 perlistbase; /* 0x154 - Periodic List Base
207 - USB Device Address */
208 u32 ep_list_addr; /* 0x158 - Next Asynchronous List
209 - End Point Address */
211 u32 burstsize; /* 0x160 - Programmable Burst Size */
212 #define FSL_EHCI_TXPBURST(X) ((X) << 8)
213 #define FSL_EHCI_RXPBURST(X) (X)
214 u32 txfilltuning; /* 0x164 - Host TT Transmit
215 pre-buffer packet tuning */
217 u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */
219 u32 config_flag; /* 0x180 - Configured Flag Register */
220 u32 portsc; /* 0x184 - Port status/control */
222 u32 otgsc; /* 0x1a4 - Oo-The-Go status and control */
223 u32 usbmode; /* 0x1a8 - USB Device Mode */
224 u32 epsetupstat; /* 0x1ac - End Point Setup Status */
225 u32 epprime; /* 0x1b0 - End Point Init Status */
226 u32 epflush; /* 0x1b4 - End Point De-initlialize */
227 u32 epstatus; /* 0x1b8 - End Point Status */
228 u32 epcomplete; /* 0x1bc - End Point Complete */
229 u32 epctrl0; /* 0x1c0 - End Point Control 0 */
230 u32 epctrl1; /* 0x1c4 - End Point Control 1 */
231 u32 epctrl2; /* 0x1c8 - End Point Control 2 */
232 u32 epctrl3; /* 0x1cc - End Point Control 3 */
233 u32 epctrl4; /* 0x1d0 - End Point Control 4 */
234 u32 epctrl5; /* 0x1d4 - End Point Control 5 */
236 u32 usbgenctrl; /* 0x200 - USB General Control */
237 u32 isiphyctrl; /* 0x204 - On-Chip PHY Control */
239 u32 snoop1; /* 0x400 - Snoop 1 */
240 u32 snoop2; /* 0x404 - Snoop 2 */
241 u32 age_cnt_limit; /* 0x408 - Age Count Threshold */
242 u32 prictrl; /* 0x40c - Priority Control */
243 u32 sictrl; /* 0x410 - System Interface Control */
245 u32 control; /* 0x500 - Control */
253 /* values for portsc field */
254 #define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
255 #define MXC_EHCI_FORCE_FS (1 << 24)
256 #define MXC_EHCI_UTMI_8BIT (0 << 28)
257 #define MXC_EHCI_UTMI_16BIT (1 << 28)
258 #define MXC_EHCI_SERIAL (1 << 29)
259 #define MXC_EHCI_MODE_UTMI (0 << 30)
260 #define MXC_EHCI_MODE_PHILIPS (1 << 30)
261 #define MXC_EHCI_MODE_ULPI (2 << 30)
262 #define MXC_EHCI_MODE_SERIAL (3 << 30)
264 /* values for flags field */
265 #define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
266 #define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
267 #define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
268 #define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
269 #define MXC_EHCI_INTERFACE_MASK (0xf)
271 #define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
272 #define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6)
273 #define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7)
274 #define MXC_EHCI_TTL_ENABLED (1 << 8)
276 #define MXC_EHCI_INTERNAL_PHY (1 << 9)
277 #define MXC_EHCI_IPPUE_DOWN (1 << 10)
278 #define MXC_EHCI_IPPUE_UP (1 << 11)
280 /* Board-specific initialization */
281 int board_ehci_hcd_init(int port);
283 #endif /* _EHCI_FSL_H */