2 * Copyright (c) 2005, 2009 Freescale Semiconductor, Inc
3 * Copyright (c) 2005 MontaVista Software
4 * Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/processor.h>
15 #define FSL_SKIP_PCI 0x100
17 /* offsets for the non-ehci registers in the FSL SOC USB controller */
18 #define FSL_SOC_USB_ULPIVP 0x170
19 #define FSL_SOC_USB_PORTSC1 0x184
20 #define PORT_PTS_MSK (3 << 30)
21 #define PORT_PTS_UTMI (0 << 30)
22 #define PORT_PTS_ULPI (2 << 30)
23 #define PORT_PTS_SERIAL (3 << 30)
24 #define PORT_PTS_PTW (1 << 28)
25 #define PORT_PFSC (1 << 24) /* Defined on Page 39-44 of the mpc5151 ERM */
26 #define PORT_PTS_PHCD (1 << 23)
27 #define PORT_PP (1 << 12)
28 #define PORT_PR (1 << 8)
30 /* USBMODE Register bits */
31 #define CM_IDLE (0 << 0)
32 #define CM_RESERVED (1 << 0)
33 #define CM_DEVICE (2 << 0)
34 #define CM_HOST (3 << 0)
35 #define ES_BE (1 << 2) /* Big Endian Select, default is LE */
36 #define USBMODE_RESERVED_2 (0 << 2)
40 /* CONTROL Register bits */
41 #define ULPI_INT_EN (1 << 0)
42 #define WU_INT_EN (1 << 1)
43 #define USB_EN (1 << 2)
44 #define LSF_EN (1 << 3)
45 #define KEEP_OTG_ON (1 << 4)
46 #define OTG_PORT (1 << 5)
47 #define REFSEL_12MHZ (0 << 6)
48 #define REFSEL_16MHZ (1 << 6)
49 #define REFSEL_48MHZ (2 << 6)
50 #define PLL_RESET (1 << 8)
51 #define UTMI_PHY_EN (1 << 9)
52 #define PHY_CLK_SEL_UTMI (0 << 10)
53 #define PHY_CLK_SEL_ULPI (1 << 10)
54 #define CLKIN_SEL_USB_CLK (0 << 11)
55 #define CLKIN_SEL_USB_CLK2 (1 << 11)
56 #define CLKIN_SEL_SYS_CLK (2 << 11)
57 #define CLKIN_SEL_SYS_CLK2 (3 << 11)
58 #define RESERVED_18 (0 << 13)
59 #define RESERVED_17 (0 << 14)
60 #define RESERVED_16 (0 << 15)
61 #define WU_INT (1 << 16)
62 #define PHY_CLK_VALID (1 << 17)
64 #define FSL_SOC_USB_PORTSC2 0x188
66 /* OTG Status Control Register bits */
67 #define FSL_SOC_USB_OTGSC 0x1a4
68 #define CTRL_VBUS_DISCHARGE (0x1<<0)
69 #define CTRL_VBUS_CHARGE (0x1<<1)
70 #define CTRL_OTG_TERMINATION (0x1<<3)
71 #define CTRL_DATA_PULSING (0x1<<4)
72 #define CTRL_ID_PULL_EN (0x1<<5)
73 #define HA_DATA_PULSE (0x1<<6)
74 #define HA_BA (0x1<<7)
75 #define STS_USB_ID (0x1<<8)
76 #define STS_A_VBUS_VALID (0x1<<9)
77 #define STS_A_SESSION_VALID (0x1<<10)
78 #define STS_B_SESSION_VALID (0x1<<11)
79 #define STS_B_SESSION_END (0x1<<12)
80 #define STS_1MS_TOGGLE (0x1<<13)
81 #define STS_DATA_PULSING (0x1<<14)
82 #define INTSTS_USB_ID (0x1<<16)
83 #define INTSTS_A_VBUS_VALID (0x1<<17)
84 #define INTSTS_A_SESSION_VALID (0x1<<18)
85 #define INTSTS_B_SESSION_VALID (0x1<<19)
86 #define INTSTS_B_SESSION_END (0x1<<20)
87 #define INTSTS_1MS (0x1<<21)
88 #define INTSTS_DATA_PULSING (0x1<<22)
89 #define INTR_USB_ID_EN (0x1<<24)
90 #define INTR_A_VBUS_VALID_EN (0x1<<25)
91 #define INTR_A_SESSION_VALID_EN (0x1<<26)
92 #define INTR_B_SESSION_VALID_EN (0x1<<27)
93 #define INTR_B_SESSION_END_EN (0x1<<28)
94 #define INTR_1MS_TIMER_EN (0x1<<29)
95 #define INTR_DATA_PULSING_EN (0x1<<30)
96 #define INTSTS_MASK (0x00ff0000)
98 /* USBCMD Bits of interest */
99 #define EHCI_FSL_USBCMD_RST (1 << 1)
100 #define EHCI_FSL_USBCMD_RS (1 << 0)
102 #define INTERRUPT_ENABLE_BITS_MASK \
104 INTR_1MS_TIMER_EN | \
105 INTR_A_VBUS_VALID_EN | \
106 INTR_A_SESSION_VALID_EN | \
107 INTR_B_SESSION_VALID_EN | \
108 INTR_B_SESSION_END_EN | \
109 INTR_DATA_PULSING_EN)
111 #define INTERRUPT_STATUS_BITS_MASK \
113 INTR_1MS_TIMER_EN | \
114 INTSTS_A_VBUS_VALID | \
115 INTSTS_A_SESSION_VALID | \
116 INTSTS_B_SESSION_VALID | \
117 INTSTS_B_SESSION_END | \
120 #define FSL_SOC_USB_USBMODE 0x1a8
122 #define USBGENCTRL 0x200 /* NOTE: big endian */
123 #define GC_WU_INT_CLR (1 << 5) /* Wakeup int clear */
124 #define GC_ULPI_SEL (1 << 4) /* ULPI i/f select (usb0 only)*/
125 #define GC_PPP (1 << 3) /* Port Power Polarity */
126 #define GC_PFP (1 << 2) /* Power Fault Polarity */
127 #define GC_WU_ULPI_EN (1 << 1) /* Wakeup on ULPI event */
128 #define GC_WU_IE (1 << 1) /* Wakeup interrupt enable */
130 #define ISIPHYCTRL 0x204 /* NOTE: big endian */
131 #define PHYCTRL_PHYE (1 << 4) /* On-chip UTMI PHY enable */
132 #define PHYCTRL_BSENH (1 << 3) /* Bit Stuff Enable High */
133 #define PHYCTRL_BSEN (1 << 2) /* Bit Stuff Enable */
134 #define PHYCTRL_LSFE (1 << 1) /* Line State Filter Enable */
135 #define PHYCTRL_PXE (1 << 0) /* PHY oscillator enable */
137 #define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */
138 #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */
139 #define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */
140 #define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
141 #define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
142 #define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
143 #define SNOOP_SIZE_2GB 0x1e
145 /* System Clock Control Register */
146 #define MPC83XX_SCCR_USB_MASK 0x00f00000
147 #define MPC83XX_SCCR_USB_DRCM_11 0x00300000
148 #define MPC83XX_SCCR_USB_DRCM_01 0x00100000
149 #define MPC83XX_SCCR_USB_DRCM_10 0x00200000
151 #if defined(CONFIG_MPC83xx)
152 #define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR
153 #elif defined(CONFIG_MPC85xx)
154 #define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC85xx_USB_ADDR
155 #elif defined(CONFIG_MPC512X)
156 #define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR
163 u32 id; /* 0x000 - Identification register */
164 u32 hwgeneral; /* 0x004 - General hardware parameters */
165 u32 hwhost; /* 0x008 - Host hardware parameters */
166 u32 hwdevice; /* 0x00C - Device hardware parameters */
167 u32 hwtxbuf; /* 0x010 - TX buffer hardware parameters */
168 u32 hwrxbuf; /* 0x014 - RX buffer hardware parameters */
170 u32 gptimer0_ld; /* 0x080 - General Purpose Timer 0 load value */
171 u32 gptimer0_ctrl; /* 0x084 - General Purpose Timer 0 control */
172 u32 gptimer1_ld; /* 0x088 - General Purpose Timer 1 load value */
173 u32 gptimer1_ctrl; /* 0x08C - General Purpose Timer 1 control */
174 u32 sbuscfg; /* 0x090 - System Bus Interface Control */
176 u8 caplength; /* 0x100 - Capability Register Length */
178 u16 hciversion; /* 0x102 - Host Interface Version */
179 u32 hcsparams; /* 0x104 - Host Structural Parameters */
180 u32 hccparams; /* 0x108 - Host Capability Parameters */
182 u32 dciversion; /* 0x120 - Device Interface Version */
183 u32 dciparams; /* 0x124 - Device Controller Params */
185 u32 usbcmd; /* 0x140 - USB Command */
186 u32 usbsts; /* 0x144 - USB Status */
187 u32 usbintr; /* 0x148 - USB Interrupt Enable */
188 u32 frindex; /* 0x14C - USB Frame Index */
190 u32 perlistbase; /* 0x154 - Periodic List Base
191 - USB Device Address */
192 u32 ep_list_addr; /* 0x158 - Next Asynchronous List
193 - End Point Address */
195 u32 burstsize; /* 0x160 - Programmable Burst Size */
196 #define FSL_EHCI_TXPBURST(X) ((X) << 8)
197 #define FSL_EHCI_RXPBURST(X) (X)
198 u32 txfilltuning; /* 0x164 - Host TT Transmit
199 pre-buffer packet tuning */
201 u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */
203 u32 config_flag; /* 0x180 - Configured Flag Register */
204 u32 portsc; /* 0x184 - Port status/control */
206 u32 otgsc; /* 0x1a4 - Oo-The-Go status and control */
207 u32 usbmode; /* 0x1a8 - USB Device Mode */
208 u32 epsetupstat; /* 0x1ac - End Point Setup Status */
209 u32 epprime; /* 0x1b0 - End Point Init Status */
210 u32 epflush; /* 0x1b4 - End Point De-initlialize */
211 u32 epstatus; /* 0x1b8 - End Point Status */
212 u32 epcomplete; /* 0x1bc - End Point Complete */
213 u32 epctrl0; /* 0x1c0 - End Point Control 0 */
214 u32 epctrl1; /* 0x1c4 - End Point Control 1 */
215 u32 epctrl2; /* 0x1c8 - End Point Control 2 */
216 u32 epctrl3; /* 0x1cc - End Point Control 3 */
217 u32 epctrl4; /* 0x1d0 - End Point Control 4 */
218 u32 epctrl5; /* 0x1d4 - End Point Control 5 */
220 u32 usbgenctrl; /* 0x200 - USB General Control */
221 u32 isiphyctrl; /* 0x204 - On-Chip PHY Control */
223 u32 snoop1; /* 0x400 - Snoop 1 */
224 u32 snoop2; /* 0x404 - Snoop 2 */
225 u32 age_cnt_limit; /* 0x408 - Age Count Threshold */
226 u32 prictrl; /* 0x40c - Priority Control */
227 u32 sictrl; /* 0x410 - System Interface Control */
229 u32 control; /* 0x500 - Control */
237 /* values for portsc field */
238 #define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
239 #define MXC_EHCI_FORCE_FS (1 << 24)
240 #define MXC_EHCI_UTMI_8BIT (0 << 28)
241 #define MXC_EHCI_UTMI_16BIT (1 << 28)
242 #define MXC_EHCI_SERIAL (1 << 29)
243 #define MXC_EHCI_MODE_UTMI (0 << 30)
244 #define MXC_EHCI_MODE_PHILIPS (1 << 30)
245 #define MXC_EHCI_MODE_ULPI (2 << 30)
246 #define MXC_EHCI_MODE_SERIAL (3 << 30)
248 /* values for flags field */
249 #define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
250 #define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
251 #define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
252 #define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
253 #define MXC_EHCI_INTERFACE_MASK (0xf)
255 #define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
256 #define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6)
257 #define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7)
258 #define MXC_EHCI_TTL_ENABLED (1 << 8)
260 #define MXC_EHCI_INTERNAL_PHY (1 << 9)
261 #define MXC_EHCI_IPPUE_DOWN (1 << 10)
262 #define MXC_EHCI_IPPUE_UP (1 << 11)
264 /* Board-specific initialization */
265 int board_ehci_hcd_init(int port);
267 #endif /* _EHCI_FSL_H */