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1 /*
2  *   ALSA driver for RME Hammerfall DSP MADI audio interface(s)
3  *
4  *      Copyright (c) 2003 Winfried Ritsch (IEM)
5  *      code based on hdsp.c   Paul Davis
6  *                             Marcus Andersson
7  *                             Thomas Charbonnel
8  *      Modified 2006-06-01 for AES32 support by Remy Bruno
9  *                                               <remy.bruno@trinnov.com>
10  *
11  *      Modified 2009-04-13 for proper metering by Florian Faber
12  *                                               <faber@faberman.de>
13  *
14  *      Modified 2009-04-14 for native float support by Florian Faber
15  *                                               <faber@faberman.de>
16  *
17  *      Modified 2009-04-26 fixed bug in rms metering by Florian Faber
18  *                                               <faber@faberman.de>
19  *
20  *      Modified 2009-04-30 added hw serial number support by Florian Faber
21  *
22  *      Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
23  *
24  *      Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
25  *
26  *   This program is free software; you can redistribute it and/or modify
27  *   it under the terms of the GNU General Public License as published by
28  *   the Free Software Foundation; either version 2 of the License, or
29  *   (at your option) any later version.
30  *
31  *   This program is distributed in the hope that it will be useful,
32  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
33  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
34  *   GNU General Public License for more details.
35  *
36  *   You should have received a copy of the GNU General Public License
37  *   along with this program; if not, write to the Free Software
38  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
39  *
40  */
41 #include <linux/init.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/moduleparam.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/math64.h>
48 #include <asm/io.h>
49
50 #include <sound/core.h>
51 #include <sound/control.h>
52 #include <sound/pcm.h>
53 #include <sound/pcm_params.h>
54 #include <sound/info.h>
55 #include <sound/asoundef.h>
56 #include <sound/rawmidi.h>
57 #include <sound/hwdep.h>
58 #include <sound/initval.h>
59
60 #include <sound/hdspm.h>
61
62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;        /* Index 0-MAX */
63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;         /* ID for this card */
64 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
65
66 module_param_array(index, int, NULL, 0444);
67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
68
69 module_param_array(id, charp, NULL, 0444);
70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
71
72 module_param_array(enable, bool, NULL, 0444);
73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
74
75
76 MODULE_AUTHOR
77 (
78         "Winfried Ritsch <ritsch_AT_iem.at>, "
79         "Paul Davis <paul@linuxaudiosystems.com>, "
80         "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
81         "Remy Bruno <remy.bruno@trinnov.com>, "
82         "Florian Faber <faberman@linuxproaudio.org>, "
83         "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
84 );
85 MODULE_DESCRIPTION("RME HDSPM");
86 MODULE_LICENSE("GPL");
87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
88
89 /* --- Write registers. ---
90   These are defined as byte-offsets from the iobase value.  */
91
92 #define HDSPM_WR_SETTINGS             0
93 #define HDSPM_outputBufferAddress    32
94 #define HDSPM_inputBufferAddress     36
95 #define HDSPM_controlRegister        64
96 #define HDSPM_interruptConfirmation  96
97 #define HDSPM_control2Reg            256  /* not in specs ???????? */
98 #define HDSPM_freqReg                256  /* for AES32 */
99 #define HDSPM_midiDataOut0           352  /* just believe in old code */
100 #define HDSPM_midiDataOut1           356
101 #define HDSPM_eeprom_wr              384  /* for AES32 */
102
103 /* DMA enable for 64 channels, only Bit 0 is relevant */
104 #define HDSPM_outputEnableBase       512  /* 512-767  input  DMA */
105 #define HDSPM_inputEnableBase        768  /* 768-1023 output DMA */
106
107 /* 16 page addresses for each of the 64 channels DMA buffer in and out
108    (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
109 #define HDSPM_pageAddressBufferOut       8192
110 #define HDSPM_pageAddressBufferIn        (HDSPM_pageAddressBufferOut+64*16*4)
111
112 #define HDSPM_MADI_mixerBase    32768   /* 32768-65535 for 2x64x64 Fader */
113
114 #define HDSPM_MATRIX_MIXER_SIZE  8192   /* = 2*64*64 * 4 Byte => 32kB */
115
116 /* --- Read registers. ---
117    These are defined as byte-offsets from the iobase value */
118 #define HDSPM_statusRegister    0
119 /*#define HDSPM_statusRegister2  96 */
120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
121  * offset 192, for AES32 *and* MADI
122  * => need to check that offset 192 is working on MADI */
123 #define HDSPM_statusRegister2  192
124 #define HDSPM_timecodeRegister 128
125
126 /* AIO, RayDAT */
127 #define HDSPM_RD_STATUS_0 0
128 #define HDSPM_RD_STATUS_1 64
129 #define HDSPM_RD_STATUS_2 128
130 #define HDSPM_RD_STATUS_3 192
131
132 #define HDSPM_RD_TCO           256
133 #define HDSPM_RD_PLL_FREQ      512
134 #define HDSPM_WR_TCO           128
135
136 #define HDSPM_TCO1_TCO_lock                     0x00000001
137 #define HDSPM_TCO1_WCK_Input_Range_LSB          0x00000002
138 #define HDSPM_TCO1_WCK_Input_Range_MSB          0x00000004
139 #define HDSPM_TCO1_LTC_Input_valid              0x00000008
140 #define HDSPM_TCO1_WCK_Input_valid              0x00000010
141 #define HDSPM_TCO1_Video_Input_Format_NTSC      0x00000020
142 #define HDSPM_TCO1_Video_Input_Format_PAL       0x00000040
143
144 #define HDSPM_TCO1_set_TC                       0x00000100
145 #define HDSPM_TCO1_set_drop_frame_flag          0x00000200
146 #define HDSPM_TCO1_LTC_Format_LSB               0x00000400
147 #define HDSPM_TCO1_LTC_Format_MSB               0x00000800
148
149 #define HDSPM_TCO2_TC_run                       0x00010000
150 #define HDSPM_TCO2_WCK_IO_ratio_LSB             0x00020000
151 #define HDSPM_TCO2_WCK_IO_ratio_MSB             0x00040000
152 #define HDSPM_TCO2_set_num_drop_frames_LSB      0x00080000
153 #define HDSPM_TCO2_set_num_drop_frames_MSB      0x00100000
154 #define HDSPM_TCO2_set_jam_sync                 0x00200000
155 #define HDSPM_TCO2_set_flywheel                 0x00400000
156
157 #define HDSPM_TCO2_set_01_4                     0x01000000
158 #define HDSPM_TCO2_set_pull_down                0x02000000
159 #define HDSPM_TCO2_set_pull_up                  0x04000000
160 #define HDSPM_TCO2_set_freq                     0x08000000
161 #define HDSPM_TCO2_set_term_75R                 0x10000000
162 #define HDSPM_TCO2_set_input_LSB                0x20000000
163 #define HDSPM_TCO2_set_input_MSB                0x40000000
164 #define HDSPM_TCO2_set_freq_from_app            0x80000000
165
166
167 #define HDSPM_midiDataOut0    352
168 #define HDSPM_midiDataOut1    356
169 #define HDSPM_midiDataOut2    368
170
171 #define HDSPM_midiDataIn0     360
172 #define HDSPM_midiDataIn1     364
173 #define HDSPM_midiDataIn2     372
174 #define HDSPM_midiDataIn3     376
175
176 /* status is data bytes in MIDI-FIFO (0-128) */
177 #define HDSPM_midiStatusOut0  384
178 #define HDSPM_midiStatusOut1  388
179 #define HDSPM_midiStatusOut2  400
180
181 #define HDSPM_midiStatusIn0   392
182 #define HDSPM_midiStatusIn1   396
183 #define HDSPM_midiStatusIn2   404
184 #define HDSPM_midiStatusIn3   408
185
186
187 /* the meters are regular i/o-mapped registers, but offset
188    considerably from the rest. the peak registers are reset
189    when read; the least-significant 4 bits are full-scale counters;
190    the actual peak value is in the most-significant 24 bits.
191 */
192
193 #define HDSPM_MADI_INPUT_PEAK           4096
194 #define HDSPM_MADI_PLAYBACK_PEAK        4352
195 #define HDSPM_MADI_OUTPUT_PEAK          4608
196
197 #define HDSPM_MADI_INPUT_RMS_L          6144
198 #define HDSPM_MADI_PLAYBACK_RMS_L       6400
199 #define HDSPM_MADI_OUTPUT_RMS_L         6656
200
201 #define HDSPM_MADI_INPUT_RMS_H          7168
202 #define HDSPM_MADI_PLAYBACK_RMS_H       7424
203 #define HDSPM_MADI_OUTPUT_RMS_H         7680
204
205 /* --- Control Register bits --------- */
206 #define HDSPM_Start                (1<<0) /* start engine */
207
208 #define HDSPM_Latency0             (1<<1) /* buffer size = 2^n */
209 #define HDSPM_Latency1             (1<<2) /* where n is defined */
210 #define HDSPM_Latency2             (1<<3) /* by Latency{2,1,0} */
211
212 #define HDSPM_ClockModeMaster      (1<<4) /* 1=Master, 0=Autosync */
213 #define HDSPM_c0Master          0x1    /* Master clock bit in settings
214                                           register [RayDAT, AIO] */
215
216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
217
218 #define HDSPM_Frequency0  (1<<6)  /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
219 #define HDSPM_Frequency1  (1<<7)  /* 0=32kHz/64kHz */
220 #define HDSPM_DoubleSpeed (1<<8)  /* 0=normal speed, 1=double speed */
221 #define HDSPM_QuadSpeed   (1<<31) /* quad speed bit */
222
223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
224 #define HDSPM_TX_64ch     (1<<10) /* Output 64channel MODE=1,
225                                      56channelMODE=0 */ /* MADI ONLY*/
226 #define HDSPM_Emphasis    (1<<10) /* Emphasis */ /* AES32 ONLY */
227
228 #define HDSPM_AutoInp     (1<<11) /* Auto Input (takeover) == Safe Mode,
229                                      0=off, 1=on  */ /* MADI ONLY */
230 #define HDSPM_Dolby       (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
231
232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
233                                     * -- MADI ONLY
234                                     */
235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
236
237 #define HDSPM_SyncRef2     (1<<13)
238 #define HDSPM_SyncRef3     (1<<25)
239
240 #define HDSPM_SMUX         (1<<18) /* Frame ??? */ /* MADI ONY */
241 #define HDSPM_clr_tms      (1<<19) /* clear track marker, do not use
242                                       AES additional bits in
243                                       lower 5 Audiodatabits ??? */
244 #define HDSPM_taxi_reset   (1<<20) /* ??? */ /* MADI ONLY ? */
245 #define HDSPM_WCK48        (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
246
247 #define HDSPM_Midi0InterruptEnable 0x0400000
248 #define HDSPM_Midi1InterruptEnable 0x0800000
249 #define HDSPM_Midi2InterruptEnable 0x0200000
250 #define HDSPM_Midi3InterruptEnable 0x4000000
251
252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
253 #define HDSPe_FLOAT_FORMAT         0x2000000
254
255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
257 #define HDSPM_QS_QuadWire   (1<<28) /* AES32 ONLY */
258
259 #define HDSPM_wclk_sel (1<<30)
260
261 /* --- bit helper defines */
262 #define HDSPM_LatencyMask    (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
263 #define HDSPM_FrequencyMask  (HDSPM_Frequency0|HDSPM_Frequency1|\
264                               HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
265 #define HDSPM_InputMask      (HDSPM_InputSelect0|HDSPM_InputSelect1)
266 #define HDSPM_InputOptical   0
267 #define HDSPM_InputCoaxial   (HDSPM_InputSelect0)
268 #define HDSPM_SyncRefMask    (HDSPM_SyncRef0|HDSPM_SyncRef1|\
269                               HDSPM_SyncRef2|HDSPM_SyncRef3)
270
271 #define HDSPM_c0_SyncRef0      0x2
272 #define HDSPM_c0_SyncRef1      0x4
273 #define HDSPM_c0_SyncRef2      0x8
274 #define HDSPM_c0_SyncRef3      0x10
275 #define HDSPM_c0_SyncRefMask   (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
276                                 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
277
278 #define HDSPM_SYNC_FROM_WORD    0       /* Preferred sync reference */
279 #define HDSPM_SYNC_FROM_MADI    1       /* choices - used by "pref_sync_ref" */
280 #define HDSPM_SYNC_FROM_TCO     2
281 #define HDSPM_SYNC_FROM_SYNC_IN 3
282
283 #define HDSPM_Frequency32KHz    HDSPM_Frequency0
284 #define HDSPM_Frequency44_1KHz  HDSPM_Frequency1
285 #define HDSPM_Frequency48KHz   (HDSPM_Frequency1|HDSPM_Frequency0)
286 #define HDSPM_Frequency64KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency0)
287 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
288 #define HDSPM_Frequency96KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
289                                 HDSPM_Frequency0)
290 #define HDSPM_Frequency128KHz   (HDSPM_QuadSpeed|HDSPM_Frequency0)
291 #define HDSPM_Frequency176_4KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1)
292 #define HDSPM_Frequency192KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1|\
293                                  HDSPM_Frequency0)
294
295
296 /* Synccheck Status */
297 #define HDSPM_SYNC_CHECK_NO_LOCK 0
298 #define HDSPM_SYNC_CHECK_LOCK    1
299 #define HDSPM_SYNC_CHECK_SYNC    2
300
301 /* AutoSync References - used by "autosync_ref" control switch */
302 #define HDSPM_AUTOSYNC_FROM_WORD      0
303 #define HDSPM_AUTOSYNC_FROM_MADI      1
304 #define HDSPM_AUTOSYNC_FROM_TCO       2
305 #define HDSPM_AUTOSYNC_FROM_SYNC_IN   3
306 #define HDSPM_AUTOSYNC_FROM_NONE      4
307
308 /* Possible sources of MADI input */
309 #define HDSPM_OPTICAL 0         /* optical   */
310 #define HDSPM_COAXIAL 1         /* BNC */
311
312 #define hdspm_encode_latency(x)       (((x)<<1) & HDSPM_LatencyMask)
313 #define hdspm_decode_latency(x)       ((((x) & HDSPM_LatencyMask)>>1))
314
315 #define hdspm_encode_in(x) (((x)&0x3)<<14)
316 #define hdspm_decode_in(x) (((x)>>14)&0x3)
317
318 /* --- control2 register bits --- */
319 #define HDSPM_TMS             (1<<0)
320 #define HDSPM_TCK             (1<<1)
321 #define HDSPM_TDI             (1<<2)
322 #define HDSPM_JTAG            (1<<3)
323 #define HDSPM_PWDN            (1<<4)
324 #define HDSPM_PROGRAM         (1<<5)
325 #define HDSPM_CONFIG_MODE_0   (1<<6)
326 #define HDSPM_CONFIG_MODE_1   (1<<7)
327 /*#define HDSPM_VERSION_BIT     (1<<8) not defined any more*/
328 #define HDSPM_BIGENDIAN_MODE  (1<<9)
329 #define HDSPM_RD_MULTIPLE     (1<<10)
330
331 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
332      that do not conflict with specific bits for AES32 seem to be valid also
333      for the AES32
334  */
335 #define HDSPM_audioIRQPending    (1<<0) /* IRQ is high and pending */
336 #define HDSPM_RX_64ch            (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
337 #define HDSPM_AB_int             (1<<2) /* InputChannel Opt=0, Coax=1
338                                          * (like inp0)
339                                          */
340
341 #define HDSPM_madiLock           (1<<3) /* MADI Locked =1, no=0 */
342 #define HDSPM_madiSync          (1<<18) /* MADI is in sync */
343
344 #define HDSPM_tcoLock    0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */
345 #define HDSPM_tcoSync    0x10000000 /* Optional TCO sync status */
346
347 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */
348 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */
349
350 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
351                         /* since 64byte accurate, last 6 bits are not used */
352
353
354
355 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
356
357 #define HDSPM_madiFreq0         (1<<22) /* system freq 0=error */
358 #define HDSPM_madiFreq1         (1<<23) /* 1=32, 2=44.1 3=48 */
359 #define HDSPM_madiFreq2         (1<<24) /* 4=64, 5=88.2 6=96 */
360 #define HDSPM_madiFreq3         (1<<25) /* 7=128, 8=176.4 9=192 */
361
362 #define HDSPM_BufferID          (1<<26) /* (Double)Buffer ID toggles with
363                                          * Interrupt
364                                          */
365 #define HDSPM_tco_detect         0x08000000
366 #define HDSPM_tco_lock           0x20000000
367
368 #define HDSPM_s2_tco_detect      0x00000040
369 #define HDSPM_s2_AEBO_D          0x00000080
370 #define HDSPM_s2_AEBI_D          0x00000100
371
372
373 #define HDSPM_midi0IRQPending    0x40000000
374 #define HDSPM_midi1IRQPending    0x80000000
375 #define HDSPM_midi2IRQPending    0x20000000
376 #define HDSPM_midi2IRQPendingAES 0x00000020
377 #define HDSPM_midi3IRQPending    0x00200000
378
379 /* --- status bit helpers */
380 #define HDSPM_madiFreqMask  (HDSPM_madiFreq0|HDSPM_madiFreq1|\
381                              HDSPM_madiFreq2|HDSPM_madiFreq3)
382 #define HDSPM_madiFreq32    (HDSPM_madiFreq0)
383 #define HDSPM_madiFreq44_1  (HDSPM_madiFreq1)
384 #define HDSPM_madiFreq48    (HDSPM_madiFreq0|HDSPM_madiFreq1)
385 #define HDSPM_madiFreq64    (HDSPM_madiFreq2)
386 #define HDSPM_madiFreq88_2  (HDSPM_madiFreq0|HDSPM_madiFreq2)
387 #define HDSPM_madiFreq96    (HDSPM_madiFreq1|HDSPM_madiFreq2)
388 #define HDSPM_madiFreq128   (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
389 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
390 #define HDSPM_madiFreq192   (HDSPM_madiFreq3|HDSPM_madiFreq0)
391
392 /* Status2 Register bits */ /* MADI ONLY */
393
394 #define HDSPM_version0 (1<<0)   /* not really defined but I guess */
395 #define HDSPM_version1 (1<<1)   /* in former cards it was ??? */
396 #define HDSPM_version2 (1<<2)
397
398 #define HDSPM_wcLock (1<<3)     /* Wordclock is detected and locked */
399 #define HDSPM_wcSync (1<<4)     /* Wordclock is in sync with systemclock */
400
401 #define HDSPM_wc_freq0 (1<<5)   /* input freq detected via autosync  */
402 #define HDSPM_wc_freq1 (1<<6)   /* 001=32, 010==44.1, 011=48, */
403 #define HDSPM_wc_freq2 (1<<7)   /* 100=64, 101=88.2, 110=96, */
404 /* missing Bit   for               111=128, 1000=176.4, 1001=192 */
405
406 #define HDSPM_SyncRef0 0x10000  /* Sync Reference */
407 #define HDSPM_SyncRef1 0x20000
408
409 #define HDSPM_SelSyncRef0 (1<<8)        /* AutoSync Source */
410 #define HDSPM_SelSyncRef1 (1<<9)        /* 000=word, 001=MADI, */
411 #define HDSPM_SelSyncRef2 (1<<10)       /* 111=no valid signal */
412
413 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
414
415 #define HDSPM_wcFreqMask  (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
416 #define HDSPM_wcFreq32    (HDSPM_wc_freq0)
417 #define HDSPM_wcFreq44_1  (HDSPM_wc_freq1)
418 #define HDSPM_wcFreq48    (HDSPM_wc_freq0|HDSPM_wc_freq1)
419 #define HDSPM_wcFreq64    (HDSPM_wc_freq2)
420 #define HDSPM_wcFreq88_2  (HDSPM_wc_freq0|HDSPM_wc_freq2)
421 #define HDSPM_wcFreq96    (HDSPM_wc_freq1|HDSPM_wc_freq2)
422
423 #define HDSPM_status1_F_0 0x0400000
424 #define HDSPM_status1_F_1 0x0800000
425 #define HDSPM_status1_F_2 0x1000000
426 #define HDSPM_status1_F_3 0x2000000
427 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
428
429
430 #define HDSPM_SelSyncRefMask       (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
431                                     HDSPM_SelSyncRef2)
432 #define HDSPM_SelSyncRef_WORD      0
433 #define HDSPM_SelSyncRef_MADI      (HDSPM_SelSyncRef0)
434 #define HDSPM_SelSyncRef_TCO       (HDSPM_SelSyncRef1)
435 #define HDSPM_SelSyncRef_SyncIn    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
436 #define HDSPM_SelSyncRef_NVALID    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
437                                     HDSPM_SelSyncRef2)
438
439 /*
440    For AES32, bits for status, status2 and timecode are different
441 */
442 /* status */
443 #define HDSPM_AES32_wcLock      0x0200000
444 #define HDSPM_AES32_wcFreq_bit  22
445 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
446   HDSPM_bit2freq */
447 #define HDSPM_AES32_syncref_bit  16
448 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
449
450 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
451 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
452 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
453 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
454 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
455 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
456 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
457 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
458 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
459 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9
460
461 /*  status2 */
462 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
463 #define HDSPM_LockAES   0x80
464 #define HDSPM_LockAES1  0x80
465 #define HDSPM_LockAES2  0x40
466 #define HDSPM_LockAES3  0x20
467 #define HDSPM_LockAES4  0x10
468 #define HDSPM_LockAES5  0x8
469 #define HDSPM_LockAES6  0x4
470 #define HDSPM_LockAES7  0x2
471 #define HDSPM_LockAES8  0x1
472 /*
473    Timecode
474    After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
475    AES i+1
476  bits 3210
477       0001  32kHz
478       0010  44.1kHz
479       0011  48kHz
480       0100  64kHz
481       0101  88.2kHz
482       0110  96kHz
483       0111  128kHz
484       1000  176.4kHz
485       1001  192kHz
486   NB: Timecode register doesn't seem to work on AES32 card revision 230
487 */
488
489 /* Mixer Values */
490 #define UNITY_GAIN          32768       /* = 65536/2 */
491 #define MINUS_INFINITY_GAIN 0
492
493 /* Number of channels for different Speed Modes */
494 #define MADI_SS_CHANNELS       64
495 #define MADI_DS_CHANNELS       32
496 #define MADI_QS_CHANNELS       16
497
498 #define RAYDAT_SS_CHANNELS     36
499 #define RAYDAT_DS_CHANNELS     20
500 #define RAYDAT_QS_CHANNELS     12
501
502 #define AIO_IN_SS_CHANNELS        14
503 #define AIO_IN_DS_CHANNELS        10
504 #define AIO_IN_QS_CHANNELS        8
505 #define AIO_OUT_SS_CHANNELS        16
506 #define AIO_OUT_DS_CHANNELS        12
507 #define AIO_OUT_QS_CHANNELS        10
508
509 #define AES32_CHANNELS          16
510
511 /* the size of a substream (1 mono data stream) */
512 #define HDSPM_CHANNEL_BUFFER_SAMPLES  (16*1024)
513 #define HDSPM_CHANNEL_BUFFER_BYTES    (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
514
515 /* the size of the area we need to allocate for DMA transfers. the
516    size is the same regardless of the number of channels, and
517    also the latency to use.
518    for one direction !!!
519 */
520 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
521 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
522
523 /* revisions >= 230 indicate AES32 card */
524 #define HDSPM_MADI_ANCIENT_REV  204
525 #define HDSPM_MADI_OLD_REV      207
526 #define HDSPM_MADI_REV          210
527 #define HDSPM_RAYDAT_REV        211
528 #define HDSPM_AIO_REV           212
529 #define HDSPM_MADIFACE_REV      213
530 #define HDSPM_AES_REV           240
531 #define HDSPM_AES32_REV         234
532 #define HDSPM_AES32_OLD_REV     233
533
534 /* speed factor modes */
535 #define HDSPM_SPEED_SINGLE 0
536 #define HDSPM_SPEED_DOUBLE 1
537 #define HDSPM_SPEED_QUAD   2
538
539 /* names for speed modes */
540 static char *hdspm_speed_names[] = { "single", "double", "quad" };
541
542 static char *texts_autosync_aes_tco[] = { "Word Clock",
543                                           "AES1", "AES2", "AES3", "AES4",
544                                           "AES5", "AES6", "AES7", "AES8",
545                                           "TCO" };
546 static char *texts_autosync_aes[] = { "Word Clock",
547                                       "AES1", "AES2", "AES3", "AES4",
548                                       "AES5", "AES6", "AES7", "AES8" };
549 static char *texts_autosync_madi_tco[] = { "Word Clock",
550                                            "MADI", "TCO", "Sync In" };
551 static char *texts_autosync_madi[] = { "Word Clock",
552                                        "MADI", "Sync In" };
553
554 static char *texts_autosync_raydat_tco[] = {
555         "Word Clock",
556         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
557         "AES", "SPDIF", "TCO", "Sync In"
558 };
559 static char *texts_autosync_raydat[] = {
560         "Word Clock",
561         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
562         "AES", "SPDIF", "Sync In"
563 };
564 static char *texts_autosync_aio_tco[] = {
565         "Word Clock",
566         "ADAT", "AES", "SPDIF", "TCO", "Sync In"
567 };
568 static char *texts_autosync_aio[] = { "Word Clock",
569                                       "ADAT", "AES", "SPDIF", "Sync In" };
570
571 static char *texts_freq[] = {
572         "No Lock",
573         "32 kHz",
574         "44.1 kHz",
575         "48 kHz",
576         "64 kHz",
577         "88.2 kHz",
578         "96 kHz",
579         "128 kHz",
580         "176.4 kHz",
581         "192 kHz"
582 };
583
584 static char *texts_ports_madi[] = {
585         "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
586         "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
587         "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
588         "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
589         "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
590         "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
591         "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
592         "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
593         "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
594         "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
595         "MADI.61", "MADI.62", "MADI.63", "MADI.64",
596 };
597
598
599 static char *texts_ports_raydat_ss[] = {
600         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
601         "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
602         "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
603         "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
604         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
605         "ADAT4.7", "ADAT4.8",
606         "AES.L", "AES.R",
607         "SPDIF.L", "SPDIF.R"
608 };
609
610 static char *texts_ports_raydat_ds[] = {
611         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
612         "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
613         "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
614         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
615         "AES.L", "AES.R",
616         "SPDIF.L", "SPDIF.R"
617 };
618
619 static char *texts_ports_raydat_qs[] = {
620         "ADAT1.1", "ADAT1.2",
621         "ADAT2.1", "ADAT2.2",
622         "ADAT3.1", "ADAT3.2",
623         "ADAT4.1", "ADAT4.2",
624         "AES.L", "AES.R",
625         "SPDIF.L", "SPDIF.R"
626 };
627
628
629 static char *texts_ports_aio_in_ss[] = {
630         "Analogue.L", "Analogue.R",
631         "AES.L", "AES.R",
632         "SPDIF.L", "SPDIF.R",
633         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
634         "ADAT.7", "ADAT.8"
635 };
636
637 static char *texts_ports_aio_out_ss[] = {
638         "Analogue.L", "Analogue.R",
639         "AES.L", "AES.R",
640         "SPDIF.L", "SPDIF.R",
641         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
642         "ADAT.7", "ADAT.8",
643         "Phone.L", "Phone.R"
644 };
645
646 static char *texts_ports_aio_in_ds[] = {
647         "Analogue.L", "Analogue.R",
648         "AES.L", "AES.R",
649         "SPDIF.L", "SPDIF.R",
650         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
651 };
652
653 static char *texts_ports_aio_out_ds[] = {
654         "Analogue.L", "Analogue.R",
655         "AES.L", "AES.R",
656         "SPDIF.L", "SPDIF.R",
657         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
658         "Phone.L", "Phone.R"
659 };
660
661 static char *texts_ports_aio_in_qs[] = {
662         "Analogue.L", "Analogue.R",
663         "AES.L", "AES.R",
664         "SPDIF.L", "SPDIF.R",
665         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
666 };
667
668 static char *texts_ports_aio_out_qs[] = {
669         "Analogue.L", "Analogue.R",
670         "AES.L", "AES.R",
671         "SPDIF.L", "SPDIF.R",
672         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
673         "Phone.L", "Phone.R"
674 };
675
676 static char *texts_ports_aes32[] = {
677         "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
678         "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
679         "AES.15", "AES.16"
680 };
681
682 /* These tables map the ALSA channels 1..N to the channels that we
683    need to use in order to find the relevant channel buffer. RME
684    refers to this kind of mapping as between "the ADAT channel and
685    the DMA channel." We index it using the logical audio channel,
686    and the value is the DMA channel (i.e. channel buffer number)
687    where the data for that channel can be read/written from/to.
688 */
689
690 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
691         0, 1, 2, 3, 4, 5, 6, 7,
692         8, 9, 10, 11, 12, 13, 14, 15,
693         16, 17, 18, 19, 20, 21, 22, 23,
694         24, 25, 26, 27, 28, 29, 30, 31,
695         32, 33, 34, 35, 36, 37, 38, 39,
696         40, 41, 42, 43, 44, 45, 46, 47,
697         48, 49, 50, 51, 52, 53, 54, 55,
698         56, 57, 58, 59, 60, 61, 62, 63
699 };
700
701 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
702         4, 5, 6, 7, 8, 9, 10, 11,       /* ADAT 1 */
703         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
704         20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
705         28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
706         0, 1,                   /* AES */
707         2, 3,                   /* SPDIF */
708         -1, -1, -1, -1,
709         -1, -1, -1, -1, -1, -1, -1, -1,
710         -1, -1, -1, -1, -1, -1, -1, -1,
711         -1, -1, -1, -1, -1, -1, -1, -1,
712 };
713
714 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
715         4, 5, 6, 7,             /* ADAT 1 */
716         8, 9, 10, 11,           /* ADAT 2 */
717         12, 13, 14, 15,         /* ADAT 3 */
718         16, 17, 18, 19,         /* ADAT 4 */
719         0, 1,                   /* AES */
720         2, 3,                   /* SPDIF */
721         -1, -1, -1, -1,
722         -1, -1, -1, -1, -1, -1, -1, -1,
723         -1, -1, -1, -1, -1, -1, -1, -1,
724         -1, -1, -1, -1, -1, -1, -1, -1,
725         -1, -1, -1, -1, -1, -1, -1, -1,
726         -1, -1, -1, -1, -1, -1, -1, -1,
727 };
728
729 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
730         4, 5,                   /* ADAT 1 */
731         6, 7,                   /* ADAT 2 */
732         8, 9,                   /* ADAT 3 */
733         10, 11,                 /* ADAT 4 */
734         0, 1,                   /* AES */
735         2, 3,                   /* SPDIF */
736         -1, -1, -1, -1,
737         -1, -1, -1, -1, -1, -1, -1, -1,
738         -1, -1, -1, -1, -1, -1, -1, -1,
739         -1, -1, -1, -1, -1, -1, -1, -1,
740         -1, -1, -1, -1, -1, -1, -1, -1,
741         -1, -1, -1, -1, -1, -1, -1, -1,
742         -1, -1, -1, -1, -1, -1, -1, -1,
743 };
744
745 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
746         0, 1,                   /* line in */
747         8, 9,                   /* aes in, */
748         10, 11,                 /* spdif in */
749         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
750         -1, -1,
751         -1, -1, -1, -1, -1, -1, -1, -1,
752         -1, -1, -1, -1, -1, -1, -1, -1,
753         -1, -1, -1, -1, -1, -1, -1, -1,
754         -1, -1, -1, -1, -1, -1, -1, -1,
755         -1, -1, -1, -1, -1, -1, -1, -1,
756         -1, -1, -1, -1, -1, -1, -1, -1,
757 };
758
759 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
760         0, 1,                   /* line out */
761         8, 9,                   /* aes out */
762         10, 11,                 /* spdif out */
763         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
764         6, 7,                   /* phone out */
765         -1, -1, -1, -1, -1, -1, -1, -1,
766         -1, -1, -1, -1, -1, -1, -1, -1,
767         -1, -1, -1, -1, -1, -1, -1, -1,
768         -1, -1, -1, -1, -1, -1, -1, -1,
769         -1, -1, -1, -1, -1, -1, -1, -1,
770         -1, -1, -1, -1, -1, -1, -1, -1,
771 };
772
773 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
774         0, 1,                   /* line in */
775         8, 9,                   /* aes in */
776         10, 11,                 /* spdif in */
777         12, 14, 16, 18,         /* adat in */
778         -1, -1, -1, -1, -1, -1,
779         -1, -1, -1, -1, -1, -1, -1, -1,
780         -1, -1, -1, -1, -1, -1, -1, -1,
781         -1, -1, -1, -1, -1, -1, -1, -1,
782         -1, -1, -1, -1, -1, -1, -1, -1,
783         -1, -1, -1, -1, -1, -1, -1, -1,
784         -1, -1, -1, -1, -1, -1, -1, -1
785 };
786
787 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
788         0, 1,                   /* line out */
789         8, 9,                   /* aes out */
790         10, 11,                 /* spdif out */
791         12, 14, 16, 18,         /* adat out */
792         6, 7,                   /* phone out */
793         -1, -1, -1, -1,
794         -1, -1, -1, -1, -1, -1, -1, -1,
795         -1, -1, -1, -1, -1, -1, -1, -1,
796         -1, -1, -1, -1, -1, -1, -1, -1,
797         -1, -1, -1, -1, -1, -1, -1, -1,
798         -1, -1, -1, -1, -1, -1, -1, -1,
799         -1, -1, -1, -1, -1, -1, -1, -1
800 };
801
802 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
803         0, 1,                   /* line in */
804         8, 9,                   /* aes in */
805         10, 11,                 /* spdif in */
806         12, 16,                 /* adat in */
807         -1, -1, -1, -1, -1, -1, -1, -1,
808         -1, -1, -1, -1, -1, -1, -1, -1,
809         -1, -1, -1, -1, -1, -1, -1, -1,
810         -1, -1, -1, -1, -1, -1, -1, -1,
811         -1, -1, -1, -1, -1, -1, -1, -1,
812         -1, -1, -1, -1, -1, -1, -1, -1,
813         -1, -1, -1, -1, -1, -1, -1, -1
814 };
815
816 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
817         0, 1,                   /* line out */
818         8, 9,                   /* aes out */
819         10, 11,                 /* spdif out */
820         12, 16,                 /* adat out */
821         6, 7,                   /* phone out */
822         -1, -1, -1, -1, -1, -1,
823         -1, -1, -1, -1, -1, -1, -1, -1,
824         -1, -1, -1, -1, -1, -1, -1, -1,
825         -1, -1, -1, -1, -1, -1, -1, -1,
826         -1, -1, -1, -1, -1, -1, -1, -1,
827         -1, -1, -1, -1, -1, -1, -1, -1,
828         -1, -1, -1, -1, -1, -1, -1, -1
829 };
830
831 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
832         0, 1, 2, 3, 4, 5, 6, 7,
833         8, 9, 10, 11, 12, 13, 14, 15,
834         -1, -1, -1, -1, -1, -1, -1, -1,
835         -1, -1, -1, -1, -1, -1, -1, -1,
836         -1, -1, -1, -1, -1, -1, -1, -1,
837         -1, -1, -1, -1, -1, -1, -1, -1,
838         -1, -1, -1, -1, -1, -1, -1, -1,
839         -1, -1, -1, -1, -1, -1, -1, -1
840 };
841
842 struct hdspm_midi {
843         struct hdspm *hdspm;
844         int id;
845         struct snd_rawmidi *rmidi;
846         struct snd_rawmidi_substream *input;
847         struct snd_rawmidi_substream *output;
848         char istimer;           /* timer in use */
849         struct timer_list timer;
850         spinlock_t lock;
851         int pending;
852         int dataIn;
853         int statusIn;
854         int dataOut;
855         int statusOut;
856         int ie;
857         int irq;
858 };
859
860 struct hdspm_tco {
861         int input;
862         int framerate;
863         int wordclock;
864         int samplerate;
865         int pull;
866         int term; /* 0 = off, 1 = on */
867 };
868
869 struct hdspm {
870         spinlock_t lock;
871         /* only one playback and/or capture stream */
872         struct snd_pcm_substream *capture_substream;
873         struct snd_pcm_substream *playback_substream;
874
875         char *card_name;             /* for procinfo */
876         unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
877
878         uint8_t io_type;
879
880         int monitor_outs;       /* set up monitoring outs init flag */
881
882         u32 control_register;   /* cached value */
883         u32 control2_register;  /* cached value */
884         u32 settings_register;
885
886         struct hdspm_midi midi[4];
887         struct tasklet_struct midi_tasklet;
888
889         size_t period_bytes;
890         unsigned char ss_in_channels;
891         unsigned char ds_in_channels;
892         unsigned char qs_in_channels;
893         unsigned char ss_out_channels;
894         unsigned char ds_out_channels;
895         unsigned char qs_out_channels;
896
897         unsigned char max_channels_in;
898         unsigned char max_channels_out;
899
900         signed char *channel_map_in;
901         signed char *channel_map_out;
902
903         signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
904         signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
905
906         char **port_names_in;
907         char **port_names_out;
908
909         char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
910         char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
911
912         unsigned char *playback_buffer; /* suitably aligned address */
913         unsigned char *capture_buffer;  /* suitably aligned address */
914
915         pid_t capture_pid;      /* process id which uses capture */
916         pid_t playback_pid;     /* process id which uses capture */
917         int running;            /* running status */
918
919         int last_external_sample_rate;  /* samplerate mystic ... */
920         int last_internal_sample_rate;
921         int system_sample_rate;
922
923         int dev;                /* Hardware vars... */
924         int irq;
925         unsigned long port;
926         void __iomem *iobase;
927
928         int irq_count;          /* for debug */
929         int midiPorts;
930
931         struct snd_card *card;  /* one card */
932         struct snd_pcm *pcm;            /* has one pcm */
933         struct snd_hwdep *hwdep;        /* and a hwdep for additional ioctl */
934         struct pci_dev *pci;    /* and an pci info */
935
936         /* Mixer vars */
937         /* fast alsa mixer */
938         struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
939         /* but input to much, so not used */
940         struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
941         /* full mixer accessible over mixer ioctl or hwdep-device */
942         struct hdspm_mixer *mixer;
943
944         struct hdspm_tco *tco;  /* NULL if no TCO detected */
945
946         char **texts_autosync;
947         int texts_autosync_items;
948
949         cycles_t last_interrupt;
950
951         struct hdspm_peak_rms peak_rms;
952 };
953
954
955 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
956         {
957          .vendor = PCI_VENDOR_ID_XILINX,
958          .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
959          .subvendor = PCI_ANY_ID,
960          .subdevice = PCI_ANY_ID,
961          .class = 0,
962          .class_mask = 0,
963          .driver_data = 0},
964         {0,}
965 };
966
967 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
968
969 /* prototypes */
970 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
971                                                    struct hdspm * hdspm);
972 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
973                                           struct hdspm * hdspm);
974
975 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
976 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
977 static int hdspm_autosync_ref(struct hdspm *hdspm);
978 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
979 static void hdspm_set_sgbuf(struct hdspm *hdspm,
980                             struct snd_pcm_substream *substream,
981                              unsigned int reg, int channels);
982
983 static inline int HDSPM_bit2freq(int n)
984 {
985         static const int bit2freq_tab[] = {
986                 0, 32000, 44100, 48000, 64000, 88200,
987                 96000, 128000, 176400, 192000 };
988         if (n < 1 || n > 9)
989                 return 0;
990         return bit2freq_tab[n];
991 }
992
993 /* Write/read to/from HDSPM with Adresses in Bytes
994    not words but only 32Bit writes are allowed */
995
996 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
997                                unsigned int val)
998 {
999         writel(val, hdspm->iobase + reg);
1000 }
1001
1002 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1003 {
1004         return readl(hdspm->iobase + reg);
1005 }
1006
1007 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1008    mixer is write only on hardware so we have to cache him for read
1009    each fader is a u32, but uses only the first 16 bit */
1010
1011 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1012                                      unsigned int in)
1013 {
1014         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1015                 return 0;
1016
1017         return hdspm->mixer->ch[chan].in[in];
1018 }
1019
1020 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1021                                      unsigned int pb)
1022 {
1023         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1024                 return 0;
1025         return hdspm->mixer->ch[chan].pb[pb];
1026 }
1027
1028 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1029                                       unsigned int in, unsigned short data)
1030 {
1031         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1032                 return -1;
1033
1034         hdspm_write(hdspm,
1035                     HDSPM_MADI_mixerBase +
1036                     ((in + 128 * chan) * sizeof(u32)),
1037                     (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1038         return 0;
1039 }
1040
1041 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1042                                       unsigned int pb, unsigned short data)
1043 {
1044         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1045                 return -1;
1046
1047         hdspm_write(hdspm,
1048                     HDSPM_MADI_mixerBase +
1049                     ((64 + pb + 128 * chan) * sizeof(u32)),
1050                     (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1051         return 0;
1052 }
1053
1054
1055 /* enable DMA for specific channels, now available for DSP-MADI */
1056 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1057 {
1058         hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1059 }
1060
1061 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1062 {
1063         hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1064 }
1065
1066 /* check if same process is writing and reading */
1067 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1068 {
1069         unsigned long flags;
1070         int ret = 1;
1071
1072         spin_lock_irqsave(&hdspm->lock, flags);
1073         if ((hdspm->playback_pid != hdspm->capture_pid) &&
1074             (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1075                 ret = 0;
1076         }
1077         spin_unlock_irqrestore(&hdspm->lock, flags);
1078         return ret;
1079 }
1080
1081 /* check for external sample rate */
1082 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1083 {
1084         unsigned int status, status2, timecode;
1085         int syncref, rate = 0, rate_bits;
1086
1087         switch (hdspm->io_type) {
1088         case AES32:
1089                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1090                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1091                 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
1092
1093                 syncref = hdspm_autosync_ref(hdspm);
1094
1095                 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
1096                                 status & HDSPM_AES32_wcLock)
1097                         return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF);
1098
1099                 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
1100                                 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
1101                                 status2 & (HDSPM_LockAES >>
1102                                 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
1103                         return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
1104                 return 0;
1105                 break;
1106
1107         case MADIface:
1108                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1109
1110                 if (!(status & HDSPM_madiLock)) {
1111                         rate = 0;  /* no lock */
1112                 } else {
1113                         switch (status & (HDSPM_status1_freqMask)) {
1114                         case HDSPM_status1_F_0*1:
1115                                 rate = 32000; break;
1116                         case HDSPM_status1_F_0*2:
1117                                 rate = 44100; break;
1118                         case HDSPM_status1_F_0*3:
1119                                 rate = 48000; break;
1120                         case HDSPM_status1_F_0*4:
1121                                 rate = 64000; break;
1122                         case HDSPM_status1_F_0*5:
1123                                 rate = 88200; break;
1124                         case HDSPM_status1_F_0*6:
1125                                 rate = 96000; break;
1126                         case HDSPM_status1_F_0*7:
1127                                 rate = 128000; break;
1128                         case HDSPM_status1_F_0*8:
1129                                 rate = 176400; break;
1130                         case HDSPM_status1_F_0*9:
1131                                 rate = 192000; break;
1132                         default:
1133                                 rate = 0; break;
1134                         }
1135                 }
1136
1137                 break;
1138
1139         case MADI:
1140         case AIO:
1141         case RayDAT:
1142                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1143                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1144                 rate = 0;
1145
1146                 /* if wordclock has synced freq and wordclock is valid */
1147                 if ((status2 & HDSPM_wcLock) != 0 &&
1148                                 (status2 & HDSPM_SelSyncRef0) == 0) {
1149
1150                         rate_bits = status2 & HDSPM_wcFreqMask;
1151
1152
1153                         switch (rate_bits) {
1154                         case HDSPM_wcFreq32:
1155                                 rate = 32000;
1156                                 break;
1157                         case HDSPM_wcFreq44_1:
1158                                 rate = 44100;
1159                                 break;
1160                         case HDSPM_wcFreq48:
1161                                 rate = 48000;
1162                                 break;
1163                         case HDSPM_wcFreq64:
1164                                 rate = 64000;
1165                                 break;
1166                         case HDSPM_wcFreq88_2:
1167                                 rate = 88200;
1168                                 break;
1169                         case HDSPM_wcFreq96:
1170                                 rate = 96000;
1171                                 break;
1172                         default:
1173                                 rate = 0;
1174                                 break;
1175                         }
1176                 }
1177
1178                 /* if rate detected and Syncref is Word than have it,
1179                  * word has priority to MADI
1180                  */
1181                 if (rate != 0 &&
1182                 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1183                         return rate;
1184
1185                 /* maybe a madi input (which is taken if sel sync is madi) */
1186                 if (status & HDSPM_madiLock) {
1187                         rate_bits = status & HDSPM_madiFreqMask;
1188
1189                         switch (rate_bits) {
1190                         case HDSPM_madiFreq32:
1191                                 rate = 32000;
1192                                 break;
1193                         case HDSPM_madiFreq44_1:
1194                                 rate = 44100;
1195                                 break;
1196                         case HDSPM_madiFreq48:
1197                                 rate = 48000;
1198                                 break;
1199                         case HDSPM_madiFreq64:
1200                                 rate = 64000;
1201                                 break;
1202                         case HDSPM_madiFreq88_2:
1203                                 rate = 88200;
1204                                 break;
1205                         case HDSPM_madiFreq96:
1206                                 rate = 96000;
1207                                 break;
1208                         case HDSPM_madiFreq128:
1209                                 rate = 128000;
1210                                 break;
1211                         case HDSPM_madiFreq176_4:
1212                                 rate = 176400;
1213                                 break;
1214                         case HDSPM_madiFreq192:
1215                                 rate = 192000;
1216                                 break;
1217                         default:
1218                                 rate = 0;
1219                                 break;
1220                         }
1221
1222                         /* QS and DS rates normally can not be detected
1223                          * automatically by the card. Only exception is MADI
1224                          * in 96k frame mode.
1225                          *
1226                          * So if we read SS values (32 .. 48k), check for
1227                          * user-provided DS/QS bits in the control register
1228                          * and multiply the base frequency accordingly.
1229                          */
1230                         if (rate <= 48000) {
1231                                 if (hdspm->control_register & HDSPM_QuadSpeed)
1232                                         rate *= 4;
1233                                 else if (hdspm->control_register &
1234                                                 HDSPM_DoubleSpeed)
1235                                         rate *= 2;
1236                         }
1237                 }
1238                 break;
1239         }
1240
1241         return rate;
1242 }
1243
1244 /* Latency function */
1245 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1246 {
1247         hdspm->period_bytes = 1 << ((hdspm_decode_latency(hdspm->control_register) + 8));
1248 }
1249
1250
1251 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1252 {
1253         int position;
1254
1255         position = hdspm_read(hdspm, HDSPM_statusRegister);
1256
1257         switch (hdspm->io_type) {
1258         case RayDAT:
1259         case AIO:
1260                 position &= HDSPM_BufferPositionMask;
1261                 position /= 4; /* Bytes per sample */
1262                 break;
1263         default:
1264                 position = (position & HDSPM_BufferID) ?
1265                         (hdspm->period_bytes / 4) : 0;
1266         }
1267
1268         return position;
1269 }
1270
1271
1272 static inline void hdspm_start_audio(struct hdspm * s)
1273 {
1274         s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1275         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1276 }
1277
1278 static inline void hdspm_stop_audio(struct hdspm * s)
1279 {
1280         s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1281         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1282 }
1283
1284 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1285 static void hdspm_silence_playback(struct hdspm *hdspm)
1286 {
1287         int i;
1288         int n = hdspm->period_bytes;
1289         void *buf = hdspm->playback_buffer;
1290
1291         if (buf == NULL)
1292                 return;
1293
1294         for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1295                 memset(buf, 0, n);
1296                 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1297         }
1298 }
1299
1300 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1301 {
1302         int n;
1303
1304         spin_lock_irq(&s->lock);
1305
1306         frames >>= 7;
1307         n = 0;
1308         while (frames) {
1309                 n++;
1310                 frames >>= 1;
1311         }
1312         s->control_register &= ~HDSPM_LatencyMask;
1313         s->control_register |= hdspm_encode_latency(n);
1314
1315         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1316
1317         hdspm_compute_period_size(s);
1318
1319         spin_unlock_irq(&s->lock);
1320
1321         return 0;
1322 }
1323
1324 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1325 {
1326         u64 freq_const;
1327
1328         if (period == 0)
1329                 return 0;
1330
1331         switch (hdspm->io_type) {
1332         case MADI:
1333         case AES32:
1334                 freq_const = 110069313433624ULL;
1335                 break;
1336         case RayDAT:
1337         case AIO:
1338                 freq_const = 104857600000000ULL;
1339                 break;
1340         case MADIface:
1341                 freq_const = 131072000000000ULL;
1342         }
1343
1344         return div_u64(freq_const, period);
1345 }
1346
1347
1348 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1349 {
1350         u64 n;
1351
1352         if (rate >= 112000)
1353                 rate /= 4;
1354         else if (rate >= 56000)
1355                 rate /= 2;
1356
1357         switch (hdspm->io_type) {
1358         case MADIface:
1359           n = 131072000000000ULL;  /* 125 MHz */
1360           break;
1361         case MADI:
1362         case AES32:
1363           n = 110069313433624ULL;  /* 105 MHz */
1364           break;
1365         case RayDAT:
1366         case AIO:
1367           n = 104857600000000ULL;  /* 100 MHz */
1368           break;
1369         }
1370
1371         n = div_u64(n, rate);
1372         /* n should be less than 2^32 for being written to FREQ register */
1373         snd_BUG_ON(n >> 32);
1374         hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1375 }
1376
1377 /* dummy set rate lets see what happens */
1378 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1379 {
1380         int current_rate;
1381         int rate_bits;
1382         int not_set = 0;
1383         int current_speed, target_speed;
1384
1385         /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1386            it (e.g. during module initialization).
1387          */
1388
1389         if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1390
1391                 /* SLAVE --- */
1392                 if (called_internally) {
1393
1394                         /* request from ctl or card initialization
1395                            just make a warning an remember setting
1396                            for future master mode switching */
1397
1398                         snd_printk(KERN_WARNING "HDSPM: "
1399                                    "Warning: device is not running "
1400                                    "as a clock master.\n");
1401                         not_set = 1;
1402                 } else {
1403
1404                         /* hw_param request while in AutoSync mode */
1405                         int external_freq =
1406                             hdspm_external_sample_rate(hdspm);
1407
1408                         if (hdspm_autosync_ref(hdspm) ==
1409                             HDSPM_AUTOSYNC_FROM_NONE) {
1410
1411                                 snd_printk(KERN_WARNING "HDSPM: "
1412                                            "Detected no Externel Sync \n");
1413                                 not_set = 1;
1414
1415                         } else if (rate != external_freq) {
1416
1417                                 snd_printk(KERN_WARNING "HDSPM: "
1418                                            "Warning: No AutoSync source for "
1419                                            "requested rate\n");
1420                                 not_set = 1;
1421                         }
1422                 }
1423         }
1424
1425         current_rate = hdspm->system_sample_rate;
1426
1427         /* Changing between Singe, Double and Quad speed is not
1428            allowed if any substreams are open. This is because such a change
1429            causes a shift in the location of the DMA buffers and a reduction
1430            in the number of available buffers.
1431
1432            Note that a similar but essentially insoluble problem exists for
1433            externally-driven rate changes. All we can do is to flag rate
1434            changes in the read/write routines.
1435          */
1436
1437         if (current_rate <= 48000)
1438                 current_speed = HDSPM_SPEED_SINGLE;
1439         else if (current_rate <= 96000)
1440                 current_speed = HDSPM_SPEED_DOUBLE;
1441         else
1442                 current_speed = HDSPM_SPEED_QUAD;
1443
1444         if (rate <= 48000)
1445                 target_speed = HDSPM_SPEED_SINGLE;
1446         else if (rate <= 96000)
1447                 target_speed = HDSPM_SPEED_DOUBLE;
1448         else
1449                 target_speed = HDSPM_SPEED_QUAD;
1450
1451         switch (rate) {
1452         case 32000:
1453                 rate_bits = HDSPM_Frequency32KHz;
1454                 break;
1455         case 44100:
1456                 rate_bits = HDSPM_Frequency44_1KHz;
1457                 break;
1458         case 48000:
1459                 rate_bits = HDSPM_Frequency48KHz;
1460                 break;
1461         case 64000:
1462                 rate_bits = HDSPM_Frequency64KHz;
1463                 break;
1464         case 88200:
1465                 rate_bits = HDSPM_Frequency88_2KHz;
1466                 break;
1467         case 96000:
1468                 rate_bits = HDSPM_Frequency96KHz;
1469                 break;
1470         case 128000:
1471                 rate_bits = HDSPM_Frequency128KHz;
1472                 break;
1473         case 176400:
1474                 rate_bits = HDSPM_Frequency176_4KHz;
1475                 break;
1476         case 192000:
1477                 rate_bits = HDSPM_Frequency192KHz;
1478                 break;
1479         default:
1480                 return -EINVAL;
1481         }
1482
1483         if (current_speed != target_speed
1484             && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1485                 snd_printk
1486                     (KERN_ERR "HDSPM: "
1487                      "cannot change from %s speed to %s speed mode "
1488                      "(capture PID = %d, playback PID = %d)\n",
1489                      hdspm_speed_names[current_speed],
1490                      hdspm_speed_names[target_speed],
1491                      hdspm->capture_pid, hdspm->playback_pid);
1492                 return -EBUSY;
1493         }
1494
1495         hdspm->control_register &= ~HDSPM_FrequencyMask;
1496         hdspm->control_register |= rate_bits;
1497         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1498
1499         /* For AES32, need to set DDS value in FREQ register
1500            For MADI, also apparently */
1501         hdspm_set_dds_value(hdspm, rate);
1502
1503         if (AES32 == hdspm->io_type && rate != current_rate)
1504                 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1505
1506         hdspm->system_sample_rate = rate;
1507
1508         if (rate <= 48000) {
1509                 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1510                 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1511                 hdspm->max_channels_in = hdspm->ss_in_channels;
1512                 hdspm->max_channels_out = hdspm->ss_out_channels;
1513                 hdspm->port_names_in = hdspm->port_names_in_ss;
1514                 hdspm->port_names_out = hdspm->port_names_out_ss;
1515         } else if (rate <= 96000) {
1516                 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1517                 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1518                 hdspm->max_channels_in = hdspm->ds_in_channels;
1519                 hdspm->max_channels_out = hdspm->ds_out_channels;
1520                 hdspm->port_names_in = hdspm->port_names_in_ds;
1521                 hdspm->port_names_out = hdspm->port_names_out_ds;
1522         } else {
1523                 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1524                 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1525                 hdspm->max_channels_in = hdspm->qs_in_channels;
1526                 hdspm->max_channels_out = hdspm->qs_out_channels;
1527                 hdspm->port_names_in = hdspm->port_names_in_qs;
1528                 hdspm->port_names_out = hdspm->port_names_out_qs;
1529         }
1530
1531         if (not_set != 0)
1532                 return -1;
1533
1534         return 0;
1535 }
1536
1537 /* mainly for init to 0 on load */
1538 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1539 {
1540         int i, j;
1541         unsigned int gain;
1542
1543         if (sgain > UNITY_GAIN)
1544                 gain = UNITY_GAIN;
1545         else if (sgain < 0)
1546                 gain = 0;
1547         else
1548                 gain = sgain;
1549
1550         for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1551                 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1552                         hdspm_write_in_gain(hdspm, i, j, gain);
1553                         hdspm_write_pb_gain(hdspm, i, j, gain);
1554                 }
1555 }
1556
1557 /*----------------------------------------------------------------------------
1558    MIDI
1559   ----------------------------------------------------------------------------*/
1560
1561 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1562                                                       int id)
1563 {
1564         /* the hardware already does the relevant bit-mask with 0xff */
1565         return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1566 }
1567
1568 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1569                                               int val)
1570 {
1571         /* the hardware already does the relevant bit-mask with 0xff */
1572         return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1573 }
1574
1575 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1576 {
1577         return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1578 }
1579
1580 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1581 {
1582         int fifo_bytes_used;
1583
1584         fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1585
1586         if (fifo_bytes_used < 128)
1587                 return  128 - fifo_bytes_used;
1588         else
1589                 return 0;
1590 }
1591
1592 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1593 {
1594         while (snd_hdspm_midi_input_available (hdspm, id))
1595                 snd_hdspm_midi_read_byte (hdspm, id);
1596 }
1597
1598 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1599 {
1600         unsigned long flags;
1601         int n_pending;
1602         int to_write;
1603         int i;
1604         unsigned char buf[128];
1605
1606         /* Output is not interrupt driven */
1607
1608         spin_lock_irqsave (&hmidi->lock, flags);
1609         if (hmidi->output &&
1610             !snd_rawmidi_transmit_empty (hmidi->output)) {
1611                 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1612                                                             hmidi->id);
1613                 if (n_pending > 0) {
1614                         if (n_pending > (int)sizeof (buf))
1615                                 n_pending = sizeof (buf);
1616
1617                         to_write = snd_rawmidi_transmit (hmidi->output, buf,
1618                                                          n_pending);
1619                         if (to_write > 0) {
1620                                 for (i = 0; i < to_write; ++i)
1621                                         snd_hdspm_midi_write_byte (hmidi->hdspm,
1622                                                                    hmidi->id,
1623                                                                    buf[i]);
1624                         }
1625                 }
1626         }
1627         spin_unlock_irqrestore (&hmidi->lock, flags);
1628         return 0;
1629 }
1630
1631 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1632 {
1633         unsigned char buf[128]; /* this buffer is designed to match the MIDI
1634                                  * input FIFO size
1635                                  */
1636         unsigned long flags;
1637         int n_pending;
1638         int i;
1639
1640         spin_lock_irqsave (&hmidi->lock, flags);
1641         n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1642         if (n_pending > 0) {
1643                 if (hmidi->input) {
1644                         if (n_pending > (int)sizeof (buf))
1645                                 n_pending = sizeof (buf);
1646                         for (i = 0; i < n_pending; ++i)
1647                                 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1648                                                                    hmidi->id);
1649                         if (n_pending)
1650                                 snd_rawmidi_receive (hmidi->input, buf,
1651                                                      n_pending);
1652                 } else {
1653                         /* flush the MIDI input FIFO */
1654                         while (n_pending--)
1655                                 snd_hdspm_midi_read_byte (hmidi->hdspm,
1656                                                           hmidi->id);
1657                 }
1658         }
1659         hmidi->pending = 0;
1660         spin_unlock_irqrestore(&hmidi->lock, flags);
1661
1662         spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1663         hmidi->hdspm->control_register |= hmidi->ie;
1664         hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1665                     hmidi->hdspm->control_register);
1666         spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1667
1668         return snd_hdspm_midi_output_write (hmidi);
1669 }
1670
1671 static void
1672 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1673 {
1674         struct hdspm *hdspm;
1675         struct hdspm_midi *hmidi;
1676         unsigned long flags;
1677
1678         hmidi = substream->rmidi->private_data;
1679         hdspm = hmidi->hdspm;
1680
1681         spin_lock_irqsave (&hdspm->lock, flags);
1682         if (up) {
1683                 if (!(hdspm->control_register & hmidi->ie)) {
1684                         snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1685                         hdspm->control_register |= hmidi->ie;
1686                 }
1687         } else {
1688                 hdspm->control_register &= ~hmidi->ie;
1689         }
1690
1691         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1692         spin_unlock_irqrestore (&hdspm->lock, flags);
1693 }
1694
1695 static void snd_hdspm_midi_output_timer(unsigned long data)
1696 {
1697         struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1698         unsigned long flags;
1699
1700         snd_hdspm_midi_output_write(hmidi);
1701         spin_lock_irqsave (&hmidi->lock, flags);
1702
1703         /* this does not bump hmidi->istimer, because the
1704            kernel automatically removed the timer when it
1705            expired, and we are now adding it back, thus
1706            leaving istimer wherever it was set before.
1707         */
1708
1709         if (hmidi->istimer) {
1710                 hmidi->timer.expires = 1 + jiffies;
1711                 add_timer(&hmidi->timer);
1712         }
1713
1714         spin_unlock_irqrestore (&hmidi->lock, flags);
1715 }
1716
1717 static void
1718 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1719 {
1720         struct hdspm_midi *hmidi;
1721         unsigned long flags;
1722
1723         hmidi = substream->rmidi->private_data;
1724         spin_lock_irqsave (&hmidi->lock, flags);
1725         if (up) {
1726                 if (!hmidi->istimer) {
1727                         init_timer(&hmidi->timer);
1728                         hmidi->timer.function = snd_hdspm_midi_output_timer;
1729                         hmidi->timer.data = (unsigned long) hmidi;
1730                         hmidi->timer.expires = 1 + jiffies;
1731                         add_timer(&hmidi->timer);
1732                         hmidi->istimer++;
1733                 }
1734         } else {
1735                 if (hmidi->istimer && --hmidi->istimer <= 0)
1736                         del_timer (&hmidi->timer);
1737         }
1738         spin_unlock_irqrestore (&hmidi->lock, flags);
1739         if (up)
1740                 snd_hdspm_midi_output_write(hmidi);
1741 }
1742
1743 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1744 {
1745         struct hdspm_midi *hmidi;
1746
1747         hmidi = substream->rmidi->private_data;
1748         spin_lock_irq (&hmidi->lock);
1749         snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1750         hmidi->input = substream;
1751         spin_unlock_irq (&hmidi->lock);
1752
1753         return 0;
1754 }
1755
1756 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1757 {
1758         struct hdspm_midi *hmidi;
1759
1760         hmidi = substream->rmidi->private_data;
1761         spin_lock_irq (&hmidi->lock);
1762         hmidi->output = substream;
1763         spin_unlock_irq (&hmidi->lock);
1764
1765         return 0;
1766 }
1767
1768 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1769 {
1770         struct hdspm_midi *hmidi;
1771
1772         snd_hdspm_midi_input_trigger (substream, 0);
1773
1774         hmidi = substream->rmidi->private_data;
1775         spin_lock_irq (&hmidi->lock);
1776         hmidi->input = NULL;
1777         spin_unlock_irq (&hmidi->lock);
1778
1779         return 0;
1780 }
1781
1782 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
1783 {
1784         struct hdspm_midi *hmidi;
1785
1786         snd_hdspm_midi_output_trigger (substream, 0);
1787
1788         hmidi = substream->rmidi->private_data;
1789         spin_lock_irq (&hmidi->lock);
1790         hmidi->output = NULL;
1791         spin_unlock_irq (&hmidi->lock);
1792
1793         return 0;
1794 }
1795
1796 static struct snd_rawmidi_ops snd_hdspm_midi_output =
1797 {
1798         .open =         snd_hdspm_midi_output_open,
1799         .close =        snd_hdspm_midi_output_close,
1800         .trigger =      snd_hdspm_midi_output_trigger,
1801 };
1802
1803 static struct snd_rawmidi_ops snd_hdspm_midi_input =
1804 {
1805         .open =         snd_hdspm_midi_input_open,
1806         .close =        snd_hdspm_midi_input_close,
1807         .trigger =      snd_hdspm_midi_input_trigger,
1808 };
1809
1810 static int __devinit snd_hdspm_create_midi (struct snd_card *card,
1811                                             struct hdspm *hdspm, int id)
1812 {
1813         int err;
1814         char buf[32];
1815
1816         hdspm->midi[id].id = id;
1817         hdspm->midi[id].hdspm = hdspm;
1818         spin_lock_init (&hdspm->midi[id].lock);
1819
1820         if (0 == id) {
1821                 if (MADIface == hdspm->io_type) {
1822                         /* MIDI-over-MADI on HDSPe MADIface */
1823                         hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
1824                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
1825                         hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
1826                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
1827                         hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
1828                         hdspm->midi[0].irq = HDSPM_midi2IRQPending;
1829                 } else {
1830                         hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
1831                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
1832                         hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
1833                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
1834                         hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
1835                         hdspm->midi[0].irq = HDSPM_midi0IRQPending;
1836                 }
1837         } else if (1 == id) {
1838                 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
1839                 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
1840                 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
1841                 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
1842                 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
1843                 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
1844         } else if ((2 == id) && (MADI == hdspm->io_type)) {
1845                 /* MIDI-over-MADI on HDSPe MADI */
1846                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1847                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1848                 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
1849                 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
1850                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1851                 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
1852         } else if (2 == id) {
1853                 /* TCO MTC, read only */
1854                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1855                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1856                 hdspm->midi[2].dataOut = -1;
1857                 hdspm->midi[2].statusOut = -1;
1858                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1859                 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
1860         } else if (3 == id) {
1861                 /* TCO MTC on HDSPe MADI */
1862                 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
1863                 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
1864                 hdspm->midi[3].dataOut = -1;
1865                 hdspm->midi[3].statusOut = -1;
1866                 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
1867                 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
1868         }
1869
1870         if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
1871                                         (MADIface == hdspm->io_type)))) {
1872                 if ((id == 0) && (MADIface == hdspm->io_type)) {
1873                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
1874                 } else if ((id == 2) && (MADI == hdspm->io_type)) {
1875                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
1876                 } else {
1877                         sprintf(buf, "%s MIDI %d", card->shortname, id+1);
1878                 }
1879                 err = snd_rawmidi_new(card, buf, id, 1, 1,
1880                                 &hdspm->midi[id].rmidi);
1881                 if (err < 0)
1882                         return err;
1883
1884                 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
1885                                 card->id, id+1);
1886                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1887
1888                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1889                                 SNDRV_RAWMIDI_STREAM_OUTPUT,
1890                                 &snd_hdspm_midi_output);
1891                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1892                                 SNDRV_RAWMIDI_STREAM_INPUT,
1893                                 &snd_hdspm_midi_input);
1894
1895                 hdspm->midi[id].rmidi->info_flags |=
1896                         SNDRV_RAWMIDI_INFO_OUTPUT |
1897                         SNDRV_RAWMIDI_INFO_INPUT |
1898                         SNDRV_RAWMIDI_INFO_DUPLEX;
1899         } else {
1900                 /* TCO MTC, read only */
1901                 sprintf(buf, "%s MTC %d", card->shortname, id+1);
1902                 err = snd_rawmidi_new(card, buf, id, 1, 1,
1903                                 &hdspm->midi[id].rmidi);
1904                 if (err < 0)
1905                         return err;
1906
1907                 sprintf(hdspm->midi[id].rmidi->name,
1908                                 "%s MTC %d", card->id, id+1);
1909                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1910
1911                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1912                                 SNDRV_RAWMIDI_STREAM_INPUT,
1913                                 &snd_hdspm_midi_input);
1914
1915                 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
1916         }
1917
1918         return 0;
1919 }
1920
1921
1922 static void hdspm_midi_tasklet(unsigned long arg)
1923 {
1924         struct hdspm *hdspm = (struct hdspm *)arg;
1925         int i = 0;
1926
1927         while (i < hdspm->midiPorts) {
1928                 if (hdspm->midi[i].pending)
1929                         snd_hdspm_midi_input_read(&hdspm->midi[i]);
1930
1931                 i++;
1932         }
1933 }
1934
1935
1936 /*-----------------------------------------------------------------------------
1937   Status Interface
1938   ----------------------------------------------------------------------------*/
1939
1940 /* get the system sample rate which is set */
1941
1942
1943 /**
1944  * Calculate the real sample rate from the
1945  * current DDS value.
1946  **/
1947 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
1948 {
1949         unsigned int period, rate;
1950
1951         period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
1952         rate = hdspm_calc_dds_value(hdspm, period);
1953
1954         return rate;
1955 }
1956
1957
1958 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
1959 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1960   .name = xname, \
1961   .index = xindex, \
1962   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1963   .info = snd_hdspm_info_system_sample_rate, \
1964   .get = snd_hdspm_get_system_sample_rate \
1965 }
1966
1967 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
1968                                              struct snd_ctl_elem_info *uinfo)
1969 {
1970         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1971         uinfo->count = 1;
1972         uinfo->value.integer.min = 27000;
1973         uinfo->value.integer.max = 207000;
1974         uinfo->value.integer.step = 1;
1975         return 0;
1976 }
1977
1978
1979 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
1980                                             struct snd_ctl_elem_value *
1981                                             ucontrol)
1982 {
1983         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1984
1985         ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
1986         return 0;
1987 }
1988
1989
1990 /**
1991  * Returns the WordClock sample rate class for the given card.
1992  **/
1993 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
1994 {
1995         int status;
1996
1997         switch (hdspm->io_type) {
1998         case RayDAT:
1999         case AIO:
2000                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2001                 return (status >> 16) & 0xF;
2002                 break;
2003         default:
2004                 break;
2005         }
2006
2007
2008         return 0;
2009 }
2010
2011
2012 /**
2013  * Returns the TCO sample rate class for the given card.
2014  **/
2015 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2016 {
2017         int status;
2018
2019         if (hdspm->tco) {
2020                 switch (hdspm->io_type) {
2021                 case RayDAT:
2022                 case AIO:
2023                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2024                         return (status >> 20) & 0xF;
2025                         break;
2026                 default:
2027                         break;
2028                 }
2029         }
2030
2031         return 0;
2032 }
2033
2034
2035 /**
2036  * Returns the SYNC_IN sample rate class for the given card.
2037  **/
2038 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2039 {
2040         int status;
2041
2042         if (hdspm->tco) {
2043                 switch (hdspm->io_type) {
2044                 case RayDAT:
2045                 case AIO:
2046                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2047                         return (status >> 12) & 0xF;
2048                         break;
2049                 default:
2050                         break;
2051                 }
2052         }
2053
2054         return 0;
2055 }
2056
2057
2058 /**
2059  * Returns the sample rate class for input source <idx> for
2060  * 'new style' cards like the AIO and RayDAT.
2061  **/
2062 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2063 {
2064         int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2065
2066         return (status >> (idx*4)) & 0xF;
2067 }
2068
2069
2070
2071 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2072 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2073         .name = xname, \
2074         .private_value = xindex, \
2075         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2076         .info = snd_hdspm_info_autosync_sample_rate, \
2077         .get = snd_hdspm_get_autosync_sample_rate \
2078 }
2079
2080
2081 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2082                                                struct snd_ctl_elem_info *uinfo)
2083 {
2084         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2085         uinfo->count = 1;
2086         uinfo->value.enumerated.items = 10;
2087
2088         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2089                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2090         strcpy(uinfo->value.enumerated.name,
2091                         texts_freq[uinfo->value.enumerated.item]);
2092         return 0;
2093 }
2094
2095
2096 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2097                                               struct snd_ctl_elem_value *
2098                                               ucontrol)
2099 {
2100         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2101
2102         switch (hdspm->io_type) {
2103         case RayDAT:
2104                 switch (kcontrol->private_value) {
2105                 case 0:
2106                         ucontrol->value.enumerated.item[0] =
2107                                 hdspm_get_wc_sample_rate(hdspm);
2108                         break;
2109                 case 7:
2110                         ucontrol->value.enumerated.item[0] =
2111                                 hdspm_get_tco_sample_rate(hdspm);
2112                         break;
2113                 case 8:
2114                         ucontrol->value.enumerated.item[0] =
2115                                 hdspm_get_sync_in_sample_rate(hdspm);
2116                         break;
2117                 default:
2118                         ucontrol->value.enumerated.item[0] =
2119                                 hdspm_get_s1_sample_rate(hdspm,
2120                                                 kcontrol->private_value-1);
2121                 }
2122
2123         case AIO:
2124                 switch (kcontrol->private_value) {
2125                 case 0: /* WC */
2126                         ucontrol->value.enumerated.item[0] =
2127                                 hdspm_get_wc_sample_rate(hdspm);
2128                         break;
2129                 case 4: /* TCO */
2130                         ucontrol->value.enumerated.item[0] =
2131                                 hdspm_get_tco_sample_rate(hdspm);
2132                         break;
2133                 case 5: /* SYNC_IN */
2134                         ucontrol->value.enumerated.item[0] =
2135                                 hdspm_get_sync_in_sample_rate(hdspm);
2136                         break;
2137                 default:
2138                         ucontrol->value.enumerated.item[0] =
2139                                 hdspm_get_s1_sample_rate(hdspm,
2140                                                 ucontrol->id.index-1);
2141                 }
2142
2143         case AES32:
2144
2145                 switch (kcontrol->private_value) {
2146                 case 0: /* WC */
2147                         ucontrol->value.enumerated.item[0] =
2148                                 hdspm_get_wc_sample_rate(hdspm);
2149                         break;
2150                 case 9: /* TCO */
2151                         ucontrol->value.enumerated.item[0] =
2152                                 hdspm_get_tco_sample_rate(hdspm);
2153                         break;
2154                 case 10: /* SYNC_IN */
2155                         ucontrol->value.enumerated.item[0] =
2156                                 hdspm_get_sync_in_sample_rate(hdspm);
2157                         break;
2158                 default: /* AES1 to AES8 */
2159                         ucontrol->value.enumerated.item[0] =
2160                                 hdspm_get_s1_sample_rate(hdspm,
2161                                                 kcontrol->private_value-1);
2162                         break;
2163
2164                 }
2165         default:
2166                 break;
2167         }
2168
2169         return 0;
2170 }
2171
2172
2173 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2174 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2175         .name = xname, \
2176         .index = xindex, \
2177         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2178                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2179         .info = snd_hdspm_info_system_clock_mode, \
2180         .get = snd_hdspm_get_system_clock_mode, \
2181         .put = snd_hdspm_put_system_clock_mode, \
2182 }
2183
2184
2185 /**
2186  * Returns the system clock mode for the given card.
2187  * @returns 0 - master, 1 - slave
2188  **/
2189 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2190 {
2191         switch (hdspm->io_type) {
2192         case AIO:
2193         case RayDAT:
2194                 if (hdspm->settings_register & HDSPM_c0Master)
2195                         return 0;
2196                 break;
2197
2198         default:
2199                 if (hdspm->control_register & HDSPM_ClockModeMaster)
2200                         return 0;
2201         }
2202
2203         return 1;
2204 }
2205
2206
2207 /**
2208  * Sets the system clock mode.
2209  * @param mode 0 - master, 1 - slave
2210  **/
2211 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2212 {
2213         switch (hdspm->io_type) {
2214         case AIO:
2215         case RayDAT:
2216                 if (0 == mode)
2217                         hdspm->settings_register |= HDSPM_c0Master;
2218                 else
2219                         hdspm->settings_register &= ~HDSPM_c0Master;
2220
2221                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2222                 break;
2223
2224         default:
2225                 if (0 == mode)
2226                         hdspm->control_register |= HDSPM_ClockModeMaster;
2227                 else
2228                         hdspm->control_register &= ~HDSPM_ClockModeMaster;
2229
2230                 hdspm_write(hdspm, HDSPM_controlRegister,
2231                                 hdspm->control_register);
2232         }
2233 }
2234
2235
2236 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2237                                             struct snd_ctl_elem_info *uinfo)
2238 {
2239         static char *texts[] = { "Master", "AutoSync" };
2240
2241         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2242         uinfo->count = 1;
2243         uinfo->value.enumerated.items = 2;
2244         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2245                 uinfo->value.enumerated.item =
2246                     uinfo->value.enumerated.items - 1;
2247         strcpy(uinfo->value.enumerated.name,
2248                texts[uinfo->value.enumerated.item]);
2249         return 0;
2250 }
2251
2252 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2253                                            struct snd_ctl_elem_value *ucontrol)
2254 {
2255         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2256
2257         ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2258         return 0;
2259 }
2260
2261 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2262                                            struct snd_ctl_elem_value *ucontrol)
2263 {
2264         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2265         int val;
2266
2267         if (!snd_hdspm_use_is_exclusive(hdspm))
2268                 return -EBUSY;
2269
2270         val = ucontrol->value.enumerated.item[0];
2271         if (val < 0)
2272                 val = 0;
2273         else if (val > 1)
2274                 val = 1;
2275
2276         hdspm_set_system_clock_mode(hdspm, val);
2277
2278         return 0;
2279 }
2280
2281
2282 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2283 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2284         .name = xname, \
2285         .index = xindex, \
2286         .info = snd_hdspm_info_clock_source, \
2287         .get = snd_hdspm_get_clock_source, \
2288         .put = snd_hdspm_put_clock_source \
2289 }
2290
2291
2292 static int hdspm_clock_source(struct hdspm * hdspm)
2293 {
2294         switch (hdspm->system_sample_rate) {
2295         case 32000: return 0;
2296         case 44100: return 1;
2297         case 48000: return 2;
2298         case 64000: return 3;
2299         case 88200: return 4;
2300         case 96000: return 5;
2301         case 128000: return 6;
2302         case 176400: return 7;
2303         case 192000: return 8;
2304         }
2305
2306         return -1;
2307 }
2308
2309 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2310 {
2311         int rate;
2312         switch (mode) {
2313         case 0:
2314                 rate = 32000; break;
2315         case 1:
2316                 rate = 44100; break;
2317         case 2:
2318                 rate = 48000; break;
2319         case 3:
2320                 rate = 64000; break;
2321         case 4:
2322                 rate = 88200; break;
2323         case 5:
2324                 rate = 96000; break;
2325         case 6:
2326                 rate = 128000; break;
2327         case 7:
2328                 rate = 176400; break;
2329         case 8:
2330                 rate = 192000; break;
2331         default:
2332                 rate = 48000;
2333         }
2334         hdspm_set_rate(hdspm, rate, 1);
2335         return 0;
2336 }
2337
2338 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2339                                        struct snd_ctl_elem_info *uinfo)
2340 {
2341         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2342         uinfo->count = 1;
2343         uinfo->value.enumerated.items = 9;
2344
2345         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2346                 uinfo->value.enumerated.item =
2347                     uinfo->value.enumerated.items - 1;
2348
2349         strcpy(uinfo->value.enumerated.name,
2350                texts_freq[uinfo->value.enumerated.item+1]);
2351
2352         return 0;
2353 }
2354
2355 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2356                                       struct snd_ctl_elem_value *ucontrol)
2357 {
2358         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2359
2360         ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2361         return 0;
2362 }
2363
2364 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2365                                       struct snd_ctl_elem_value *ucontrol)
2366 {
2367         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2368         int change;
2369         int val;
2370
2371         if (!snd_hdspm_use_is_exclusive(hdspm))
2372                 return -EBUSY;
2373         val = ucontrol->value.enumerated.item[0];
2374         if (val < 0)
2375                 val = 0;
2376         if (val > 9)
2377                 val = 9;
2378         spin_lock_irq(&hdspm->lock);
2379         if (val != hdspm_clock_source(hdspm))
2380                 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2381         else
2382                 change = 0;
2383         spin_unlock_irq(&hdspm->lock);
2384         return change;
2385 }
2386
2387
2388 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2389 {.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2390         .name = xname, \
2391         .index = xindex, \
2392         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2393                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2394         .info = snd_hdspm_info_pref_sync_ref, \
2395         .get = snd_hdspm_get_pref_sync_ref, \
2396         .put = snd_hdspm_put_pref_sync_ref \
2397 }
2398
2399
2400 /**
2401  * Returns the current preferred sync reference setting.
2402  * The semantics of the return value are depending on the
2403  * card, please see the comments for clarification.
2404  **/
2405 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2406 {
2407         switch (hdspm->io_type) {
2408         case AES32:
2409                 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2410                 case 0: return 0;  /* WC */
2411                 case HDSPM_SyncRef0: return 1; /* AES 1 */
2412                 case HDSPM_SyncRef1: return 2; /* AES 2 */
2413                 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2414                 case HDSPM_SyncRef2: return 4; /* AES 4 */
2415                 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2416                 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2417                 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2418                                                     return 7; /* AES 7 */
2419                 case HDSPM_SyncRef3: return 8; /* AES 8 */
2420                 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2421                 }
2422                 break;
2423
2424         case MADI:
2425         case MADIface:
2426                 if (hdspm->tco) {
2427                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2428                         case 0: return 0;  /* WC */
2429                         case HDSPM_SyncRef0: return 1;  /* MADI */
2430                         case HDSPM_SyncRef1: return 2;  /* TCO */
2431                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2432                                              return 3;  /* SYNC_IN */
2433                         }
2434                 } else {
2435                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2436                         case 0: return 0;  /* WC */
2437                         case HDSPM_SyncRef0: return 1;  /* MADI */
2438                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2439                                              return 2;  /* SYNC_IN */
2440                         }
2441                 }
2442                 break;
2443
2444         case RayDAT:
2445                 if (hdspm->tco) {
2446                         switch ((hdspm->settings_register &
2447                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2448                         case 0: return 0;  /* WC */
2449                         case 3: return 1;  /* ADAT 1 */
2450                         case 4: return 2;  /* ADAT 2 */
2451                         case 5: return 3;  /* ADAT 3 */
2452                         case 6: return 4;  /* ADAT 4 */
2453                         case 1: return 5;  /* AES */
2454                         case 2: return 6;  /* SPDIF */
2455                         case 9: return 7;  /* TCO */
2456                         case 10: return 8; /* SYNC_IN */
2457                         }
2458                 } else {
2459                         switch ((hdspm->settings_register &
2460                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2461                         case 0: return 0;  /* WC */
2462                         case 3: return 1;  /* ADAT 1 */
2463                         case 4: return 2;  /* ADAT 2 */
2464                         case 5: return 3;  /* ADAT 3 */
2465                         case 6: return 4;  /* ADAT 4 */
2466                         case 1: return 5;  /* AES */
2467                         case 2: return 6;  /* SPDIF */
2468                         case 10: return 7; /* SYNC_IN */
2469                         }
2470                 }
2471
2472                 break;
2473
2474         case AIO:
2475                 if (hdspm->tco) {
2476                         switch ((hdspm->settings_register &
2477                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2478                         case 0: return 0;  /* WC */
2479                         case 3: return 1;  /* ADAT */
2480                         case 1: return 2;  /* AES */
2481                         case 2: return 3;  /* SPDIF */
2482                         case 9: return 4;  /* TCO */
2483                         case 10: return 5; /* SYNC_IN */
2484                         }
2485                 } else {
2486                         switch ((hdspm->settings_register &
2487                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2488                         case 0: return 0;  /* WC */
2489                         case 3: return 1;  /* ADAT */
2490                         case 1: return 2;  /* AES */
2491                         case 2: return 3;  /* SPDIF */
2492                         case 10: return 4; /* SYNC_IN */
2493                         }
2494                 }
2495
2496                 break;
2497         }
2498
2499         return -1;
2500 }
2501
2502
2503 /**
2504  * Set the preferred sync reference to <pref>. The semantics
2505  * of <pref> are depending on the card type, see the comments
2506  * for clarification.
2507  **/
2508 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2509 {
2510         int p = 0;
2511
2512         switch (hdspm->io_type) {
2513         case AES32:
2514                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2515                 switch (pref) {
2516                 case 0: /* WC  */
2517                         break;
2518                 case 1: /* AES 1 */
2519                         hdspm->control_register |= HDSPM_SyncRef0;
2520                         break;
2521                 case 2: /* AES 2 */
2522                         hdspm->control_register |= HDSPM_SyncRef1;
2523                         break;
2524                 case 3: /* AES 3 */
2525                         hdspm->control_register |=
2526                                 HDSPM_SyncRef1+HDSPM_SyncRef0;
2527                         break;
2528                 case 4: /* AES 4 */
2529                         hdspm->control_register |= HDSPM_SyncRef2;
2530                         break;
2531                 case 5: /* AES 5 */
2532                         hdspm->control_register |=
2533                                 HDSPM_SyncRef2+HDSPM_SyncRef0;
2534                         break;
2535                 case 6: /* AES 6 */
2536                         hdspm->control_register |=
2537                                 HDSPM_SyncRef2+HDSPM_SyncRef1;
2538                         break;
2539                 case 7: /* AES 7 */
2540                         hdspm->control_register |=
2541                                 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2542                         break;
2543                 case 8: /* AES 8 */
2544                         hdspm->control_register |= HDSPM_SyncRef3;
2545                         break;
2546                 case 9: /* TCO */
2547                         hdspm->control_register |=
2548                                 HDSPM_SyncRef3+HDSPM_SyncRef0;
2549                         break;
2550                 default:
2551                         return -1;
2552                 }
2553
2554                 break;
2555
2556         case MADI:
2557         case MADIface:
2558                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2559                 if (hdspm->tco) {
2560                         switch (pref) {
2561                         case 0: /* WC */
2562                                 break;
2563                         case 1: /* MADI */
2564                                 hdspm->control_register |= HDSPM_SyncRef0;
2565                                 break;
2566                         case 2: /* TCO */
2567                                 hdspm->control_register |= HDSPM_SyncRef1;
2568                                 break;
2569                         case 3: /* SYNC_IN */
2570                                 hdspm->control_register |=
2571                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2572                                 break;
2573                         default:
2574                                 return -1;
2575                         }
2576                 } else {
2577                         switch (pref) {
2578                         case 0: /* WC */
2579                                 break;
2580                         case 1: /* MADI */
2581                                 hdspm->control_register |= HDSPM_SyncRef0;
2582                                 break;
2583                         case 2: /* SYNC_IN */
2584                                 hdspm->control_register |=
2585                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2586                                 break;
2587                         default:
2588                                 return -1;
2589                         }
2590                 }
2591
2592                 break;
2593
2594         case RayDAT:
2595                 if (hdspm->tco) {
2596                         switch (pref) {
2597                         case 0: p = 0; break;  /* WC */
2598                         case 1: p = 3; break;  /* ADAT 1 */
2599                         case 2: p = 4; break;  /* ADAT 2 */
2600                         case 3: p = 5; break;  /* ADAT 3 */
2601                         case 4: p = 6; break;  /* ADAT 4 */
2602                         case 5: p = 1; break;  /* AES */
2603                         case 6: p = 2; break;  /* SPDIF */
2604                         case 7: p = 9; break;  /* TCO */
2605                         case 8: p = 10; break; /* SYNC_IN */
2606                         default: return -1;
2607                         }
2608                 } else {
2609                         switch (pref) {
2610                         case 0: p = 0; break;  /* WC */
2611                         case 1: p = 3; break;  /* ADAT 1 */
2612                         case 2: p = 4; break;  /* ADAT 2 */
2613                         case 3: p = 5; break;  /* ADAT 3 */
2614                         case 4: p = 6; break;  /* ADAT 4 */
2615                         case 5: p = 1; break;  /* AES */
2616                         case 6: p = 2; break;  /* SPDIF */
2617                         case 7: p = 10; break; /* SYNC_IN */
2618                         default: return -1;
2619                         }
2620                 }
2621                 break;
2622
2623         case AIO:
2624                 if (hdspm->tco) {
2625                         switch (pref) {
2626                         case 0: p = 0; break;  /* WC */
2627                         case 1: p = 3; break;  /* ADAT */
2628                         case 2: p = 1; break;  /* AES */
2629                         case 3: p = 2; break;  /* SPDIF */
2630                         case 4: p = 9; break;  /* TCO */
2631                         case 5: p = 10; break; /* SYNC_IN */
2632                         default: return -1;
2633                         }
2634                 } else {
2635                         switch (pref) {
2636                         case 0: p = 0; break;  /* WC */
2637                         case 1: p = 3; break;  /* ADAT */
2638                         case 2: p = 1; break;  /* AES */
2639                         case 3: p = 2; break;  /* SPDIF */
2640                         case 4: p = 10; break; /* SYNC_IN */
2641                         default: return -1;
2642                         }
2643                 }
2644                 break;
2645         }
2646
2647         switch (hdspm->io_type) {
2648         case RayDAT:
2649         case AIO:
2650                 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2651                 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2652                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2653                 break;
2654
2655         case MADI:
2656         case MADIface:
2657         case AES32:
2658                 hdspm_write(hdspm, HDSPM_controlRegister,
2659                                 hdspm->control_register);
2660         }
2661
2662         return 0;
2663 }
2664
2665
2666 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2667                                         struct snd_ctl_elem_info *uinfo)
2668 {
2669         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2670
2671         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2672         uinfo->count = 1;
2673         uinfo->value.enumerated.items = hdspm->texts_autosync_items;
2674
2675         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2676                 uinfo->value.enumerated.item =
2677                         uinfo->value.enumerated.items - 1;
2678
2679         strcpy(uinfo->value.enumerated.name,
2680                         hdspm->texts_autosync[uinfo->value.enumerated.item]);
2681
2682         return 0;
2683 }
2684
2685 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2686                                        struct snd_ctl_elem_value *ucontrol)
2687 {
2688         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2689         int psf = hdspm_pref_sync_ref(hdspm);
2690
2691         if (psf >= 0) {
2692                 ucontrol->value.enumerated.item[0] = psf;
2693                 return 0;
2694         }
2695
2696         return -1;
2697 }
2698
2699 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2700                                        struct snd_ctl_elem_value *ucontrol)
2701 {
2702         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2703         int val, change = 0;
2704
2705         if (!snd_hdspm_use_is_exclusive(hdspm))
2706                 return -EBUSY;
2707
2708         val = ucontrol->value.enumerated.item[0];
2709
2710         if (val < 0)
2711                 val = 0;
2712         else if (val >= hdspm->texts_autosync_items)
2713                 val = hdspm->texts_autosync_items-1;
2714
2715         spin_lock_irq(&hdspm->lock);
2716         if (val != hdspm_pref_sync_ref(hdspm))
2717                 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
2718
2719         spin_unlock_irq(&hdspm->lock);
2720         return change;
2721 }
2722
2723
2724 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
2725 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2726   .name = xname, \
2727   .index = xindex, \
2728   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2729   .info = snd_hdspm_info_autosync_ref, \
2730   .get = snd_hdspm_get_autosync_ref, \
2731 }
2732
2733 static int hdspm_autosync_ref(struct hdspm *hdspm)
2734 {
2735         if (AES32 == hdspm->io_type) {
2736                 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
2737                 unsigned int syncref =
2738                         (status >> HDSPM_AES32_syncref_bit) & 0xF;
2739                 if (syncref == 0)
2740                         return HDSPM_AES32_AUTOSYNC_FROM_WORD;
2741                 if (syncref <= 8)
2742                         return syncref;
2743                 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
2744         } else if (MADI == hdspm->io_type) {
2745                 /* This looks at the autosync selected sync reference */
2746                 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2747
2748                 switch (status2 & HDSPM_SelSyncRefMask) {
2749                 case HDSPM_SelSyncRef_WORD:
2750                         return HDSPM_AUTOSYNC_FROM_WORD;
2751                 case HDSPM_SelSyncRef_MADI:
2752                         return HDSPM_AUTOSYNC_FROM_MADI;
2753                 case HDSPM_SelSyncRef_TCO:
2754                         return HDSPM_AUTOSYNC_FROM_TCO;
2755                 case HDSPM_SelSyncRef_SyncIn:
2756                         return HDSPM_AUTOSYNC_FROM_SYNC_IN;
2757                 case HDSPM_SelSyncRef_NVALID:
2758                         return HDSPM_AUTOSYNC_FROM_NONE;
2759                 default:
2760                         return 0;
2761                 }
2762
2763         }
2764         return 0;
2765 }
2766
2767
2768 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
2769                                        struct snd_ctl_elem_info *uinfo)
2770 {
2771         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2772
2773         if (AES32 == hdspm->io_type) {
2774                 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
2775                         "AES4", "AES5", "AES6", "AES7", "AES8", "None"};
2776
2777                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2778                 uinfo->count = 1;
2779                 uinfo->value.enumerated.items = 10;
2780                 if (uinfo->value.enumerated.item >=
2781                     uinfo->value.enumerated.items)
2782                         uinfo->value.enumerated.item =
2783                                 uinfo->value.enumerated.items - 1;
2784                 strcpy(uinfo->value.enumerated.name,
2785                                 texts[uinfo->value.enumerated.item]);
2786         } else if (MADI == hdspm->io_type) {
2787                 static char *texts[] = {"Word Clock", "MADI", "TCO",
2788                         "Sync In", "None" };
2789
2790                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2791                 uinfo->count = 1;
2792                 uinfo->value.enumerated.items = 5;
2793                 if (uinfo->value.enumerated.item >=
2794                                 uinfo->value.enumerated.items)
2795                         uinfo->value.enumerated.item =
2796                                 uinfo->value.enumerated.items - 1;
2797                 strcpy(uinfo->value.enumerated.name,
2798                                 texts[uinfo->value.enumerated.item]);
2799         }
2800         return 0;
2801 }
2802
2803 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
2804                                       struct snd_ctl_elem_value *ucontrol)
2805 {
2806         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2807
2808         ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
2809         return 0;
2810 }
2811
2812
2813 #define HDSPM_LINE_OUT(xname, xindex) \
2814 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2815   .name = xname, \
2816   .index = xindex, \
2817   .info = snd_hdspm_info_line_out, \
2818   .get = snd_hdspm_get_line_out, \
2819   .put = snd_hdspm_put_line_out \
2820 }
2821
2822 static int hdspm_line_out(struct hdspm * hdspm)
2823 {
2824         return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0;
2825 }
2826
2827
2828 static int hdspm_set_line_output(struct hdspm * hdspm, int out)
2829 {
2830         if (out)
2831                 hdspm->control_register |= HDSPM_LineOut;
2832         else
2833                 hdspm->control_register &= ~HDSPM_LineOut;
2834         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2835
2836         return 0;
2837 }
2838
2839 #define snd_hdspm_info_line_out         snd_ctl_boolean_mono_info
2840
2841 static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol,
2842                                   struct snd_ctl_elem_value *ucontrol)
2843 {
2844         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2845
2846         spin_lock_irq(&hdspm->lock);
2847         ucontrol->value.integer.value[0] = hdspm_line_out(hdspm);
2848         spin_unlock_irq(&hdspm->lock);
2849         return 0;
2850 }
2851
2852 static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol,
2853                                   struct snd_ctl_elem_value *ucontrol)
2854 {
2855         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2856         int change;
2857         unsigned int val;
2858
2859         if (!snd_hdspm_use_is_exclusive(hdspm))
2860                 return -EBUSY;
2861         val = ucontrol->value.integer.value[0] & 1;
2862         spin_lock_irq(&hdspm->lock);
2863         change = (int) val != hdspm_line_out(hdspm);
2864         hdspm_set_line_output(hdspm, val);
2865         spin_unlock_irq(&hdspm->lock);
2866         return change;
2867 }
2868
2869
2870 #define HDSPM_TX_64(xname, xindex) \
2871 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2872   .name = xname, \
2873   .index = xindex, \
2874   .info = snd_hdspm_info_tx_64, \
2875   .get = snd_hdspm_get_tx_64, \
2876   .put = snd_hdspm_put_tx_64 \
2877 }
2878
2879 static int hdspm_tx_64(struct hdspm * hdspm)
2880 {
2881         return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0;
2882 }
2883
2884 static int hdspm_set_tx_64(struct hdspm * hdspm, int out)
2885 {
2886         if (out)
2887                 hdspm->control_register |= HDSPM_TX_64ch;
2888         else
2889                 hdspm->control_register &= ~HDSPM_TX_64ch;
2890         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2891
2892         return 0;
2893 }
2894
2895 #define snd_hdspm_info_tx_64            snd_ctl_boolean_mono_info
2896
2897 static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol,
2898                                struct snd_ctl_elem_value *ucontrol)
2899 {
2900         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2901
2902         spin_lock_irq(&hdspm->lock);
2903         ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm);
2904         spin_unlock_irq(&hdspm->lock);
2905         return 0;
2906 }
2907
2908 static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol,
2909                                struct snd_ctl_elem_value *ucontrol)
2910 {
2911         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2912         int change;
2913         unsigned int val;
2914
2915         if (!snd_hdspm_use_is_exclusive(hdspm))
2916                 return -EBUSY;
2917         val = ucontrol->value.integer.value[0] & 1;
2918         spin_lock_irq(&hdspm->lock);
2919         change = (int) val != hdspm_tx_64(hdspm);
2920         hdspm_set_tx_64(hdspm, val);
2921         spin_unlock_irq(&hdspm->lock);
2922         return change;
2923 }
2924
2925
2926 #define HDSPM_C_TMS(xname, xindex) \
2927 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2928   .name = xname, \
2929   .index = xindex, \
2930   .info = snd_hdspm_info_c_tms, \
2931   .get = snd_hdspm_get_c_tms, \
2932   .put = snd_hdspm_put_c_tms \
2933 }
2934
2935 static int hdspm_c_tms(struct hdspm * hdspm)
2936 {
2937         return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0;
2938 }
2939
2940 static int hdspm_set_c_tms(struct hdspm * hdspm, int out)
2941 {
2942         if (out)
2943                 hdspm->control_register |= HDSPM_clr_tms;
2944         else
2945                 hdspm->control_register &= ~HDSPM_clr_tms;
2946         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2947
2948         return 0;
2949 }
2950
2951 #define snd_hdspm_info_c_tms            snd_ctl_boolean_mono_info
2952
2953 static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol,
2954                                struct snd_ctl_elem_value *ucontrol)
2955 {
2956         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2957
2958         spin_lock_irq(&hdspm->lock);
2959         ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm);
2960         spin_unlock_irq(&hdspm->lock);
2961         return 0;
2962 }
2963
2964 static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol,
2965                                struct snd_ctl_elem_value *ucontrol)
2966 {
2967         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2968         int change;
2969         unsigned int val;
2970
2971         if (!snd_hdspm_use_is_exclusive(hdspm))
2972                 return -EBUSY;
2973         val = ucontrol->value.integer.value[0] & 1;
2974         spin_lock_irq(&hdspm->lock);
2975         change = (int) val != hdspm_c_tms(hdspm);
2976         hdspm_set_c_tms(hdspm, val);
2977         spin_unlock_irq(&hdspm->lock);
2978         return change;
2979 }
2980
2981
2982 #define HDSPM_SAFE_MODE(xname, xindex) \
2983 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2984   .name = xname, \
2985   .index = xindex, \
2986   .info = snd_hdspm_info_safe_mode, \
2987   .get = snd_hdspm_get_safe_mode, \
2988   .put = snd_hdspm_put_safe_mode \
2989 }
2990
2991 static int hdspm_safe_mode(struct hdspm * hdspm)
2992 {
2993         return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0;
2994 }
2995
2996 static int hdspm_set_safe_mode(struct hdspm * hdspm, int out)
2997 {
2998         if (out)
2999                 hdspm->control_register |= HDSPM_AutoInp;
3000         else
3001                 hdspm->control_register &= ~HDSPM_AutoInp;
3002         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3003
3004         return 0;
3005 }
3006
3007 #define snd_hdspm_info_safe_mode        snd_ctl_boolean_mono_info
3008
3009 static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol,
3010                                    struct snd_ctl_elem_value *ucontrol)
3011 {
3012         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3013
3014         spin_lock_irq(&hdspm->lock);
3015         ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm);
3016         spin_unlock_irq(&hdspm->lock);
3017         return 0;
3018 }
3019
3020 static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol,
3021                                    struct snd_ctl_elem_value *ucontrol)
3022 {
3023         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3024         int change;
3025         unsigned int val;
3026
3027         if (!snd_hdspm_use_is_exclusive(hdspm))
3028                 return -EBUSY;
3029         val = ucontrol->value.integer.value[0] & 1;
3030         spin_lock_irq(&hdspm->lock);
3031         change = (int) val != hdspm_safe_mode(hdspm);
3032         hdspm_set_safe_mode(hdspm, val);
3033         spin_unlock_irq(&hdspm->lock);
3034         return change;
3035 }
3036
3037
3038 #define HDSPM_EMPHASIS(xname, xindex) \
3039 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3040   .name = xname, \
3041   .index = xindex, \
3042   .info = snd_hdspm_info_emphasis, \
3043   .get = snd_hdspm_get_emphasis, \
3044   .put = snd_hdspm_put_emphasis \
3045 }
3046
3047 static int hdspm_emphasis(struct hdspm * hdspm)
3048 {
3049         return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0;
3050 }
3051
3052 static int hdspm_set_emphasis(struct hdspm * hdspm, int emp)
3053 {
3054         if (emp)
3055                 hdspm->control_register |= HDSPM_Emphasis;
3056         else
3057                 hdspm->control_register &= ~HDSPM_Emphasis;
3058         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3059
3060         return 0;
3061 }
3062
3063 #define snd_hdspm_info_emphasis         snd_ctl_boolean_mono_info
3064
3065 static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol,
3066                                   struct snd_ctl_elem_value *ucontrol)
3067 {
3068         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3069
3070         spin_lock_irq(&hdspm->lock);
3071         ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm);
3072         spin_unlock_irq(&hdspm->lock);
3073         return 0;
3074 }
3075
3076 static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol,
3077                                   struct snd_ctl_elem_value *ucontrol)
3078 {
3079         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3080         int change;
3081         unsigned int val;
3082
3083         if (!snd_hdspm_use_is_exclusive(hdspm))
3084                 return -EBUSY;
3085         val = ucontrol->value.integer.value[0] & 1;
3086         spin_lock_irq(&hdspm->lock);
3087         change = (int) val != hdspm_emphasis(hdspm);
3088         hdspm_set_emphasis(hdspm, val);
3089         spin_unlock_irq(&hdspm->lock);
3090         return change;
3091 }
3092
3093
3094 #define HDSPM_DOLBY(xname, xindex) \
3095 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3096   .name = xname, \
3097   .index = xindex, \
3098   .info = snd_hdspm_info_dolby, \
3099   .get = snd_hdspm_get_dolby, \
3100   .put = snd_hdspm_put_dolby \
3101 }
3102
3103 static int hdspm_dolby(struct hdspm * hdspm)
3104 {
3105         return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0;
3106 }
3107
3108 static int hdspm_set_dolby(struct hdspm * hdspm, int dol)
3109 {
3110         if (dol)
3111                 hdspm->control_register |= HDSPM_Dolby;
3112         else
3113                 hdspm->control_register &= ~HDSPM_Dolby;
3114         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3115
3116         return 0;
3117 }
3118
3119 #define snd_hdspm_info_dolby            snd_ctl_boolean_mono_info
3120
3121 static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol,
3122                                struct snd_ctl_elem_value *ucontrol)
3123 {
3124         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3125
3126         spin_lock_irq(&hdspm->lock);
3127         ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm);
3128         spin_unlock_irq(&hdspm->lock);
3129         return 0;
3130 }
3131
3132 static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol,
3133                                struct snd_ctl_elem_value *ucontrol)
3134 {
3135         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3136         int change;
3137         unsigned int val;
3138
3139         if (!snd_hdspm_use_is_exclusive(hdspm))
3140                 return -EBUSY;
3141         val = ucontrol->value.integer.value[0] & 1;
3142         spin_lock_irq(&hdspm->lock);
3143         change = (int) val != hdspm_dolby(hdspm);
3144         hdspm_set_dolby(hdspm, val);
3145         spin_unlock_irq(&hdspm->lock);
3146         return change;
3147 }
3148
3149
3150 #define HDSPM_PROFESSIONAL(xname, xindex) \
3151 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3152   .name = xname, \
3153   .index = xindex, \
3154   .info = snd_hdspm_info_professional, \
3155   .get = snd_hdspm_get_professional, \
3156   .put = snd_hdspm_put_professional \
3157 }
3158
3159 static int hdspm_professional(struct hdspm * hdspm)
3160 {
3161         return (hdspm->control_register & HDSPM_Professional) ? 1 : 0;
3162 }
3163
3164 static int hdspm_set_professional(struct hdspm * hdspm, int dol)
3165 {
3166         if (dol)
3167                 hdspm->control_register |= HDSPM_Professional;
3168         else
3169                 hdspm->control_register &= ~HDSPM_Professional;
3170         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3171
3172         return 0;
3173 }
3174
3175 #define snd_hdspm_info_professional     snd_ctl_boolean_mono_info
3176
3177 static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol,
3178                                       struct snd_ctl_elem_value *ucontrol)
3179 {
3180         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3181
3182         spin_lock_irq(&hdspm->lock);
3183         ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm);
3184         spin_unlock_irq(&hdspm->lock);
3185         return 0;
3186 }
3187
3188 static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol,
3189                                       struct snd_ctl_elem_value *ucontrol)
3190 {
3191         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3192         int change;
3193         unsigned int val;
3194
3195         if (!snd_hdspm_use_is_exclusive(hdspm))
3196                 return -EBUSY;
3197         val = ucontrol->value.integer.value[0] & 1;
3198         spin_lock_irq(&hdspm->lock);
3199         change = (int) val != hdspm_professional(hdspm);
3200         hdspm_set_professional(hdspm, val);
3201         spin_unlock_irq(&hdspm->lock);
3202         return change;
3203 }
3204
3205 #define HDSPM_INPUT_SELECT(xname, xindex) \
3206 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3207   .name = xname, \
3208   .index = xindex, \
3209   .info = snd_hdspm_info_input_select, \
3210   .get = snd_hdspm_get_input_select, \
3211   .put = snd_hdspm_put_input_select \
3212 }
3213
3214 static int hdspm_input_select(struct hdspm * hdspm)
3215 {
3216         return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3217 }
3218
3219 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3220 {
3221         if (out)
3222                 hdspm->control_register |= HDSPM_InputSelect0;
3223         else
3224                 hdspm->control_register &= ~HDSPM_InputSelect0;
3225         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3226
3227         return 0;
3228 }
3229
3230 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3231                                        struct snd_ctl_elem_info *uinfo)
3232 {
3233         static char *texts[] = { "optical", "coaxial" };
3234
3235         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3236         uinfo->count = 1;
3237         uinfo->value.enumerated.items = 2;
3238
3239         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3240                 uinfo->value.enumerated.item =
3241                     uinfo->value.enumerated.items - 1;
3242         strcpy(uinfo->value.enumerated.name,
3243                texts[uinfo->value.enumerated.item]);
3244
3245         return 0;
3246 }
3247
3248 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3249                                       struct snd_ctl_elem_value *ucontrol)
3250 {
3251         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3252
3253         spin_lock_irq(&hdspm->lock);
3254         ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3255         spin_unlock_irq(&hdspm->lock);
3256         return 0;
3257 }
3258
3259 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3260                                       struct snd_ctl_elem_value *ucontrol)
3261 {
3262         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3263         int change;
3264         unsigned int val;
3265
3266         if (!snd_hdspm_use_is_exclusive(hdspm))
3267                 return -EBUSY;
3268         val = ucontrol->value.integer.value[0] & 1;
3269         spin_lock_irq(&hdspm->lock);
3270         change = (int) val != hdspm_input_select(hdspm);
3271         hdspm_set_input_select(hdspm, val);
3272         spin_unlock_irq(&hdspm->lock);
3273         return change;
3274 }
3275
3276
3277 #define HDSPM_DS_WIRE(xname, xindex) \
3278 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3279   .name = xname, \
3280   .index = xindex, \
3281   .info = snd_hdspm_info_ds_wire, \
3282   .get = snd_hdspm_get_ds_wire, \
3283   .put = snd_hdspm_put_ds_wire \
3284 }
3285
3286 static int hdspm_ds_wire(struct hdspm * hdspm)
3287 {
3288         return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3289 }
3290
3291 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3292 {
3293         if (ds)
3294                 hdspm->control_register |= HDSPM_DS_DoubleWire;
3295         else
3296                 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3297         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3298
3299         return 0;
3300 }
3301
3302 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3303                                   struct snd_ctl_elem_info *uinfo)
3304 {
3305         static char *texts[] = { "Single", "Double" };
3306
3307         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3308         uinfo->count = 1;
3309         uinfo->value.enumerated.items = 2;
3310
3311         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3312                 uinfo->value.enumerated.item =
3313                     uinfo->value.enumerated.items - 1;
3314         strcpy(uinfo->value.enumerated.name,
3315                texts[uinfo->value.enumerated.item]);
3316
3317         return 0;
3318 }
3319
3320 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3321                                  struct snd_ctl_elem_value *ucontrol)
3322 {
3323         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3324
3325         spin_lock_irq(&hdspm->lock);
3326         ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3327         spin_unlock_irq(&hdspm->lock);
3328         return 0;
3329 }
3330
3331 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3332                                  struct snd_ctl_elem_value *ucontrol)
3333 {
3334         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3335         int change;
3336         unsigned int val;
3337
3338         if (!snd_hdspm_use_is_exclusive(hdspm))
3339                 return -EBUSY;
3340         val = ucontrol->value.integer.value[0] & 1;
3341         spin_lock_irq(&hdspm->lock);
3342         change = (int) val != hdspm_ds_wire(hdspm);
3343         hdspm_set_ds_wire(hdspm, val);
3344         spin_unlock_irq(&hdspm->lock);
3345         return change;
3346 }
3347
3348
3349 #define HDSPM_QS_WIRE(xname, xindex) \
3350 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3351   .name = xname, \
3352   .index = xindex, \
3353   .info = snd_hdspm_info_qs_wire, \
3354   .get = snd_hdspm_get_qs_wire, \
3355   .put = snd_hdspm_put_qs_wire \
3356 }
3357
3358 static int hdspm_qs_wire(struct hdspm * hdspm)
3359 {
3360         if (hdspm->control_register & HDSPM_QS_DoubleWire)
3361                 return 1;
3362         if (hdspm->control_register & HDSPM_QS_QuadWire)
3363                 return 2;
3364         return 0;
3365 }
3366
3367 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3368 {
3369         hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3370         switch (mode) {
3371         case 0:
3372                 break;
3373         case 1:
3374                 hdspm->control_register |= HDSPM_QS_DoubleWire;
3375                 break;
3376         case 2:
3377                 hdspm->control_register |= HDSPM_QS_QuadWire;
3378                 break;
3379         }
3380         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3381
3382         return 0;
3383 }
3384
3385 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3386                                        struct snd_ctl_elem_info *uinfo)
3387 {
3388         static char *texts[] = { "Single", "Double", "Quad" };
3389
3390         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3391         uinfo->count = 1;
3392         uinfo->value.enumerated.items = 3;
3393
3394         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3395                 uinfo->value.enumerated.item =
3396                     uinfo->value.enumerated.items - 1;
3397         strcpy(uinfo->value.enumerated.name,
3398                texts[uinfo->value.enumerated.item]);
3399
3400         return 0;
3401 }
3402
3403 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3404                                       struct snd_ctl_elem_value *ucontrol)
3405 {
3406         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3407
3408         spin_lock_irq(&hdspm->lock);
3409         ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3410         spin_unlock_irq(&hdspm->lock);
3411         return 0;
3412 }
3413
3414 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3415                                       struct snd_ctl_elem_value *ucontrol)
3416 {
3417         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3418         int change;
3419         int val;
3420
3421         if (!snd_hdspm_use_is_exclusive(hdspm))
3422                 return -EBUSY;
3423         val = ucontrol->value.integer.value[0];
3424         if (val < 0)
3425                 val = 0;
3426         if (val > 2)
3427                 val = 2;
3428         spin_lock_irq(&hdspm->lock);
3429         change = val != hdspm_qs_wire(hdspm);
3430         hdspm_set_qs_wire(hdspm, val);
3431         spin_unlock_irq(&hdspm->lock);
3432         return change;
3433 }
3434
3435 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3436 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3437         .name = xname, \
3438         .index = xindex, \
3439         .info = snd_hdspm_info_madi_speedmode, \
3440         .get = snd_hdspm_get_madi_speedmode, \
3441         .put = snd_hdspm_put_madi_speedmode \
3442 }
3443
3444 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3445 {
3446         if (hdspm->control_register & HDSPM_QuadSpeed)
3447                 return 2;
3448         if (hdspm->control_register & HDSPM_DoubleSpeed)
3449                 return 1;
3450         return 0;
3451 }
3452
3453 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3454 {
3455         hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3456         switch (mode) {
3457         case 0:
3458                 break;
3459         case 1:
3460                 hdspm->control_register |= HDSPM_DoubleSpeed;
3461                 break;
3462         case 2:
3463                 hdspm->control_register |= HDSPM_QuadSpeed;
3464                 break;
3465         }
3466         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3467
3468         return 0;
3469 }
3470
3471 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3472                                        struct snd_ctl_elem_info *uinfo)
3473 {
3474         static char *texts[] = { "Single", "Double", "Quad" };
3475
3476         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3477         uinfo->count = 1;
3478         uinfo->value.enumerated.items = 3;
3479
3480         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3481                 uinfo->value.enumerated.item =
3482                     uinfo->value.enumerated.items - 1;
3483         strcpy(uinfo->value.enumerated.name,
3484                texts[uinfo->value.enumerated.item]);
3485
3486         return 0;
3487 }
3488
3489 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3490                                       struct snd_ctl_elem_value *ucontrol)
3491 {
3492         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3493
3494         spin_lock_irq(&hdspm->lock);
3495         ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3496         spin_unlock_irq(&hdspm->lock);
3497         return 0;
3498 }
3499
3500 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3501                                       struct snd_ctl_elem_value *ucontrol)
3502 {
3503         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3504         int change;
3505         int val;
3506
3507         if (!snd_hdspm_use_is_exclusive(hdspm))
3508                 return -EBUSY;
3509         val = ucontrol->value.integer.value[0];
3510         if (val < 0)
3511                 val = 0;
3512         if (val > 2)
3513                 val = 2;
3514         spin_lock_irq(&hdspm->lock);
3515         change = val != hdspm_madi_speedmode(hdspm);
3516         hdspm_set_madi_speedmode(hdspm, val);
3517         spin_unlock_irq(&hdspm->lock);
3518         return change;
3519 }
3520
3521 #define HDSPM_MIXER(xname, xindex) \
3522 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3523   .name = xname, \
3524   .index = xindex, \
3525   .device = 0, \
3526   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3527                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3528   .info = snd_hdspm_info_mixer, \
3529   .get = snd_hdspm_get_mixer, \
3530   .put = snd_hdspm_put_mixer \
3531 }
3532
3533 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3534                                 struct snd_ctl_elem_info *uinfo)
3535 {
3536         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3537         uinfo->count = 3;
3538         uinfo->value.integer.min = 0;
3539         uinfo->value.integer.max = 65535;
3540         uinfo->value.integer.step = 1;
3541         return 0;
3542 }
3543
3544 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3545                                struct snd_ctl_elem_value *ucontrol)
3546 {
3547         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3548         int source;
3549         int destination;
3550
3551         source = ucontrol->value.integer.value[0];
3552         if (source < 0)
3553                 source = 0;
3554         else if (source >= 2 * HDSPM_MAX_CHANNELS)
3555                 source = 2 * HDSPM_MAX_CHANNELS - 1;
3556
3557         destination = ucontrol->value.integer.value[1];
3558         if (destination < 0)
3559                 destination = 0;
3560         else if (destination >= HDSPM_MAX_CHANNELS)
3561                 destination = HDSPM_MAX_CHANNELS - 1;
3562
3563         spin_lock_irq(&hdspm->lock);
3564         if (source >= HDSPM_MAX_CHANNELS)
3565                 ucontrol->value.integer.value[2] =
3566                     hdspm_read_pb_gain(hdspm, destination,
3567                                        source - HDSPM_MAX_CHANNELS);
3568         else
3569                 ucontrol->value.integer.value[2] =
3570                     hdspm_read_in_gain(hdspm, destination, source);
3571
3572         spin_unlock_irq(&hdspm->lock);
3573
3574         return 0;
3575 }
3576
3577 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3578                                struct snd_ctl_elem_value *ucontrol)
3579 {
3580         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3581         int change;
3582         int source;
3583         int destination;
3584         int gain;
3585
3586         if (!snd_hdspm_use_is_exclusive(hdspm))
3587                 return -EBUSY;
3588
3589         source = ucontrol->value.integer.value[0];
3590         destination = ucontrol->value.integer.value[1];
3591
3592         if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3593                 return -1;
3594         if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3595                 return -1;
3596
3597         gain = ucontrol->value.integer.value[2];
3598
3599         spin_lock_irq(&hdspm->lock);
3600
3601         if (source >= HDSPM_MAX_CHANNELS)
3602                 change = gain != hdspm_read_pb_gain(hdspm, destination,
3603                                                     source -
3604                                                     HDSPM_MAX_CHANNELS);
3605         else
3606                 change = gain != hdspm_read_in_gain(hdspm, destination,
3607                                                     source);
3608
3609         if (change) {
3610                 if (source >= HDSPM_MAX_CHANNELS)
3611                         hdspm_write_pb_gain(hdspm, destination,
3612                                             source - HDSPM_MAX_CHANNELS,
3613                                             gain);
3614                 else
3615                         hdspm_write_in_gain(hdspm, destination, source,
3616                                             gain);
3617         }
3618         spin_unlock_irq(&hdspm->lock);
3619
3620         return change;
3621 }
3622
3623 /* The simple mixer control(s) provide gain control for the
3624    basic 1:1 mappings of playback streams to output
3625    streams.
3626 */
3627
3628 #define HDSPM_PLAYBACK_MIXER \
3629 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3630   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3631                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3632   .info = snd_hdspm_info_playback_mixer, \
3633   .get = snd_hdspm_get_playback_mixer, \
3634   .put = snd_hdspm_put_playback_mixer \
3635 }
3636
3637 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3638                                          struct snd_ctl_elem_info *uinfo)
3639 {
3640         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3641         uinfo->count = 1;
3642         uinfo->value.integer.min = 0;
3643         uinfo->value.integer.max = 64;
3644         uinfo->value.integer.step = 1;
3645         return 0;
3646 }
3647
3648 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3649                                         struct snd_ctl_elem_value *ucontrol)
3650 {
3651         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3652         int channel;
3653
3654         channel = ucontrol->id.index - 1;
3655
3656         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3657                 return -EINVAL;
3658
3659         spin_lock_irq(&hdspm->lock);
3660         ucontrol->value.integer.value[0] =
3661           (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3662         spin_unlock_irq(&hdspm->lock);
3663
3664         return 0;
3665 }
3666
3667 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3668                                         struct snd_ctl_elem_value *ucontrol)
3669 {
3670         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3671         int change;
3672         int channel;
3673         int gain;
3674
3675         if (!snd_hdspm_use_is_exclusive(hdspm))
3676                 return -EBUSY;
3677
3678         channel = ucontrol->id.index - 1;
3679
3680         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3681                 return -EINVAL;
3682
3683         gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3684
3685         spin_lock_irq(&hdspm->lock);
3686         change =
3687             gain != hdspm_read_pb_gain(hdspm, channel,
3688                                        channel);
3689         if (change)
3690                 hdspm_write_pb_gain(hdspm, channel, channel,
3691                                     gain);
3692         spin_unlock_irq(&hdspm->lock);
3693         return change;
3694 }
3695
3696 #define HDSPM_SYNC_CHECK(xname, xindex) \
3697 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3698         .name = xname, \
3699         .private_value = xindex, \
3700         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3701         .info = snd_hdspm_info_sync_check, \
3702         .get = snd_hdspm_get_sync_check \
3703 }
3704
3705
3706 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3707                                      struct snd_ctl_elem_info *uinfo)
3708 {
3709         static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3710         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3711         uinfo->count = 1;
3712         uinfo->value.enumerated.items = 4;
3713         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3714                 uinfo->value.enumerated.item =
3715                         uinfo->value.enumerated.items - 1;
3716         strcpy(uinfo->value.enumerated.name,
3717                         texts[uinfo->value.enumerated.item]);
3718         return 0;
3719 }
3720
3721 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3722 {
3723         int status, status2;
3724
3725         switch (hdspm->io_type) {
3726         case AES32:
3727                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3728                 if (status & HDSPM_wcSync)
3729                         return 2;
3730                 else if (status & HDSPM_wcLock)
3731                         return 1;
3732                 return 0;
3733                 break;
3734
3735         case MADI:
3736                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3737                 if (status2 & HDSPM_wcLock) {
3738                         if (status2 & HDSPM_wcSync)
3739                                 return 2;
3740                         else
3741                                 return 1;
3742                 }
3743                 return 0;
3744                 break;
3745
3746         case RayDAT:
3747         case AIO:
3748                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3749
3750                 if (status & 0x2000000)
3751                         return 2;
3752                 else if (status & 0x1000000)
3753                         return 1;
3754                 return 0;
3755
3756                 break;
3757
3758         case MADIface:
3759                 break;
3760         }
3761
3762
3763         return 3;
3764 }
3765
3766
3767 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3768 {
3769         int status = hdspm_read(hdspm, HDSPM_statusRegister);
3770         if (status & HDSPM_madiLock) {
3771                 if (status & HDSPM_madiSync)
3772                         return 2;
3773                 else
3774                         return 1;
3775         }
3776         return 0;
3777 }
3778
3779
3780 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3781 {
3782         int status, lock, sync;
3783
3784         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3785
3786         lock = (status & (0x1<<idx)) ? 1 : 0;
3787         sync = (status & (0x100<<idx)) ? 1 : 0;
3788
3789         if (lock && sync)
3790                 return 2;
3791         else if (lock)
3792                 return 1;
3793         return 0;
3794 }
3795
3796
3797 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3798 {
3799         int status, lock = 0, sync = 0;
3800
3801         switch (hdspm->io_type) {
3802         case RayDAT:
3803         case AIO:
3804                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3805                 lock = (status & 0x400) ? 1 : 0;
3806                 sync = (status & 0x800) ? 1 : 0;
3807                 break;
3808
3809         case MADI:
3810         case AES32:
3811                 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3812                 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3813                 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3814                 break;
3815
3816         case MADIface:
3817                 break;
3818         }
3819
3820         if (lock && sync)
3821                 return 2;
3822         else if (lock)
3823                 return 1;
3824
3825         return 0;
3826 }
3827
3828 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3829 {
3830         int status2, lock, sync;
3831         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3832
3833         lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3834         sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3835
3836         if (sync)
3837                 return 2;
3838         else if (lock)
3839                 return 1;
3840         return 0;
3841 }
3842
3843
3844 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3845 {
3846         int status;
3847
3848         if (hdspm->tco) {
3849                 switch (hdspm->io_type) {
3850                 case MADI:
3851                 case AES32:
3852                         status = hdspm_read(hdspm, HDSPM_statusRegister);
3853                         if (status & HDSPM_tcoLock) {
3854                                 if (status & HDSPM_tcoSync)
3855                                         return 2;
3856                                 else
3857                                         return 1;
3858                         }
3859                         return 0;
3860
3861                         break;
3862
3863                 case RayDAT:
3864                 case AIO:
3865                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3866
3867                         if (status & 0x8000000)
3868                                 return 2; /* Sync */
3869                         if (status & 0x4000000)
3870                                 return 1; /* Lock */
3871                         return 0; /* No signal */
3872                         break;
3873
3874                 default:
3875                         break;
3876                 }
3877         }
3878
3879         return 3; /* N/A */
3880 }
3881
3882
3883 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
3884                                     struct snd_ctl_elem_value *ucontrol)
3885 {
3886         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3887         int val = -1;
3888
3889         switch (hdspm->io_type) {
3890         case RayDAT:
3891                 switch (kcontrol->private_value) {
3892                 case 0: /* WC */
3893                         val = hdspm_wc_sync_check(hdspm); break;
3894                 case 7: /* TCO */
3895                         val = hdspm_tco_sync_check(hdspm); break;
3896                 case 8: /* SYNC IN */
3897                         val = hdspm_sync_in_sync_check(hdspm); break;
3898                 default:
3899                         val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3900                 }
3901
3902         case AIO:
3903                 switch (kcontrol->private_value) {
3904                 case 0: /* WC */
3905                         val = hdspm_wc_sync_check(hdspm); break;
3906                 case 4: /* TCO */
3907                         val = hdspm_tco_sync_check(hdspm); break;
3908                 case 5: /* SYNC IN */
3909                         val = hdspm_sync_in_sync_check(hdspm); break;
3910                 default:
3911                         val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3912                 }
3913
3914         case MADI:
3915                 switch (kcontrol->private_value) {
3916                 case 0: /* WC */
3917                         val = hdspm_wc_sync_check(hdspm); break;
3918                 case 1: /* MADI */
3919                         val = hdspm_madi_sync_check(hdspm); break;
3920                 case 2: /* TCO */
3921                         val = hdspm_tco_sync_check(hdspm); break;
3922                 case 3: /* SYNC_IN */
3923                         val = hdspm_sync_in_sync_check(hdspm); break;
3924                 }
3925
3926         case MADIface:
3927                 val = hdspm_madi_sync_check(hdspm); /* MADI */
3928                 break;
3929
3930         case AES32:
3931                 switch (kcontrol->private_value) {
3932                 case 0: /* WC */
3933                         val = hdspm_wc_sync_check(hdspm); break;
3934                 case 9: /* TCO */
3935                         val = hdspm_tco_sync_check(hdspm); break;
3936                 case 10 /* SYNC IN */:
3937                         val = hdspm_sync_in_sync_check(hdspm); break;
3938                 default: /* AES1 to AES8 */
3939                          val = hdspm_aes_sync_check(hdspm,
3940                                          kcontrol->private_value-1);
3941                 }
3942
3943         }
3944
3945         if (-1 == val)
3946                 val = 3;
3947
3948         ucontrol->value.enumerated.item[0] = val;
3949         return 0;
3950 }
3951
3952
3953
3954 /**
3955  * TCO controls
3956  **/
3957 static void hdspm_tco_write(struct hdspm *hdspm)
3958 {
3959         unsigned int tc[4] = { 0, 0, 0, 0};
3960
3961         switch (hdspm->tco->input) {
3962         case 0:
3963                 tc[2] |= HDSPM_TCO2_set_input_MSB;
3964                 break;
3965         case 1:
3966                 tc[2] |= HDSPM_TCO2_set_input_LSB;
3967                 break;
3968         default:
3969                 break;
3970         }
3971
3972         switch (hdspm->tco->framerate) {
3973         case 1:
3974                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
3975                 break;
3976         case 2:
3977                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
3978                 break;
3979         case 3:
3980                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
3981                         HDSPM_TCO1_set_drop_frame_flag;
3982                 break;
3983         case 4:
3984                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
3985                         HDSPM_TCO1_LTC_Format_MSB;
3986                 break;
3987         case 5:
3988                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
3989                         HDSPM_TCO1_LTC_Format_MSB +
3990                         HDSPM_TCO1_set_drop_frame_flag;
3991                 break;
3992         default:
3993                 break;
3994         }
3995
3996         switch (hdspm->tco->wordclock) {
3997         case 1:
3998                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
3999                 break;
4000         case 2:
4001                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
4002                 break;
4003         default:
4004                 break;
4005         }
4006
4007         switch (hdspm->tco->samplerate) {
4008         case 1:
4009                 tc[2] |= HDSPM_TCO2_set_freq;
4010                 break;
4011         case 2:
4012                 tc[2] |= HDSPM_TCO2_set_freq_from_app;
4013                 break;
4014         default:
4015                 break;
4016         }
4017
4018         switch (hdspm->tco->pull) {
4019         case 1:
4020                 tc[2] |= HDSPM_TCO2_set_pull_up;
4021                 break;
4022         case 2:
4023                 tc[2] |= HDSPM_TCO2_set_pull_down;
4024                 break;
4025         case 3:
4026                 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4027                 break;
4028         case 4:
4029                 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4030                 break;
4031         default:
4032                 break;
4033         }
4034
4035         if (1 == hdspm->tco->term) {
4036                 tc[2] |= HDSPM_TCO2_set_term_75R;
4037         }
4038
4039         hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4040         hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4041         hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4042         hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4043 }
4044
4045
4046 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4047 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4048         .name = xname, \
4049         .index = xindex, \
4050         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4051                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4052         .info = snd_hdspm_info_tco_sample_rate, \
4053         .get = snd_hdspm_get_tco_sample_rate, \
4054         .put = snd_hdspm_put_tco_sample_rate \
4055 }
4056
4057 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4058                                           struct snd_ctl_elem_info *uinfo)
4059 {
4060         static char *texts[] = { "44.1 kHz", "48 kHz" };
4061         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4062         uinfo->count = 1;
4063         uinfo->value.enumerated.items = 2;
4064
4065         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4066                 uinfo->value.enumerated.item =
4067                         uinfo->value.enumerated.items - 1;
4068
4069         strcpy(uinfo->value.enumerated.name,
4070                         texts[uinfo->value.enumerated.item]);
4071
4072         return 0;
4073 }
4074
4075 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4076                                       struct snd_ctl_elem_value *ucontrol)
4077 {
4078         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4079
4080         ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4081
4082         return 0;
4083 }
4084
4085 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4086                                          struct snd_ctl_elem_value *ucontrol)
4087 {
4088         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4089
4090         if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4091                 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4092
4093                 hdspm_tco_write(hdspm);
4094
4095                 return 1;
4096         }
4097
4098         return 0;
4099 }
4100
4101
4102 #define HDSPM_TCO_PULL(xname, xindex) \
4103 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4104         .name = xname, \
4105         .index = xindex, \
4106         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4107                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4108         .info = snd_hdspm_info_tco_pull, \
4109         .get = snd_hdspm_get_tco_pull, \
4110         .put = snd_hdspm_put_tco_pull \
4111 }
4112
4113 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4114                                    struct snd_ctl_elem_info *uinfo)
4115 {
4116         static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" };
4117         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4118         uinfo->count = 1;
4119         uinfo->value.enumerated.items = 5;
4120
4121         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4122                 uinfo->value.enumerated.item =
4123                         uinfo->value.enumerated.items - 1;
4124
4125         strcpy(uinfo->value.enumerated.name,
4126                         texts[uinfo->value.enumerated.item]);
4127
4128         return 0;
4129 }
4130
4131 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4132                                   struct snd_ctl_elem_value *ucontrol)
4133 {
4134         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4135
4136         ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4137
4138         return 0;
4139 }
4140
4141 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4142                                   struct snd_ctl_elem_value *ucontrol)
4143 {
4144         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4145
4146         if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4147                 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4148
4149                 hdspm_tco_write(hdspm);
4150
4151                 return 1;
4152         }
4153
4154         return 0;
4155 }
4156
4157 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4158 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4159         .name = xname, \
4160         .index = xindex, \
4161         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4162                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4163         .info = snd_hdspm_info_tco_wck_conversion, \
4164         .get = snd_hdspm_get_tco_wck_conversion, \
4165         .put = snd_hdspm_put_tco_wck_conversion \
4166 }
4167
4168 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4169                                              struct snd_ctl_elem_info *uinfo)
4170 {
4171         static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4172         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4173         uinfo->count = 1;
4174         uinfo->value.enumerated.items = 3;
4175
4176         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4177                 uinfo->value.enumerated.item =
4178                         uinfo->value.enumerated.items - 1;
4179
4180         strcpy(uinfo->value.enumerated.name,
4181                         texts[uinfo->value.enumerated.item]);
4182
4183         return 0;
4184 }
4185
4186 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4187                                             struct snd_ctl_elem_value *ucontrol)
4188 {
4189         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4190
4191         ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4192
4193         return 0;
4194 }
4195
4196 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4197                                             struct snd_ctl_elem_value *ucontrol)
4198 {
4199         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4200
4201         if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4202                 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4203
4204                 hdspm_tco_write(hdspm);
4205
4206                 return 1;
4207         }
4208
4209         return 0;
4210 }
4211
4212
4213 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4214 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4215         .name = xname, \
4216         .index = xindex, \
4217         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4218                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4219         .info = snd_hdspm_info_tco_frame_rate, \
4220         .get = snd_hdspm_get_tco_frame_rate, \
4221         .put = snd_hdspm_put_tco_frame_rate \
4222 }
4223
4224 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4225                                           struct snd_ctl_elem_info *uinfo)
4226 {
4227         static char *texts[] = { "24 fps", "25 fps", "29.97fps",
4228                 "29.97 dfps", "30 fps", "30 dfps" };
4229         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4230         uinfo->count = 1;
4231         uinfo->value.enumerated.items = 6;
4232
4233         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4234                 uinfo->value.enumerated.item =
4235                         uinfo->value.enumerated.items - 1;
4236
4237         strcpy(uinfo->value.enumerated.name,
4238                         texts[uinfo->value.enumerated.item]);
4239
4240         return 0;
4241 }
4242
4243 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4244                                         struct snd_ctl_elem_value *ucontrol)
4245 {
4246         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4247
4248         ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4249
4250         return 0;
4251 }
4252
4253 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4254                                         struct snd_ctl_elem_value *ucontrol)
4255 {
4256         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4257
4258         if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4259                 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4260
4261                 hdspm_tco_write(hdspm);
4262
4263                 return 1;
4264         }
4265
4266         return 0;
4267 }
4268
4269
4270 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4271 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4272         .name = xname, \
4273         .index = xindex, \
4274         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4275                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4276         .info = snd_hdspm_info_tco_sync_source, \
4277         .get = snd_hdspm_get_tco_sync_source, \
4278         .put = snd_hdspm_put_tco_sync_source \
4279 }
4280
4281 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4282                                           struct snd_ctl_elem_info *uinfo)
4283 {
4284         static char *texts[] = { "LTC", "Video", "WCK" };
4285         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4286         uinfo->count = 1;
4287         uinfo->value.enumerated.items = 3;
4288
4289         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4290                 uinfo->value.enumerated.item =
4291                         uinfo->value.enumerated.items - 1;
4292
4293         strcpy(uinfo->value.enumerated.name,
4294                         texts[uinfo->value.enumerated.item]);
4295
4296         return 0;
4297 }
4298
4299 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4300                                          struct snd_ctl_elem_value *ucontrol)
4301 {
4302         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4303
4304         ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4305
4306         return 0;
4307 }
4308
4309 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4310                                          struct snd_ctl_elem_value *ucontrol)
4311 {
4312         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4313
4314         if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4315                 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4316
4317                 hdspm_tco_write(hdspm);
4318
4319                 return 1;
4320         }
4321
4322         return 0;
4323 }
4324
4325
4326 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4327 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4328         .name = xname, \
4329         .index = xindex, \
4330         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4331                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4332         .info = snd_hdspm_info_tco_word_term, \
4333         .get = snd_hdspm_get_tco_word_term, \
4334         .put = snd_hdspm_put_tco_word_term \
4335 }
4336
4337 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4338                                         struct snd_ctl_elem_info *uinfo)
4339 {
4340         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4341         uinfo->count = 1;
4342         uinfo->value.integer.min = 0;
4343         uinfo->value.integer.max = 1;
4344
4345         return 0;
4346 }
4347
4348
4349 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4350                                        struct snd_ctl_elem_value *ucontrol)
4351 {
4352         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4353
4354         ucontrol->value.enumerated.item[0] = hdspm->tco->term;
4355
4356         return 0;
4357 }
4358
4359
4360 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4361                                        struct snd_ctl_elem_value *ucontrol)
4362 {
4363         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4364
4365         if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
4366                 hdspm->tco->term = ucontrol->value.enumerated.item[0];
4367
4368                 hdspm_tco_write(hdspm);
4369
4370                 return 1;
4371         }
4372
4373         return 0;
4374 }
4375
4376
4377
4378
4379 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4380         HDSPM_MIXER("Mixer", 0),
4381         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4382         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4383         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4384         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4385         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4386         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4387         HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4388         HDSPM_SYNC_CHECK("TCO SyncCHeck", 2),
4389         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4390         HDSPM_LINE_OUT("Line Out", 0),
4391         HDSPM_TX_64("TX 64 channels mode", 0),
4392         HDSPM_C_TMS("Clear Track Marker", 0),
4393         HDSPM_SAFE_MODE("Safe Mode", 0),
4394         HDSPM_INPUT_SELECT("Input Select", 0),
4395         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4396 };
4397
4398
4399 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4400         HDSPM_MIXER("Mixer", 0),
4401         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4402         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4403         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4404         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4405         HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4406         HDSPM_TX_64("TX 64 channels mode", 0),
4407         HDSPM_C_TMS("Clear Track Marker", 0),
4408         HDSPM_SAFE_MODE("Safe Mode", 0),
4409         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4410 };
4411
4412 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4413         HDSPM_MIXER("Mixer", 0),
4414         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4415         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4416         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4417         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4418         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4419         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4420         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4421         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4422         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4423         HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4424         HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4425         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4426         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4427         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4428         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4429         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4430         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4431         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5)
4432
4433                 /*
4434                    HDSPM_INPUT_SELECT("Input Select", 0),
4435                    HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4436                    HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4437                    HDSPM_SPDIF_IN("SPDIF In", 0);
4438                    HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4439                    HDSPM_INPUT_LEVEL("Input Level", 0);
4440                    HDSPM_OUTPUT_LEVEL("Output Level", 0);
4441                    HDSPM_PHONES("Phones", 0);
4442                    */
4443 };
4444
4445 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4446         HDSPM_MIXER("Mixer", 0),
4447         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4448         HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4449         HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4450         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4451         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4452         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4453         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4454         HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4455         HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4456         HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4457         HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4458         HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4459         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4460         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4461         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4462         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4463         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4464         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4465         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4466         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4467         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4468         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8)
4469 };
4470
4471 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4472         HDSPM_MIXER("Mixer", 0),
4473         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4474         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4475         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4476         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4477         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4478         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4479         HDSPM_SYNC_CHECK("WC Sync Check", 0),
4480         HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4481         HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4482         HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4483         HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4484         HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4485         HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4486         HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4487         HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4488         HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4489         HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4490         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4491         HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4492         HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4493         HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4494         HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4495         HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4496         HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4497         HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4498         HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4499         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4500         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4501         HDSPM_LINE_OUT("Line Out", 0),
4502         HDSPM_EMPHASIS("Emphasis", 0),
4503         HDSPM_DOLBY("Non Audio", 0),
4504         HDSPM_PROFESSIONAL("Professional", 0),
4505         HDSPM_C_TMS("Clear Track Marker", 0),
4506         HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4507         HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4508 };
4509
4510
4511
4512 /* Control elements for the optional TCO module */
4513 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4514         HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4515         HDSPM_TCO_PULL("TCO Pull", 0),
4516         HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4517         HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4518         HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4519         HDSPM_TCO_WORD_TERM("TCO Word Term", 0)
4520 };
4521
4522
4523 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4524
4525
4526 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4527 {
4528         int i;
4529
4530         for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4531                 if (hdspm->system_sample_rate > 48000) {
4532                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4533                                 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4534                                 SNDRV_CTL_ELEM_ACCESS_READ |
4535                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4536                 } else {
4537                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4538                                 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4539                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4540                 }
4541                 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4542                                 SNDRV_CTL_EVENT_MASK_INFO,
4543                                 &hdspm->playback_mixer_ctls[i]->id);
4544         }
4545
4546         return 0;
4547 }
4548
4549
4550 static int snd_hdspm_create_controls(struct snd_card *card,
4551                                         struct hdspm *hdspm)
4552 {
4553         unsigned int idx, limit;
4554         int err;
4555         struct snd_kcontrol *kctl;
4556         struct snd_kcontrol_new *list = NULL;
4557
4558         switch (hdspm->io_type) {
4559         case MADI:
4560                 list = snd_hdspm_controls_madi;
4561                 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4562                 break;
4563         case MADIface:
4564                 list = snd_hdspm_controls_madiface;
4565                 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4566                 break;
4567         case AIO:
4568                 list = snd_hdspm_controls_aio;
4569                 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4570                 break;
4571         case RayDAT:
4572                 list = snd_hdspm_controls_raydat;
4573                 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4574                 break;
4575         case AES32:
4576                 list = snd_hdspm_controls_aes32;
4577                 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4578                 break;
4579         }
4580
4581         if (NULL != list) {
4582                 for (idx = 0; idx < limit; idx++) {
4583                         err = snd_ctl_add(card,
4584                                         snd_ctl_new1(&list[idx], hdspm));
4585                         if (err < 0)
4586                                 return err;
4587                 }
4588         }
4589
4590
4591         /* create simple 1:1 playback mixer controls */
4592         snd_hdspm_playback_mixer.name = "Chn";
4593         if (hdspm->system_sample_rate >= 128000) {
4594                 limit = hdspm->qs_out_channels;
4595         } else if (hdspm->system_sample_rate >= 64000) {
4596                 limit = hdspm->ds_out_channels;
4597         } else {
4598                 limit = hdspm->ss_out_channels;
4599         }
4600         for (idx = 0; idx < limit; ++idx) {
4601                 snd_hdspm_playback_mixer.index = idx + 1;
4602                 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4603                 err = snd_ctl_add(card, kctl);
4604                 if (err < 0)
4605                         return err;
4606                 hdspm->playback_mixer_ctls[idx] = kctl;
4607         }
4608
4609
4610         if (hdspm->tco) {
4611                 /* add tco control elements */
4612                 list = snd_hdspm_controls_tco;
4613                 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4614                 for (idx = 0; idx < limit; idx++) {
4615                         err = snd_ctl_add(card,
4616                                         snd_ctl_new1(&list[idx], hdspm));
4617                         if (err < 0)
4618                                 return err;
4619                 }
4620         }
4621
4622         return 0;
4623 }
4624
4625 /*------------------------------------------------------------
4626    /proc interface
4627  ------------------------------------------------------------*/
4628
4629 static void
4630 snd_hdspm_proc_read_madi(struct snd_info_entry * entry,
4631                          struct snd_info_buffer *buffer)
4632 {
4633         struct hdspm *hdspm = entry->private_data;
4634         unsigned int status, status2, control, freq;
4635
4636         char *pref_sync_ref;
4637         char *autosync_ref;
4638         char *system_clock_mode;
4639         char *insel;
4640         int x, x2;
4641
4642         /* TCO stuff */
4643         int a, ltc, frames, seconds, minutes, hours;
4644         unsigned int period;
4645         u64 freq_const = 0;
4646         u32 rate;
4647
4648         status = hdspm_read(hdspm, HDSPM_statusRegister);
4649         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4650         control = hdspm->control_register;
4651         freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
4652
4653         snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4654                         hdspm->card_name, hdspm->card->number + 1,
4655                         hdspm->firmware_rev,
4656                         (status2 & HDSPM_version0) |
4657                         (status2 & HDSPM_version1) | (status2 &
4658                                 HDSPM_version2));
4659
4660         snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4661                         (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4662                         (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF);
4663
4664         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4665                         hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4666
4667         snd_iprintf(buffer, "--- System ---\n");
4668
4669         snd_iprintf(buffer,
4670                 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4671                 status & HDSPM_audioIRQPending,
4672                 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4673                 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4674                 hdspm->irq_count);
4675         snd_iprintf(buffer,
4676                 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4677                 "estimated= %ld (bytes)\n",
4678                 ((status & HDSPM_BufferID) ? 1 : 0),
4679                 (status & HDSPM_BufferPositionMask),
4680                 (status & HDSPM_BufferPositionMask) %
4681                 (2 * (int)hdspm->period_bytes),
4682                 ((status & HDSPM_BufferPositionMask) - 64) %
4683                 (2 * (int)hdspm->period_bytes),
4684                 (long) hdspm_hw_pointer(hdspm) * 4);
4685
4686         snd_iprintf(buffer,
4687                 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4688                 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4689                 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4690                 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4691                 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4692         snd_iprintf(buffer,
4693                 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4694                 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4695                 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4696         snd_iprintf(buffer,
4697                 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4698                 "status2=0x%x\n",
4699                 hdspm->control_register, hdspm->control2_register,
4700                 status, status2);
4701         if (status & HDSPM_tco_detect) {
4702                 snd_iprintf(buffer, "TCO module detected.\n");
4703                 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4704                 if (a & HDSPM_TCO1_LTC_Input_valid) {
4705                         snd_iprintf(buffer, "  LTC valid, ");
4706                         switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4707                                                 HDSPM_TCO1_LTC_Format_MSB)) {
4708                         case 0:
4709                                 snd_iprintf(buffer, "24 fps, ");
4710                                 break;
4711                         case HDSPM_TCO1_LTC_Format_LSB:
4712                                 snd_iprintf(buffer, "25 fps, ");
4713                                 break;
4714                         case HDSPM_TCO1_LTC_Format_MSB:
4715                                 snd_iprintf(buffer, "29.97 fps, ");
4716                                 break;
4717                         default:
4718                                 snd_iprintf(buffer, "30 fps, ");
4719                                 break;
4720                         }
4721                         if (a & HDSPM_TCO1_set_drop_frame_flag) {
4722                                 snd_iprintf(buffer, "drop frame\n");
4723                         } else {
4724                                 snd_iprintf(buffer, "full frame\n");
4725                         }
4726                 } else {
4727                         snd_iprintf(buffer, "  no LTC\n");
4728                 }
4729                 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4730                         snd_iprintf(buffer, "  Video: NTSC\n");
4731                 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4732                         snd_iprintf(buffer, "  Video: PAL\n");
4733                 } else {
4734                         snd_iprintf(buffer, "  No video\n");
4735                 }
4736                 if (a & HDSPM_TCO1_TCO_lock) {
4737                         snd_iprintf(buffer, "  Sync: lock\n");
4738                 } else {
4739                         snd_iprintf(buffer, "  Sync: no lock\n");
4740                 }
4741
4742                 switch (hdspm->io_type) {
4743                 case MADI:
4744                 case AES32:
4745                         freq_const = 110069313433624ULL;
4746                         break;
4747                 case RayDAT:
4748                 case AIO:
4749                         freq_const = 104857600000000ULL;
4750                         break;
4751                 case MADIface:
4752                         break; /* no TCO possible */
4753                 }
4754
4755                 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4756                 snd_iprintf(buffer, "    period: %u\n", period);
4757
4758
4759                 /* rate = freq_const/period; */
4760                 rate = div_u64(freq_const, period);
4761
4762                 if (control & HDSPM_QuadSpeed) {
4763                         rate *= 4;
4764                 } else if (control & HDSPM_DoubleSpeed) {
4765                         rate *= 2;
4766                 }
4767
4768                 snd_iprintf(buffer, "  Frequency: %u Hz\n",
4769                                 (unsigned int) rate);
4770
4771                 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4772                 frames = ltc & 0xF;
4773                 ltc >>= 4;
4774                 frames += (ltc & 0x3) * 10;
4775                 ltc >>= 4;
4776                 seconds = ltc & 0xF;
4777                 ltc >>= 4;
4778                 seconds += (ltc & 0x7) * 10;
4779                 ltc >>= 4;
4780                 minutes = ltc & 0xF;
4781                 ltc >>= 4;
4782                 minutes += (ltc & 0x7) * 10;
4783                 ltc >>= 4;
4784                 hours = ltc & 0xF;
4785                 ltc >>= 4;
4786                 hours += (ltc & 0x3) * 10;
4787                 snd_iprintf(buffer,
4788                         "  LTC In: %02d:%02d:%02d:%02d\n",
4789                         hours, minutes, seconds, frames);
4790
4791         } else {
4792                 snd_iprintf(buffer, "No TCO module detected.\n");
4793         }
4794
4795         snd_iprintf(buffer, "--- Settings ---\n");
4796
4797         x = 1 << (6 + hdspm_decode_latency(hdspm->control_register &
4798                                                         HDSPM_LatencyMask));
4799
4800         snd_iprintf(buffer,
4801                 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4802                 x, (unsigned long) hdspm->period_bytes);
4803
4804         snd_iprintf(buffer, "Line out: %s\n",
4805                 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4806
4807         switch (hdspm->control_register & HDSPM_InputMask) {
4808         case HDSPM_InputOptical:
4809                 insel = "Optical";
4810                 break;
4811         case HDSPM_InputCoaxial:
4812                 insel = "Coaxial";
4813                 break;
4814         default:
4815                 insel = "Unkown";
4816         }
4817
4818         snd_iprintf(buffer,
4819                 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4820                 "Auto Input %s\n",
4821                 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4822                 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4823                 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4824
4825
4826         if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4827                 system_clock_mode = "AutoSync";
4828         else
4829                 system_clock_mode = "Master";
4830         snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4831
4832         switch (hdspm_pref_sync_ref(hdspm)) {
4833         case HDSPM_SYNC_FROM_WORD:
4834                 pref_sync_ref = "Word Clock";
4835                 break;
4836         case HDSPM_SYNC_FROM_MADI:
4837                 pref_sync_ref = "MADI Sync";
4838                 break;
4839         case HDSPM_SYNC_FROM_TCO:
4840                 pref_sync_ref = "TCO";
4841                 break;
4842         case HDSPM_SYNC_FROM_SYNC_IN:
4843                 pref_sync_ref = "Sync In";
4844                 break;
4845         default:
4846                 pref_sync_ref = "XXXX Clock";
4847                 break;
4848         }
4849         snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4850                         pref_sync_ref);
4851
4852         snd_iprintf(buffer, "System Clock Frequency: %d\n",
4853                         hdspm->system_sample_rate);
4854
4855
4856         snd_iprintf(buffer, "--- Status:\n");
4857
4858         x = status & HDSPM_madiSync;
4859         x2 = status2 & HDSPM_wcSync;
4860
4861         snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4862                         (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4863                         "NoLock",
4864                         (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4865                         "NoLock");
4866
4867         switch (hdspm_autosync_ref(hdspm)) {
4868         case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4869                 autosync_ref = "Sync In";
4870                 break;
4871         case HDSPM_AUTOSYNC_FROM_TCO:
4872                 autosync_ref = "TCO";
4873                 break;
4874         case HDSPM_AUTOSYNC_FROM_WORD:
4875                 autosync_ref = "Word Clock";
4876                 break;
4877         case HDSPM_AUTOSYNC_FROM_MADI:
4878                 autosync_ref = "MADI Sync";
4879                 break;
4880         case HDSPM_AUTOSYNC_FROM_NONE:
4881                 autosync_ref = "Input not valid";
4882                 break;
4883         default:
4884                 autosync_ref = "---";
4885                 break;
4886         }
4887         snd_iprintf(buffer,
4888                 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
4889                 autosync_ref, hdspm_external_sample_rate(hdspm),
4890                 (status & HDSPM_madiFreqMask) >> 22,
4891                 (status2 & HDSPM_wcFreqMask) >> 5);
4892
4893         snd_iprintf(buffer, "Input: %s, Mode=%s\n",
4894                 (status & HDSPM_AB_int) ? "Coax" : "Optical",
4895                 (status & HDSPM_RX_64ch) ? "64 channels" :
4896                 "56 channels");
4897
4898         snd_iprintf(buffer, "\n");
4899 }
4900
4901 static void
4902 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
4903                           struct snd_info_buffer *buffer)
4904 {
4905         struct hdspm *hdspm = entry->private_data;
4906         unsigned int status;
4907         unsigned int status2;
4908         unsigned int timecode;
4909         int pref_syncref;
4910         char *autosync_ref;
4911         int x;
4912
4913         status = hdspm_read(hdspm, HDSPM_statusRegister);
4914         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4915         timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
4916
4917         snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
4918                     hdspm->card_name, hdspm->card->number + 1,
4919                     hdspm->firmware_rev);
4920
4921         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4922                     hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4923
4924         snd_iprintf(buffer, "--- System ---\n");
4925
4926         snd_iprintf(buffer,
4927                     "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4928                     status & HDSPM_audioIRQPending,
4929                     (status & HDSPM_midi0IRQPending) ? 1 : 0,
4930                     (status & HDSPM_midi1IRQPending) ? 1 : 0,
4931                     hdspm->irq_count);
4932         snd_iprintf(buffer,
4933                     "HW pointer: id = %d, rawptr = %d (%d->%d) "
4934                     "estimated= %ld (bytes)\n",
4935                     ((status & HDSPM_BufferID) ? 1 : 0),
4936                     (status & HDSPM_BufferPositionMask),
4937                     (status & HDSPM_BufferPositionMask) %
4938                     (2 * (int)hdspm->period_bytes),
4939                     ((status & HDSPM_BufferPositionMask) - 64) %
4940                     (2 * (int)hdspm->period_bytes),
4941                     (long) hdspm_hw_pointer(hdspm) * 4);
4942
4943         snd_iprintf(buffer,
4944                     "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4945                     hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4946                     hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4947                     hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4948                     hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4949         snd_iprintf(buffer,
4950                     "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4951                     hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4952                     hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4953         snd_iprintf(buffer,
4954                     "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4955                     "status2=0x%x\n",
4956                     hdspm->control_register, hdspm->control2_register,
4957                     status, status2);
4958
4959         snd_iprintf(buffer, "--- Settings ---\n");
4960
4961         x = 1 << (6 + hdspm_decode_latency(hdspm->control_register &
4962                                 HDSPM_LatencyMask));
4963
4964         snd_iprintf(buffer,
4965                     "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4966                     x, (unsigned long) hdspm->period_bytes);
4967
4968         snd_iprintf(buffer, "Line out: %s\n",
4969                     (hdspm->
4970                      control_register & HDSPM_LineOut) ? "on " : "off");
4971
4972         snd_iprintf(buffer,
4973                     "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
4974                     (hdspm->
4975                      control_register & HDSPM_clr_tms) ? "on" : "off",
4976                     (hdspm->
4977                      control_register & HDSPM_Emphasis) ? "on" : "off",
4978                     (hdspm->
4979                      control_register & HDSPM_Dolby) ? "on" : "off");
4980
4981
4982         pref_syncref = hdspm_pref_sync_ref(hdspm);
4983         if (pref_syncref == 0)
4984                 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
4985         else
4986                 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
4987                                 pref_syncref);
4988
4989         snd_iprintf(buffer, "System Clock Frequency: %d\n",
4990                     hdspm->system_sample_rate);
4991
4992         snd_iprintf(buffer, "Double speed: %s\n",
4993                         hdspm->control_register & HDSPM_DS_DoubleWire?
4994                         "Double wire" : "Single wire");
4995         snd_iprintf(buffer, "Quad speed: %s\n",
4996                         hdspm->control_register & HDSPM_QS_DoubleWire?
4997                         "Double wire" :
4998                         hdspm->control_register & HDSPM_QS_QuadWire?
4999                         "Quad wire" : "Single wire");
5000
5001         snd_iprintf(buffer, "--- Status:\n");
5002
5003         snd_iprintf(buffer, "Word: %s  Frequency: %d\n",
5004                     (status & HDSPM_AES32_wcLock) ? "Sync   " : "No Lock",
5005                     HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
5006
5007         for (x = 0; x < 8; x++) {
5008                 snd_iprintf(buffer, "AES%d: %s  Frequency: %d\n",
5009                             x+1,
5010                             (status2 & (HDSPM_LockAES >> x)) ?
5011                             "Sync   " : "No Lock",
5012                             HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
5013         }
5014
5015         switch (hdspm_autosync_ref(hdspm)) {
5016         case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5017                 autosync_ref = "None"; break;
5018         case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5019                 autosync_ref = "Word Clock"; break;
5020         case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5021                 autosync_ref = "AES1"; break;
5022         case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5023                 autosync_ref = "AES2"; break;
5024         case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5025                 autosync_ref = "AES3"; break;
5026         case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5027                 autosync_ref = "AES4"; break;
5028         case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5029                 autosync_ref = "AES5"; break;
5030         case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5031                 autosync_ref = "AES6"; break;
5032         case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5033                 autosync_ref = "AES7"; break;
5034         case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5035                 autosync_ref = "AES8"; break;
5036         default:
5037                 autosync_ref = "---"; break;
5038         }
5039         snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5040
5041         snd_iprintf(buffer, "\n");
5042 }
5043
5044 static void
5045 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5046                          struct snd_info_buffer *buffer)
5047 {
5048         struct hdspm *hdspm = entry->private_data;
5049         unsigned int status1, status2, status3, control, i;
5050         unsigned int lock, sync;
5051
5052         status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5053         status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5054         status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5055
5056         control = hdspm->control_register;
5057
5058         snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5059         snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5060         snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5061
5062
5063         snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5064
5065         snd_iprintf(buffer, "Clock mode      : %s\n",
5066                 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5067         snd_iprintf(buffer, "System frequency: %d Hz\n",
5068                 hdspm_get_system_sample_rate(hdspm));
5069
5070         snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5071
5072         lock = 0x1;
5073         sync = 0x100;
5074
5075         for (i = 0; i < 8; i++) {
5076                 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5077                                 i,
5078                                 (status1 & lock) ? 1 : 0,
5079                                 (status1 & sync) ? 1 : 0,
5080                                 texts_freq[(status2 >> (i * 4)) & 0xF]);
5081
5082                 lock = lock<<1;
5083                 sync = sync<<1;
5084         }
5085
5086         snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5087                         (status1 & 0x1000000) ? 1 : 0,
5088                         (status1 & 0x2000000) ? 1 : 0,
5089                         texts_freq[(status1 >> 16) & 0xF]);
5090
5091         snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5092                         (status1 & 0x4000000) ? 1 : 0,
5093                         (status1 & 0x8000000) ? 1 : 0,
5094                         texts_freq[(status1 >> 20) & 0xF]);
5095
5096         snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5097                         (status3 & 0x400) ? 1 : 0,
5098                         (status3 & 0x800) ? 1 : 0,
5099                         texts_freq[(status2 >> 12) & 0xF]);
5100
5101 }
5102
5103 #ifdef CONFIG_SND_DEBUG
5104 static void
5105 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5106                           struct snd_info_buffer *buffer)
5107 {
5108         struct hdspm *hdspm = entry->private_data;
5109
5110         int j,i;
5111
5112         for (i = 0; i < 256 /* 1024*64 */; i += j) {
5113                 snd_iprintf(buffer, "0x%08X: ", i);
5114                 for (j = 0; j < 16; j += 4)
5115                         snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5116                 snd_iprintf(buffer, "\n");
5117         }
5118 }
5119 #endif
5120
5121
5122 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5123                           struct snd_info_buffer *buffer)
5124 {
5125         struct hdspm *hdspm = entry->private_data;
5126         int i;
5127
5128         snd_iprintf(buffer, "# generated by hdspm\n");
5129
5130         for (i = 0; i < hdspm->max_channels_in; i++) {
5131                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5132         }
5133 }
5134
5135 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5136                           struct snd_info_buffer *buffer)
5137 {
5138         struct hdspm *hdspm = entry->private_data;
5139         int i;
5140
5141         snd_iprintf(buffer, "# generated by hdspm\n");
5142
5143         for (i = 0; i < hdspm->max_channels_out; i++) {
5144                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5145         }
5146 }
5147
5148
5149 static void __devinit snd_hdspm_proc_init(struct hdspm *hdspm)
5150 {
5151         struct snd_info_entry *entry;
5152
5153         if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5154                 switch (hdspm->io_type) {
5155                 case AES32:
5156                         snd_info_set_text_ops(entry, hdspm,
5157                                         snd_hdspm_proc_read_aes32);
5158                         break;
5159                 case MADI:
5160                         snd_info_set_text_ops(entry, hdspm,
5161                                         snd_hdspm_proc_read_madi);
5162                         break;
5163                 case MADIface:
5164                         /* snd_info_set_text_ops(entry, hdspm,
5165                          snd_hdspm_proc_read_madiface); */
5166                         break;
5167                 case RayDAT:
5168                         snd_info_set_text_ops(entry, hdspm,
5169                                         snd_hdspm_proc_read_raydat);
5170                         break;
5171                 case AIO:
5172                         break;
5173                 }
5174         }
5175
5176         if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5177                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5178         }
5179
5180         if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5181                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5182         }
5183
5184 #ifdef CONFIG_SND_DEBUG
5185         /* debug file to read all hdspm registers */
5186         if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5187                 snd_info_set_text_ops(entry, hdspm,
5188                                 snd_hdspm_proc_read_debug);
5189 #endif
5190 }
5191
5192 /*------------------------------------------------------------
5193    hdspm intitialize
5194  ------------------------------------------------------------*/
5195
5196 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5197 {
5198         /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5199            hold it (e.g. during module initialization).
5200            */
5201
5202         /* set defaults:       */
5203
5204         hdspm->settings_register = 0;
5205
5206         switch (hdspm->io_type) {
5207         case MADI:
5208         case MADIface:
5209                 hdspm->control_register =
5210                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5211                 break;
5212
5213         case RayDAT:
5214         case AIO:
5215                 hdspm->settings_register = 0x1 + 0x1000;
5216                 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5217                  * line_out */
5218                 hdspm->control_register =
5219                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5220                 break;
5221
5222         case AES32:
5223                 hdspm->control_register =
5224                         HDSPM_ClockModeMaster | /* Master Cloack Mode on */
5225                         hdspm_encode_latency(7) | /* latency max=8192samples */
5226                         HDSPM_SyncRef0 |        /* AES1 is syncclock */
5227                         HDSPM_LineOut | /* Analog output in */
5228                         HDSPM_Professional;  /* Professional mode */
5229                 break;
5230         }
5231
5232         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5233
5234         if (AES32 == hdspm->io_type) {
5235                 /* No control2 register for AES32 */
5236 #ifdef SNDRV_BIG_ENDIAN
5237                 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5238 #else
5239                 hdspm->control2_register = 0;
5240 #endif
5241
5242                 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5243         }
5244         hdspm_compute_period_size(hdspm);
5245
5246         /* silence everything */
5247
5248         all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5249
5250         if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) {
5251                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5252         }
5253
5254         /* set a default rate so that the channel map is set up. */
5255         hdspm_set_rate(hdspm, 48000, 1);
5256
5257         return 0;
5258 }
5259
5260
5261 /*------------------------------------------------------------
5262    interrupt
5263  ------------------------------------------------------------*/
5264
5265 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5266 {
5267         struct hdspm *hdspm = (struct hdspm *) dev_id;
5268         unsigned int status;
5269         int i, audio, midi, schedule = 0;
5270         /* cycles_t now; */
5271
5272         status = hdspm_read(hdspm, HDSPM_statusRegister);
5273
5274         audio = status & HDSPM_audioIRQPending;
5275         midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5276                         HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5277
5278         /* now = get_cycles(); */
5279         /**
5280          *   LAT_2..LAT_0 period  counter (win)  counter (mac)
5281          *          6       4096   ~256053425     ~514672358
5282          *          5       2048   ~128024983     ~257373821
5283          *          4       1024    ~64023706     ~128718089
5284          *          3        512    ~32005945      ~64385999
5285          *          2        256    ~16003039      ~32260176
5286          *          1        128     ~7998738      ~16194507
5287          *          0         64     ~3998231       ~8191558
5288          **/
5289         /*
5290            snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5291            now-hdspm->last_interrupt, status & 0xFFC0);
5292            hdspm->last_interrupt = now;
5293         */
5294
5295         if (!audio && !midi)
5296                 return IRQ_NONE;
5297
5298         hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5299         hdspm->irq_count++;
5300
5301
5302         if (audio) {
5303                 if (hdspm->capture_substream)
5304                         snd_pcm_period_elapsed(hdspm->capture_substream);
5305
5306                 if (hdspm->playback_substream)
5307                         snd_pcm_period_elapsed(hdspm->playback_substream);
5308         }
5309
5310         if (midi) {
5311                 i = 0;
5312                 while (i < hdspm->midiPorts) {
5313                         if ((hdspm_read(hdspm,
5314                                 hdspm->midi[i].statusIn) & 0xff) &&
5315                                         (status & hdspm->midi[i].irq)) {
5316                                 /* we disable interrupts for this input until
5317                                  * processing is done
5318                                  */
5319                                 hdspm->control_register &= ~hdspm->midi[i].ie;
5320                                 hdspm_write(hdspm, HDSPM_controlRegister,
5321                                                 hdspm->control_register);
5322                                 hdspm->midi[i].pending = 1;
5323                                 schedule = 1;
5324                         }
5325
5326                         i++;
5327                 }
5328
5329                 if (schedule)
5330                         tasklet_hi_schedule(&hdspm->midi_tasklet);
5331         }
5332
5333         return IRQ_HANDLED;
5334 }
5335
5336 /*------------------------------------------------------------
5337    pcm interface
5338   ------------------------------------------------------------*/
5339
5340
5341 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5342                                               *substream)
5343 {
5344         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5345         return hdspm_hw_pointer(hdspm);
5346 }
5347
5348
5349 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5350 {
5351         struct snd_pcm_runtime *runtime = substream->runtime;
5352         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5353         struct snd_pcm_substream *other;
5354
5355         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5356                 other = hdspm->capture_substream;
5357         else
5358                 other = hdspm->playback_substream;
5359
5360         if (hdspm->running)
5361                 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5362         else
5363                 runtime->status->hw_ptr = 0;
5364         if (other) {
5365                 struct snd_pcm_substream *s;
5366                 struct snd_pcm_runtime *oruntime = other->runtime;
5367                 snd_pcm_group_for_each_entry(s, substream) {
5368                         if (s == other) {
5369                                 oruntime->status->hw_ptr =
5370                                         runtime->status->hw_ptr;
5371                                 break;
5372                         }
5373                 }
5374         }
5375         return 0;
5376 }
5377
5378 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5379                                struct snd_pcm_hw_params *params)
5380 {
5381         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5382         int err;
5383         int i;
5384         pid_t this_pid;
5385         pid_t other_pid;
5386
5387         spin_lock_irq(&hdspm->lock);
5388
5389         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5390                 this_pid = hdspm->playback_pid;
5391                 other_pid = hdspm->capture_pid;
5392         } else {
5393                 this_pid = hdspm->capture_pid;
5394                 other_pid = hdspm->playback_pid;
5395         }
5396
5397         if (other_pid > 0 && this_pid != other_pid) {
5398
5399                 /* The other stream is open, and not by the same
5400                    task as this one. Make sure that the parameters
5401                    that matter are the same.
5402                    */
5403
5404                 if (params_rate(params) != hdspm->system_sample_rate) {
5405                         spin_unlock_irq(&hdspm->lock);
5406                         _snd_pcm_hw_param_setempty(params,
5407                                         SNDRV_PCM_HW_PARAM_RATE);
5408                         return -EBUSY;
5409                 }
5410
5411                 if (params_period_size(params) != hdspm->period_bytes / 4) {
5412                         spin_unlock_irq(&hdspm->lock);
5413                         _snd_pcm_hw_param_setempty(params,
5414                                         SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5415                         return -EBUSY;
5416                 }
5417
5418         }
5419         /* We're fine. */
5420         spin_unlock_irq(&hdspm->lock);
5421
5422         /* how to make sure that the rate matches an externally-set one ?   */
5423
5424         spin_lock_irq(&hdspm->lock);
5425         err = hdspm_set_rate(hdspm, params_rate(params), 0);
5426         if (err < 0) {
5427                 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
5428                 spin_unlock_irq(&hdspm->lock);
5429                 _snd_pcm_hw_param_setempty(params,
5430                                 SNDRV_PCM_HW_PARAM_RATE);
5431                 return err;
5432         }
5433         spin_unlock_irq(&hdspm->lock);
5434
5435         err = hdspm_set_interrupt_interval(hdspm,
5436                         params_period_size(params));
5437         if (err < 0) {
5438                 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
5439                 _snd_pcm_hw_param_setempty(params,
5440                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5441                 return err;
5442         }
5443
5444         /* Memory allocation, takashi's method, dont know if we should
5445          * spinlock
5446          */
5447         /* malloc all buffer even if not enabled to get sure */
5448         /* Update for MADI rev 204: we need to allocate for all channels,
5449          * otherwise it doesn't work at 96kHz */
5450
5451         err =
5452                 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5453         if (err < 0) {
5454                 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
5455                 return err;
5456         }
5457
5458         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5459
5460                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5461                                 params_channels(params));
5462
5463                 for (i = 0; i < params_channels(params); ++i)
5464                         snd_hdspm_enable_out(hdspm, i, 1);
5465
5466                 hdspm->playback_buffer =
5467                         (unsigned char *) substream->runtime->dma_area;
5468                 snd_printdd("Allocated sample buffer for playback at %p\n",
5469                                 hdspm->playback_buffer);
5470         } else {
5471                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5472                                 params_channels(params));
5473
5474                 for (i = 0; i < params_channels(params); ++i)
5475                         snd_hdspm_enable_in(hdspm, i, 1);
5476
5477                 hdspm->capture_buffer =
5478                         (unsigned char *) substream->runtime->dma_area;
5479                 snd_printdd("Allocated sample buffer for capture at %p\n",
5480                                 hdspm->capture_buffer);
5481         }
5482
5483         /*
5484            snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5485            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5486            "playback" : "capture",
5487            snd_pcm_sgbuf_get_addr(substream, 0));
5488            */
5489         /*
5490            snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5491            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5492            "playback" : "capture",
5493            params_rate(params), params_channels(params),
5494            params_buffer_size(params));
5495            */
5496
5497
5498         /* Switch to native float format if requested */
5499         if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5500                 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5501                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
5502
5503                 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5504         } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5505                 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5506                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
5507
5508                 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5509         }
5510         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5511
5512         return 0;
5513 }
5514
5515 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5516 {
5517         int i;
5518         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5519
5520         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5521
5522                 /* params_channels(params) should be enough,
5523                    but to get sure in case of error */
5524                 for (i = 0; i < hdspm->max_channels_out; ++i)
5525                         snd_hdspm_enable_out(hdspm, i, 0);
5526
5527                 hdspm->playback_buffer = NULL;
5528         } else {
5529                 for (i = 0; i < hdspm->max_channels_in; ++i)
5530                         snd_hdspm_enable_in(hdspm, i, 0);
5531
5532                 hdspm->capture_buffer = NULL;
5533
5534         }
5535
5536         snd_pcm_lib_free_pages(substream);
5537
5538         return 0;
5539 }
5540
5541
5542 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5543                 struct snd_pcm_channel_info *info)
5544 {
5545         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5546
5547         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5548                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5549                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
5550                         return -EINVAL;
5551                 }
5552
5553                 if (hdspm->channel_map_out[info->channel] < 0) {
5554                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
5555                         return -EINVAL;
5556                 }
5557
5558                 info->offset = hdspm->channel_map_out[info->channel] *
5559                         HDSPM_CHANNEL_BUFFER_BYTES;
5560         } else {
5561                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5562                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
5563                         return -EINVAL;
5564                 }
5565
5566                 if (hdspm->channel_map_in[info->channel] < 0) {
5567                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
5568                         return -EINVAL;
5569                 }
5570
5571                 info->offset = hdspm->channel_map_in[info->channel] *
5572                         HDSPM_CHANNEL_BUFFER_BYTES;
5573         }
5574
5575         info->first = 0;
5576         info->step = 32;
5577         return 0;
5578 }
5579
5580
5581 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5582                 unsigned int cmd, void *arg)
5583 {
5584         switch (cmd) {
5585         case SNDRV_PCM_IOCTL1_RESET:
5586                 return snd_hdspm_reset(substream);
5587
5588         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5589                 {
5590                         struct snd_pcm_channel_info *info = arg;
5591                         return snd_hdspm_channel_info(substream, info);
5592                 }
5593         default:
5594                 break;
5595         }
5596
5597         return snd_pcm_lib_ioctl(substream, cmd, arg);
5598 }
5599
5600 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5601 {
5602         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5603         struct snd_pcm_substream *other;
5604         int running;
5605
5606         spin_lock(&hdspm->lock);
5607         running = hdspm->running;
5608         switch (cmd) {
5609         case SNDRV_PCM_TRIGGER_START:
5610                 running |= 1 << substream->stream;
5611                 break;
5612         case SNDRV_PCM_TRIGGER_STOP:
5613                 running &= ~(1 << substream->stream);
5614                 break;
5615         default:
5616                 snd_BUG();
5617                 spin_unlock(&hdspm->lock);
5618                 return -EINVAL;
5619         }
5620         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5621                 other = hdspm->capture_substream;
5622         else
5623                 other = hdspm->playback_substream;
5624
5625         if (other) {
5626                 struct snd_pcm_substream *s;
5627                 snd_pcm_group_for_each_entry(s, substream) {
5628                         if (s == other) {
5629                                 snd_pcm_trigger_done(s, substream);
5630                                 if (cmd == SNDRV_PCM_TRIGGER_START)
5631                                         running |= 1 << s->stream;
5632                                 else
5633                                         running &= ~(1 << s->stream);
5634                                 goto _ok;
5635                         }
5636                 }
5637                 if (cmd == SNDRV_PCM_TRIGGER_START) {
5638                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5639                                         && substream->stream ==
5640                                         SNDRV_PCM_STREAM_CAPTURE)
5641                                 hdspm_silence_playback(hdspm);
5642                 } else {
5643                         if (running &&
5644                                 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5645                                 hdspm_silence_playback(hdspm);
5646                 }
5647         } else {
5648                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5649                         hdspm_silence_playback(hdspm);
5650         }
5651 _ok:
5652         snd_pcm_trigger_done(substream, substream);
5653         if (!hdspm->running && running)
5654                 hdspm_start_audio(hdspm);
5655         else if (hdspm->running && !running)
5656                 hdspm_stop_audio(hdspm);
5657         hdspm->running = running;
5658         spin_unlock(&hdspm->lock);
5659
5660         return 0;
5661 }
5662
5663 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5664 {
5665         return 0;
5666 }
5667
5668 static unsigned int period_sizes_old[] = {
5669         64, 128, 256, 512, 1024, 2048, 4096
5670 };
5671
5672 static unsigned int period_sizes_new[] = {
5673         32, 64, 128, 256, 512, 1024, 2048, 4096
5674 };
5675
5676 /* RayDAT and AIO always have a buffer of 16384 samples per channel */
5677 static unsigned int raydat_aio_buffer_sizes[] = {
5678         16384
5679 };
5680
5681 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5682         .info = (SNDRV_PCM_INFO_MMAP |
5683                  SNDRV_PCM_INFO_MMAP_VALID |
5684                  SNDRV_PCM_INFO_NONINTERLEAVED |
5685                  SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5686         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5687         .rates = (SNDRV_PCM_RATE_32000 |
5688                   SNDRV_PCM_RATE_44100 |
5689                   SNDRV_PCM_RATE_48000 |
5690                   SNDRV_PCM_RATE_64000 |
5691                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5692                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5693         .rate_min = 32000,
5694         .rate_max = 192000,
5695         .channels_min = 1,
5696         .channels_max = HDSPM_MAX_CHANNELS,
5697         .buffer_bytes_max =
5698             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5699         .period_bytes_min = (64 * 4),
5700         .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS,
5701         .periods_min = 2,
5702         .periods_max = 512,
5703         .fifo_size = 0
5704 };
5705
5706 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5707         .info = (SNDRV_PCM_INFO_MMAP |
5708                  SNDRV_PCM_INFO_MMAP_VALID |
5709                  SNDRV_PCM_INFO_NONINTERLEAVED |
5710                  SNDRV_PCM_INFO_SYNC_START),
5711         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5712         .rates = (SNDRV_PCM_RATE_32000 |
5713                   SNDRV_PCM_RATE_44100 |
5714                   SNDRV_PCM_RATE_48000 |
5715                   SNDRV_PCM_RATE_64000 |
5716                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5717                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5718         .rate_min = 32000,
5719         .rate_max = 192000,
5720         .channels_min = 1,
5721         .channels_max = HDSPM_MAX_CHANNELS,
5722         .buffer_bytes_max =
5723             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5724         .period_bytes_min = (64 * 4),
5725         .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS,
5726         .periods_min = 2,
5727         .periods_max = 512,
5728         .fifo_size = 0
5729 };
5730
5731 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_old = {
5732         .count = ARRAY_SIZE(period_sizes_old),
5733         .list = period_sizes_old,
5734         .mask = 0
5735 };
5736
5737 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_new = {
5738         .count = ARRAY_SIZE(period_sizes_new),
5739         .list = period_sizes_new,
5740         .mask = 0
5741 };
5742
5743 static struct snd_pcm_hw_constraint_list hw_constraints_raydat_io_buffer = {
5744         .count = ARRAY_SIZE(raydat_aio_buffer_sizes),
5745         .list = raydat_aio_buffer_sizes,
5746         .mask = 0
5747 };
5748
5749 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5750                                            struct snd_pcm_hw_rule *rule)
5751 {
5752         struct hdspm *hdspm = rule->private;
5753         struct snd_interval *c =
5754             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5755         struct snd_interval *r =
5756             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5757
5758         if (r->min > 96000 && r->max <= 192000) {
5759                 struct snd_interval t = {
5760                         .min = hdspm->qs_in_channels,
5761                         .max = hdspm->qs_in_channels,
5762                         .integer = 1,
5763                 };
5764                 return snd_interval_refine(c, &t);
5765         } else if (r->min > 48000 && r->max <= 96000) {
5766                 struct snd_interval t = {
5767                         .min = hdspm->ds_in_channels,
5768                         .max = hdspm->ds_in_channels,
5769                         .integer = 1,
5770                 };
5771                 return snd_interval_refine(c, &t);
5772         } else if (r->max < 64000) {
5773                 struct snd_interval t = {
5774                         .min = hdspm->ss_in_channels,
5775                         .max = hdspm->ss_in_channels,
5776                         .integer = 1,
5777                 };
5778                 return snd_interval_refine(c, &t);
5779         }
5780
5781         return 0;
5782 }
5783
5784 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5785                                            struct snd_pcm_hw_rule * rule)
5786 {
5787         struct hdspm *hdspm = rule->private;
5788         struct snd_interval *c =
5789             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5790         struct snd_interval *r =
5791             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5792
5793         if (r->min > 96000 && r->max <= 192000) {
5794                 struct snd_interval t = {
5795                         .min = hdspm->qs_out_channels,
5796                         .max = hdspm->qs_out_channels,
5797                         .integer = 1,
5798                 };
5799                 return snd_interval_refine(c, &t);
5800         } else if (r->min > 48000 && r->max <= 96000) {
5801                 struct snd_interval t = {
5802                         .min = hdspm->ds_out_channels,
5803                         .max = hdspm->ds_out_channels,
5804                         .integer = 1,
5805                 };
5806                 return snd_interval_refine(c, &t);
5807         } else if (r->max < 64000) {
5808                 struct snd_interval t = {
5809                         .min = hdspm->ss_out_channels,
5810                         .max = hdspm->ss_out_channels,
5811                         .integer = 1,
5812                 };
5813                 return snd_interval_refine(c, &t);
5814         } else {
5815         }
5816         return 0;
5817 }
5818
5819 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5820                                            struct snd_pcm_hw_rule * rule)
5821 {
5822         struct hdspm *hdspm = rule->private;
5823         struct snd_interval *c =
5824             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5825         struct snd_interval *r =
5826             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5827
5828         if (c->min >= hdspm->ss_in_channels) {
5829                 struct snd_interval t = {
5830                         .min = 32000,
5831                         .max = 48000,
5832                         .integer = 1,
5833                 };
5834                 return snd_interval_refine(r, &t);
5835         } else if (c->max <= hdspm->qs_in_channels) {
5836                 struct snd_interval t = {
5837                         .min = 128000,
5838                         .max = 192000,
5839                         .integer = 1,
5840                 };
5841                 return snd_interval_refine(r, &t);
5842         } else if (c->max <= hdspm->ds_in_channels) {
5843                 struct snd_interval t = {
5844                         .min = 64000,
5845                         .max = 96000,
5846                         .integer = 1,
5847                 };
5848                 return snd_interval_refine(r, &t);
5849         }
5850
5851         return 0;
5852 }
5853 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5854                                            struct snd_pcm_hw_rule *rule)
5855 {
5856         struct hdspm *hdspm = rule->private;
5857         struct snd_interval *c =
5858             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5859         struct snd_interval *r =
5860             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5861
5862         if (c->min >= hdspm->ss_out_channels) {
5863                 struct snd_interval t = {
5864                         .min = 32000,
5865                         .max = 48000,
5866                         .integer = 1,
5867                 };
5868                 return snd_interval_refine(r, &t);
5869         } else if (c->max <= hdspm->qs_out_channels) {
5870                 struct snd_interval t = {
5871                         .min = 128000,
5872                         .max = 192000,
5873                         .integer = 1,
5874                 };
5875                 return snd_interval_refine(r, &t);
5876         } else if (c->max <= hdspm->ds_out_channels) {
5877                 struct snd_interval t = {
5878                         .min = 64000,
5879                         .max = 96000,
5880                         .integer = 1,
5881                 };
5882                 return snd_interval_refine(r, &t);
5883         }
5884
5885         return 0;
5886 }
5887
5888 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
5889                                       struct snd_pcm_hw_rule *rule)
5890 {
5891         unsigned int list[3];
5892         struct hdspm *hdspm = rule->private;
5893         struct snd_interval *c = hw_param_interval(params,
5894                         SNDRV_PCM_HW_PARAM_CHANNELS);
5895
5896         list[0] = hdspm->qs_in_channels;
5897         list[1] = hdspm->ds_in_channels;
5898         list[2] = hdspm->ss_in_channels;
5899         return snd_interval_list(c, 3, list, 0);
5900 }
5901
5902 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
5903                                       struct snd_pcm_hw_rule *rule)
5904 {
5905         unsigned int list[3];
5906         struct hdspm *hdspm = rule->private;
5907         struct snd_interval *c = hw_param_interval(params,
5908                         SNDRV_PCM_HW_PARAM_CHANNELS);
5909
5910         list[0] = hdspm->qs_out_channels;
5911         list[1] = hdspm->ds_out_channels;
5912         list[2] = hdspm->ss_out_channels;
5913         return snd_interval_list(c, 3, list, 0);
5914 }
5915
5916
5917 static unsigned int hdspm_aes32_sample_rates[] = {
5918         32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
5919 };
5920
5921 static struct snd_pcm_hw_constraint_list
5922 hdspm_hw_constraints_aes32_sample_rates = {
5923         .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
5924         .list = hdspm_aes32_sample_rates,
5925         .mask = 0
5926 };
5927
5928 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
5929 {
5930         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5931         struct snd_pcm_runtime *runtime = substream->runtime;
5932
5933         spin_lock_irq(&hdspm->lock);
5934
5935         snd_pcm_set_sync(substream);
5936
5937
5938         runtime->hw = snd_hdspm_playback_subinfo;
5939
5940         if (hdspm->capture_substream == NULL)
5941                 hdspm_stop_audio(hdspm);
5942
5943         hdspm->playback_pid = current->pid;
5944         hdspm->playback_substream = substream;
5945
5946         spin_unlock_irq(&hdspm->lock);
5947
5948         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
5949
5950         switch (hdspm->io_type) {
5951         case AIO:
5952         case RayDAT:
5953                 snd_pcm_hw_constraint_list(runtime, 0,
5954                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5955                                 &hw_constraints_period_sizes_new);
5956                 snd_pcm_hw_constraint_list(runtime, 0,
5957                                 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
5958                                 &hw_constraints_raydat_io_buffer);
5959
5960                 break;
5961
5962         default:
5963                 snd_pcm_hw_constraint_list(runtime, 0,
5964                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5965                                 &hw_constraints_period_sizes_old);
5966         }
5967
5968         if (AES32 == hdspm->io_type) {
5969                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5970                                 &hdspm_hw_constraints_aes32_sample_rates);
5971         } else {
5972                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5973                                 snd_hdspm_hw_rule_rate_out_channels, hdspm,
5974                                 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5975         }
5976
5977         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5978                         snd_hdspm_hw_rule_out_channels, hdspm,
5979                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5980
5981         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5982                         snd_hdspm_hw_rule_out_channels_rate, hdspm,
5983                         SNDRV_PCM_HW_PARAM_RATE, -1);
5984
5985         return 0;
5986 }
5987
5988 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
5989 {
5990         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5991
5992         spin_lock_irq(&hdspm->lock);
5993
5994         hdspm->playback_pid = -1;
5995         hdspm->playback_substream = NULL;
5996
5997         spin_unlock_irq(&hdspm->lock);
5998
5999         return 0;
6000 }
6001
6002
6003 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
6004 {
6005         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6006         struct snd_pcm_runtime *runtime = substream->runtime;
6007
6008         spin_lock_irq(&hdspm->lock);
6009         snd_pcm_set_sync(substream);
6010         runtime->hw = snd_hdspm_capture_subinfo;
6011
6012         if (hdspm->playback_substream == NULL)
6013                 hdspm_stop_audio(hdspm);
6014
6015         hdspm->capture_pid = current->pid;
6016         hdspm->capture_substream = substream;
6017
6018         spin_unlock_irq(&hdspm->lock);
6019
6020         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6021         switch (hdspm->io_type) {
6022         case AIO:
6023         case RayDAT:
6024           snd_pcm_hw_constraint_list(runtime, 0,
6025                                      SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6026                                      &hw_constraints_period_sizes_new);
6027           snd_pcm_hw_constraint_list(runtime, 0,
6028                                      SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6029                                      &hw_constraints_raydat_io_buffer);
6030           break;
6031
6032         default:
6033           snd_pcm_hw_constraint_list(runtime, 0,
6034                                      SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6035                                      &hw_constraints_period_sizes_old);
6036         }
6037
6038         if (AES32 == hdspm->io_type) {
6039                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6040                                 &hdspm_hw_constraints_aes32_sample_rates);
6041         } else {
6042                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6043                                 snd_hdspm_hw_rule_rate_in_channels, hdspm,
6044                                 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6045         }
6046
6047         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6048                         snd_hdspm_hw_rule_in_channels, hdspm,
6049                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6050
6051         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6052                         snd_hdspm_hw_rule_in_channels_rate, hdspm,
6053                         SNDRV_PCM_HW_PARAM_RATE, -1);
6054
6055         return 0;
6056 }
6057
6058 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
6059 {
6060         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6061
6062         spin_lock_irq(&hdspm->lock);
6063
6064         hdspm->capture_pid = -1;
6065         hdspm->capture_substream = NULL;
6066
6067         spin_unlock_irq(&hdspm->lock);
6068         return 0;
6069 }
6070
6071 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
6072 {
6073         /* we have nothing to initialize but the call is required */
6074         return 0;
6075 }
6076
6077 static inline int copy_u32_le(void __user *dest, void __iomem *src)
6078 {
6079         u32 val = readl(src);
6080         return copy_to_user(dest, &val, 4);
6081 }
6082
6083 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
6084                 unsigned int cmd, unsigned long __user arg)
6085 {
6086         void __user *argp = (void __user *)arg;
6087         struct hdspm *hdspm = hw->private_data;
6088         struct hdspm_mixer_ioctl mixer;
6089         struct hdspm_config info;
6090         struct hdspm_status status;
6091         struct hdspm_version hdspm_version;
6092         struct hdspm_peak_rms *levels;
6093         struct hdspm_ltc ltc;
6094         unsigned int statusregister;
6095         long unsigned int s;
6096         int i = 0;
6097
6098         switch (cmd) {
6099
6100         case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
6101                 levels = &hdspm->peak_rms;
6102                 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
6103                         levels->input_peaks[i] =
6104                                 readl(hdspm->iobase +
6105                                                 HDSPM_MADI_INPUT_PEAK + i*4);
6106                         levels->playback_peaks[i] =
6107                                 readl(hdspm->iobase +
6108                                                 HDSPM_MADI_PLAYBACK_PEAK + i*4);
6109                         levels->output_peaks[i] =
6110                                 readl(hdspm->iobase +
6111                                                 HDSPM_MADI_OUTPUT_PEAK + i*4);
6112
6113                         levels->input_rms[i] =
6114                                 ((uint64_t) readl(hdspm->iobase +
6115                                         HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6116                                 (uint64_t) readl(hdspm->iobase +
6117                                                 HDSPM_MADI_INPUT_RMS_L + i*4);
6118                         levels->playback_rms[i] =
6119                                 ((uint64_t)readl(hdspm->iobase +
6120                                         HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6121                                 (uint64_t)readl(hdspm->iobase +
6122                                         HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6123                         levels->output_rms[i] =
6124                                 ((uint64_t)readl(hdspm->iobase +
6125                                         HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6126                                 (uint64_t)readl(hdspm->iobase +
6127                                                 HDSPM_MADI_OUTPUT_RMS_L + i*4);
6128                 }
6129
6130                 if (hdspm->system_sample_rate > 96000) {
6131                         levels->speed = qs;
6132                 } else if (hdspm->system_sample_rate > 48000) {
6133                         levels->speed = ds;
6134                 } else {
6135                         levels->speed = ss;
6136                 }
6137                 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6138
6139                 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
6140                 if (0 != s) {
6141                         /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu
6142                          [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6143                          */
6144                         return -EFAULT;
6145                 }
6146                 break;
6147
6148         case SNDRV_HDSPM_IOCTL_GET_LTC:
6149                 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6150                 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6151                 if (i & HDSPM_TCO1_LTC_Input_valid) {
6152                         switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6153                                 HDSPM_TCO1_LTC_Format_MSB)) {
6154                         case 0:
6155                                 ltc.format = fps_24;
6156                                 break;
6157                         case HDSPM_TCO1_LTC_Format_LSB:
6158                                 ltc.format = fps_25;
6159                                 break;
6160                         case HDSPM_TCO1_LTC_Format_MSB:
6161                                 ltc.format = fps_2997;
6162                                 break;
6163                         default:
6164                                 ltc.format = 30;
6165                                 break;
6166                         }
6167                         if (i & HDSPM_TCO1_set_drop_frame_flag) {
6168                                 ltc.frame = drop_frame;
6169                         } else {
6170                                 ltc.frame = full_frame;
6171                         }
6172                 } else {
6173                         ltc.format = format_invalid;
6174                         ltc.frame = frame_invalid;
6175                 }
6176                 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6177                         ltc.input_format = ntsc;
6178                 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6179                         ltc.input_format = pal;
6180                 } else {
6181                         ltc.input_format = no_video;
6182                 }
6183
6184                 s = copy_to_user(argp, &ltc, sizeof(struct hdspm_ltc));
6185                 if (0 != s) {
6186                         /*
6187                          snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6188                         return -EFAULT;
6189                 }
6190
6191                 break;
6192
6193         case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6194
6195                 memset(&info, 0, sizeof(info));
6196                 spin_lock_irq(&hdspm->lock);
6197                 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6198                 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6199
6200                 info.system_sample_rate = hdspm->system_sample_rate;
6201                 info.autosync_sample_rate =
6202                         hdspm_external_sample_rate(hdspm);
6203                 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6204                 info.clock_source = hdspm_clock_source(hdspm);
6205                 info.autosync_ref = hdspm_autosync_ref(hdspm);
6206                 info.line_out = hdspm_line_out(hdspm);
6207                 info.passthru = 0;
6208                 spin_unlock_irq(&hdspm->lock);
6209                 if (copy_to_user((void __user *) arg, &info, sizeof(info)))
6210                         return -EFAULT;
6211                 break;
6212
6213         case SNDRV_HDSPM_IOCTL_GET_STATUS:
6214                 status.card_type = hdspm->io_type;
6215
6216                 status.autosync_source = hdspm_autosync_ref(hdspm);
6217
6218                 status.card_clock = 110069313433624ULL;
6219                 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6220
6221                 switch (hdspm->io_type) {
6222                 case MADI:
6223                 case MADIface:
6224                         status.card_specific.madi.sync_wc =
6225                                 hdspm_wc_sync_check(hdspm);
6226                         status.card_specific.madi.sync_madi =
6227                                 hdspm_madi_sync_check(hdspm);
6228                         status.card_specific.madi.sync_tco =
6229                                 hdspm_tco_sync_check(hdspm);
6230                         status.card_specific.madi.sync_in =
6231                                 hdspm_sync_in_sync_check(hdspm);
6232
6233                         statusregister =
6234                                 hdspm_read(hdspm, HDSPM_statusRegister);
6235                         status.card_specific.madi.madi_input =
6236                                 (statusregister & HDSPM_AB_int) ? 1 : 0;
6237                         status.card_specific.madi.channel_format =
6238                                 (statusregister & HDSPM_TX_64ch) ? 1 : 0;
6239                         /* TODO: Mac driver sets it when f_s>48kHz */
6240                         status.card_specific.madi.frame_format = 0;
6241
6242                 default:
6243                         break;
6244                 }
6245
6246                 if (copy_to_user((void __user *) arg, &status, sizeof(status)))
6247                         return -EFAULT;
6248
6249
6250                 break;
6251
6252         case SNDRV_HDSPM_IOCTL_GET_VERSION:
6253                 hdspm_version.card_type = hdspm->io_type;
6254                 strncpy(hdspm_version.cardname, hdspm->card_name,
6255                                 sizeof(hdspm_version.cardname));
6256                 hdspm_version.serial = (hdspm_read(hdspm,
6257                                         HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6258                 hdspm_version.firmware_rev = hdspm->firmware_rev;
6259                 hdspm_version.addons = 0;
6260                 if (hdspm->tco)
6261                         hdspm_version.addons |= HDSPM_ADDON_TCO;
6262
6263                 if (copy_to_user((void __user *) arg, &hdspm_version,
6264                                         sizeof(hdspm_version)))
6265                         return -EFAULT;
6266                 break;
6267
6268         case SNDRV_HDSPM_IOCTL_GET_MIXER:
6269                 if (copy_from_user(&mixer, (void __user *)arg, sizeof(mixer)))
6270                         return -EFAULT;
6271                 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6272                                         sizeof(struct hdspm_mixer)))
6273                         return -EFAULT;
6274                 break;
6275
6276         default:
6277                 return -EINVAL;
6278         }
6279         return 0;
6280 }
6281
6282 static struct snd_pcm_ops snd_hdspm_playback_ops = {
6283         .open = snd_hdspm_playback_open,
6284         .close = snd_hdspm_playback_release,
6285         .ioctl = snd_hdspm_ioctl,
6286         .hw_params = snd_hdspm_hw_params,
6287         .hw_free = snd_hdspm_hw_free,
6288         .prepare = snd_hdspm_prepare,
6289         .trigger = snd_hdspm_trigger,
6290         .pointer = snd_hdspm_hw_pointer,
6291         .page = snd_pcm_sgbuf_ops_page,
6292 };
6293
6294 static struct snd_pcm_ops snd_hdspm_capture_ops = {
6295         .open = snd_hdspm_capture_open,
6296         .close = snd_hdspm_capture_release,
6297         .ioctl = snd_hdspm_ioctl,
6298         .hw_params = snd_hdspm_hw_params,
6299         .hw_free = snd_hdspm_hw_free,
6300         .prepare = snd_hdspm_prepare,
6301         .trigger = snd_hdspm_trigger,
6302         .pointer = snd_hdspm_hw_pointer,
6303         .page = snd_pcm_sgbuf_ops_page,
6304 };
6305
6306 static int __devinit snd_hdspm_create_hwdep(struct snd_card *card,
6307                                             struct hdspm * hdspm)
6308 {
6309         struct snd_hwdep *hw;
6310         int err;
6311
6312         err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6313         if (err < 0)
6314                 return err;
6315
6316         hdspm->hwdep = hw;
6317         hw->private_data = hdspm;
6318         strcpy(hw->name, "HDSPM hwdep interface");
6319
6320         hw->ops.open = snd_hdspm_hwdep_dummy_op;
6321         hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6322         hw->ops.release = snd_hdspm_hwdep_dummy_op;
6323
6324         return 0;
6325 }
6326
6327
6328 /*------------------------------------------------------------
6329    memory interface
6330  ------------------------------------------------------------*/
6331 static int __devinit snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6332 {
6333         int err;
6334         struct snd_pcm *pcm;
6335         size_t wanted;
6336
6337         pcm = hdspm->pcm;
6338
6339         wanted = HDSPM_DMA_AREA_BYTES;
6340
6341         err =
6342              snd_pcm_lib_preallocate_pages_for_all(pcm,
6343                                                    SNDRV_DMA_TYPE_DEV_SG,
6344                                                    snd_dma_pci_data(hdspm->pci),
6345                                                    wanted,
6346                                                    wanted);
6347         if (err < 0) {
6348                 snd_printdd("Could not preallocate %zd Bytes\n", wanted);
6349
6350                 return err;
6351         } else
6352                 snd_printdd(" Preallocated %zd Bytes\n", wanted);
6353
6354         return 0;
6355 }
6356
6357
6358 static void hdspm_set_sgbuf(struct hdspm *hdspm,
6359                             struct snd_pcm_substream *substream,
6360                              unsigned int reg, int channels)
6361 {
6362         int i;
6363
6364         /* continuous memory segment */
6365         for (i = 0; i < (channels * 16); i++)
6366                 hdspm_write(hdspm, reg + 4 * i,
6367                                 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6368 }
6369
6370
6371 /* ------------- ALSA Devices ---------------------------- */
6372 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
6373                                           struct hdspm *hdspm)
6374 {
6375         struct snd_pcm *pcm;
6376         int err;
6377
6378         err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6379         if (err < 0)
6380                 return err;
6381
6382         hdspm->pcm = pcm;
6383         pcm->private_data = hdspm;
6384         strcpy(pcm->name, hdspm->card_name);
6385
6386         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6387                         &snd_hdspm_playback_ops);
6388         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6389                         &snd_hdspm_capture_ops);
6390
6391         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6392
6393         err = snd_hdspm_preallocate_memory(hdspm);
6394         if (err < 0)
6395                 return err;
6396
6397         return 0;
6398 }
6399
6400 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6401 {
6402         int i;
6403
6404         for (i = 0; i < hdspm->midiPorts; i++)
6405                 snd_hdspm_flush_midi_input(hdspm, i);
6406 }
6407
6408 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
6409                                                    struct hdspm * hdspm)
6410 {
6411         int err, i;
6412
6413         snd_printdd("Create card...\n");
6414         err = snd_hdspm_create_pcm(card, hdspm);
6415         if (err < 0)
6416                 return err;
6417
6418         i = 0;
6419         while (i < hdspm->midiPorts) {
6420                 err = snd_hdspm_create_midi(card, hdspm, i);
6421                 if (err < 0) {
6422                         return err;
6423                 }
6424                 i++;
6425         }
6426
6427         err = snd_hdspm_create_controls(card, hdspm);
6428         if (err < 0)
6429                 return err;
6430
6431         err = snd_hdspm_create_hwdep(card, hdspm);
6432         if (err < 0)
6433                 return err;
6434
6435         snd_printdd("proc init...\n");
6436         snd_hdspm_proc_init(hdspm);
6437
6438         hdspm->system_sample_rate = -1;
6439         hdspm->last_external_sample_rate = -1;
6440         hdspm->last_internal_sample_rate = -1;
6441         hdspm->playback_pid = -1;
6442         hdspm->capture_pid = -1;
6443         hdspm->capture_substream = NULL;
6444         hdspm->playback_substream = NULL;
6445
6446         snd_printdd("Set defaults...\n");
6447         err = snd_hdspm_set_defaults(hdspm);
6448         if (err < 0)
6449                 return err;
6450
6451         snd_printdd("Update mixer controls...\n");
6452         hdspm_update_simple_mixer_controls(hdspm);
6453
6454         snd_printdd("Initializeing complete ???\n");
6455
6456         err = snd_card_register(card);
6457         if (err < 0) {
6458                 snd_printk(KERN_ERR "HDSPM: error registering card\n");
6459                 return err;
6460         }
6461
6462         snd_printdd("... yes now\n");
6463
6464         return 0;
6465 }
6466
6467 static int __devinit snd_hdspm_create(struct snd_card *card,
6468                 struct hdspm *hdspm) {
6469
6470         struct pci_dev *pci = hdspm->pci;
6471         int err;
6472         unsigned long io_extent;
6473
6474         hdspm->irq = -1;
6475         hdspm->card = card;
6476
6477         spin_lock_init(&hdspm->lock);
6478
6479         pci_read_config_word(hdspm->pci,
6480                         PCI_CLASS_REVISION, &hdspm->firmware_rev);
6481
6482         strcpy(card->mixername, "Xilinx FPGA");
6483         strcpy(card->driver, "HDSPM");
6484
6485         switch (hdspm->firmware_rev) {
6486         case HDSPM_MADI_REV:
6487         case HDSPM_MADI_OLD_REV:
6488         case HDSPM_MADI_ANCIENT_REV:
6489                 hdspm->io_type = MADI;
6490                 hdspm->card_name = "RME MADI";
6491                 hdspm->midiPorts = 3;
6492                 break;
6493         case HDSPM_RAYDAT_REV:
6494                 hdspm->io_type = RayDAT;
6495                 hdspm->card_name = "RME RayDAT";
6496                 hdspm->midiPorts = 2;
6497                 break;
6498         case HDSPM_AIO_REV:
6499                 hdspm->io_type = AIO;
6500                 hdspm->card_name = "RME AIO";
6501                 hdspm->midiPorts = 1;
6502                 break;
6503         case HDSPM_MADIFACE_REV:
6504                 hdspm->io_type = MADIface;
6505                 hdspm->card_name = "RME MADIface";
6506                 hdspm->midiPorts = 1;
6507                 break;
6508         case HDSPM_AES_REV:
6509         case HDSPM_AES32_REV:
6510         case HDSPM_AES32_OLD_REV:
6511                 hdspm->io_type = AES32;
6512                 hdspm->card_name = "RME AES32";
6513                 hdspm->midiPorts = 2;
6514                 break;
6515         default:
6516                 snd_printk(KERN_ERR "HDSPM: unknown firmware revision %x\n",
6517                                 hdspm->firmware_rev);
6518                 return -ENODEV;
6519         }
6520
6521         err = pci_enable_device(pci);
6522         if (err < 0)
6523                 return err;
6524
6525         pci_set_master(hdspm->pci);
6526
6527         err = pci_request_regions(pci, "hdspm");
6528         if (err < 0)
6529                 return err;
6530
6531         hdspm->port = pci_resource_start(pci, 0);
6532         io_extent = pci_resource_len(pci, 0);
6533
6534         snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
6535                         hdspm->port, hdspm->port + io_extent - 1);
6536
6537         hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6538         if (!hdspm->iobase) {
6539                 snd_printk(KERN_ERR "HDSPM: "
6540                                 "unable to remap region 0x%lx-0x%lx\n",
6541                                 hdspm->port, hdspm->port + io_extent - 1);
6542                 return -EBUSY;
6543         }
6544         snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
6545                         (unsigned long)hdspm->iobase, hdspm->port,
6546                         hdspm->port + io_extent - 1);
6547
6548         if (request_irq(pci->irq, snd_hdspm_interrupt,
6549                         IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
6550                 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
6551                 return -EBUSY;
6552         }
6553
6554         snd_printdd("use IRQ %d\n", pci->irq);
6555
6556         hdspm->irq = pci->irq;
6557
6558         snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
6559                         sizeof(struct hdspm_mixer));
6560         hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6561         if (!hdspm->mixer) {
6562                 snd_printk(KERN_ERR "HDSPM: "
6563                                 "unable to kmalloc Mixer memory of %d Bytes\n",
6564                                 (int)sizeof(struct hdspm_mixer));
6565                 return err;
6566         }
6567
6568         hdspm->port_names_in = NULL;
6569         hdspm->port_names_out = NULL;
6570
6571         switch (hdspm->io_type) {
6572         case AES32:
6573                 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6574                 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6575                 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6576
6577                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6578                         channel_map_aes32;
6579                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6580                         channel_map_aes32;
6581                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6582                         channel_map_aes32;
6583                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6584                         texts_ports_aes32;
6585                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6586                         texts_ports_aes32;
6587                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6588                         texts_ports_aes32;
6589
6590                 hdspm->max_channels_out = hdspm->max_channels_in =
6591                         AES32_CHANNELS;
6592                 hdspm->port_names_in = hdspm->port_names_out =
6593                         texts_ports_aes32;
6594                 hdspm->channel_map_in = hdspm->channel_map_out =
6595                         channel_map_aes32;
6596
6597                 break;
6598
6599         case MADI:
6600         case MADIface:
6601                 hdspm->ss_in_channels = hdspm->ss_out_channels =
6602                         MADI_SS_CHANNELS;
6603                 hdspm->ds_in_channels = hdspm->ds_out_channels =
6604                         MADI_DS_CHANNELS;
6605                 hdspm->qs_in_channels = hdspm->qs_out_channels =
6606                         MADI_QS_CHANNELS;
6607
6608                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6609                         channel_map_unity_ss;
6610                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6611                         channel_map_unity_ss;
6612                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6613                         channel_map_unity_ss;
6614
6615                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6616                         texts_ports_madi;
6617                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6618                         texts_ports_madi;
6619                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6620                         texts_ports_madi;
6621                 break;
6622
6623         case AIO:
6624                 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6625                         snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n");
6626                 }
6627
6628                 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6629                 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6630                 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6631                 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6632                 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6633                 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6634
6635                 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6636                 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6637                 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6638
6639                 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6640                 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6641                 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6642
6643                 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6644                 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6645                 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6646                 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6647                 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6648                 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6649
6650                 break;
6651
6652         case RayDAT:
6653                 hdspm->ss_in_channels = hdspm->ss_out_channels =
6654                         RAYDAT_SS_CHANNELS;
6655                 hdspm->ds_in_channels = hdspm->ds_out_channels =
6656                         RAYDAT_DS_CHANNELS;
6657                 hdspm->qs_in_channels = hdspm->qs_out_channels =
6658                         RAYDAT_QS_CHANNELS;
6659
6660                 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6661                 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6662
6663                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6664                         channel_map_raydat_ss;
6665                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6666                         channel_map_raydat_ds;
6667                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6668                         channel_map_raydat_qs;
6669                 hdspm->channel_map_in = hdspm->channel_map_out =
6670                         channel_map_raydat_ss;
6671
6672                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6673                         texts_ports_raydat_ss;
6674                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6675                         texts_ports_raydat_ds;
6676                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6677                         texts_ports_raydat_qs;
6678
6679
6680                 break;
6681
6682         }
6683
6684         /* TCO detection */
6685         switch (hdspm->io_type) {
6686         case AIO:
6687         case RayDAT:
6688                 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6689                                 HDSPM_s2_tco_detect) {
6690                         hdspm->midiPorts++;
6691                         hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6692                                         GFP_KERNEL);
6693                         if (NULL != hdspm->tco) {
6694                                 hdspm_tco_write(hdspm);
6695                         }
6696                         snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n");
6697                 } else {
6698                         hdspm->tco = NULL;
6699                 }
6700                 break;
6701
6702         case MADI:
6703                 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6704                         hdspm->midiPorts++;
6705                         hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6706                                         GFP_KERNEL);
6707                         if (NULL != hdspm->tco) {
6708                                 hdspm_tco_write(hdspm);
6709                         }
6710                         snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n");
6711                 } else {
6712                         hdspm->tco = NULL;
6713                 }
6714                 break;
6715
6716         default:
6717                 hdspm->tco = NULL;
6718         }
6719
6720         /* texts */
6721         switch (hdspm->io_type) {
6722         case AES32:
6723                 if (hdspm->tco) {
6724                         hdspm->texts_autosync = texts_autosync_aes_tco;
6725                         hdspm->texts_autosync_items = 10;
6726                 } else {
6727                         hdspm->texts_autosync = texts_autosync_aes;
6728                         hdspm->texts_autosync_items = 9;
6729                 }
6730                 break;
6731
6732         case MADI:
6733                 if (hdspm->tco) {
6734                         hdspm->texts_autosync = texts_autosync_madi_tco;
6735                         hdspm->texts_autosync_items = 4;
6736                 } else {
6737                         hdspm->texts_autosync = texts_autosync_madi;
6738                         hdspm->texts_autosync_items = 3;
6739                 }
6740                 break;
6741
6742         case MADIface:
6743
6744                 break;
6745
6746         case RayDAT:
6747                 if (hdspm->tco) {
6748                         hdspm->texts_autosync = texts_autosync_raydat_tco;
6749                         hdspm->texts_autosync_items = 9;
6750                 } else {
6751                         hdspm->texts_autosync = texts_autosync_raydat;
6752                         hdspm->texts_autosync_items = 8;
6753                 }
6754                 break;
6755
6756         case AIO:
6757                 if (hdspm->tco) {
6758                         hdspm->texts_autosync = texts_autosync_aio_tco;
6759                         hdspm->texts_autosync_items = 6;
6760                 } else {
6761                         hdspm->texts_autosync = texts_autosync_aio;
6762                         hdspm->texts_autosync_items = 5;
6763                 }
6764                 break;
6765
6766         }
6767
6768         tasklet_init(&hdspm->midi_tasklet,
6769                         hdspm_midi_tasklet, (unsigned long) hdspm);
6770
6771         snd_printdd("create alsa devices.\n");
6772         err = snd_hdspm_create_alsa_devices(card, hdspm);
6773         if (err < 0)
6774                 return err;
6775
6776         snd_hdspm_initialize_midi_flush(hdspm);
6777
6778         return 0;
6779 }
6780
6781
6782 static int snd_hdspm_free(struct hdspm * hdspm)
6783 {
6784
6785         if (hdspm->port) {
6786
6787                 /* stop th audio, and cancel all interrupts */
6788                 hdspm->control_register &=
6789                     ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6790                       HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6791                       HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6792                 hdspm_write(hdspm, HDSPM_controlRegister,
6793                             hdspm->control_register);
6794         }
6795
6796         if (hdspm->irq >= 0)
6797                 free_irq(hdspm->irq, (void *) hdspm);
6798
6799         kfree(hdspm->mixer);
6800
6801         if (hdspm->iobase)
6802                 iounmap(hdspm->iobase);
6803
6804         if (hdspm->port)
6805                 pci_release_regions(hdspm->pci);
6806
6807         pci_disable_device(hdspm->pci);
6808         return 0;
6809 }
6810
6811
6812 static void snd_hdspm_card_free(struct snd_card *card)
6813 {
6814         struct hdspm *hdspm = card->private_data;
6815
6816         if (hdspm)
6817                 snd_hdspm_free(hdspm);
6818 }
6819
6820
6821 static int __devinit snd_hdspm_probe(struct pci_dev *pci,
6822                                      const struct pci_device_id *pci_id)
6823 {
6824         static int dev;
6825         struct hdspm *hdspm;
6826         struct snd_card *card;
6827         int err;
6828
6829         if (dev >= SNDRV_CARDS)
6830                 return -ENODEV;
6831         if (!enable[dev]) {
6832                 dev++;
6833                 return -ENOENT;
6834         }
6835
6836         err = snd_card_create(index[dev], id[dev],
6837                         THIS_MODULE, sizeof(struct hdspm), &card);
6838         if (err < 0)
6839                 return err;
6840
6841         hdspm = card->private_data;
6842         card->private_free = snd_hdspm_card_free;
6843         hdspm->dev = dev;
6844         hdspm->pci = pci;
6845
6846         snd_card_set_dev(card, &pci->dev);
6847
6848         err = snd_hdspm_create(card, hdspm);
6849         if (err < 0) {
6850                 snd_card_free(card);
6851                 return err;
6852         }
6853
6854         if (hdspm->io_type != MADIface) {
6855                 sprintf(card->shortname, "%s_%x",
6856                         hdspm->card_name,
6857                         (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF);
6858                 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
6859                         hdspm->card_name,
6860                         (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF,
6861                         hdspm->port, hdspm->irq);
6862         } else {
6863                 sprintf(card->shortname, "%s", hdspm->card_name);
6864                 sprintf(card->longname, "%s at 0x%lx, irq %d",
6865                                 hdspm->card_name, hdspm->port, hdspm->irq);
6866         }
6867
6868         err = snd_card_register(card);
6869         if (err < 0) {
6870                 snd_card_free(card);
6871                 return err;
6872         }
6873
6874         pci_set_drvdata(pci, card);
6875
6876         dev++;
6877         return 0;
6878 }
6879
6880 static void __devexit snd_hdspm_remove(struct pci_dev *pci)
6881 {
6882         snd_card_free(pci_get_drvdata(pci));
6883         pci_set_drvdata(pci, NULL);
6884 }
6885
6886 static struct pci_driver driver = {
6887         .name = KBUILD_MODNAME,
6888         .id_table = snd_hdspm_ids,
6889         .probe = snd_hdspm_probe,
6890         .remove = __devexit_p(snd_hdspm_remove),
6891 };
6892
6893
6894 static int __init alsa_card_hdspm_init(void)
6895 {
6896         return pci_register_driver(&driver);
6897 }
6898
6899 static void __exit alsa_card_hdspm_exit(void)
6900 {
6901         pci_unregister_driver(&driver);
6902 }
6903
6904 module_init(alsa_card_hdspm_init)
6905 module_exit(alsa_card_hdspm_exit)